1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3 * Copyright (C) 2020 SiFive
4 */
5
6 #ifndef _ASM_RISCV_INSN_H
7 #define _ASM_RISCV_INSN_H
8
9 #include <linux/bits.h>
10
11 #define RV_INSN_FUNCT3_MASK GENMASK(14, 12)
12 #define RV_INSN_FUNCT3_OPOFF 12
13 #define RV_INSN_OPCODE_MASK GENMASK(6, 0)
14 #define RV_INSN_OPCODE_OPOFF 0
15 #define RV_INSN_FUNCT12_OPOFF 20
16
17 #define RV_ENCODE_FUNCT3(f_) (RVG_FUNCT3_##f_ << RV_INSN_FUNCT3_OPOFF)
18 #define RV_ENCODE_FUNCT12(f_) (RVG_FUNCT12_##f_ << RV_INSN_FUNCT12_OPOFF)
19
20 /* The bit field of immediate value in I-type instruction */
21 #define RV_I_IMM_SIGN_OPOFF 31
22 #define RV_I_IMM_11_0_OPOFF 20
23 #define RV_I_IMM_SIGN_OFF 12
24 #define RV_I_IMM_11_0_OFF 0
25 #define RV_I_IMM_11_0_MASK GENMASK(11, 0)
26
27 /* The bit field of immediate value in J-type instruction */
28 #define RV_J_IMM_SIGN_OPOFF 31
29 #define RV_J_IMM_10_1_OPOFF 21
30 #define RV_J_IMM_11_OPOFF 20
31 #define RV_J_IMM_19_12_OPOFF 12
32 #define RV_J_IMM_SIGN_OFF 20
33 #define RV_J_IMM_10_1_OFF 1
34 #define RV_J_IMM_11_OFF 11
35 #define RV_J_IMM_19_12_OFF 12
36 #define RV_J_IMM_10_1_MASK GENMASK(9, 0)
37 #define RV_J_IMM_11_MASK GENMASK(0, 0)
38 #define RV_J_IMM_19_12_MASK GENMASK(7, 0)
39
40 /*
41 * U-type IMMs contain the upper 20bits [31:20] of an immediate with
42 * the rest filled in by zeros, so no shifting required. Similarly,
43 * bit31 contains the signed state, so no sign extension necessary.
44 */
45 #define RV_U_IMM_SIGN_OPOFF 31
46 #define RV_U_IMM_31_12_OPOFF 0
47 #define RV_U_IMM_31_12_MASK GENMASK(31, 12)
48
49 /* The bit field of immediate value in B-type instruction */
50 #define RV_B_IMM_SIGN_OPOFF 31
51 #define RV_B_IMM_10_5_OPOFF 25
52 #define RV_B_IMM_4_1_OPOFF 8
53 #define RV_B_IMM_11_OPOFF 7
54 #define RV_B_IMM_SIGN_OFF 12
55 #define RV_B_IMM_10_5_OFF 5
56 #define RV_B_IMM_4_1_OFF 1
57 #define RV_B_IMM_11_OFF 11
58 #define RV_B_IMM_10_5_MASK GENMASK(5, 0)
59 #define RV_B_IMM_4_1_MASK GENMASK(3, 0)
60 #define RV_B_IMM_11_MASK GENMASK(0, 0)
61
62 /* The register offset in RVG instruction */
63 #define RVG_RS1_OPOFF 15
64 #define RVG_RS2_OPOFF 20
65 #define RVG_RD_OPOFF 7
66 #define RVG_RS1_MASK GENMASK(4, 0)
67 #define RVG_RD_MASK GENMASK(4, 0)
68
69 /* The bit field of immediate value in RVC J instruction */
70 #define RVC_J_IMM_SIGN_OPOFF 12
71 #define RVC_J_IMM_4_OPOFF 11
72 #define RVC_J_IMM_9_8_OPOFF 9
73 #define RVC_J_IMM_10_OPOFF 8
74 #define RVC_J_IMM_6_OPOFF 7
75 #define RVC_J_IMM_7_OPOFF 6
76 #define RVC_J_IMM_3_1_OPOFF 3
77 #define RVC_J_IMM_5_OPOFF 2
78 #define RVC_J_IMM_SIGN_OFF 11
79 #define RVC_J_IMM_4_OFF 4
80 #define RVC_J_IMM_9_8_OFF 8
81 #define RVC_J_IMM_10_OFF 10
82 #define RVC_J_IMM_6_OFF 6
83 #define RVC_J_IMM_7_OFF 7
84 #define RVC_J_IMM_3_1_OFF 1
85 #define RVC_J_IMM_5_OFF 5
86 #define RVC_J_IMM_4_MASK GENMASK(0, 0)
87 #define RVC_J_IMM_9_8_MASK GENMASK(1, 0)
88 #define RVC_J_IMM_10_MASK GENMASK(0, 0)
89 #define RVC_J_IMM_6_MASK GENMASK(0, 0)
90 #define RVC_J_IMM_7_MASK GENMASK(0, 0)
91 #define RVC_J_IMM_3_1_MASK GENMASK(2, 0)
92 #define RVC_J_IMM_5_MASK GENMASK(0, 0)
93
94 /* The bit field of immediate value in RVC B instruction */
95 #define RVC_B_IMM_SIGN_OPOFF 12
96 #define RVC_B_IMM_4_3_OPOFF 10
97 #define RVC_B_IMM_7_6_OPOFF 5
98 #define RVC_B_IMM_2_1_OPOFF 3
99 #define RVC_B_IMM_5_OPOFF 2
100 #define RVC_B_IMM_SIGN_OFF 8
101 #define RVC_B_IMM_4_3_OFF 3
102 #define RVC_B_IMM_7_6_OFF 6
103 #define RVC_B_IMM_2_1_OFF 1
104 #define RVC_B_IMM_5_OFF 5
105 #define RVC_B_IMM_4_3_MASK GENMASK(1, 0)
106 #define RVC_B_IMM_7_6_MASK GENMASK(1, 0)
107 #define RVC_B_IMM_2_1_MASK GENMASK(1, 0)
108 #define RVC_B_IMM_5_MASK GENMASK(0, 0)
109
110 #define RVC_INSN_FUNCT4_MASK GENMASK(15, 12)
111 #define RVC_INSN_FUNCT4_OPOFF 12
112 #define RVC_INSN_FUNCT3_MASK GENMASK(15, 13)
113 #define RVC_INSN_FUNCT3_OPOFF 13
114 #define RVC_INSN_J_RS1_MASK GENMASK(11, 7)
115 #define RVC_INSN_J_RS2_MASK GENMASK(6, 2)
116 #define RVC_INSN_OPCODE_MASK GENMASK(1, 0)
117 #define RVC_ENCODE_FUNCT3(f_) (RVC_FUNCT3_##f_ << RVC_INSN_FUNCT3_OPOFF)
118 #define RVC_ENCODE_FUNCT4(f_) (RVC_FUNCT4_##f_ << RVC_INSN_FUNCT4_OPOFF)
119
120 /* The register offset in RVC op=C0 instruction */
121 #define RVC_C0_RS1_OPOFF 7
122 #define RVC_C0_RS2_OPOFF 2
123 #define RVC_C0_RD_OPOFF 2
124
125 /* The register offset in RVC op=C1 instruction */
126 #define RVC_C1_RS1_OPOFF 7
127 #define RVC_C1_RS2_OPOFF 2
128 #define RVC_C1_RD_OPOFF 7
129
130 /* The register offset in RVC op=C2 instruction */
131 #define RVC_C2_RS1_OPOFF 7
132 #define RVC_C2_RS2_OPOFF 2
133 #define RVC_C2_RD_OPOFF 7
134 #define RVC_C2_RS1_MASK GENMASK(4, 0)
135
136 /* parts of opcode for RVG*/
137 #define RVG_OPCODE_FENCE 0x0f
138 #define RVG_OPCODE_AUIPC 0x17
139 #define RVG_OPCODE_BRANCH 0x63
140 #define RVG_OPCODE_JALR 0x67
141 #define RVG_OPCODE_JAL 0x6f
142 #define RVG_OPCODE_SYSTEM 0x73
143 #define RVG_SYSTEM_CSR_OFF 20
144 #define RVG_SYSTEM_CSR_MASK GENMASK(12, 0)
145
146 /* parts of opcode for RVF, RVD and RVQ */
147 #define RVFDQ_FL_FS_WIDTH_OFF 12
148 #define RVFDQ_FL_FS_WIDTH_MASK GENMASK(3, 0)
149 #define RVFDQ_FL_FS_WIDTH_W 2
150 #define RVFDQ_FL_FS_WIDTH_D 3
151 #define RVFDQ_LS_FS_WIDTH_Q 4
152 #define RVFDQ_OPCODE_FL 0x07
153 #define RVFDQ_OPCODE_FS 0x27
154
155 /* parts of opcode for RVV */
156 #define RVV_OPCODE_VECTOR 0x57
157 #define RVV_VL_VS_WIDTH_8 0
158 #define RVV_VL_VS_WIDTH_16 5
159 #define RVV_VL_VS_WIDTH_32 6
160 #define RVV_VL_VS_WIDTH_64 7
161 #define RVV_OPCODE_VL RVFDQ_OPCODE_FL
162 #define RVV_OPCODE_VS RVFDQ_OPCODE_FS
163
164 /* parts of opcode for RVC*/
165 #define RVC_OPCODE_C0 0x0
166 #define RVC_OPCODE_C1 0x1
167 #define RVC_OPCODE_C2 0x2
168
169 /* parts of funct3 code for I, M, A extension*/
170 #define RVG_FUNCT3_JALR 0x0
171 #define RVG_FUNCT3_BEQ 0x0
172 #define RVG_FUNCT3_BNE 0x1
173 #define RVG_FUNCT3_BLT 0x4
174 #define RVG_FUNCT3_BGE 0x5
175 #define RVG_FUNCT3_BLTU 0x6
176 #define RVG_FUNCT3_BGEU 0x7
177
178 /* parts of funct3 code for C extension*/
179 #define RVC_FUNCT3_C_BEQZ 0x6
180 #define RVC_FUNCT3_C_BNEZ 0x7
181 #define RVC_FUNCT3_C_J 0x5
182 #define RVC_FUNCT3_C_JAL 0x1
183 #define RVC_FUNCT4_C_JR 0x8
184 #define RVC_FUNCT4_C_JALR 0x9
185 #define RVC_FUNCT4_C_EBREAK 0x9
186
187 #define RVG_FUNCT12_EBREAK 0x1
188 #define RVG_FUNCT12_SRET 0x102
189
190 #define RVG_MATCH_AUIPC (RVG_OPCODE_AUIPC)
191 #define RVG_MATCH_JALR (RV_ENCODE_FUNCT3(JALR) | RVG_OPCODE_JALR)
192 #define RVG_MATCH_JAL (RVG_OPCODE_JAL)
193 #define RVG_MATCH_FENCE (RVG_OPCODE_FENCE)
194 #define RVG_MATCH_BEQ (RV_ENCODE_FUNCT3(BEQ) | RVG_OPCODE_BRANCH)
195 #define RVG_MATCH_BNE (RV_ENCODE_FUNCT3(BNE) | RVG_OPCODE_BRANCH)
196 #define RVG_MATCH_BLT (RV_ENCODE_FUNCT3(BLT) | RVG_OPCODE_BRANCH)
197 #define RVG_MATCH_BGE (RV_ENCODE_FUNCT3(BGE) | RVG_OPCODE_BRANCH)
198 #define RVG_MATCH_BLTU (RV_ENCODE_FUNCT3(BLTU) | RVG_OPCODE_BRANCH)
199 #define RVG_MATCH_BGEU (RV_ENCODE_FUNCT3(BGEU) | RVG_OPCODE_BRANCH)
200 #define RVG_MATCH_EBREAK (RV_ENCODE_FUNCT12(EBREAK) | RVG_OPCODE_SYSTEM)
201 #define RVG_MATCH_SRET (RV_ENCODE_FUNCT12(SRET) | RVG_OPCODE_SYSTEM)
202 #define RVC_MATCH_C_BEQZ (RVC_ENCODE_FUNCT3(C_BEQZ) | RVC_OPCODE_C1)
203 #define RVC_MATCH_C_BNEZ (RVC_ENCODE_FUNCT3(C_BNEZ) | RVC_OPCODE_C1)
204 #define RVC_MATCH_C_J (RVC_ENCODE_FUNCT3(C_J) | RVC_OPCODE_C1)
205 #define RVC_MATCH_C_JAL (RVC_ENCODE_FUNCT3(C_JAL) | RVC_OPCODE_C1)
206 #define RVC_MATCH_C_JR (RVC_ENCODE_FUNCT4(C_JR) | RVC_OPCODE_C2)
207 #define RVC_MATCH_C_JALR (RVC_ENCODE_FUNCT4(C_JALR) | RVC_OPCODE_C2)
208 #define RVC_MATCH_C_EBREAK (RVC_ENCODE_FUNCT4(C_EBREAK) | RVC_OPCODE_C2)
209
210 #define RVG_MASK_AUIPC (RV_INSN_OPCODE_MASK)
211 #define RVG_MASK_JALR (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
212 #define RVG_MASK_JAL (RV_INSN_OPCODE_MASK)
213 #define RVG_MASK_FENCE (RV_INSN_OPCODE_MASK)
214 #define RVC_MASK_C_JALR (RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK)
215 #define RVC_MASK_C_JR (RVC_INSN_FUNCT4_MASK | RVC_INSN_J_RS2_MASK | RVC_INSN_OPCODE_MASK)
216 #define RVC_MASK_C_JAL (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
217 #define RVC_MASK_C_J (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
218 #define RVG_MASK_BEQ (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
219 #define RVG_MASK_BNE (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
220 #define RVG_MASK_BLT (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
221 #define RVG_MASK_BGE (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
222 #define RVG_MASK_BLTU (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
223 #define RVG_MASK_BGEU (RV_INSN_FUNCT3_MASK | RV_INSN_OPCODE_MASK)
224 #define RVC_MASK_C_BEQZ (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
225 #define RVC_MASK_C_BNEZ (RVC_INSN_FUNCT3_MASK | RVC_INSN_OPCODE_MASK)
226 #define RVC_MASK_C_EBREAK 0xffff
227 #define RVG_MASK_EBREAK 0xffffffff
228 #define RVG_MASK_SRET 0xffffffff
229
230 #define __INSN_LENGTH_MASK _UL(0x3)
231 #define __INSN_LENGTH_GE_32 _UL(0x3)
232 #define __INSN_OPCODE_MASK _UL(0x7F)
233 #define __INSN_BRANCH_OPCODE _UL(RVG_OPCODE_BRANCH)
234
235 #define __RISCV_INSN_FUNCS(name, mask, val) \
236 static __always_inline bool riscv_insn_is_##name(u32 code) \
237 { \
238 BUILD_BUG_ON(~(mask) & (val)); \
239 return (code & (mask)) == (val); \
240 } \
241
242 #if __riscv_xlen == 32
243 /* C.JAL is an RV32C-only instruction */
244 __RISCV_INSN_FUNCS(c_jal, RVC_MASK_C_JAL, RVC_MATCH_C_JAL)
245 #else
246 #define riscv_insn_is_c_jal(opcode) 0
247 #endif
248 __RISCV_INSN_FUNCS(auipc, RVG_MASK_AUIPC, RVG_MATCH_AUIPC)
249 __RISCV_INSN_FUNCS(jalr, RVG_MASK_JALR, RVG_MATCH_JALR)
250 __RISCV_INSN_FUNCS(jal, RVG_MASK_JAL, RVG_MATCH_JAL)
251 __RISCV_INSN_FUNCS(c_j, RVC_MASK_C_J, RVC_MATCH_C_J)
252 __RISCV_INSN_FUNCS(beq, RVG_MASK_BEQ, RVG_MATCH_BEQ)
253 __RISCV_INSN_FUNCS(bne, RVG_MASK_BNE, RVG_MATCH_BNE)
254 __RISCV_INSN_FUNCS(blt, RVG_MASK_BLT, RVG_MATCH_BLT)
255 __RISCV_INSN_FUNCS(bge, RVG_MASK_BGE, RVG_MATCH_BGE)
256 __RISCV_INSN_FUNCS(bltu, RVG_MASK_BLTU, RVG_MATCH_BLTU)
257 __RISCV_INSN_FUNCS(bgeu, RVG_MASK_BGEU, RVG_MATCH_BGEU)
258 __RISCV_INSN_FUNCS(c_beqz, RVC_MASK_C_BEQZ, RVC_MATCH_C_BEQZ)
259 __RISCV_INSN_FUNCS(c_bnez, RVC_MASK_C_BNEZ, RVC_MATCH_C_BNEZ)
260 __RISCV_INSN_FUNCS(c_ebreak, RVC_MASK_C_EBREAK, RVC_MATCH_C_EBREAK)
261 __RISCV_INSN_FUNCS(ebreak, RVG_MASK_EBREAK, RVG_MATCH_EBREAK)
262 __RISCV_INSN_FUNCS(sret, RVG_MASK_SRET, RVG_MATCH_SRET)
263 __RISCV_INSN_FUNCS(fence, RVG_MASK_FENCE, RVG_MATCH_FENCE);
264
265 /* special case to catch _any_ system instruction */
riscv_insn_is_system(u32 code)266 static __always_inline bool riscv_insn_is_system(u32 code)
267 {
268 return (code & RV_INSN_OPCODE_MASK) == RVG_OPCODE_SYSTEM;
269 }
270
271 /* special case to catch _any_ branch instruction */
riscv_insn_is_branch(u32 code)272 static __always_inline bool riscv_insn_is_branch(u32 code)
273 {
274 return (code & RV_INSN_OPCODE_MASK) == RVG_OPCODE_BRANCH;
275 }
276
riscv_insn_is_c_jr(u32 code)277 static __always_inline bool riscv_insn_is_c_jr(u32 code)
278 {
279 return (code & RVC_MASK_C_JR) == RVC_MATCH_C_JR &&
280 (code & RVC_INSN_J_RS1_MASK) != 0;
281 }
282
riscv_insn_is_c_jalr(u32 code)283 static __always_inline bool riscv_insn_is_c_jalr(u32 code)
284 {
285 return (code & RVC_MASK_C_JALR) == RVC_MATCH_C_JALR &&
286 (code & RVC_INSN_J_RS1_MASK) != 0;
287 }
288
289 #define RV_IMM_SIGN(x) (-(((x) >> 31) & 1))
290 #define RVC_IMM_SIGN(x) (-(((x) >> 12) & 1))
291 #define RV_X(X, s, mask) (((X) >> (s)) & (mask))
292 #define RVC_X(X, s, mask) RV_X(X, s, mask)
293
294 #define RV_EXTRACT_RS1_REG(x) \
295 ({typeof(x) x_ = (x); \
296 (RV_X(x_, RVG_RS1_OPOFF, RVG_RS1_MASK)); })
297
298 #define RV_EXTRACT_RD_REG(x) \
299 ({typeof(x) x_ = (x); \
300 (RV_X(x_, RVG_RD_OPOFF, RVG_RD_MASK)); })
301
302 #define RV_EXTRACT_UTYPE_IMM(x) \
303 ({typeof(x) x_ = (x); \
304 (RV_X(x_, RV_U_IMM_31_12_OPOFF, RV_U_IMM_31_12_MASK)); })
305
306 #define RV_EXTRACT_JTYPE_IMM(x) \
307 ({typeof(x) x_ = (x); \
308 (RV_X(x_, RV_J_IMM_10_1_OPOFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OFF) | \
309 (RV_X(x_, RV_J_IMM_11_OPOFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OFF) | \
310 (RV_X(x_, RV_J_IMM_19_12_OPOFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OFF) | \
311 (RV_IMM_SIGN(x_) << RV_J_IMM_SIGN_OFF); })
312
313 #define RV_EXTRACT_ITYPE_IMM(x) \
314 ({typeof(x) x_ = (x); \
315 (RV_X(x_, RV_I_IMM_11_0_OPOFF, RV_I_IMM_11_0_MASK)) | \
316 (RV_IMM_SIGN(x_) << RV_I_IMM_SIGN_OFF); })
317
318 #define RV_EXTRACT_BTYPE_IMM(x) \
319 ({typeof(x) x_ = (x); \
320 (RV_X(x_, RV_B_IMM_4_1_OPOFF, RV_B_IMM_4_1_MASK) << RV_B_IMM_4_1_OFF) | \
321 (RV_X(x_, RV_B_IMM_10_5_OPOFF, RV_B_IMM_10_5_MASK) << RV_B_IMM_10_5_OFF) | \
322 (RV_X(x_, RV_B_IMM_11_OPOFF, RV_B_IMM_11_MASK) << RV_B_IMM_11_OFF) | \
323 (RV_IMM_SIGN(x_) << RV_B_IMM_SIGN_OFF); })
324
325 #define RVC_EXTRACT_C2_RS1_REG(x) \
326 ({typeof(x) x_ = (x); \
327 (RV_X(x_, RVC_C2_RS1_OPOFF, RVC_C2_RS1_MASK)); })
328
329 #define RVC_EXTRACT_JTYPE_IMM(x) \
330 ({typeof(x) x_ = (x); \
331 (RVC_X(x_, RVC_J_IMM_3_1_OPOFF, RVC_J_IMM_3_1_MASK) << RVC_J_IMM_3_1_OFF) | \
332 (RVC_X(x_, RVC_J_IMM_4_OPOFF, RVC_J_IMM_4_MASK) << RVC_J_IMM_4_OFF) | \
333 (RVC_X(x_, RVC_J_IMM_5_OPOFF, RVC_J_IMM_5_MASK) << RVC_J_IMM_5_OFF) | \
334 (RVC_X(x_, RVC_J_IMM_6_OPOFF, RVC_J_IMM_6_MASK) << RVC_J_IMM_6_OFF) | \
335 (RVC_X(x_, RVC_J_IMM_7_OPOFF, RVC_J_IMM_7_MASK) << RVC_J_IMM_7_OFF) | \
336 (RVC_X(x_, RVC_J_IMM_9_8_OPOFF, RVC_J_IMM_9_8_MASK) << RVC_J_IMM_9_8_OFF) | \
337 (RVC_X(x_, RVC_J_IMM_10_OPOFF, RVC_J_IMM_10_MASK) << RVC_J_IMM_10_OFF) | \
338 (RVC_IMM_SIGN(x_) << RVC_J_IMM_SIGN_OFF); })
339
340 #define RVC_EXTRACT_BTYPE_IMM(x) \
341 ({typeof(x) x_ = (x); \
342 (RVC_X(x_, RVC_B_IMM_2_1_OPOFF, RVC_B_IMM_2_1_MASK) << RVC_B_IMM_2_1_OFF) | \
343 (RVC_X(x_, RVC_B_IMM_4_3_OPOFF, RVC_B_IMM_4_3_MASK) << RVC_B_IMM_4_3_OFF) | \
344 (RVC_X(x_, RVC_B_IMM_5_OPOFF, RVC_B_IMM_5_MASK) << RVC_B_IMM_5_OFF) | \
345 (RVC_X(x_, RVC_B_IMM_7_6_OPOFF, RVC_B_IMM_7_6_MASK) << RVC_B_IMM_7_6_OFF) | \
346 (RVC_IMM_SIGN(x_) << RVC_B_IMM_SIGN_OFF); })
347
348 #define RVG_EXTRACT_SYSTEM_CSR(x) \
349 ({typeof(x) x_ = (x); RV_X(x_, RVG_SYSTEM_CSR_OFF, RVG_SYSTEM_CSR_MASK); })
350
351 #define RVFDQ_EXTRACT_FL_FS_WIDTH(x) \
352 ({typeof(x) x_ = (x); RV_X(x_, RVFDQ_FL_FS_WIDTH_OFF, \
353 RVFDQ_FL_FS_WIDTH_MASK); })
354
355 #define RVV_EXRACT_VL_VS_WIDTH(x) RVFDQ_EXTRACT_FL_FS_WIDTH(x)
356
357 /*
358 * Get the immediate from a J-type instruction.
359 *
360 * @insn: instruction to process
361 * Return: immediate
362 */
riscv_insn_extract_jtype_imm(u32 insn)363 static inline s32 riscv_insn_extract_jtype_imm(u32 insn)
364 {
365 return RV_EXTRACT_JTYPE_IMM(insn);
366 }
367
368 /*
369 * Update a J-type instruction with an immediate value.
370 *
371 * @insn: pointer to the jtype instruction
372 * @imm: the immediate to insert into the instruction
373 */
riscv_insn_insert_jtype_imm(u32 * insn,s32 imm)374 static inline void riscv_insn_insert_jtype_imm(u32 *insn, s32 imm)
375 {
376 /* drop the old IMMs, all jal IMM bits sit at 31:12 */
377 *insn &= ~GENMASK(31, 12);
378 *insn |= (RV_X(imm, RV_J_IMM_10_1_OFF, RV_J_IMM_10_1_MASK) << RV_J_IMM_10_1_OPOFF) |
379 (RV_X(imm, RV_J_IMM_11_OFF, RV_J_IMM_11_MASK) << RV_J_IMM_11_OPOFF) |
380 (RV_X(imm, RV_J_IMM_19_12_OFF, RV_J_IMM_19_12_MASK) << RV_J_IMM_19_12_OPOFF) |
381 (RV_X(imm, RV_J_IMM_SIGN_OFF, 1) << RV_J_IMM_SIGN_OPOFF);
382 }
383
384 /*
385 * Put together one immediate from a U-type and I-type instruction pair.
386 *
387 * The U-type contains an upper immediate, meaning bits[31:12] with [11:0]
388 * being zero, while the I-type contains a 12bit immediate.
389 * Combined these can encode larger 32bit values and are used for example
390 * in auipc + jalr pairs to allow larger jumps.
391 *
392 * @utype_insn: instruction containing the upper immediate
393 * @itype_insn: instruction
394 * Return: combined immediate
395 */
riscv_insn_extract_utype_itype_imm(u32 utype_insn,u32 itype_insn)396 static inline s32 riscv_insn_extract_utype_itype_imm(u32 utype_insn, u32 itype_insn)
397 {
398 s32 imm;
399
400 imm = RV_EXTRACT_UTYPE_IMM(utype_insn);
401 imm += RV_EXTRACT_ITYPE_IMM(itype_insn);
402
403 return imm;
404 }
405
406 /*
407 * Update a set of two instructions (U-type + I-type) with an immediate value.
408 *
409 * Used for example in auipc+jalrs pairs the U-type instructions contains
410 * a 20bit upper immediate representing bits[31:12], while the I-type
411 * instruction contains a 12bit immediate representing bits[11:0].
412 *
413 * This also takes into account that both separate immediates are
414 * considered as signed values, so if the I-type immediate becomes
415 * negative (BIT(11) set) the U-type part gets adjusted.
416 *
417 * @utype_insn: pointer to the utype instruction of the pair
418 * @itype_insn: pointer to the itype instruction of the pair
419 * @imm: the immediate to insert into the two instructions
420 */
riscv_insn_insert_utype_itype_imm(u32 * utype_insn,u32 * itype_insn,s32 imm)421 static inline void riscv_insn_insert_utype_itype_imm(u32 *utype_insn, u32 *itype_insn, s32 imm)
422 {
423 /* drop possible old IMM values */
424 *utype_insn &= ~(RV_U_IMM_31_12_MASK);
425 *itype_insn &= ~(RV_I_IMM_11_0_MASK << RV_I_IMM_11_0_OPOFF);
426
427 /* add the adapted IMMs */
428 *utype_insn |= (imm & RV_U_IMM_31_12_MASK) + ((imm & BIT(11)) << 1);
429 *itype_insn |= ((imm & RV_I_IMM_11_0_MASK) << RV_I_IMM_11_0_OPOFF);
430 }
431 #endif /* _ASM_RISCV_INSN_H */
432