1 // SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause
2 /* Copyright(c) 2019-2020 Realtek Corporation
3 */
4
5 #include <linux/vmalloc.h>
6
7 #include "coex.h"
8 #include "debug.h"
9 #include "fw.h"
10 #include "mac.h"
11 #include "pci.h"
12 #include "ps.h"
13 #include "reg.h"
14 #include "sar.h"
15
16 #ifdef CONFIG_RTW89_DEBUGMSG
17 unsigned int rtw89_debug_mask;
18 EXPORT_SYMBOL(rtw89_debug_mask);
19 module_param_named(debug_mask, rtw89_debug_mask, uint, 0644);
20 MODULE_PARM_DESC(debug_mask, "Debugging mask");
21 #endif
22
23 #ifdef CONFIG_RTW89_DEBUGFS
24 struct rtw89_debugfs_priv {
25 struct rtw89_dev *rtwdev;
26 int (*cb_read)(struct seq_file *m, void *v);
27 ssize_t (*cb_write)(struct file *filp, const char __user *buffer,
28 size_t count, loff_t *loff);
29 union {
30 u32 cb_data;
31 struct {
32 u32 addr;
33 u32 len;
34 } read_reg;
35 struct {
36 u32 addr;
37 u32 mask;
38 u8 path;
39 } read_rf;
40 struct {
41 u8 ss_dbg:1;
42 u8 dle_dbg:1;
43 u8 dmac_dbg:1;
44 u8 cmac_dbg:1;
45 u8 dbg_port:1;
46 } dbgpkg_en;
47 struct {
48 u32 start;
49 u32 len;
50 u8 sel;
51 } mac_mem;
52 };
53 };
54
55 static const u16 rtw89_rate_info_bw_to_mhz_map[] = {
56 [RATE_INFO_BW_20] = 20,
57 [RATE_INFO_BW_40] = 40,
58 [RATE_INFO_BW_80] = 80,
59 [RATE_INFO_BW_160] = 160,
60 [RATE_INFO_BW_320] = 320,
61 };
62
rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw)63 static u16 rtw89_rate_info_bw_to_mhz(enum rate_info_bw bw)
64 {
65 if (bw < ARRAY_SIZE(rtw89_rate_info_bw_to_mhz_map))
66 return rtw89_rate_info_bw_to_mhz_map[bw];
67
68 return 0;
69 }
70
rtw89_debugfs_single_show(struct seq_file * m,void * v)71 static int rtw89_debugfs_single_show(struct seq_file *m, void *v)
72 {
73 struct rtw89_debugfs_priv *debugfs_priv = m->private;
74
75 return debugfs_priv->cb_read(m, v);
76 }
77
rtw89_debugfs_single_write(struct file * filp,const char __user * buffer,size_t count,loff_t * loff)78 static ssize_t rtw89_debugfs_single_write(struct file *filp,
79 const char __user *buffer,
80 size_t count, loff_t *loff)
81 {
82 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
83
84 return debugfs_priv->cb_write(filp, buffer, count, loff);
85 }
86
rtw89_debugfs_seq_file_write(struct file * filp,const char __user * buffer,size_t count,loff_t * loff)87 static ssize_t rtw89_debugfs_seq_file_write(struct file *filp,
88 const char __user *buffer,
89 size_t count, loff_t *loff)
90 {
91 struct seq_file *seqpriv = (struct seq_file *)filp->private_data;
92 struct rtw89_debugfs_priv *debugfs_priv = seqpriv->private;
93
94 return debugfs_priv->cb_write(filp, buffer, count, loff);
95 }
96
rtw89_debugfs_single_open(struct inode * inode,struct file * filp)97 static int rtw89_debugfs_single_open(struct inode *inode, struct file *filp)
98 {
99 return single_open(filp, rtw89_debugfs_single_show, inode->i_private);
100 }
101
rtw89_debugfs_close(struct inode * inode,struct file * filp)102 static int rtw89_debugfs_close(struct inode *inode, struct file *filp)
103 {
104 return 0;
105 }
106
107 static const struct file_operations file_ops_single_r = {
108 .owner = THIS_MODULE,
109 .open = rtw89_debugfs_single_open,
110 .read = seq_read,
111 .llseek = seq_lseek,
112 .release = single_release,
113 };
114
115 static const struct file_operations file_ops_common_rw = {
116 .owner = THIS_MODULE,
117 .open = rtw89_debugfs_single_open,
118 .release = single_release,
119 .read = seq_read,
120 .llseek = seq_lseek,
121 .write = rtw89_debugfs_seq_file_write,
122 };
123
124 static const struct file_operations file_ops_single_w = {
125 .owner = THIS_MODULE,
126 .write = rtw89_debugfs_single_write,
127 .open = simple_open,
128 .release = rtw89_debugfs_close,
129 };
130
131 static ssize_t
rtw89_debug_priv_read_reg_select(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)132 rtw89_debug_priv_read_reg_select(struct file *filp,
133 const char __user *user_buf,
134 size_t count, loff_t *loff)
135 {
136 struct seq_file *m = (struct seq_file *)filp->private_data;
137 struct rtw89_debugfs_priv *debugfs_priv = m->private;
138 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
139 char buf[32];
140 size_t buf_size;
141 u32 addr, len;
142 int num;
143
144 buf_size = min(count, sizeof(buf) - 1);
145 if (copy_from_user(buf, user_buf, buf_size))
146 return -EFAULT;
147
148 buf[buf_size] = '\0';
149 num = sscanf(buf, "%x %x", &addr, &len);
150 if (num != 2) {
151 rtw89_info(rtwdev, "invalid format: <addr> <len>\n");
152 return -EINVAL;
153 }
154
155 debugfs_priv->read_reg.addr = addr;
156 debugfs_priv->read_reg.len = len;
157
158 rtw89_info(rtwdev, "select read %d bytes from 0x%08x\n", len, addr);
159
160 return count;
161 }
162
rtw89_debug_priv_read_reg_get(struct seq_file * m,void * v)163 static int rtw89_debug_priv_read_reg_get(struct seq_file *m, void *v)
164 {
165 struct rtw89_debugfs_priv *debugfs_priv = m->private;
166 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
167 u32 addr, end, data, k;
168 u32 len;
169
170 len = debugfs_priv->read_reg.len;
171 addr = debugfs_priv->read_reg.addr;
172
173 if (len > 4)
174 goto ndata;
175
176 switch (len) {
177 case 1:
178 data = rtw89_read8(rtwdev, addr);
179 break;
180 case 2:
181 data = rtw89_read16(rtwdev, addr);
182 break;
183 case 4:
184 data = rtw89_read32(rtwdev, addr);
185 break;
186 default:
187 rtw89_info(rtwdev, "invalid read reg len %d\n", len);
188 return -EINVAL;
189 }
190
191 seq_printf(m, "get %d bytes at 0x%08x=0x%08x\n", len, addr, data);
192
193 return 0;
194
195 ndata:
196 end = addr + len;
197
198 for (; addr < end; addr += 16) {
199 seq_printf(m, "%08xh : ", 0x18600000 + addr);
200 for (k = 0; k < 16; k += 4) {
201 data = rtw89_read32(rtwdev, addr + k);
202 seq_printf(m, "%08x ", data);
203 }
204 seq_puts(m, "\n");
205 }
206
207 return 0;
208 }
209
rtw89_debug_priv_write_reg_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)210 static ssize_t rtw89_debug_priv_write_reg_set(struct file *filp,
211 const char __user *user_buf,
212 size_t count, loff_t *loff)
213 {
214 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
215 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
216 char buf[32];
217 size_t buf_size;
218 u32 addr, val, len;
219 int num;
220
221 buf_size = min(count, sizeof(buf) - 1);
222 if (copy_from_user(buf, user_buf, buf_size))
223 return -EFAULT;
224
225 buf[buf_size] = '\0';
226 num = sscanf(buf, "%x %x %x", &addr, &val, &len);
227 if (num != 3) {
228 rtw89_info(rtwdev, "invalid format: <addr> <val> <len>\n");
229 return -EINVAL;
230 }
231
232 switch (len) {
233 case 1:
234 rtw89_info(rtwdev, "reg write8 0x%08x: 0x%02x\n", addr, val);
235 rtw89_write8(rtwdev, addr, (u8)val);
236 break;
237 case 2:
238 rtw89_info(rtwdev, "reg write16 0x%08x: 0x%04x\n", addr, val);
239 rtw89_write16(rtwdev, addr, (u16)val);
240 break;
241 case 4:
242 rtw89_info(rtwdev, "reg write32 0x%08x: 0x%08x\n", addr, val);
243 rtw89_write32(rtwdev, addr, (u32)val);
244 break;
245 default:
246 rtw89_info(rtwdev, "invalid read write len %d\n", len);
247 break;
248 }
249
250 return count;
251 }
252
253 static ssize_t
rtw89_debug_priv_read_rf_select(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)254 rtw89_debug_priv_read_rf_select(struct file *filp,
255 const char __user *user_buf,
256 size_t count, loff_t *loff)
257 {
258 struct seq_file *m = (struct seq_file *)filp->private_data;
259 struct rtw89_debugfs_priv *debugfs_priv = m->private;
260 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
261 char buf[32];
262 size_t buf_size;
263 u32 addr, mask;
264 u8 path;
265 int num;
266
267 buf_size = min(count, sizeof(buf) - 1);
268 if (copy_from_user(buf, user_buf, buf_size))
269 return -EFAULT;
270
271 buf[buf_size] = '\0';
272 num = sscanf(buf, "%hhd %x %x", &path, &addr, &mask);
273 if (num != 3) {
274 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask>\n");
275 return -EINVAL;
276 }
277
278 if (path >= rtwdev->chip->rf_path_num) {
279 rtw89_info(rtwdev, "wrong rf path\n");
280 return -EINVAL;
281 }
282 debugfs_priv->read_rf.addr = addr;
283 debugfs_priv->read_rf.mask = mask;
284 debugfs_priv->read_rf.path = path;
285
286 rtw89_info(rtwdev, "select read rf path %d from 0x%08x\n", path, addr);
287
288 return count;
289 }
290
rtw89_debug_priv_read_rf_get(struct seq_file * m,void * v)291 static int rtw89_debug_priv_read_rf_get(struct seq_file *m, void *v)
292 {
293 struct rtw89_debugfs_priv *debugfs_priv = m->private;
294 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
295 u32 addr, data, mask;
296 u8 path;
297
298 addr = debugfs_priv->read_rf.addr;
299 mask = debugfs_priv->read_rf.mask;
300 path = debugfs_priv->read_rf.path;
301
302 data = rtw89_read_rf(rtwdev, path, addr, mask);
303
304 seq_printf(m, "path %d, rf register 0x%08x=0x%08x\n", path, addr, data);
305
306 return 0;
307 }
308
rtw89_debug_priv_write_rf_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)309 static ssize_t rtw89_debug_priv_write_rf_set(struct file *filp,
310 const char __user *user_buf,
311 size_t count, loff_t *loff)
312 {
313 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
314 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
315 char buf[32];
316 size_t buf_size;
317 u32 addr, val, mask;
318 u8 path;
319 int num;
320
321 buf_size = min(count, sizeof(buf) - 1);
322 if (copy_from_user(buf, user_buf, buf_size))
323 return -EFAULT;
324
325 buf[buf_size] = '\0';
326 num = sscanf(buf, "%hhd %x %x %x", &path, &addr, &mask, &val);
327 if (num != 4) {
328 rtw89_info(rtwdev, "invalid format: <path> <addr> <mask> <val>\n");
329 return -EINVAL;
330 }
331
332 if (path >= rtwdev->chip->rf_path_num) {
333 rtw89_info(rtwdev, "wrong rf path\n");
334 return -EINVAL;
335 }
336
337 rtw89_info(rtwdev, "path %d, rf register write 0x%08x=0x%08x (mask = 0x%08x)\n",
338 path, addr, val, mask);
339 rtw89_write_rf(rtwdev, path, addr, mask, val);
340
341 return count;
342 }
343
rtw89_debug_priv_rf_reg_dump_get(struct seq_file * m,void * v)344 static int rtw89_debug_priv_rf_reg_dump_get(struct seq_file *m, void *v)
345 {
346 struct rtw89_debugfs_priv *debugfs_priv = m->private;
347 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
348 const struct rtw89_chip_info *chip = rtwdev->chip;
349 u32 addr, offset, data;
350 u8 path;
351
352 for (path = 0; path < chip->rf_path_num; path++) {
353 seq_printf(m, "RF path %d:\n\n", path);
354 for (addr = 0; addr < 0x100; addr += 4) {
355 seq_printf(m, "0x%08x: ", addr);
356 for (offset = 0; offset < 4; offset++) {
357 data = rtw89_read_rf(rtwdev, path,
358 addr + offset, RFREG_MASK);
359 seq_printf(m, "0x%05x ", data);
360 }
361 seq_puts(m, "\n");
362 }
363 seq_puts(m, "\n");
364 }
365
366 return 0;
367 }
368
369 struct txpwr_ent {
370 const char *txt;
371 u8 len;
372 };
373
374 struct txpwr_map {
375 const struct txpwr_ent *ent;
376 u8 size;
377 u32 addr_from;
378 u32 addr_to;
379 u32 addr_to_1ss;
380 };
381
382 #define __GEN_TXPWR_ENT2(_t, _e0, _e1) \
383 { .len = 2, .txt = _t "\t- " _e0 " " _e1 }
384
385 #define __GEN_TXPWR_ENT4(_t, _e0, _e1, _e2, _e3) \
386 { .len = 4, .txt = _t "\t- " _e0 " " _e1 " " _e2 " " _e3 }
387
388 #define __GEN_TXPWR_ENT8(_t, _e0, _e1, _e2, _e3, _e4, _e5, _e6, _e7) \
389 { .len = 8, .txt = _t "\t- " \
390 _e0 " " _e1 " " _e2 " " _e3 " " \
391 _e4 " " _e5 " " _e6 " " _e7 }
392
393 static const struct txpwr_ent __txpwr_ent_byr[] = {
394 __GEN_TXPWR_ENT4("CCK ", "1M ", "2M ", "5.5M ", "11M "),
395 __GEN_TXPWR_ENT4("LEGACY ", "6M ", "9M ", "12M ", "18M "),
396 __GEN_TXPWR_ENT4("LEGACY ", "24M ", "36M ", "48M ", "54M "),
397 /* 1NSS */
398 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
399 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
400 __GEN_TXPWR_ENT4("MCS_1NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
401 __GEN_TXPWR_ENT4("HEDCM_1NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
402 /* 2NSS */
403 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS0 ", "MCS1 ", "MCS2 ", "MCS3 "),
404 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS4 ", "MCS5 ", "MCS6 ", "MCS7 "),
405 __GEN_TXPWR_ENT4("MCS_2NSS ", "MCS8 ", "MCS9 ", "MCS10", "MCS11"),
406 __GEN_TXPWR_ENT4("HEDCM_2NSS", "MCS0 ", "MCS1 ", "MCS3 ", "MCS4 "),
407 };
408
409 static_assert((ARRAY_SIZE(__txpwr_ent_byr) * 4) ==
410 (R_AX_PWR_BY_RATE_MAX - R_AX_PWR_BY_RATE + 4));
411
412 static const struct txpwr_map __txpwr_map_byr = {
413 .ent = __txpwr_ent_byr,
414 .size = ARRAY_SIZE(__txpwr_ent_byr),
415 .addr_from = R_AX_PWR_BY_RATE,
416 .addr_to = R_AX_PWR_BY_RATE_MAX,
417 .addr_to_1ss = R_AX_PWR_BY_RATE_1SS_MAX,
418 };
419
420 static const struct txpwr_ent __txpwr_ent_lmt[] = {
421 /* 1TX */
422 __GEN_TXPWR_ENT2("CCK_1TX_20M ", "NON_BF", "BF"),
423 __GEN_TXPWR_ENT2("CCK_1TX_40M ", "NON_BF", "BF"),
424 __GEN_TXPWR_ENT2("OFDM_1TX ", "NON_BF", "BF"),
425 __GEN_TXPWR_ENT2("MCS_1TX_20M_0 ", "NON_BF", "BF"),
426 __GEN_TXPWR_ENT2("MCS_1TX_20M_1 ", "NON_BF", "BF"),
427 __GEN_TXPWR_ENT2("MCS_1TX_20M_2 ", "NON_BF", "BF"),
428 __GEN_TXPWR_ENT2("MCS_1TX_20M_3 ", "NON_BF", "BF"),
429 __GEN_TXPWR_ENT2("MCS_1TX_20M_4 ", "NON_BF", "BF"),
430 __GEN_TXPWR_ENT2("MCS_1TX_20M_5 ", "NON_BF", "BF"),
431 __GEN_TXPWR_ENT2("MCS_1TX_20M_6 ", "NON_BF", "BF"),
432 __GEN_TXPWR_ENT2("MCS_1TX_20M_7 ", "NON_BF", "BF"),
433 __GEN_TXPWR_ENT2("MCS_1TX_40M_0 ", "NON_BF", "BF"),
434 __GEN_TXPWR_ENT2("MCS_1TX_40M_1 ", "NON_BF", "BF"),
435 __GEN_TXPWR_ENT2("MCS_1TX_40M_2 ", "NON_BF", "BF"),
436 __GEN_TXPWR_ENT2("MCS_1TX_40M_3 ", "NON_BF", "BF"),
437 __GEN_TXPWR_ENT2("MCS_1TX_80M_0 ", "NON_BF", "BF"),
438 __GEN_TXPWR_ENT2("MCS_1TX_80M_1 ", "NON_BF", "BF"),
439 __GEN_TXPWR_ENT2("MCS_1TX_160M ", "NON_BF", "BF"),
440 __GEN_TXPWR_ENT2("MCS_1TX_40M_0p5", "NON_BF", "BF"),
441 __GEN_TXPWR_ENT2("MCS_1TX_40M_2p5", "NON_BF", "BF"),
442 /* 2TX */
443 __GEN_TXPWR_ENT2("CCK_2TX_20M ", "NON_BF", "BF"),
444 __GEN_TXPWR_ENT2("CCK_2TX_40M ", "NON_BF", "BF"),
445 __GEN_TXPWR_ENT2("OFDM_2TX ", "NON_BF", "BF"),
446 __GEN_TXPWR_ENT2("MCS_2TX_20M_0 ", "NON_BF", "BF"),
447 __GEN_TXPWR_ENT2("MCS_2TX_20M_1 ", "NON_BF", "BF"),
448 __GEN_TXPWR_ENT2("MCS_2TX_20M_2 ", "NON_BF", "BF"),
449 __GEN_TXPWR_ENT2("MCS_2TX_20M_3 ", "NON_BF", "BF"),
450 __GEN_TXPWR_ENT2("MCS_2TX_20M_4 ", "NON_BF", "BF"),
451 __GEN_TXPWR_ENT2("MCS_2TX_20M_5 ", "NON_BF", "BF"),
452 __GEN_TXPWR_ENT2("MCS_2TX_20M_6 ", "NON_BF", "BF"),
453 __GEN_TXPWR_ENT2("MCS_2TX_20M_7 ", "NON_BF", "BF"),
454 __GEN_TXPWR_ENT2("MCS_2TX_40M_0 ", "NON_BF", "BF"),
455 __GEN_TXPWR_ENT2("MCS_2TX_40M_1 ", "NON_BF", "BF"),
456 __GEN_TXPWR_ENT2("MCS_2TX_40M_2 ", "NON_BF", "BF"),
457 __GEN_TXPWR_ENT2("MCS_2TX_40M_3 ", "NON_BF", "BF"),
458 __GEN_TXPWR_ENT2("MCS_2TX_80M_0 ", "NON_BF", "BF"),
459 __GEN_TXPWR_ENT2("MCS_2TX_80M_1 ", "NON_BF", "BF"),
460 __GEN_TXPWR_ENT2("MCS_2TX_160M ", "NON_BF", "BF"),
461 __GEN_TXPWR_ENT2("MCS_2TX_40M_0p5", "NON_BF", "BF"),
462 __GEN_TXPWR_ENT2("MCS_2TX_40M_2p5", "NON_BF", "BF"),
463 };
464
465 static_assert((ARRAY_SIZE(__txpwr_ent_lmt) * 2) ==
466 (R_AX_PWR_LMT_MAX - R_AX_PWR_LMT + 4));
467
468 static const struct txpwr_map __txpwr_map_lmt = {
469 .ent = __txpwr_ent_lmt,
470 .size = ARRAY_SIZE(__txpwr_ent_lmt),
471 .addr_from = R_AX_PWR_LMT,
472 .addr_to = R_AX_PWR_LMT_MAX,
473 .addr_to_1ss = R_AX_PWR_LMT_1SS_MAX,
474 };
475
476 static const struct txpwr_ent __txpwr_ent_lmt_ru[] = {
477 /* 1TX */
478 __GEN_TXPWR_ENT8("1TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3",
479 "RU26__4", "RU26__5", "RU26__6", "RU26__7"),
480 __GEN_TXPWR_ENT8("1TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3",
481 "RU52__4", "RU52__5", "RU52__6", "RU52__7"),
482 __GEN_TXPWR_ENT8("1TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3",
483 "RU106_4", "RU106_5", "RU106_6", "RU106_7"),
484 /* 2TX */
485 __GEN_TXPWR_ENT8("2TX", "RU26__0", "RU26__1", "RU26__2", "RU26__3",
486 "RU26__4", "RU26__5", "RU26__6", "RU26__7"),
487 __GEN_TXPWR_ENT8("2TX", "RU52__0", "RU52__1", "RU52__2", "RU52__3",
488 "RU52__4", "RU52__5", "RU52__6", "RU52__7"),
489 __GEN_TXPWR_ENT8("2TX", "RU106_0", "RU106_1", "RU106_2", "RU106_3",
490 "RU106_4", "RU106_5", "RU106_6", "RU106_7"),
491 };
492
493 static_assert((ARRAY_SIZE(__txpwr_ent_lmt_ru) * 8) ==
494 (R_AX_PWR_RU_LMT_MAX - R_AX_PWR_RU_LMT + 4));
495
496 static const struct txpwr_map __txpwr_map_lmt_ru = {
497 .ent = __txpwr_ent_lmt_ru,
498 .size = ARRAY_SIZE(__txpwr_ent_lmt_ru),
499 .addr_from = R_AX_PWR_RU_LMT,
500 .addr_to = R_AX_PWR_RU_LMT_MAX,
501 .addr_to_1ss = R_AX_PWR_RU_LMT_1SS_MAX,
502 };
503
__print_txpwr_ent(struct seq_file * m,const struct txpwr_ent * ent,const s8 * buf,const u8 cur)504 static u8 __print_txpwr_ent(struct seq_file *m, const struct txpwr_ent *ent,
505 const s8 *buf, const u8 cur)
506 {
507 char *fmt;
508
509 switch (ent->len) {
510 case 2:
511 fmt = "%s\t| %3d, %3d,\tdBm\n";
512 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1]);
513 return 2;
514 case 4:
515 fmt = "%s\t| %3d, %3d, %3d, %3d,\tdBm\n";
516 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1],
517 buf[cur + 2], buf[cur + 3]);
518 return 4;
519 case 8:
520 fmt = "%s\t| %3d, %3d, %3d, %3d, %3d, %3d, %3d, %3d,\tdBm\n";
521 seq_printf(m, fmt, ent->txt, buf[cur], buf[cur + 1],
522 buf[cur + 2], buf[cur + 3], buf[cur + 4],
523 buf[cur + 5], buf[cur + 6], buf[cur + 7]);
524 return 8;
525 default:
526 return 0;
527 }
528 }
529
__print_txpwr_map(struct seq_file * m,struct rtw89_dev * rtwdev,const struct txpwr_map * map)530 static int __print_txpwr_map(struct seq_file *m, struct rtw89_dev *rtwdev,
531 const struct txpwr_map *map)
532 {
533 u8 fct = rtwdev->chip->txpwr_factor_mac;
534 u8 path_num = rtwdev->chip->rf_path_num;
535 u32 max_valid_addr;
536 u32 val, addr;
537 s8 *buf, tmp;
538 u8 cur, i;
539 int ret;
540
541 buf = vzalloc(map->addr_to - map->addr_from + 4);
542 if (!buf)
543 return -ENOMEM;
544
545 if (path_num == 1)
546 max_valid_addr = map->addr_to_1ss;
547 else
548 max_valid_addr = map->addr_to;
549
550 for (addr = map->addr_from; addr <= max_valid_addr; addr += 4) {
551 ret = rtw89_mac_txpwr_read32(rtwdev, RTW89_PHY_0, addr, &val);
552 if (ret)
553 val = MASKDWORD;
554
555 cur = addr - map->addr_from;
556 for (i = 0; i < 4; i++, val >>= 8) {
557 /* signed 7 bits, and reserved BIT(7) */
558 tmp = sign_extend32(val, 6);
559 buf[cur + i] = tmp >> fct;
560 }
561 }
562
563 for (cur = 0, i = 0; i < map->size; i++)
564 cur += __print_txpwr_ent(m, &map->ent[i], buf, cur);
565
566 vfree(buf);
567 return 0;
568 }
569
570 #define case_REGD(_regd) \
571 case RTW89_ ## _regd: \
572 seq_puts(m, #_regd "\n"); \
573 break
574
__print_regd(struct seq_file * m,struct rtw89_dev * rtwdev,const struct rtw89_chan * chan)575 static void __print_regd(struct seq_file *m, struct rtw89_dev *rtwdev,
576 const struct rtw89_chan *chan)
577 {
578 u8 band = chan->band_type;
579 u8 regd = rtw89_regd_get(rtwdev, band);
580
581 switch (regd) {
582 default:
583 seq_printf(m, "UNKNOWN: %d\n", regd);
584 break;
585 case_REGD(WW);
586 case_REGD(ETSI);
587 case_REGD(FCC);
588 case_REGD(MKK);
589 case_REGD(NA);
590 case_REGD(IC);
591 case_REGD(KCC);
592 case_REGD(NCC);
593 case_REGD(CHILE);
594 case_REGD(ACMA);
595 case_REGD(MEXICO);
596 case_REGD(UKRAINE);
597 case_REGD(CN);
598 }
599 }
600
601 #undef case_REGD
602
rtw89_debug_priv_txpwr_table_get(struct seq_file * m,void * v)603 static int rtw89_debug_priv_txpwr_table_get(struct seq_file *m, void *v)
604 {
605 struct rtw89_debugfs_priv *debugfs_priv = m->private;
606 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
607 const struct rtw89_chan *chan;
608 int ret = 0;
609
610 mutex_lock(&rtwdev->mutex);
611 rtw89_leave_ps_mode(rtwdev);
612 chan = rtw89_chan_get(rtwdev, RTW89_SUB_ENTITY_0);
613
614 seq_puts(m, "[Regulatory] ");
615 __print_regd(m, rtwdev, chan);
616
617 seq_puts(m, "[SAR]\n");
618 rtw89_print_sar(m, rtwdev, chan->freq);
619
620 seq_puts(m, "[TAS]\n");
621 rtw89_print_tas(m, rtwdev);
622
623 seq_puts(m, "\n[TX power byrate]\n");
624 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_byr);
625 if (ret)
626 goto err;
627
628 seq_puts(m, "\n[TX power limit]\n");
629 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt);
630 if (ret)
631 goto err;
632
633 seq_puts(m, "\n[TX power limit_ru]\n");
634 ret = __print_txpwr_map(m, rtwdev, &__txpwr_map_lmt_ru);
635 if (ret)
636 goto err;
637
638 err:
639 mutex_unlock(&rtwdev->mutex);
640 return ret;
641 }
642
643 static ssize_t
rtw89_debug_priv_mac_reg_dump_select(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)644 rtw89_debug_priv_mac_reg_dump_select(struct file *filp,
645 const char __user *user_buf,
646 size_t count, loff_t *loff)
647 {
648 struct seq_file *m = (struct seq_file *)filp->private_data;
649 struct rtw89_debugfs_priv *debugfs_priv = m->private;
650 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
651 const struct rtw89_chip_info *chip = rtwdev->chip;
652 char buf[32];
653 size_t buf_size;
654 int sel;
655 int ret;
656
657 buf_size = min(count, sizeof(buf) - 1);
658 if (copy_from_user(buf, user_buf, buf_size))
659 return -EFAULT;
660
661 buf[buf_size] = '\0';
662 ret = kstrtoint(buf, 0, &sel);
663 if (ret)
664 return ret;
665
666 if (sel < RTW89_DBG_SEL_MAC_00 || sel > RTW89_DBG_SEL_RFC) {
667 rtw89_info(rtwdev, "invalid args: %d\n", sel);
668 return -EINVAL;
669 }
670
671 if (sel == RTW89_DBG_SEL_MAC_30 && chip->chip_id != RTL8852C) {
672 rtw89_info(rtwdev, "sel %d is address hole on chip %d\n", sel,
673 chip->chip_id);
674 return -EINVAL;
675 }
676
677 debugfs_priv->cb_data = sel;
678 rtw89_info(rtwdev, "select mac page dump %d\n", debugfs_priv->cb_data);
679
680 return count;
681 }
682
683 #define RTW89_MAC_PAGE_SIZE 0x100
684
rtw89_debug_priv_mac_reg_dump_get(struct seq_file * m,void * v)685 static int rtw89_debug_priv_mac_reg_dump_get(struct seq_file *m, void *v)
686 {
687 struct rtw89_debugfs_priv *debugfs_priv = m->private;
688 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
689 enum rtw89_debug_mac_reg_sel reg_sel = debugfs_priv->cb_data;
690 u32 start, end;
691 u32 i, j, k, page;
692 u32 val;
693
694 switch (reg_sel) {
695 case RTW89_DBG_SEL_MAC_00:
696 seq_puts(m, "Debug selected MAC page 0x00\n");
697 start = 0x000;
698 end = 0x014;
699 break;
700 case RTW89_DBG_SEL_MAC_30:
701 seq_puts(m, "Debug selected MAC page 0x30\n");
702 start = 0x030;
703 end = 0x033;
704 break;
705 case RTW89_DBG_SEL_MAC_40:
706 seq_puts(m, "Debug selected MAC page 0x40\n");
707 start = 0x040;
708 end = 0x07f;
709 break;
710 case RTW89_DBG_SEL_MAC_80:
711 seq_puts(m, "Debug selected MAC page 0x80\n");
712 start = 0x080;
713 end = 0x09f;
714 break;
715 case RTW89_DBG_SEL_MAC_C0:
716 seq_puts(m, "Debug selected MAC page 0xc0\n");
717 start = 0x0c0;
718 end = 0x0df;
719 break;
720 case RTW89_DBG_SEL_MAC_E0:
721 seq_puts(m, "Debug selected MAC page 0xe0\n");
722 start = 0x0e0;
723 end = 0x0ff;
724 break;
725 case RTW89_DBG_SEL_BB:
726 seq_puts(m, "Debug selected BB register\n");
727 start = 0x100;
728 end = 0x17f;
729 break;
730 case RTW89_DBG_SEL_IQK:
731 seq_puts(m, "Debug selected IQK register\n");
732 start = 0x180;
733 end = 0x1bf;
734 break;
735 case RTW89_DBG_SEL_RFC:
736 seq_puts(m, "Debug selected RFC register\n");
737 start = 0x1c0;
738 end = 0x1ff;
739 break;
740 default:
741 seq_puts(m, "Selected invalid register page\n");
742 return -EINVAL;
743 }
744
745 for (i = start; i <= end; i++) {
746 page = i << 8;
747 for (j = page; j < page + RTW89_MAC_PAGE_SIZE; j += 16) {
748 seq_printf(m, "%08xh : ", 0x18600000 + j);
749 for (k = 0; k < 4; k++) {
750 val = rtw89_read32(rtwdev, j + (k << 2));
751 seq_printf(m, "%08x ", val);
752 }
753 seq_puts(m, "\n");
754 }
755 }
756
757 return 0;
758 }
759
760 static ssize_t
rtw89_debug_priv_mac_mem_dump_select(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)761 rtw89_debug_priv_mac_mem_dump_select(struct file *filp,
762 const char __user *user_buf,
763 size_t count, loff_t *loff)
764 {
765 struct seq_file *m = (struct seq_file *)filp->private_data;
766 struct rtw89_debugfs_priv *debugfs_priv = m->private;
767 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
768 char buf[32];
769 size_t buf_size;
770 u32 sel, start_addr, len;
771 int num;
772
773 buf_size = min(count, sizeof(buf) - 1);
774 if (copy_from_user(buf, user_buf, buf_size))
775 return -EFAULT;
776
777 buf[buf_size] = '\0';
778 num = sscanf(buf, "%x %x %x", &sel, &start_addr, &len);
779 if (num != 3) {
780 rtw89_info(rtwdev, "invalid format: <sel> <start> <len>\n");
781 return -EINVAL;
782 }
783
784 debugfs_priv->mac_mem.sel = sel;
785 debugfs_priv->mac_mem.start = start_addr;
786 debugfs_priv->mac_mem.len = len;
787
788 rtw89_info(rtwdev, "select mem %d start %d len %d\n",
789 sel, start_addr, len);
790
791 return count;
792 }
793
rtw89_debug_dump_mac_mem(struct seq_file * m,struct rtw89_dev * rtwdev,u8 sel,u32 start_addr,u32 len)794 static void rtw89_debug_dump_mac_mem(struct seq_file *m,
795 struct rtw89_dev *rtwdev,
796 u8 sel, u32 start_addr, u32 len)
797 {
798 const struct rtw89_mac_gen_def *mac = rtwdev->chip->mac_def;
799 u32 filter_model_addr = mac->filter_model_addr;
800 u32 indir_access_addr = mac->indir_access_addr;
801 u32 base_addr, start_page, residue;
802 u32 i, j, p, pages;
803 u32 dump_len, remain;
804 u32 val;
805
806 remain = len;
807 pages = len / MAC_MEM_DUMP_PAGE_SIZE + 1;
808 start_page = start_addr / MAC_MEM_DUMP_PAGE_SIZE;
809 residue = start_addr % MAC_MEM_DUMP_PAGE_SIZE;
810 base_addr = mac->mem_base_addrs[sel];
811 base_addr += start_page * MAC_MEM_DUMP_PAGE_SIZE;
812
813 for (p = 0; p < pages; p++) {
814 dump_len = min_t(u32, remain, MAC_MEM_DUMP_PAGE_SIZE);
815 rtw89_write32(rtwdev, filter_model_addr, base_addr);
816 for (i = indir_access_addr + residue;
817 i < indir_access_addr + dump_len;) {
818 seq_printf(m, "%08xh:", i);
819 for (j = 0;
820 j < 4 && i < indir_access_addr + dump_len;
821 j++, i += 4) {
822 val = rtw89_read32(rtwdev, i);
823 seq_printf(m, " %08x", val);
824 remain -= 4;
825 }
826 seq_puts(m, "\n");
827 }
828 base_addr += MAC_MEM_DUMP_PAGE_SIZE;
829 }
830 }
831
832 static int
rtw89_debug_priv_mac_mem_dump_get(struct seq_file * m,void * v)833 rtw89_debug_priv_mac_mem_dump_get(struct seq_file *m, void *v)
834 {
835 struct rtw89_debugfs_priv *debugfs_priv = m->private;
836 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
837 bool grant_read = false;
838
839 if (debugfs_priv->mac_mem.sel >= RTW89_MAC_MEM_NUM)
840 return -ENOENT;
841
842 if (rtwdev->chip->chip_id == RTL8852C) {
843 switch (debugfs_priv->mac_mem.sel) {
844 case RTW89_MAC_MEM_TXD_FIFO_0_V1:
845 case RTW89_MAC_MEM_TXD_FIFO_1_V1:
846 case RTW89_MAC_MEM_TXDATA_FIFO_0:
847 case RTW89_MAC_MEM_TXDATA_FIFO_1:
848 grant_read = true;
849 break;
850 default:
851 break;
852 }
853 }
854
855 mutex_lock(&rtwdev->mutex);
856 rtw89_leave_ps_mode(rtwdev);
857 if (grant_read)
858 rtw89_write32_set(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO);
859 rtw89_debug_dump_mac_mem(m, rtwdev,
860 debugfs_priv->mac_mem.sel,
861 debugfs_priv->mac_mem.start,
862 debugfs_priv->mac_mem.len);
863 if (grant_read)
864 rtw89_write32_clr(rtwdev, R_AX_TCR1, B_AX_TCR_FORCE_READ_TXDFIFO);
865 mutex_unlock(&rtwdev->mutex);
866
867 return 0;
868 }
869
870 static ssize_t
rtw89_debug_priv_mac_dbg_port_dump_select(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)871 rtw89_debug_priv_mac_dbg_port_dump_select(struct file *filp,
872 const char __user *user_buf,
873 size_t count, loff_t *loff)
874 {
875 struct seq_file *m = (struct seq_file *)filp->private_data;
876 struct rtw89_debugfs_priv *debugfs_priv = m->private;
877 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
878 char buf[32];
879 size_t buf_size;
880 int sel, set;
881 int num;
882 bool enable;
883
884 buf_size = min(count, sizeof(buf) - 1);
885 if (copy_from_user(buf, user_buf, buf_size))
886 return -EFAULT;
887
888 buf[buf_size] = '\0';
889 num = sscanf(buf, "%d %d", &sel, &set);
890 if (num != 2) {
891 rtw89_info(rtwdev, "invalid format: <sel> <set>\n");
892 return -EINVAL;
893 }
894
895 enable = set != 0;
896 switch (sel) {
897 case 0:
898 debugfs_priv->dbgpkg_en.ss_dbg = enable;
899 break;
900 case 1:
901 debugfs_priv->dbgpkg_en.dle_dbg = enable;
902 break;
903 case 2:
904 debugfs_priv->dbgpkg_en.dmac_dbg = enable;
905 break;
906 case 3:
907 debugfs_priv->dbgpkg_en.cmac_dbg = enable;
908 break;
909 case 4:
910 debugfs_priv->dbgpkg_en.dbg_port = enable;
911 break;
912 default:
913 rtw89_info(rtwdev, "invalid args: sel %d set %d\n", sel, set);
914 return -EINVAL;
915 }
916
917 rtw89_info(rtwdev, "%s debug port dump %d\n",
918 enable ? "Enable" : "Disable", sel);
919
920 return count;
921 }
922
rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev * rtwdev,struct seq_file * m)923 static int rtw89_debug_mac_dump_ss_dbg(struct rtw89_dev *rtwdev,
924 struct seq_file *m)
925 {
926 return 0;
927 }
928
rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev * rtwdev,struct seq_file * m)929 static int rtw89_debug_mac_dump_dle_dbg(struct rtw89_dev *rtwdev,
930 struct seq_file *m)
931 {
932 #define DLE_DFI_DUMP(__type, __target, __sel) \
933 ({ \
934 u32 __ctrl; \
935 u32 __reg_ctrl = R_AX_##__type##_DBG_FUN_INTF_CTL; \
936 u32 __reg_data = R_AX_##__type##_DBG_FUN_INTF_DATA; \
937 u32 __data, __val32; \
938 int __ret; \
939 \
940 __ctrl = FIELD_PREP(B_AX_##__type##_DFI_TRGSEL_MASK, \
941 DLE_DFI_TYPE_##__target) | \
942 FIELD_PREP(B_AX_##__type##_DFI_ADDR_MASK, __sel) | \
943 B_AX_WDE_DFI_ACTIVE; \
944 rtw89_write32(rtwdev, __reg_ctrl, __ctrl); \
945 __ret = read_poll_timeout(rtw89_read32, __val32, \
946 !(__val32 & B_AX_##__type##_DFI_ACTIVE), \
947 1000, 50000, false, \
948 rtwdev, __reg_ctrl); \
949 if (__ret) { \
950 rtw89_err(rtwdev, "failed to dump DLE %s %s %d\n", \
951 #__type, #__target, __sel); \
952 return __ret; \
953 } \
954 \
955 __data = rtw89_read32(rtwdev, __reg_data); \
956 __data; \
957 })
958
959 #define DLE_DFI_FREE_PAGE_DUMP(__m, __type) \
960 ({ \
961 u32 __freepg, __pubpg; \
962 u32 __freepg_head, __freepg_tail, __pubpg_num; \
963 \
964 __freepg = DLE_DFI_DUMP(__type, FREEPG, 0); \
965 __pubpg = DLE_DFI_DUMP(__type, FREEPG, 1); \
966 __freepg_head = FIELD_GET(B_AX_DLE_FREE_HEADPG, __freepg); \
967 __freepg_tail = FIELD_GET(B_AX_DLE_FREE_TAILPG, __freepg); \
968 __pubpg_num = FIELD_GET(B_AX_DLE_PUB_PGNUM, __pubpg); \
969 seq_printf(__m, "[%s] freepg head: %d\n", \
970 #__type, __freepg_head); \
971 seq_printf(__m, "[%s] freepg tail: %d\n", \
972 #__type, __freepg_tail); \
973 seq_printf(__m, "[%s] pubpg num : %d\n", \
974 #__type, __pubpg_num); \
975 })
976
977 #define case_QUOTA(__m, __type, __id) \
978 case __type##_QTAID_##__id: \
979 val32 = DLE_DFI_DUMP(__type, QUOTA, __type##_QTAID_##__id); \
980 rsv_pgnum = FIELD_GET(B_AX_DLE_RSV_PGNUM, val32); \
981 use_pgnum = FIELD_GET(B_AX_DLE_USE_PGNUM, val32); \
982 seq_printf(__m, "[%s][%s] rsv_pgnum: %d\n", \
983 #__type, #__id, rsv_pgnum); \
984 seq_printf(__m, "[%s][%s] use_pgnum: %d\n", \
985 #__type, #__id, use_pgnum); \
986 break
987 u32 quota_id;
988 u32 val32;
989 u16 rsv_pgnum, use_pgnum;
990 int ret;
991
992 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
993 if (ret) {
994 seq_puts(m, "[DLE] : DMAC not enabled\n");
995 return ret;
996 }
997
998 DLE_DFI_FREE_PAGE_DUMP(m, WDE);
999 DLE_DFI_FREE_PAGE_DUMP(m, PLE);
1000 for (quota_id = 0; quota_id <= WDE_QTAID_CPUIO; quota_id++) {
1001 switch (quota_id) {
1002 case_QUOTA(m, WDE, HOST_IF);
1003 case_QUOTA(m, WDE, WLAN_CPU);
1004 case_QUOTA(m, WDE, DATA_CPU);
1005 case_QUOTA(m, WDE, PKTIN);
1006 case_QUOTA(m, WDE, CPUIO);
1007 }
1008 }
1009 for (quota_id = 0; quota_id <= PLE_QTAID_CPUIO; quota_id++) {
1010 switch (quota_id) {
1011 case_QUOTA(m, PLE, B0_TXPL);
1012 case_QUOTA(m, PLE, B1_TXPL);
1013 case_QUOTA(m, PLE, C2H);
1014 case_QUOTA(m, PLE, H2C);
1015 case_QUOTA(m, PLE, WLAN_CPU);
1016 case_QUOTA(m, PLE, MPDU);
1017 case_QUOTA(m, PLE, CMAC0_RX);
1018 case_QUOTA(m, PLE, CMAC1_RX);
1019 case_QUOTA(m, PLE, CMAC1_BBRPT);
1020 case_QUOTA(m, PLE, WDRLS);
1021 case_QUOTA(m, PLE, CPUIO);
1022 }
1023 }
1024
1025 return 0;
1026
1027 #undef case_QUOTA
1028 #undef DLE_DFI_DUMP
1029 #undef DLE_DFI_FREE_PAGE_DUMP
1030 }
1031
rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev * rtwdev,struct seq_file * m)1032 static int rtw89_debug_mac_dump_dmac_dbg(struct rtw89_dev *rtwdev,
1033 struct seq_file *m)
1034 {
1035 const struct rtw89_chip_info *chip = rtwdev->chip;
1036 u32 dmac_err;
1037 int i, ret;
1038
1039 ret = rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL);
1040 if (ret) {
1041 seq_puts(m, "[DMAC] : DMAC not enabled\n");
1042 return ret;
1043 }
1044
1045 dmac_err = rtw89_read32(rtwdev, R_AX_DMAC_ERR_ISR);
1046 seq_printf(m, "R_AX_DMAC_ERR_ISR=0x%08x\n", dmac_err);
1047 seq_printf(m, "R_AX_DMAC_ERR_IMR=0x%08x\n",
1048 rtw89_read32(rtwdev, R_AX_DMAC_ERR_IMR));
1049
1050 if (dmac_err) {
1051 seq_printf(m, "R_AX_WDE_ERR_FLAG_CFG=0x%08x\n",
1052 rtw89_read32(rtwdev, R_AX_WDE_ERR_FLAG_CFG_NUM1));
1053 seq_printf(m, "R_AX_PLE_ERR_FLAG_CFG=0x%08x\n",
1054 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_CFG_NUM1));
1055 if (chip->chip_id == RTL8852C) {
1056 seq_printf(m, "R_AX_PLE_ERRFLAG_MSG=0x%08x\n",
1057 rtw89_read32(rtwdev, R_AX_PLE_ERRFLAG_MSG));
1058 seq_printf(m, "R_AX_WDE_ERRFLAG_MSG=0x%08x\n",
1059 rtw89_read32(rtwdev, R_AX_WDE_ERRFLAG_MSG));
1060 seq_printf(m, "R_AX_PLE_DBGERR_LOCKEN=0x%08x\n",
1061 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_LOCKEN));
1062 seq_printf(m, "R_AX_PLE_DBGERR_STS=0x%08x\n",
1063 rtw89_read32(rtwdev, R_AX_PLE_DBGERR_STS));
1064 }
1065 }
1066
1067 if (dmac_err & B_AX_WDRLS_ERR_FLAG) {
1068 seq_printf(m, "R_AX_WDRLS_ERR_IMR=0x%08x\n",
1069 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_IMR));
1070 seq_printf(m, "R_AX_WDRLS_ERR_ISR=0x%08x\n",
1071 rtw89_read32(rtwdev, R_AX_WDRLS_ERR_ISR));
1072 if (chip->chip_id == RTL8852C)
1073 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
1074 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX_V1));
1075 else
1076 seq_printf(m, "R_AX_RPQ_RXBD_IDX=0x%08x\n",
1077 rtw89_read32(rtwdev, R_AX_RPQ_RXBD_IDX));
1078 }
1079
1080 if (dmac_err & B_AX_WSEC_ERR_FLAG) {
1081 if (chip->chip_id == RTL8852C) {
1082 seq_printf(m, "R_AX_SEC_ERR_IMR=0x%08x\n",
1083 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG_IMR));
1084 seq_printf(m, "R_AX_SEC_ERR_ISR=0x%08x\n",
1085 rtw89_read32(rtwdev, R_AX_SEC_ERROR_FLAG));
1086 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n",
1087 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
1088 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n",
1089 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
1090 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
1091 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
1092 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n",
1093 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
1094 seq_printf(m, "R_AX_SEC_DEBUG1=0x%08x\n",
1095 rtw89_read32(rtwdev, R_AX_SEC_DEBUG1));
1096 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n",
1097 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
1098 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n",
1099 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
1100
1101 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
1102 B_AX_DBG_SEL0, 0x8B);
1103 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
1104 B_AX_DBG_SEL1, 0x8B);
1105 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1,
1106 B_AX_SEL_0XC0_MASK, 1);
1107 for (i = 0; i < 0x10; i++) {
1108 rtw89_write32_mask(rtwdev, R_AX_SEC_ENG_CTRL,
1109 B_AX_SEC_DBG_PORT_FIELD_MASK, i);
1110 seq_printf(m, "sel=%x,R_AX_SEC_DEBUG2=0x%08x\n",
1111 i, rtw89_read32(rtwdev, R_AX_SEC_DEBUG2));
1112 }
1113 } else {
1114 seq_printf(m, "R_AX_SEC_ERR_IMR_ISR=0x%08x\n",
1115 rtw89_read32(rtwdev, R_AX_SEC_DEBUG));
1116 seq_printf(m, "R_AX_SEC_ENG_CTRL=0x%08x\n",
1117 rtw89_read32(rtwdev, R_AX_SEC_ENG_CTRL));
1118 seq_printf(m, "R_AX_SEC_MPDU_PROC=0x%08x\n",
1119 rtw89_read32(rtwdev, R_AX_SEC_MPDU_PROC));
1120 seq_printf(m, "R_AX_SEC_CAM_ACCESS=0x%08x\n",
1121 rtw89_read32(rtwdev, R_AX_SEC_CAM_ACCESS));
1122 seq_printf(m, "R_AX_SEC_CAM_RDATA=0x%08x\n",
1123 rtw89_read32(rtwdev, R_AX_SEC_CAM_RDATA));
1124 seq_printf(m, "R_AX_SEC_CAM_WDATA=0x%08x\n",
1125 rtw89_read32(rtwdev, R_AX_SEC_CAM_WDATA));
1126 seq_printf(m, "R_AX_SEC_TX_DEBUG=0x%08x\n",
1127 rtw89_read32(rtwdev, R_AX_SEC_TX_DEBUG));
1128 seq_printf(m, "R_AX_SEC_RX_DEBUG=0x%08x\n",
1129 rtw89_read32(rtwdev, R_AX_SEC_RX_DEBUG));
1130 seq_printf(m, "R_AX_SEC_TRX_PKT_CNT=0x%08x\n",
1131 rtw89_read32(rtwdev, R_AX_SEC_TRX_PKT_CNT));
1132 seq_printf(m, "R_AX_SEC_TRX_BLK_CNT=0x%08x\n",
1133 rtw89_read32(rtwdev, R_AX_SEC_TRX_BLK_CNT));
1134 }
1135 }
1136
1137 if (dmac_err & B_AX_MPDU_ERR_FLAG) {
1138 seq_printf(m, "R_AX_MPDU_TX_ERR_IMR=0x%08x\n",
1139 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_IMR));
1140 seq_printf(m, "R_AX_MPDU_TX_ERR_ISR=0x%08x\n",
1141 rtw89_read32(rtwdev, R_AX_MPDU_TX_ERR_ISR));
1142 seq_printf(m, "R_AX_MPDU_RX_ERR_IMR=0x%08x\n",
1143 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_IMR));
1144 seq_printf(m, "R_AX_MPDU_RX_ERR_ISR=0x%08x\n",
1145 rtw89_read32(rtwdev, R_AX_MPDU_RX_ERR_ISR));
1146 }
1147
1148 if (dmac_err & B_AX_STA_SCHEDULER_ERR_FLAG) {
1149 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_IMR=0x%08x\n",
1150 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_IMR));
1151 seq_printf(m, "R_AX_STA_SCHEDULER_ERR_ISR=0x%08x\n",
1152 rtw89_read32(rtwdev, R_AX_STA_SCHEDULER_ERR_ISR));
1153 }
1154
1155 if (dmac_err & B_AX_WDE_DLE_ERR_FLAG) {
1156 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n",
1157 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
1158 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n",
1159 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
1160 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n",
1161 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
1162 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
1163 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
1164 }
1165
1166 if (dmac_err & B_AX_TXPKTCTRL_ERR_FLAG) {
1167 if (chip->chip_id == RTL8852C) {
1168 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_IMR=0x%08x\n",
1169 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_IMR));
1170 seq_printf(m, "R_AX_TXPKTCTL_B0_ERRFLAG_ISR=0x%08x\n",
1171 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B0_ERRFLAG_ISR));
1172 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_IMR=0x%08x\n",
1173 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_IMR));
1174 seq_printf(m, "R_AX_TXPKTCTL_B1_ERRFLAG_ISR=0x%08x\n",
1175 rtw89_read32(rtwdev, R_AX_TXPKTCTL_B1_ERRFLAG_ISR));
1176 } else {
1177 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR=0x%08x\n",
1178 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR));
1179 seq_printf(m, "R_AX_TXPKTCTL_ERR_IMR_ISR_B1=0x%08x\n",
1180 rtw89_read32(rtwdev, R_AX_TXPKTCTL_ERR_IMR_ISR_B1));
1181 }
1182 }
1183
1184 if (dmac_err & B_AX_PLE_DLE_ERR_FLAG) {
1185 seq_printf(m, "R_AX_WDE_ERR_IMR=0x%08x\n",
1186 rtw89_read32(rtwdev, R_AX_WDE_ERR_IMR));
1187 seq_printf(m, "R_AX_WDE_ERR_ISR=0x%08x\n",
1188 rtw89_read32(rtwdev, R_AX_WDE_ERR_ISR));
1189 seq_printf(m, "R_AX_PLE_ERR_IMR=0x%08x\n",
1190 rtw89_read32(rtwdev, R_AX_PLE_ERR_IMR));
1191 seq_printf(m, "R_AX_PLE_ERR_FLAG_ISR=0x%08x\n",
1192 rtw89_read32(rtwdev, R_AX_PLE_ERR_FLAG_ISR));
1193 seq_printf(m, "R_AX_WD_CPUQ_OP_0=0x%08x\n",
1194 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_0));
1195 seq_printf(m, "R_AX_WD_CPUQ_OP_1=0x%08x\n",
1196 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_1));
1197 seq_printf(m, "R_AX_WD_CPUQ_OP_2=0x%08x\n",
1198 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_2));
1199 seq_printf(m, "R_AX_WD_CPUQ_OP_STATUS=0x%08x\n",
1200 rtw89_read32(rtwdev, R_AX_WD_CPUQ_OP_STATUS));
1201 seq_printf(m, "R_AX_PL_CPUQ_OP_0=0x%08x\n",
1202 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_0));
1203 seq_printf(m, "R_AX_PL_CPUQ_OP_1=0x%08x\n",
1204 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_1));
1205 seq_printf(m, "R_AX_PL_CPUQ_OP_2=0x%08x\n",
1206 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_2));
1207 seq_printf(m, "R_AX_PL_CPUQ_OP_STATUS=0x%08x\n",
1208 rtw89_read32(rtwdev, R_AX_PL_CPUQ_OP_STATUS));
1209 if (chip->chip_id == RTL8852C) {
1210 seq_printf(m, "R_AX_RX_CTRL0=0x%08x\n",
1211 rtw89_read32(rtwdev, R_AX_RX_CTRL0));
1212 seq_printf(m, "R_AX_RX_CTRL1=0x%08x\n",
1213 rtw89_read32(rtwdev, R_AX_RX_CTRL1));
1214 seq_printf(m, "R_AX_RX_CTRL2=0x%08x\n",
1215 rtw89_read32(rtwdev, R_AX_RX_CTRL2));
1216 } else {
1217 seq_printf(m, "R_AX_RXDMA_PKT_INFO_0=0x%08x\n",
1218 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_0));
1219 seq_printf(m, "R_AX_RXDMA_PKT_INFO_1=0x%08x\n",
1220 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_1));
1221 seq_printf(m, "R_AX_RXDMA_PKT_INFO_2=0x%08x\n",
1222 rtw89_read32(rtwdev, R_AX_RXDMA_PKT_INFO_2));
1223 }
1224 }
1225
1226 if (dmac_err & B_AX_PKTIN_ERR_FLAG) {
1227 seq_printf(m, "R_AX_PKTIN_ERR_IMR=0x%08x\n",
1228 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_IMR));
1229 seq_printf(m, "R_AX_PKTIN_ERR_ISR=0x%08x\n",
1230 rtw89_read32(rtwdev, R_AX_PKTIN_ERR_ISR));
1231 }
1232
1233 if (dmac_err & B_AX_DISPATCH_ERR_FLAG) {
1234 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_IMR=0x%08x\n",
1235 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_IMR));
1236 seq_printf(m, "R_AX_HOST_DISPATCHER_ERR_ISR=0x%08x\n",
1237 rtw89_read32(rtwdev, R_AX_HOST_DISPATCHER_ERR_ISR));
1238 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_IMR=0x%08x\n",
1239 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_IMR));
1240 seq_printf(m, "R_AX_CPU_DISPATCHER_ERR_ISR=0x%08x\n",
1241 rtw89_read32(rtwdev, R_AX_CPU_DISPATCHER_ERR_ISR));
1242 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_IMR=0x%08x\n",
1243 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_IMR));
1244 seq_printf(m, "R_AX_OTHER_DISPATCHER_ERR_ISR=0x%08x\n",
1245 rtw89_read32(rtwdev, R_AX_OTHER_DISPATCHER_ERR_ISR));
1246 }
1247
1248 if (dmac_err & B_AX_BBRPT_ERR_FLAG) {
1249 if (chip->chip_id == RTL8852C) {
1250 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR=0x%08x\n",
1251 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR));
1252 seq_printf(m, "R_AX_BBRPT_COM_ERR_ISR=0x%08x\n",
1253 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_ISR));
1254 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
1255 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
1256 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
1257 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
1258 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
1259 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
1260 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
1261 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
1262 } else {
1263 seq_printf(m, "R_AX_BBRPT_COM_ERR_IMR_ISR=0x%08x\n",
1264 rtw89_read32(rtwdev, R_AX_BBRPT_COM_ERR_IMR_ISR));
1265 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_ISR=0x%08x\n",
1266 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_ISR));
1267 seq_printf(m, "R_AX_BBRPT_CHINFO_ERR_IMR=0x%08x\n",
1268 rtw89_read32(rtwdev, R_AX_BBRPT_CHINFO_ERR_IMR));
1269 seq_printf(m, "R_AX_BBRPT_DFS_ERR_IMR=0x%08x\n",
1270 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_IMR));
1271 seq_printf(m, "R_AX_BBRPT_DFS_ERR_ISR=0x%08x\n",
1272 rtw89_read32(rtwdev, R_AX_BBRPT_DFS_ERR_ISR));
1273 }
1274 }
1275
1276 if (dmac_err & B_AX_HAXIDMA_ERR_FLAG && chip->chip_id == RTL8852C) {
1277 seq_printf(m, "R_AX_HAXIDMA_ERR_IMR=0x%08x\n",
1278 rtw89_read32(rtwdev, R_AX_HAXI_IDCT_MSK));
1279 seq_printf(m, "R_AX_HAXIDMA_ERR_ISR=0x%08x\n",
1280 rtw89_read32(rtwdev, R_AX_HAXI_IDCT));
1281 }
1282
1283 return 0;
1284 }
1285
rtw89_debug_mac_dump_cmac_err(struct rtw89_dev * rtwdev,struct seq_file * m,enum rtw89_mac_idx band)1286 static int rtw89_debug_mac_dump_cmac_err(struct rtw89_dev *rtwdev,
1287 struct seq_file *m,
1288 enum rtw89_mac_idx band)
1289 {
1290 const struct rtw89_chip_info *chip = rtwdev->chip;
1291 u32 offset = 0;
1292 u32 cmac_err;
1293 int ret;
1294
1295 ret = rtw89_mac_check_mac_en(rtwdev, band, RTW89_CMAC_SEL);
1296 if (ret) {
1297 if (band)
1298 seq_puts(m, "[CMAC] : CMAC1 not enabled\n");
1299 else
1300 seq_puts(m, "[CMAC] : CMAC0 not enabled\n");
1301 return ret;
1302 }
1303
1304 if (band)
1305 offset = RTW89_MAC_AX_BAND_REG_OFFSET;
1306
1307 cmac_err = rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset);
1308 seq_printf(m, "R_AX_CMAC_ERR_ISR [%d]=0x%08x\n", band,
1309 rtw89_read32(rtwdev, R_AX_CMAC_ERR_ISR + offset));
1310 seq_printf(m, "R_AX_CMAC_FUNC_EN [%d]=0x%08x\n", band,
1311 rtw89_read32(rtwdev, R_AX_CMAC_FUNC_EN + offset));
1312 seq_printf(m, "R_AX_CK_EN [%d]=0x%08x\n", band,
1313 rtw89_read32(rtwdev, R_AX_CK_EN + offset));
1314
1315 if (cmac_err & B_AX_SCHEDULE_TOP_ERR_IND) {
1316 seq_printf(m, "R_AX_SCHEDULE_ERR_IMR [%d]=0x%08x\n", band,
1317 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_IMR + offset));
1318 seq_printf(m, "R_AX_SCHEDULE_ERR_ISR [%d]=0x%08x\n", band,
1319 rtw89_read32(rtwdev, R_AX_SCHEDULE_ERR_ISR + offset));
1320 }
1321
1322 if (cmac_err & B_AX_PTCL_TOP_ERR_IND) {
1323 seq_printf(m, "R_AX_PTCL_IMR0 [%d]=0x%08x\n", band,
1324 rtw89_read32(rtwdev, R_AX_PTCL_IMR0 + offset));
1325 seq_printf(m, "R_AX_PTCL_ISR0 [%d]=0x%08x\n", band,
1326 rtw89_read32(rtwdev, R_AX_PTCL_ISR0 + offset));
1327 }
1328
1329 if (cmac_err & B_AX_DMA_TOP_ERR_IND) {
1330 if (chip->chip_id == RTL8852C) {
1331 seq_printf(m, "R_AX_RX_ERR_FLAG [%d]=0x%08x\n", band,
1332 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG + offset));
1333 seq_printf(m, "R_AX_RX_ERR_FLAG_IMR [%d]=0x%08x\n", band,
1334 rtw89_read32(rtwdev, R_AX_RX_ERR_FLAG_IMR + offset));
1335 } else {
1336 seq_printf(m, "R_AX_DLE_CTRL [%d]=0x%08x\n", band,
1337 rtw89_read32(rtwdev, R_AX_DLE_CTRL + offset));
1338 }
1339 }
1340
1341 if (cmac_err & B_AX_DMA_TOP_ERR_IND || cmac_err & B_AX_WMAC_RX_ERR_IND) {
1342 if (chip->chip_id == RTL8852C) {
1343 seq_printf(m, "R_AX_PHYINFO_ERR_ISR [%d]=0x%08x\n", band,
1344 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_ISR + offset));
1345 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
1346 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
1347 } else {
1348 seq_printf(m, "R_AX_PHYINFO_ERR_IMR [%d]=0x%08x\n", band,
1349 rtw89_read32(rtwdev, R_AX_PHYINFO_ERR_IMR + offset));
1350 }
1351 }
1352
1353 if (cmac_err & B_AX_TXPWR_CTRL_ERR_IND) {
1354 seq_printf(m, "R_AX_TXPWR_IMR [%d]=0x%08x\n", band,
1355 rtw89_read32(rtwdev, R_AX_TXPWR_IMR + offset));
1356 seq_printf(m, "R_AX_TXPWR_ISR [%d]=0x%08x\n", band,
1357 rtw89_read32(rtwdev, R_AX_TXPWR_ISR + offset));
1358 }
1359
1360 if (cmac_err & B_AX_WMAC_TX_ERR_IND) {
1361 if (chip->chip_id == RTL8852C) {
1362 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA [%d]=0x%08x\n", band,
1363 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA + offset));
1364 seq_printf(m, "R_AX_TRXPTCL_ERROR_INDICA_MASK [%d]=0x%08x\n", band,
1365 rtw89_read32(rtwdev, R_AX_TRXPTCL_ERROR_INDICA_MASK + offset));
1366 } else {
1367 seq_printf(m, "R_AX_TMAC_ERR_IMR_ISR [%d]=0x%08x\n", band,
1368 rtw89_read32(rtwdev, R_AX_TMAC_ERR_IMR_ISR + offset));
1369 }
1370 seq_printf(m, "R_AX_DBGSEL_TRXPTCL [%d]=0x%08x\n", band,
1371 rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL + offset));
1372 }
1373
1374 seq_printf(m, "R_AX_CMAC_ERR_IMR [%d]=0x%08x\n", band,
1375 rtw89_read32(rtwdev, R_AX_CMAC_ERR_IMR + offset));
1376
1377 return 0;
1378 }
1379
rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev * rtwdev,struct seq_file * m)1380 static int rtw89_debug_mac_dump_cmac_dbg(struct rtw89_dev *rtwdev,
1381 struct seq_file *m)
1382 {
1383 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_0);
1384 if (rtwdev->dbcc_en)
1385 rtw89_debug_mac_dump_cmac_err(rtwdev, m, RTW89_MAC_1);
1386
1387 return 0;
1388 }
1389
1390 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c0 = {
1391 .sel_addr = R_AX_PTCL_DBG,
1392 .sel_byte = 1,
1393 .sel_msk = B_AX_PTCL_DBG_SEL_MASK,
1394 .srt = 0x00,
1395 .end = 0x3F,
1396 .rd_addr = R_AX_PTCL_DBG_INFO,
1397 .rd_byte = 4,
1398 .rd_msk = B_AX_PTCL_DBG_INFO_MASK
1399 };
1400
1401 static const struct rtw89_mac_dbg_port_info dbg_port_ptcl_c1 = {
1402 .sel_addr = R_AX_PTCL_DBG_C1,
1403 .sel_byte = 1,
1404 .sel_msk = B_AX_PTCL_DBG_SEL_MASK,
1405 .srt = 0x00,
1406 .end = 0x3F,
1407 .rd_addr = R_AX_PTCL_DBG_INFO_C1,
1408 .rd_byte = 4,
1409 .rd_msk = B_AX_PTCL_DBG_INFO_MASK
1410 };
1411
1412 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx0_5 = {
1413 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1414 .sel_byte = 2,
1415 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1416 .srt = 0x0,
1417 .end = 0xD,
1418 .rd_addr = R_AX_DBG_PORT_SEL,
1419 .rd_byte = 4,
1420 .rd_msk = B_AX_DEBUG_ST_MASK
1421 };
1422
1423 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx6 = {
1424 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1425 .sel_byte = 2,
1426 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1427 .srt = 0x0,
1428 .end = 0x5,
1429 .rd_addr = R_AX_DBG_PORT_SEL,
1430 .rd_byte = 4,
1431 .rd_msk = B_AX_DEBUG_ST_MASK
1432 };
1433
1434 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx7 = {
1435 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1436 .sel_byte = 2,
1437 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1438 .srt = 0x0,
1439 .end = 0x9,
1440 .rd_addr = R_AX_DBG_PORT_SEL,
1441 .rd_byte = 4,
1442 .rd_msk = B_AX_DEBUG_ST_MASK
1443 };
1444
1445 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx8 = {
1446 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1447 .sel_byte = 2,
1448 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1449 .srt = 0x0,
1450 .end = 0x3,
1451 .rd_addr = R_AX_DBG_PORT_SEL,
1452 .rd_byte = 4,
1453 .rd_msk = B_AX_DEBUG_ST_MASK
1454 };
1455
1456 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_tx9_C = {
1457 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1458 .sel_byte = 2,
1459 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1460 .srt = 0x0,
1461 .end = 0x1,
1462 .rd_addr = R_AX_DBG_PORT_SEL,
1463 .rd_byte = 4,
1464 .rd_msk = B_AX_DEBUG_ST_MASK
1465 };
1466
1467 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_txD = {
1468 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1469 .sel_byte = 2,
1470 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1471 .srt = 0x0,
1472 .end = 0x0,
1473 .rd_addr = R_AX_DBG_PORT_SEL,
1474 .rd_byte = 4,
1475 .rd_msk = B_AX_DEBUG_ST_MASK
1476 };
1477
1478 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx0 = {
1479 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1480 .sel_byte = 2,
1481 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1482 .srt = 0x0,
1483 .end = 0xB,
1484 .rd_addr = R_AX_DBG_PORT_SEL,
1485 .rd_byte = 4,
1486 .rd_msk = B_AX_DEBUG_ST_MASK
1487 };
1488
1489 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx1 = {
1490 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1491 .sel_byte = 2,
1492 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1493 .srt = 0x0,
1494 .end = 0x4,
1495 .rd_addr = R_AX_DBG_PORT_SEL,
1496 .rd_byte = 4,
1497 .rd_msk = B_AX_DEBUG_ST_MASK
1498 };
1499
1500 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx3 = {
1501 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1502 .sel_byte = 2,
1503 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1504 .srt = 0x0,
1505 .end = 0x8,
1506 .rd_addr = R_AX_DBG_PORT_SEL,
1507 .rd_byte = 4,
1508 .rd_msk = B_AX_DEBUG_ST_MASK
1509 };
1510
1511 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx4 = {
1512 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1513 .sel_byte = 2,
1514 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1515 .srt = 0x0,
1516 .end = 0x7,
1517 .rd_addr = R_AX_DBG_PORT_SEL,
1518 .rd_byte = 4,
1519 .rd_msk = B_AX_DEBUG_ST_MASK
1520 };
1521
1522 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx5_8 = {
1523 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1524 .sel_byte = 2,
1525 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1526 .srt = 0x0,
1527 .end = 0x1,
1528 .rd_addr = R_AX_DBG_PORT_SEL,
1529 .rd_byte = 4,
1530 .rd_msk = B_AX_DEBUG_ST_MASK
1531 };
1532
1533 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_tx9 = {
1534 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1535 .sel_byte = 2,
1536 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1537 .srt = 0x0,
1538 .end = 0x3,
1539 .rd_addr = R_AX_DBG_PORT_SEL,
1540 .rd_byte = 4,
1541 .rd_msk = B_AX_DEBUG_ST_MASK
1542 };
1543
1544 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_txA_C = {
1545 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1546 .sel_byte = 2,
1547 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1548 .srt = 0x0,
1549 .end = 0x0,
1550 .rd_addr = R_AX_DBG_PORT_SEL,
1551 .rd_byte = 4,
1552 .rd_msk = B_AX_DEBUG_ST_MASK
1553 };
1554
1555 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx0 = {
1556 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1557 .sel_byte = 2,
1558 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1559 .srt = 0x0,
1560 .end = 0x8,
1561 .rd_addr = R_AX_DBG_PORT_SEL,
1562 .rd_byte = 4,
1563 .rd_msk = B_AX_DEBUG_ST_MASK
1564 };
1565
1566 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx1_2 = {
1567 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1568 .sel_byte = 2,
1569 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1570 .srt = 0x0,
1571 .end = 0x0,
1572 .rd_addr = R_AX_DBG_PORT_SEL,
1573 .rd_byte = 4,
1574 .rd_msk = B_AX_DEBUG_ST_MASK
1575 };
1576
1577 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx3 = {
1578 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1579 .sel_byte = 2,
1580 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1581 .srt = 0x0,
1582 .end = 0x6,
1583 .rd_addr = R_AX_DBG_PORT_SEL,
1584 .rd_byte = 4,
1585 .rd_msk = B_AX_DEBUG_ST_MASK
1586 };
1587
1588 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx4 = {
1589 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1590 .sel_byte = 2,
1591 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1592 .srt = 0x0,
1593 .end = 0x0,
1594 .rd_addr = R_AX_DBG_PORT_SEL,
1595 .rd_byte = 4,
1596 .rd_msk = B_AX_DEBUG_ST_MASK
1597 };
1598
1599 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_hdt_rx5 = {
1600 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1601 .sel_byte = 2,
1602 .sel_msk = B_AX_DISPATCHER_DBG_SEL_MASK,
1603 .srt = 0x0,
1604 .end = 0x0,
1605 .rd_addr = R_AX_DBG_PORT_SEL,
1606 .rd_byte = 4,
1607 .rd_msk = B_AX_DEBUG_ST_MASK
1608 };
1609
1610 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_0 = {
1611 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1612 .sel_byte = 1,
1613 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
1614 .srt = 0x0,
1615 .end = 0x3,
1616 .rd_addr = R_AX_DBG_PORT_SEL,
1617 .rd_byte = 4,
1618 .rd_msk = B_AX_DEBUG_ST_MASK
1619 };
1620
1621 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_1 = {
1622 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1623 .sel_byte = 1,
1624 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
1625 .srt = 0x0,
1626 .end = 0x6,
1627 .rd_addr = R_AX_DBG_PORT_SEL,
1628 .rd_byte = 4,
1629 .rd_msk = B_AX_DEBUG_ST_MASK
1630 };
1631
1632 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p0_2 = {
1633 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1634 .sel_byte = 1,
1635 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
1636 .srt = 0x0,
1637 .end = 0x0,
1638 .rd_addr = R_AX_DBG_PORT_SEL,
1639 .rd_byte = 4,
1640 .rd_msk = B_AX_DEBUG_ST_MASK
1641 };
1642
1643 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_cdt_rx_p1 = {
1644 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1645 .sel_byte = 1,
1646 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
1647 .srt = 0x8,
1648 .end = 0xE,
1649 .rd_addr = R_AX_DBG_PORT_SEL,
1650 .rd_byte = 4,
1651 .rd_msk = B_AX_DEBUG_ST_MASK
1652 };
1653
1654 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_stf_ctrl = {
1655 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1656 .sel_byte = 1,
1657 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
1658 .srt = 0x0,
1659 .end = 0x5,
1660 .rd_addr = R_AX_DBG_PORT_SEL,
1661 .rd_byte = 4,
1662 .rd_msk = B_AX_DEBUG_ST_MASK
1663 };
1664
1665 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_addr_ctrl = {
1666 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1667 .sel_byte = 1,
1668 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
1669 .srt = 0x0,
1670 .end = 0x6,
1671 .rd_addr = R_AX_DBG_PORT_SEL,
1672 .rd_byte = 4,
1673 .rd_msk = B_AX_DEBUG_ST_MASK
1674 };
1675
1676 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_wde_intf = {
1677 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1678 .sel_byte = 1,
1679 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
1680 .srt = 0x0,
1681 .end = 0xF,
1682 .rd_addr = R_AX_DBG_PORT_SEL,
1683 .rd_byte = 4,
1684 .rd_msk = B_AX_DEBUG_ST_MASK
1685 };
1686
1687 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_ple_intf = {
1688 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1689 .sel_byte = 1,
1690 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
1691 .srt = 0x0,
1692 .end = 0x9,
1693 .rd_addr = R_AX_DBG_PORT_SEL,
1694 .rd_byte = 4,
1695 .rd_msk = B_AX_DEBUG_ST_MASK
1696 };
1697
1698 static const struct rtw89_mac_dbg_port_info dbg_port_dspt_flow_ctrl = {
1699 .sel_addr = R_AX_DISPATCHER_DBG_PORT,
1700 .sel_byte = 1,
1701 .sel_msk = B_AX_DISPATCHER_CH_SEL_MASK,
1702 .srt = 0x0,
1703 .end = 0x3,
1704 .rd_addr = R_AX_DBG_PORT_SEL,
1705 .rd_byte = 4,
1706 .rd_msk = B_AX_DEBUG_ST_MASK
1707 };
1708
1709 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c0 = {
1710 .sel_addr = R_AX_SCH_DBG_SEL,
1711 .sel_byte = 1,
1712 .sel_msk = B_AX_SCH_DBG_SEL_MASK,
1713 .srt = 0x00,
1714 .end = 0x2F,
1715 .rd_addr = R_AX_SCH_DBG,
1716 .rd_byte = 4,
1717 .rd_msk = B_AX_SCHEDULER_DBG_MASK
1718 };
1719
1720 static const struct rtw89_mac_dbg_port_info dbg_port_sch_c1 = {
1721 .sel_addr = R_AX_SCH_DBG_SEL_C1,
1722 .sel_byte = 1,
1723 .sel_msk = B_AX_SCH_DBG_SEL_MASK,
1724 .srt = 0x00,
1725 .end = 0x2F,
1726 .rd_addr = R_AX_SCH_DBG_C1,
1727 .rd_byte = 4,
1728 .rd_msk = B_AX_SCHEDULER_DBG_MASK
1729 };
1730
1731 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c0 = {
1732 .sel_addr = R_AX_MACTX_DBG_SEL_CNT,
1733 .sel_byte = 1,
1734 .sel_msk = B_AX_DBGSEL_MACTX_MASK,
1735 .srt = 0x00,
1736 .end = 0x19,
1737 .rd_addr = R_AX_DBG_PORT_SEL,
1738 .rd_byte = 4,
1739 .rd_msk = B_AX_DEBUG_ST_MASK
1740 };
1741
1742 static const struct rtw89_mac_dbg_port_info dbg_port_tmac_c1 = {
1743 .sel_addr = R_AX_MACTX_DBG_SEL_CNT_C1,
1744 .sel_byte = 1,
1745 .sel_msk = B_AX_DBGSEL_MACTX_MASK,
1746 .srt = 0x00,
1747 .end = 0x19,
1748 .rd_addr = R_AX_DBG_PORT_SEL,
1749 .rd_byte = 4,
1750 .rd_msk = B_AX_DEBUG_ST_MASK
1751 };
1752
1753 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c0 = {
1754 .sel_addr = R_AX_RX_DEBUG_SELECT,
1755 .sel_byte = 1,
1756 .sel_msk = B_AX_DEBUG_SEL_MASK,
1757 .srt = 0x00,
1758 .end = 0x58,
1759 .rd_addr = R_AX_DBG_PORT_SEL,
1760 .rd_byte = 4,
1761 .rd_msk = B_AX_DEBUG_ST_MASK
1762 };
1763
1764 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_c1 = {
1765 .sel_addr = R_AX_RX_DEBUG_SELECT_C1,
1766 .sel_byte = 1,
1767 .sel_msk = B_AX_DEBUG_SEL_MASK,
1768 .srt = 0x00,
1769 .end = 0x58,
1770 .rd_addr = R_AX_DBG_PORT_SEL,
1771 .rd_byte = 4,
1772 .rd_msk = B_AX_DEBUG_ST_MASK
1773 };
1774
1775 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c0 = {
1776 .sel_addr = R_AX_RX_STATE_MONITOR,
1777 .sel_byte = 1,
1778 .sel_msk = B_AX_STATE_SEL_MASK,
1779 .srt = 0x00,
1780 .end = 0x17,
1781 .rd_addr = R_AX_RX_STATE_MONITOR,
1782 .rd_byte = 4,
1783 .rd_msk = B_AX_RX_STATE_MONITOR_MASK
1784 };
1785
1786 static const struct rtw89_mac_dbg_port_info dbg_port_rmacst_c1 = {
1787 .sel_addr = R_AX_RX_STATE_MONITOR_C1,
1788 .sel_byte = 1,
1789 .sel_msk = B_AX_STATE_SEL_MASK,
1790 .srt = 0x00,
1791 .end = 0x17,
1792 .rd_addr = R_AX_RX_STATE_MONITOR_C1,
1793 .rd_byte = 4,
1794 .rd_msk = B_AX_RX_STATE_MONITOR_MASK
1795 };
1796
1797 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c0 = {
1798 .sel_addr = R_AX_RMAC_PLCP_MON,
1799 .sel_byte = 4,
1800 .sel_msk = B_AX_PCLP_MON_SEL_MASK,
1801 .srt = 0x0,
1802 .end = 0xF,
1803 .rd_addr = R_AX_RMAC_PLCP_MON,
1804 .rd_byte = 4,
1805 .rd_msk = B_AX_RMAC_PLCP_MON_MASK
1806 };
1807
1808 static const struct rtw89_mac_dbg_port_info dbg_port_rmac_plcp_c1 = {
1809 .sel_addr = R_AX_RMAC_PLCP_MON_C1,
1810 .sel_byte = 4,
1811 .sel_msk = B_AX_PCLP_MON_SEL_MASK,
1812 .srt = 0x0,
1813 .end = 0xF,
1814 .rd_addr = R_AX_RMAC_PLCP_MON_C1,
1815 .rd_byte = 4,
1816 .rd_msk = B_AX_RMAC_PLCP_MON_MASK
1817 };
1818
1819 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c0 = {
1820 .sel_addr = R_AX_DBGSEL_TRXPTCL,
1821 .sel_byte = 1,
1822 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK,
1823 .srt = 0x08,
1824 .end = 0x10,
1825 .rd_addr = R_AX_DBG_PORT_SEL,
1826 .rd_byte = 4,
1827 .rd_msk = B_AX_DEBUG_ST_MASK
1828 };
1829
1830 static const struct rtw89_mac_dbg_port_info dbg_port_trxptcl_c1 = {
1831 .sel_addr = R_AX_DBGSEL_TRXPTCL_C1,
1832 .sel_byte = 1,
1833 .sel_msk = B_AX_DBGSEL_TRXPTCL_MASK,
1834 .srt = 0x08,
1835 .end = 0x10,
1836 .rd_addr = R_AX_DBG_PORT_SEL,
1837 .rd_byte = 4,
1838 .rd_msk = B_AX_DEBUG_ST_MASK
1839 };
1840
1841 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c0 = {
1842 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG,
1843 .sel_byte = 1,
1844 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
1845 .srt = 0x00,
1846 .end = 0x07,
1847 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG,
1848 .rd_byte = 4,
1849 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK
1850 };
1851
1852 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c0 = {
1853 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG,
1854 .sel_byte = 1,
1855 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
1856 .srt = 0x00,
1857 .end = 0x07,
1858 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG,
1859 .rd_byte = 4,
1860 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK
1861 };
1862
1863 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infol_c1 = {
1864 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1,
1865 .sel_byte = 1,
1866 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
1867 .srt = 0x00,
1868 .end = 0x07,
1869 .rd_addr = R_AX_WMAC_TX_INFO0_DEBUG_C1,
1870 .rd_byte = 4,
1871 .rd_msk = B_AX_TX_CTRL_INFO_P0_MASK
1872 };
1873
1874 static const struct rtw89_mac_dbg_port_info dbg_port_tx_infoh_c1 = {
1875 .sel_addr = R_AX_WMAC_TX_CTRL_DEBUG_C1,
1876 .sel_byte = 1,
1877 .sel_msk = B_AX_TX_CTRL_DEBUG_SEL_MASK,
1878 .srt = 0x00,
1879 .end = 0x07,
1880 .rd_addr = R_AX_WMAC_TX_INFO1_DEBUG_C1,
1881 .rd_byte = 4,
1882 .rd_msk = B_AX_TX_CTRL_INFO_P1_MASK
1883 };
1884
1885 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c0 = {
1886 .sel_addr = R_AX_WMAC_TX_TF_INFO_0,
1887 .sel_byte = 1,
1888 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
1889 .srt = 0x00,
1890 .end = 0x04,
1891 .rd_addr = R_AX_WMAC_TX_TF_INFO_1,
1892 .rd_byte = 4,
1893 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK
1894 };
1895
1896 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c0 = {
1897 .sel_addr = R_AX_WMAC_TX_TF_INFO_0,
1898 .sel_byte = 1,
1899 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
1900 .srt = 0x00,
1901 .end = 0x04,
1902 .rd_addr = R_AX_WMAC_TX_TF_INFO_2,
1903 .rd_byte = 4,
1904 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK
1905 };
1906
1907 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infol_c1 = {
1908 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1,
1909 .sel_byte = 1,
1910 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
1911 .srt = 0x00,
1912 .end = 0x04,
1913 .rd_addr = R_AX_WMAC_TX_TF_INFO_1_C1,
1914 .rd_byte = 4,
1915 .rd_msk = B_AX_WMAC_TX_TF_INFO_P0_MASK
1916 };
1917
1918 static const struct rtw89_mac_dbg_port_info dbg_port_txtf_infoh_c1 = {
1919 .sel_addr = R_AX_WMAC_TX_TF_INFO_0_C1,
1920 .sel_byte = 1,
1921 .sel_msk = B_AX_WMAC_TX_TF_INFO_SEL_MASK,
1922 .srt = 0x00,
1923 .end = 0x04,
1924 .rd_addr = R_AX_WMAC_TX_TF_INFO_2_C1,
1925 .rd_byte = 4,
1926 .rd_msk = B_AX_WMAC_TX_TF_INFO_P1_MASK
1927 };
1928
1929 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_freepg = {
1930 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1931 .sel_byte = 4,
1932 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1933 .srt = 0x80000000,
1934 .end = 0x80000001,
1935 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1936 .rd_byte = 4,
1937 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1938 };
1939
1940 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_quota = {
1941 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1942 .sel_byte = 4,
1943 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1944 .srt = 0x80010000,
1945 .end = 0x80010004,
1946 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1947 .rd_byte = 4,
1948 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1949 };
1950
1951 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pagellt = {
1952 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1953 .sel_byte = 4,
1954 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1955 .srt = 0x80020000,
1956 .end = 0x80020FFF,
1957 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1958 .rd_byte = 4,
1959 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1960 };
1961
1962 static const struct rtw89_mac_dbg_port_info dbg_port_wde_bufmgn_pktinfo = {
1963 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1964 .sel_byte = 4,
1965 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1966 .srt = 0x80030000,
1967 .end = 0x80030FFF,
1968 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1969 .rd_byte = 4,
1970 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1971 };
1972
1973 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_prepkt = {
1974 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1975 .sel_byte = 4,
1976 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1977 .srt = 0x80040000,
1978 .end = 0x80040FFF,
1979 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1980 .rd_byte = 4,
1981 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1982 };
1983
1984 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_nxtpkt = {
1985 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1986 .sel_byte = 4,
1987 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1988 .srt = 0x80050000,
1989 .end = 0x80050FFF,
1990 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
1991 .rd_byte = 4,
1992 .rd_msk = B_AX_WDE_DFI_DATA_MASK
1993 };
1994
1995 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qlnktbl = {
1996 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
1997 .sel_byte = 4,
1998 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
1999 .srt = 0x80060000,
2000 .end = 0x80060453,
2001 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
2002 .rd_byte = 4,
2003 .rd_msk = B_AX_WDE_DFI_DATA_MASK
2004 };
2005
2006 static const struct rtw89_mac_dbg_port_info dbg_port_wde_quemgn_qempty = {
2007 .sel_addr = R_AX_WDE_DBG_FUN_INTF_CTL,
2008 .sel_byte = 4,
2009 .sel_msk = B_AX_WDE_DFI_DATA_MASK,
2010 .srt = 0x80070000,
2011 .end = 0x80070011,
2012 .rd_addr = R_AX_WDE_DBG_FUN_INTF_DATA,
2013 .rd_byte = 4,
2014 .rd_msk = B_AX_WDE_DFI_DATA_MASK
2015 };
2016
2017 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_freepg = {
2018 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2019 .sel_byte = 4,
2020 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2021 .srt = 0x80000000,
2022 .end = 0x80000001,
2023 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2024 .rd_byte = 4,
2025 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2026 };
2027
2028 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_quota = {
2029 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2030 .sel_byte = 4,
2031 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2032 .srt = 0x80010000,
2033 .end = 0x8001000A,
2034 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2035 .rd_byte = 4,
2036 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2037 };
2038
2039 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pagellt = {
2040 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2041 .sel_byte = 4,
2042 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2043 .srt = 0x80020000,
2044 .end = 0x80020DBF,
2045 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2046 .rd_byte = 4,
2047 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2048 };
2049
2050 static const struct rtw89_mac_dbg_port_info dbg_port_ple_bufmgn_pktinfo = {
2051 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2052 .sel_byte = 4,
2053 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2054 .srt = 0x80030000,
2055 .end = 0x80030DBF,
2056 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2057 .rd_byte = 4,
2058 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2059 };
2060
2061 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_prepkt = {
2062 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2063 .sel_byte = 4,
2064 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2065 .srt = 0x80040000,
2066 .end = 0x80040DBF,
2067 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2068 .rd_byte = 4,
2069 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2070 };
2071
2072 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_nxtpkt = {
2073 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2074 .sel_byte = 4,
2075 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2076 .srt = 0x80050000,
2077 .end = 0x80050DBF,
2078 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2079 .rd_byte = 4,
2080 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2081 };
2082
2083 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qlnktbl = {
2084 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2085 .sel_byte = 4,
2086 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2087 .srt = 0x80060000,
2088 .end = 0x80060041,
2089 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2090 .rd_byte = 4,
2091 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2092 };
2093
2094 static const struct rtw89_mac_dbg_port_info dbg_port_ple_quemgn_qempty = {
2095 .sel_addr = R_AX_PLE_DBG_FUN_INTF_CTL,
2096 .sel_byte = 4,
2097 .sel_msk = B_AX_PLE_DFI_DATA_MASK,
2098 .srt = 0x80070000,
2099 .end = 0x80070001,
2100 .rd_addr = R_AX_PLE_DBG_FUN_INTF_DATA,
2101 .rd_byte = 4,
2102 .rd_msk = B_AX_PLE_DFI_DATA_MASK
2103 };
2104
2105 static const struct rtw89_mac_dbg_port_info dbg_port_pktinfo = {
2106 .sel_addr = R_AX_DBG_FUN_INTF_CTL,
2107 .sel_byte = 4,
2108 .sel_msk = B_AX_DFI_DATA_MASK,
2109 .srt = 0x80000000,
2110 .end = 0x8000017f,
2111 .rd_addr = R_AX_DBG_FUN_INTF_DATA,
2112 .rd_byte = 4,
2113 .rd_msk = B_AX_DFI_DATA_MASK
2114 };
2115
2116 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_txdma = {
2117 .sel_addr = R_AX_PCIE_DBG_CTRL,
2118 .sel_byte = 2,
2119 .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
2120 .srt = 0x00,
2121 .end = 0x03,
2122 .rd_addr = R_AX_DBG_PORT_SEL,
2123 .rd_byte = 4,
2124 .rd_msk = B_AX_DEBUG_ST_MASK
2125 };
2126
2127 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_rxdma = {
2128 .sel_addr = R_AX_PCIE_DBG_CTRL,
2129 .sel_byte = 2,
2130 .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
2131 .srt = 0x00,
2132 .end = 0x04,
2133 .rd_addr = R_AX_DBG_PORT_SEL,
2134 .rd_byte = 4,
2135 .rd_msk = B_AX_DEBUG_ST_MASK
2136 };
2137
2138 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cvt = {
2139 .sel_addr = R_AX_PCIE_DBG_CTRL,
2140 .sel_byte = 2,
2141 .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
2142 .srt = 0x00,
2143 .end = 0x01,
2144 .rd_addr = R_AX_DBG_PORT_SEL,
2145 .rd_byte = 4,
2146 .rd_msk = B_AX_DEBUG_ST_MASK
2147 };
2148
2149 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_cxpl = {
2150 .sel_addr = R_AX_PCIE_DBG_CTRL,
2151 .sel_byte = 2,
2152 .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
2153 .srt = 0x00,
2154 .end = 0x05,
2155 .rd_addr = R_AX_DBG_PORT_SEL,
2156 .rd_byte = 4,
2157 .rd_msk = B_AX_DEBUG_ST_MASK
2158 };
2159
2160 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_io = {
2161 .sel_addr = R_AX_PCIE_DBG_CTRL,
2162 .sel_byte = 2,
2163 .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
2164 .srt = 0x00,
2165 .end = 0x05,
2166 .rd_addr = R_AX_DBG_PORT_SEL,
2167 .rd_byte = 4,
2168 .rd_msk = B_AX_DEBUG_ST_MASK
2169 };
2170
2171 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc = {
2172 .sel_addr = R_AX_PCIE_DBG_CTRL,
2173 .sel_byte = 2,
2174 .sel_msk = B_AX_PCIE_DBG_SEL_MASK,
2175 .srt = 0x00,
2176 .end = 0x06,
2177 .rd_addr = R_AX_DBG_PORT_SEL,
2178 .rd_byte = 4,
2179 .rd_msk = B_AX_DEBUG_ST_MASK
2180 };
2181
2182 static const struct rtw89_mac_dbg_port_info dbg_port_pcie_misc2 = {
2183 .sel_addr = R_AX_DBG_CTRL,
2184 .sel_byte = 1,
2185 .sel_msk = B_AX_DBG_SEL0,
2186 .srt = 0x34,
2187 .end = 0x3C,
2188 .rd_addr = R_AX_DBG_PORT_SEL,
2189 .rd_byte = 4,
2190 .rd_msk = B_AX_DEBUG_ST_MASK
2191 };
2192
2193 static const struct rtw89_mac_dbg_port_info *
rtw89_debug_mac_dbg_port_sel(struct seq_file * m,struct rtw89_dev * rtwdev,u32 sel)2194 rtw89_debug_mac_dbg_port_sel(struct seq_file *m,
2195 struct rtw89_dev *rtwdev, u32 sel)
2196 {
2197 const struct rtw89_mac_dbg_port_info *info;
2198 u32 index;
2199 u32 val32;
2200 u16 val16;
2201 u8 val8;
2202
2203 switch (sel) {
2204 case RTW89_DBG_PORT_SEL_PTCL_C0:
2205 info = &dbg_port_ptcl_c0;
2206 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG);
2207 val16 |= B_AX_PTCL_DBG_EN;
2208 rtw89_write16(rtwdev, R_AX_PTCL_DBG, val16);
2209 seq_puts(m, "Enable PTCL C0 dbgport.\n");
2210 break;
2211 case RTW89_DBG_PORT_SEL_PTCL_C1:
2212 info = &dbg_port_ptcl_c1;
2213 val16 = rtw89_read16(rtwdev, R_AX_PTCL_DBG_C1);
2214 val16 |= B_AX_PTCL_DBG_EN;
2215 rtw89_write16(rtwdev, R_AX_PTCL_DBG_C1, val16);
2216 seq_puts(m, "Enable PTCL C1 dbgport.\n");
2217 break;
2218 case RTW89_DBG_PORT_SEL_SCH_C0:
2219 info = &dbg_port_sch_c0;
2220 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL);
2221 val32 |= B_AX_SCH_DBG_EN;
2222 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL, val32);
2223 seq_puts(m, "Enable SCH C0 dbgport.\n");
2224 break;
2225 case RTW89_DBG_PORT_SEL_SCH_C1:
2226 info = &dbg_port_sch_c1;
2227 val32 = rtw89_read32(rtwdev, R_AX_SCH_DBG_SEL_C1);
2228 val32 |= B_AX_SCH_DBG_EN;
2229 rtw89_write32(rtwdev, R_AX_SCH_DBG_SEL_C1, val32);
2230 seq_puts(m, "Enable SCH C1 dbgport.\n");
2231 break;
2232 case RTW89_DBG_PORT_SEL_TMAC_C0:
2233 info = &dbg_port_tmac_c0;
2234 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL);
2235 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC,
2236 B_AX_DBGSEL_TRXPTCL_MASK);
2237 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32);
2238
2239 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2240 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL0);
2241 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C0, B_AX_DBG_SEL1);
2242 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2243
2244 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
2245 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
2246 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
2247 seq_puts(m, "Enable TMAC C0 dbgport.\n");
2248 break;
2249 case RTW89_DBG_PORT_SEL_TMAC_C1:
2250 info = &dbg_port_tmac_c1;
2251 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1);
2252 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_TMAC,
2253 B_AX_DBGSEL_TRXPTCL_MASK);
2254 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32);
2255
2256 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2257 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL0);
2258 val32 = u32_replace_bits(val32, TMAC_DBG_SEL_C1, B_AX_DBG_SEL1);
2259 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2260
2261 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
2262 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
2263 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
2264 seq_puts(m, "Enable TMAC C1 dbgport.\n");
2265 break;
2266 case RTW89_DBG_PORT_SEL_RMAC_C0:
2267 info = &dbg_port_rmac_c0;
2268 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL);
2269 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC,
2270 B_AX_DBGSEL_TRXPTCL_MASK);
2271 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL, val32);
2272
2273 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2274 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL0);
2275 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C0, B_AX_DBG_SEL1);
2276 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2277
2278 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
2279 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
2280 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
2281
2282 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL);
2283 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL,
2284 B_AX_DBGSEL_TRXPTCL_MASK);
2285 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL, val8);
2286 seq_puts(m, "Enable RMAC C0 dbgport.\n");
2287 break;
2288 case RTW89_DBG_PORT_SEL_RMAC_C1:
2289 info = &dbg_port_rmac_c1;
2290 val32 = rtw89_read32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1);
2291 val32 = u32_replace_bits(val32, TRXPTRL_DBG_SEL_RMAC,
2292 B_AX_DBGSEL_TRXPTCL_MASK);
2293 rtw89_write32(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val32);
2294
2295 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2296 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL0);
2297 val32 = u32_replace_bits(val32, RMAC_DBG_SEL_C1, B_AX_DBG_SEL1);
2298 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2299
2300 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
2301 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
2302 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
2303
2304 val8 = rtw89_read8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1);
2305 val8 = u8_replace_bits(val8, RMAC_CMAC_DBG_SEL,
2306 B_AX_DBGSEL_TRXPTCL_MASK);
2307 rtw89_write8(rtwdev, R_AX_DBGSEL_TRXPTCL_C1, val8);
2308 seq_puts(m, "Enable RMAC C1 dbgport.\n");
2309 break;
2310 case RTW89_DBG_PORT_SEL_RMACST_C0:
2311 info = &dbg_port_rmacst_c0;
2312 seq_puts(m, "Enable RMAC state C0 dbgport.\n");
2313 break;
2314 case RTW89_DBG_PORT_SEL_RMACST_C1:
2315 info = &dbg_port_rmacst_c1;
2316 seq_puts(m, "Enable RMAC state C1 dbgport.\n");
2317 break;
2318 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C0:
2319 info = &dbg_port_rmac_plcp_c0;
2320 seq_puts(m, "Enable RMAC PLCP C0 dbgport.\n");
2321 break;
2322 case RTW89_DBG_PORT_SEL_RMAC_PLCP_C1:
2323 info = &dbg_port_rmac_plcp_c1;
2324 seq_puts(m, "Enable RMAC PLCP C1 dbgport.\n");
2325 break;
2326 case RTW89_DBG_PORT_SEL_TRXPTCL_C0:
2327 info = &dbg_port_trxptcl_c0;
2328 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2329 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL0);
2330 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C0, B_AX_DBG_SEL1);
2331 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2332
2333 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
2334 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
2335 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
2336 seq_puts(m, "Enable TRXPTCL C0 dbgport.\n");
2337 break;
2338 case RTW89_DBG_PORT_SEL_TRXPTCL_C1:
2339 info = &dbg_port_trxptcl_c1;
2340 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2341 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL0);
2342 val32 = u32_replace_bits(val32, TRXPTCL_DBG_SEL_C1, B_AX_DBG_SEL1);
2343 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2344
2345 val32 = rtw89_read32(rtwdev, R_AX_SYS_STATUS1);
2346 val32 = u32_replace_bits(val32, MAC_DBG_SEL, B_AX_SEL_0XC0_MASK);
2347 rtw89_write32(rtwdev, R_AX_SYS_STATUS1, val32);
2348 seq_puts(m, "Enable TRXPTCL C1 dbgport.\n");
2349 break;
2350 case RTW89_DBG_PORT_SEL_TX_INFOL_C0:
2351 info = &dbg_port_tx_infol_c0;
2352 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
2353 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2354 rtw89_write32(rtwdev, R_AX_TCR1, val32);
2355 seq_puts(m, "Enable tx infol dump.\n");
2356 break;
2357 case RTW89_DBG_PORT_SEL_TX_INFOH_C0:
2358 info = &dbg_port_tx_infoh_c0;
2359 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
2360 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2361 rtw89_write32(rtwdev, R_AX_TCR1, val32);
2362 seq_puts(m, "Enable tx infoh dump.\n");
2363 break;
2364 case RTW89_DBG_PORT_SEL_TX_INFOL_C1:
2365 info = &dbg_port_tx_infol_c1;
2366 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
2367 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2368 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
2369 seq_puts(m, "Enable tx infol dump.\n");
2370 break;
2371 case RTW89_DBG_PORT_SEL_TX_INFOH_C1:
2372 info = &dbg_port_tx_infoh_c1;
2373 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
2374 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2375 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
2376 seq_puts(m, "Enable tx infoh dump.\n");
2377 break;
2378 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C0:
2379 info = &dbg_port_txtf_infol_c0;
2380 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
2381 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2382 rtw89_write32(rtwdev, R_AX_TCR1, val32);
2383 seq_puts(m, "Enable tx tf infol dump.\n");
2384 break;
2385 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C0:
2386 info = &dbg_port_txtf_infoh_c0;
2387 val32 = rtw89_read32(rtwdev, R_AX_TCR1);
2388 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2389 rtw89_write32(rtwdev, R_AX_TCR1, val32);
2390 seq_puts(m, "Enable tx tf infoh dump.\n");
2391 break;
2392 case RTW89_DBG_PORT_SEL_TXTF_INFOL_C1:
2393 info = &dbg_port_txtf_infol_c1;
2394 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
2395 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2396 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
2397 seq_puts(m, "Enable tx tf infol dump.\n");
2398 break;
2399 case RTW89_DBG_PORT_SEL_TXTF_INFOH_C1:
2400 info = &dbg_port_txtf_infoh_c1;
2401 val32 = rtw89_read32(rtwdev, R_AX_TCR1_C1);
2402 val32 |= B_AX_TCR_FORCE_READ_TXDFIFO;
2403 rtw89_write32(rtwdev, R_AX_TCR1_C1, val32);
2404 seq_puts(m, "Enable tx tf infoh dump.\n");
2405 break;
2406 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG:
2407 info = &dbg_port_wde_bufmgn_freepg;
2408 seq_puts(m, "Enable wde bufmgn freepg dump.\n");
2409 break;
2410 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_QUOTA:
2411 info = &dbg_port_wde_bufmgn_quota;
2412 seq_puts(m, "Enable wde bufmgn quota dump.\n");
2413 break;
2414 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PAGELLT:
2415 info = &dbg_port_wde_bufmgn_pagellt;
2416 seq_puts(m, "Enable wde bufmgn pagellt dump.\n");
2417 break;
2418 case RTW89_DBG_PORT_SEL_WDE_BUFMGN_PKTINFO:
2419 info = &dbg_port_wde_bufmgn_pktinfo;
2420 seq_puts(m, "Enable wde bufmgn pktinfo dump.\n");
2421 break;
2422 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_PREPKT:
2423 info = &dbg_port_wde_quemgn_prepkt;
2424 seq_puts(m, "Enable wde quemgn prepkt dump.\n");
2425 break;
2426 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_NXTPKT:
2427 info = &dbg_port_wde_quemgn_nxtpkt;
2428 seq_puts(m, "Enable wde quemgn nxtpkt dump.\n");
2429 break;
2430 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QLNKTBL:
2431 info = &dbg_port_wde_quemgn_qlnktbl;
2432 seq_puts(m, "Enable wde quemgn qlnktbl dump.\n");
2433 break;
2434 case RTW89_DBG_PORT_SEL_WDE_QUEMGN_QEMPTY:
2435 info = &dbg_port_wde_quemgn_qempty;
2436 seq_puts(m, "Enable wde quemgn qempty dump.\n");
2437 break;
2438 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_FREEPG:
2439 info = &dbg_port_ple_bufmgn_freepg;
2440 seq_puts(m, "Enable ple bufmgn freepg dump.\n");
2441 break;
2442 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_QUOTA:
2443 info = &dbg_port_ple_bufmgn_quota;
2444 seq_puts(m, "Enable ple bufmgn quota dump.\n");
2445 break;
2446 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PAGELLT:
2447 info = &dbg_port_ple_bufmgn_pagellt;
2448 seq_puts(m, "Enable ple bufmgn pagellt dump.\n");
2449 break;
2450 case RTW89_DBG_PORT_SEL_PLE_BUFMGN_PKTINFO:
2451 info = &dbg_port_ple_bufmgn_pktinfo;
2452 seq_puts(m, "Enable ple bufmgn pktinfo dump.\n");
2453 break;
2454 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_PREPKT:
2455 info = &dbg_port_ple_quemgn_prepkt;
2456 seq_puts(m, "Enable ple quemgn prepkt dump.\n");
2457 break;
2458 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_NXTPKT:
2459 info = &dbg_port_ple_quemgn_nxtpkt;
2460 seq_puts(m, "Enable ple quemgn nxtpkt dump.\n");
2461 break;
2462 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QLNKTBL:
2463 info = &dbg_port_ple_quemgn_qlnktbl;
2464 seq_puts(m, "Enable ple quemgn qlnktbl dump.\n");
2465 break;
2466 case RTW89_DBG_PORT_SEL_PLE_QUEMGN_QEMPTY:
2467 info = &dbg_port_ple_quemgn_qempty;
2468 seq_puts(m, "Enable ple quemgn qempty dump.\n");
2469 break;
2470 case RTW89_DBG_PORT_SEL_PKTINFO:
2471 info = &dbg_port_pktinfo;
2472 seq_puts(m, "Enable pktinfo dump.\n");
2473 break;
2474 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX0:
2475 rtw89_write32_mask(rtwdev, R_AX_DBG_CTRL,
2476 B_AX_DBG_SEL0, 0x80);
2477 rtw89_write32_mask(rtwdev, R_AX_SYS_STATUS1,
2478 B_AX_SEL_0XC0_MASK, 1);
2479 fallthrough;
2480 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX1:
2481 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX2:
2482 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX3:
2483 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX4:
2484 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX5:
2485 info = &dbg_port_dspt_hdt_tx0_5;
2486 index = sel - RTW89_DBG_PORT_SEL_DSPT_HDT_TX0;
2487 rtw89_write16_mask(rtwdev, info->sel_addr,
2488 B_AX_DISPATCHER_INTN_SEL_MASK, 0);
2489 rtw89_write16_mask(rtwdev, info->sel_addr,
2490 B_AX_DISPATCHER_CH_SEL_MASK, index);
2491 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index);
2492 break;
2493 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX6:
2494 info = &dbg_port_dspt_hdt_tx6;
2495 rtw89_write16_mask(rtwdev, info->sel_addr,
2496 B_AX_DISPATCHER_INTN_SEL_MASK, 0);
2497 rtw89_write16_mask(rtwdev, info->sel_addr,
2498 B_AX_DISPATCHER_CH_SEL_MASK, 6);
2499 seq_puts(m, "Enable Dispatcher hdt tx6 dump.\n");
2500 break;
2501 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX7:
2502 info = &dbg_port_dspt_hdt_tx7;
2503 rtw89_write16_mask(rtwdev, info->sel_addr,
2504 B_AX_DISPATCHER_INTN_SEL_MASK, 0);
2505 rtw89_write16_mask(rtwdev, info->sel_addr,
2506 B_AX_DISPATCHER_CH_SEL_MASK, 7);
2507 seq_puts(m, "Enable Dispatcher hdt tx7 dump.\n");
2508 break;
2509 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX8:
2510 info = &dbg_port_dspt_hdt_tx8;
2511 rtw89_write16_mask(rtwdev, info->sel_addr,
2512 B_AX_DISPATCHER_INTN_SEL_MASK, 0);
2513 rtw89_write16_mask(rtwdev, info->sel_addr,
2514 B_AX_DISPATCHER_CH_SEL_MASK, 8);
2515 seq_puts(m, "Enable Dispatcher hdt tx8 dump.\n");
2516 break;
2517 case RTW89_DBG_PORT_SEL_DSPT_HDT_TX9:
2518 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXA:
2519 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXB:
2520 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXC:
2521 info = &dbg_port_dspt_hdt_tx9_C;
2522 index = sel + 9 - RTW89_DBG_PORT_SEL_DSPT_HDT_TX9;
2523 rtw89_write16_mask(rtwdev, info->sel_addr,
2524 B_AX_DISPATCHER_INTN_SEL_MASK, 0);
2525 rtw89_write16_mask(rtwdev, info->sel_addr,
2526 B_AX_DISPATCHER_CH_SEL_MASK, index);
2527 seq_printf(m, "Enable Dispatcher hdt tx%x dump.\n", index);
2528 break;
2529 case RTW89_DBG_PORT_SEL_DSPT_HDT_TXD:
2530 info = &dbg_port_dspt_hdt_txD;
2531 rtw89_write16_mask(rtwdev, info->sel_addr,
2532 B_AX_DISPATCHER_INTN_SEL_MASK, 0);
2533 rtw89_write16_mask(rtwdev, info->sel_addr,
2534 B_AX_DISPATCHER_CH_SEL_MASK, 0xD);
2535 seq_puts(m, "Enable Dispatcher hdt txD dump.\n");
2536 break;
2537 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX0:
2538 info = &dbg_port_dspt_cdt_tx0;
2539 rtw89_write16_mask(rtwdev, info->sel_addr,
2540 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
2541 rtw89_write16_mask(rtwdev, info->sel_addr,
2542 B_AX_DISPATCHER_CH_SEL_MASK, 0);
2543 seq_puts(m, "Enable Dispatcher cdt tx0 dump.\n");
2544 break;
2545 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX1:
2546 info = &dbg_port_dspt_cdt_tx1;
2547 rtw89_write16_mask(rtwdev, info->sel_addr,
2548 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
2549 rtw89_write16_mask(rtwdev, info->sel_addr,
2550 B_AX_DISPATCHER_CH_SEL_MASK, 1);
2551 seq_puts(m, "Enable Dispatcher cdt tx1 dump.\n");
2552 break;
2553 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX3:
2554 info = &dbg_port_dspt_cdt_tx3;
2555 rtw89_write16_mask(rtwdev, info->sel_addr,
2556 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
2557 rtw89_write16_mask(rtwdev, info->sel_addr,
2558 B_AX_DISPATCHER_CH_SEL_MASK, 3);
2559 seq_puts(m, "Enable Dispatcher cdt tx3 dump.\n");
2560 break;
2561 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX4:
2562 info = &dbg_port_dspt_cdt_tx4;
2563 rtw89_write16_mask(rtwdev, info->sel_addr,
2564 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
2565 rtw89_write16_mask(rtwdev, info->sel_addr,
2566 B_AX_DISPATCHER_CH_SEL_MASK, 4);
2567 seq_puts(m, "Enable Dispatcher cdt tx4 dump.\n");
2568 break;
2569 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX5:
2570 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX6:
2571 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX7:
2572 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX8:
2573 info = &dbg_port_dspt_cdt_tx5_8;
2574 index = sel + 5 - RTW89_DBG_PORT_SEL_DSPT_CDT_TX5;
2575 rtw89_write16_mask(rtwdev, info->sel_addr,
2576 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
2577 rtw89_write16_mask(rtwdev, info->sel_addr,
2578 B_AX_DISPATCHER_CH_SEL_MASK, index);
2579 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index);
2580 break;
2581 case RTW89_DBG_PORT_SEL_DSPT_CDT_TX9:
2582 info = &dbg_port_dspt_cdt_tx9;
2583 rtw89_write16_mask(rtwdev, info->sel_addr,
2584 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
2585 rtw89_write16_mask(rtwdev, info->sel_addr,
2586 B_AX_DISPATCHER_CH_SEL_MASK, 9);
2587 seq_puts(m, "Enable Dispatcher cdt tx9 dump.\n");
2588 break;
2589 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXA:
2590 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXB:
2591 case RTW89_DBG_PORT_SEL_DSPT_CDT_TXC:
2592 info = &dbg_port_dspt_cdt_txA_C;
2593 index = sel + 0xA - RTW89_DBG_PORT_SEL_DSPT_CDT_TXA;
2594 rtw89_write16_mask(rtwdev, info->sel_addr,
2595 B_AX_DISPATCHER_INTN_SEL_MASK, 1);
2596 rtw89_write16_mask(rtwdev, info->sel_addr,
2597 B_AX_DISPATCHER_CH_SEL_MASK, index);
2598 seq_printf(m, "Enable Dispatcher cdt tx%x dump.\n", index);
2599 break;
2600 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX0:
2601 info = &dbg_port_dspt_hdt_rx0;
2602 rtw89_write16_mask(rtwdev, info->sel_addr,
2603 B_AX_DISPATCHER_INTN_SEL_MASK, 2);
2604 rtw89_write16_mask(rtwdev, info->sel_addr,
2605 B_AX_DISPATCHER_CH_SEL_MASK, 0);
2606 seq_puts(m, "Enable Dispatcher hdt rx0 dump.\n");
2607 break;
2608 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX1:
2609 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX2:
2610 info = &dbg_port_dspt_hdt_rx1_2;
2611 index = sel + 1 - RTW89_DBG_PORT_SEL_DSPT_HDT_RX1;
2612 rtw89_write16_mask(rtwdev, info->sel_addr,
2613 B_AX_DISPATCHER_INTN_SEL_MASK, 2);
2614 rtw89_write16_mask(rtwdev, info->sel_addr,
2615 B_AX_DISPATCHER_CH_SEL_MASK, index);
2616 seq_printf(m, "Enable Dispatcher hdt rx%x dump.\n", index);
2617 break;
2618 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX3:
2619 info = &dbg_port_dspt_hdt_rx3;
2620 rtw89_write16_mask(rtwdev, info->sel_addr,
2621 B_AX_DISPATCHER_INTN_SEL_MASK, 2);
2622 rtw89_write16_mask(rtwdev, info->sel_addr,
2623 B_AX_DISPATCHER_CH_SEL_MASK, 3);
2624 seq_puts(m, "Enable Dispatcher hdt rx3 dump.\n");
2625 break;
2626 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX4:
2627 info = &dbg_port_dspt_hdt_rx4;
2628 rtw89_write16_mask(rtwdev, info->sel_addr,
2629 B_AX_DISPATCHER_INTN_SEL_MASK, 2);
2630 rtw89_write16_mask(rtwdev, info->sel_addr,
2631 B_AX_DISPATCHER_CH_SEL_MASK, 4);
2632 seq_puts(m, "Enable Dispatcher hdt rx4 dump.\n");
2633 break;
2634 case RTW89_DBG_PORT_SEL_DSPT_HDT_RX5:
2635 info = &dbg_port_dspt_hdt_rx5;
2636 rtw89_write16_mask(rtwdev, info->sel_addr,
2637 B_AX_DISPATCHER_INTN_SEL_MASK, 2);
2638 rtw89_write16_mask(rtwdev, info->sel_addr,
2639 B_AX_DISPATCHER_CH_SEL_MASK, 5);
2640 seq_puts(m, "Enable Dispatcher hdt rx5 dump.\n");
2641 break;
2642 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_0:
2643 info = &dbg_port_dspt_cdt_rx_p0_0;
2644 rtw89_write16_mask(rtwdev, info->sel_addr,
2645 B_AX_DISPATCHER_INTN_SEL_MASK, 3);
2646 rtw89_write16_mask(rtwdev, info->sel_addr,
2647 B_AX_DISPATCHER_CH_SEL_MASK, 0);
2648 seq_puts(m, "Enable Dispatcher cdt rx part0 0 dump.\n");
2649 break;
2650 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0:
2651 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_1:
2652 info = &dbg_port_dspt_cdt_rx_p0_1;
2653 rtw89_write16_mask(rtwdev, info->sel_addr,
2654 B_AX_DISPATCHER_INTN_SEL_MASK, 3);
2655 rtw89_write16_mask(rtwdev, info->sel_addr,
2656 B_AX_DISPATCHER_CH_SEL_MASK, 1);
2657 seq_puts(m, "Enable Dispatcher cdt rx part0 1 dump.\n");
2658 break;
2659 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P0_2:
2660 info = &dbg_port_dspt_cdt_rx_p0_2;
2661 rtw89_write16_mask(rtwdev, info->sel_addr,
2662 B_AX_DISPATCHER_INTN_SEL_MASK, 3);
2663 rtw89_write16_mask(rtwdev, info->sel_addr,
2664 B_AX_DISPATCHER_CH_SEL_MASK, 2);
2665 seq_puts(m, "Enable Dispatcher cdt rx part0 2 dump.\n");
2666 break;
2667 case RTW89_DBG_PORT_SEL_DSPT_CDT_RX_P1:
2668 info = &dbg_port_dspt_cdt_rx_p1;
2669 rtw89_write8_mask(rtwdev, info->sel_addr,
2670 B_AX_DISPATCHER_INTN_SEL_MASK, 3);
2671 seq_puts(m, "Enable Dispatcher cdt rx part1 dump.\n");
2672 break;
2673 case RTW89_DBG_PORT_SEL_DSPT_STF_CTRL:
2674 info = &dbg_port_dspt_stf_ctrl;
2675 rtw89_write8_mask(rtwdev, info->sel_addr,
2676 B_AX_DISPATCHER_INTN_SEL_MASK, 4);
2677 seq_puts(m, "Enable Dispatcher stf control dump.\n");
2678 break;
2679 case RTW89_DBG_PORT_SEL_DSPT_ADDR_CTRL:
2680 info = &dbg_port_dspt_addr_ctrl;
2681 rtw89_write8_mask(rtwdev, info->sel_addr,
2682 B_AX_DISPATCHER_INTN_SEL_MASK, 5);
2683 seq_puts(m, "Enable Dispatcher addr control dump.\n");
2684 break;
2685 case RTW89_DBG_PORT_SEL_DSPT_WDE_INTF:
2686 info = &dbg_port_dspt_wde_intf;
2687 rtw89_write8_mask(rtwdev, info->sel_addr,
2688 B_AX_DISPATCHER_INTN_SEL_MASK, 6);
2689 seq_puts(m, "Enable Dispatcher wde interface dump.\n");
2690 break;
2691 case RTW89_DBG_PORT_SEL_DSPT_PLE_INTF:
2692 info = &dbg_port_dspt_ple_intf;
2693 rtw89_write8_mask(rtwdev, info->sel_addr,
2694 B_AX_DISPATCHER_INTN_SEL_MASK, 7);
2695 seq_puts(m, "Enable Dispatcher ple interface dump.\n");
2696 break;
2697 case RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL:
2698 info = &dbg_port_dspt_flow_ctrl;
2699 rtw89_write8_mask(rtwdev, info->sel_addr,
2700 B_AX_DISPATCHER_INTN_SEL_MASK, 8);
2701 seq_puts(m, "Enable Dispatcher flow control dump.\n");
2702 break;
2703 case RTW89_DBG_PORT_SEL_PCIE_TXDMA:
2704 info = &dbg_port_pcie_txdma;
2705 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2706 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL0);
2707 val32 = u32_replace_bits(val32, PCIE_TXDMA_DBG_SEL, B_AX_DBG_SEL1);
2708 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2709 seq_puts(m, "Enable pcie txdma dump.\n");
2710 break;
2711 case RTW89_DBG_PORT_SEL_PCIE_RXDMA:
2712 info = &dbg_port_pcie_rxdma;
2713 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2714 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL0);
2715 val32 = u32_replace_bits(val32, PCIE_RXDMA_DBG_SEL, B_AX_DBG_SEL1);
2716 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2717 seq_puts(m, "Enable pcie rxdma dump.\n");
2718 break;
2719 case RTW89_DBG_PORT_SEL_PCIE_CVT:
2720 info = &dbg_port_pcie_cvt;
2721 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2722 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL0);
2723 val32 = u32_replace_bits(val32, PCIE_CVT_DBG_SEL, B_AX_DBG_SEL1);
2724 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2725 seq_puts(m, "Enable pcie cvt dump.\n");
2726 break;
2727 case RTW89_DBG_PORT_SEL_PCIE_CXPL:
2728 info = &dbg_port_pcie_cxpl;
2729 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2730 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL0);
2731 val32 = u32_replace_bits(val32, PCIE_CXPL_DBG_SEL, B_AX_DBG_SEL1);
2732 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2733 seq_puts(m, "Enable pcie cxpl dump.\n");
2734 break;
2735 case RTW89_DBG_PORT_SEL_PCIE_IO:
2736 info = &dbg_port_pcie_io;
2737 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2738 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL0);
2739 val32 = u32_replace_bits(val32, PCIE_IO_DBG_SEL, B_AX_DBG_SEL1);
2740 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2741 seq_puts(m, "Enable pcie io dump.\n");
2742 break;
2743 case RTW89_DBG_PORT_SEL_PCIE_MISC:
2744 info = &dbg_port_pcie_misc;
2745 val32 = rtw89_read32(rtwdev, R_AX_DBG_CTRL);
2746 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL0);
2747 val32 = u32_replace_bits(val32, PCIE_MISC_DBG_SEL, B_AX_DBG_SEL1);
2748 rtw89_write32(rtwdev, R_AX_DBG_CTRL, val32);
2749 seq_puts(m, "Enable pcie misc dump.\n");
2750 break;
2751 case RTW89_DBG_PORT_SEL_PCIE_MISC2:
2752 info = &dbg_port_pcie_misc2;
2753 val16 = rtw89_read16(rtwdev, R_AX_PCIE_DBG_CTRL);
2754 val16 = u16_replace_bits(val16, PCIE_MISC2_DBG_SEL,
2755 B_AX_PCIE_DBG_SEL_MASK);
2756 rtw89_write16(rtwdev, R_AX_PCIE_DBG_CTRL, val16);
2757 seq_puts(m, "Enable pcie misc2 dump.\n");
2758 break;
2759 default:
2760 seq_puts(m, "Dbg port select err\n");
2761 return NULL;
2762 }
2763
2764 return info;
2765 }
2766
is_dbg_port_valid(struct rtw89_dev * rtwdev,u32 sel)2767 static bool is_dbg_port_valid(struct rtw89_dev *rtwdev, u32 sel)
2768 {
2769 if (rtwdev->hci.type != RTW89_HCI_TYPE_PCIE &&
2770 sel >= RTW89_DBG_PORT_SEL_PCIE_TXDMA &&
2771 sel <= RTW89_DBG_PORT_SEL_PCIE_MISC2)
2772 return false;
2773 if (rtwdev->chip->chip_id == RTL8852B &&
2774 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 &&
2775 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1)
2776 return false;
2777 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) &&
2778 sel >= RTW89_DBG_PORT_SEL_WDE_BUFMGN_FREEPG &&
2779 sel <= RTW89_DBG_PORT_SEL_PKTINFO)
2780 return false;
2781 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_DMAC_SEL) &&
2782 sel >= RTW89_DBG_PORT_SEL_DSPT_HDT_TX0 &&
2783 sel <= RTW89_DBG_PORT_SEL_DSPT_FLOW_CTRL)
2784 return false;
2785 if (rtw89_mac_check_mac_en(rtwdev, 0, RTW89_CMAC_SEL) &&
2786 sel >= RTW89_DBG_PORT_SEL_PTCL_C0 &&
2787 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C0)
2788 return false;
2789 if (rtw89_mac_check_mac_en(rtwdev, 1, RTW89_CMAC_SEL) &&
2790 sel >= RTW89_DBG_PORT_SEL_PTCL_C1 &&
2791 sel <= RTW89_DBG_PORT_SEL_TXTF_INFOH_C1)
2792 return false;
2793
2794 return true;
2795 }
2796
rtw89_debug_mac_dbg_port_dump(struct rtw89_dev * rtwdev,struct seq_file * m,u32 sel)2797 static int rtw89_debug_mac_dbg_port_dump(struct rtw89_dev *rtwdev,
2798 struct seq_file *m, u32 sel)
2799 {
2800 const struct rtw89_mac_dbg_port_info *info;
2801 u8 val8;
2802 u16 val16;
2803 u32 val32;
2804 u32 i;
2805
2806 info = rtw89_debug_mac_dbg_port_sel(m, rtwdev, sel);
2807 if (!info) {
2808 rtw89_err(rtwdev, "failed to select debug port %d\n", sel);
2809 return -EINVAL;
2810 }
2811
2812 #define case_DBG_SEL(__sel) \
2813 case RTW89_DBG_PORT_SEL_##__sel: \
2814 seq_puts(m, "Dump debug port " #__sel ":\n"); \
2815 break
2816
2817 switch (sel) {
2818 case_DBG_SEL(PTCL_C0);
2819 case_DBG_SEL(PTCL_C1);
2820 case_DBG_SEL(SCH_C0);
2821 case_DBG_SEL(SCH_C1);
2822 case_DBG_SEL(TMAC_C0);
2823 case_DBG_SEL(TMAC_C1);
2824 case_DBG_SEL(RMAC_C0);
2825 case_DBG_SEL(RMAC_C1);
2826 case_DBG_SEL(RMACST_C0);
2827 case_DBG_SEL(RMACST_C1);
2828 case_DBG_SEL(TRXPTCL_C0);
2829 case_DBG_SEL(TRXPTCL_C1);
2830 case_DBG_SEL(TX_INFOL_C0);
2831 case_DBG_SEL(TX_INFOH_C0);
2832 case_DBG_SEL(TX_INFOL_C1);
2833 case_DBG_SEL(TX_INFOH_C1);
2834 case_DBG_SEL(TXTF_INFOL_C0);
2835 case_DBG_SEL(TXTF_INFOH_C0);
2836 case_DBG_SEL(TXTF_INFOL_C1);
2837 case_DBG_SEL(TXTF_INFOH_C1);
2838 case_DBG_SEL(WDE_BUFMGN_FREEPG);
2839 case_DBG_SEL(WDE_BUFMGN_QUOTA);
2840 case_DBG_SEL(WDE_BUFMGN_PAGELLT);
2841 case_DBG_SEL(WDE_BUFMGN_PKTINFO);
2842 case_DBG_SEL(WDE_QUEMGN_PREPKT);
2843 case_DBG_SEL(WDE_QUEMGN_NXTPKT);
2844 case_DBG_SEL(WDE_QUEMGN_QLNKTBL);
2845 case_DBG_SEL(WDE_QUEMGN_QEMPTY);
2846 case_DBG_SEL(PLE_BUFMGN_FREEPG);
2847 case_DBG_SEL(PLE_BUFMGN_QUOTA);
2848 case_DBG_SEL(PLE_BUFMGN_PAGELLT);
2849 case_DBG_SEL(PLE_BUFMGN_PKTINFO);
2850 case_DBG_SEL(PLE_QUEMGN_PREPKT);
2851 case_DBG_SEL(PLE_QUEMGN_NXTPKT);
2852 case_DBG_SEL(PLE_QUEMGN_QLNKTBL);
2853 case_DBG_SEL(PLE_QUEMGN_QEMPTY);
2854 case_DBG_SEL(PKTINFO);
2855 case_DBG_SEL(DSPT_HDT_TX0);
2856 case_DBG_SEL(DSPT_HDT_TX1);
2857 case_DBG_SEL(DSPT_HDT_TX2);
2858 case_DBG_SEL(DSPT_HDT_TX3);
2859 case_DBG_SEL(DSPT_HDT_TX4);
2860 case_DBG_SEL(DSPT_HDT_TX5);
2861 case_DBG_SEL(DSPT_HDT_TX6);
2862 case_DBG_SEL(DSPT_HDT_TX7);
2863 case_DBG_SEL(DSPT_HDT_TX8);
2864 case_DBG_SEL(DSPT_HDT_TX9);
2865 case_DBG_SEL(DSPT_HDT_TXA);
2866 case_DBG_SEL(DSPT_HDT_TXB);
2867 case_DBG_SEL(DSPT_HDT_TXC);
2868 case_DBG_SEL(DSPT_HDT_TXD);
2869 case_DBG_SEL(DSPT_HDT_TXE);
2870 case_DBG_SEL(DSPT_HDT_TXF);
2871 case_DBG_SEL(DSPT_CDT_TX0);
2872 case_DBG_SEL(DSPT_CDT_TX1);
2873 case_DBG_SEL(DSPT_CDT_TX3);
2874 case_DBG_SEL(DSPT_CDT_TX4);
2875 case_DBG_SEL(DSPT_CDT_TX5);
2876 case_DBG_SEL(DSPT_CDT_TX6);
2877 case_DBG_SEL(DSPT_CDT_TX7);
2878 case_DBG_SEL(DSPT_CDT_TX8);
2879 case_DBG_SEL(DSPT_CDT_TX9);
2880 case_DBG_SEL(DSPT_CDT_TXA);
2881 case_DBG_SEL(DSPT_CDT_TXB);
2882 case_DBG_SEL(DSPT_CDT_TXC);
2883 case_DBG_SEL(DSPT_HDT_RX0);
2884 case_DBG_SEL(DSPT_HDT_RX1);
2885 case_DBG_SEL(DSPT_HDT_RX2);
2886 case_DBG_SEL(DSPT_HDT_RX3);
2887 case_DBG_SEL(DSPT_HDT_RX4);
2888 case_DBG_SEL(DSPT_HDT_RX5);
2889 case_DBG_SEL(DSPT_CDT_RX_P0);
2890 case_DBG_SEL(DSPT_CDT_RX_P0_0);
2891 case_DBG_SEL(DSPT_CDT_RX_P0_1);
2892 case_DBG_SEL(DSPT_CDT_RX_P0_2);
2893 case_DBG_SEL(DSPT_CDT_RX_P1);
2894 case_DBG_SEL(DSPT_STF_CTRL);
2895 case_DBG_SEL(DSPT_ADDR_CTRL);
2896 case_DBG_SEL(DSPT_WDE_INTF);
2897 case_DBG_SEL(DSPT_PLE_INTF);
2898 case_DBG_SEL(DSPT_FLOW_CTRL);
2899 case_DBG_SEL(PCIE_TXDMA);
2900 case_DBG_SEL(PCIE_RXDMA);
2901 case_DBG_SEL(PCIE_CVT);
2902 case_DBG_SEL(PCIE_CXPL);
2903 case_DBG_SEL(PCIE_IO);
2904 case_DBG_SEL(PCIE_MISC);
2905 case_DBG_SEL(PCIE_MISC2);
2906 }
2907
2908 #undef case_DBG_SEL
2909
2910 seq_printf(m, "Sel addr = 0x%X\n", info->sel_addr);
2911 seq_printf(m, "Read addr = 0x%X\n", info->rd_addr);
2912
2913 for (i = info->srt; i <= info->end; i++) {
2914 switch (info->sel_byte) {
2915 case 1:
2916 default:
2917 rtw89_write8_mask(rtwdev, info->sel_addr,
2918 info->sel_msk, i);
2919 seq_printf(m, "0x%02X: ", i);
2920 break;
2921 case 2:
2922 rtw89_write16_mask(rtwdev, info->sel_addr,
2923 info->sel_msk, i);
2924 seq_printf(m, "0x%04X: ", i);
2925 break;
2926 case 4:
2927 rtw89_write32_mask(rtwdev, info->sel_addr,
2928 info->sel_msk, i);
2929 seq_printf(m, "0x%04X: ", i);
2930 break;
2931 }
2932
2933 udelay(10);
2934
2935 switch (info->rd_byte) {
2936 case 1:
2937 default:
2938 val8 = rtw89_read8_mask(rtwdev,
2939 info->rd_addr, info->rd_msk);
2940 seq_printf(m, "0x%02X\n", val8);
2941 break;
2942 case 2:
2943 val16 = rtw89_read16_mask(rtwdev,
2944 info->rd_addr, info->rd_msk);
2945 seq_printf(m, "0x%04X\n", val16);
2946 break;
2947 case 4:
2948 val32 = rtw89_read32_mask(rtwdev,
2949 info->rd_addr, info->rd_msk);
2950 seq_printf(m, "0x%08X\n", val32);
2951 break;
2952 }
2953 }
2954
2955 return 0;
2956 }
2957
rtw89_debug_mac_dump_dbg_port(struct rtw89_dev * rtwdev,struct seq_file * m)2958 static int rtw89_debug_mac_dump_dbg_port(struct rtw89_dev *rtwdev,
2959 struct seq_file *m)
2960 {
2961 u32 sel;
2962 int ret = 0;
2963
2964 for (sel = RTW89_DBG_PORT_SEL_PTCL_C0;
2965 sel < RTW89_DBG_PORT_SEL_LAST; sel++) {
2966 if (!is_dbg_port_valid(rtwdev, sel))
2967 continue;
2968 ret = rtw89_debug_mac_dbg_port_dump(rtwdev, m, sel);
2969 if (ret) {
2970 rtw89_err(rtwdev,
2971 "failed to dump debug port %d\n", sel);
2972 break;
2973 }
2974 }
2975
2976 return ret;
2977 }
2978
2979 static int
rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file * m,void * v)2980 rtw89_debug_priv_mac_dbg_port_dump_get(struct seq_file *m, void *v)
2981 {
2982 struct rtw89_debugfs_priv *debugfs_priv = m->private;
2983 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
2984
2985 if (debugfs_priv->dbgpkg_en.ss_dbg)
2986 rtw89_debug_mac_dump_ss_dbg(rtwdev, m);
2987 if (debugfs_priv->dbgpkg_en.dle_dbg)
2988 rtw89_debug_mac_dump_dle_dbg(rtwdev, m);
2989 if (debugfs_priv->dbgpkg_en.dmac_dbg)
2990 rtw89_debug_mac_dump_dmac_dbg(rtwdev, m);
2991 if (debugfs_priv->dbgpkg_en.cmac_dbg)
2992 rtw89_debug_mac_dump_cmac_dbg(rtwdev, m);
2993 if (debugfs_priv->dbgpkg_en.dbg_port)
2994 rtw89_debug_mac_dump_dbg_port(rtwdev, m);
2995
2996 return 0;
2997 };
2998
rtw89_hex2bin_user(struct rtw89_dev * rtwdev,const char __user * user_buf,size_t count)2999 static u8 *rtw89_hex2bin_user(struct rtw89_dev *rtwdev,
3000 const char __user *user_buf, size_t count)
3001 {
3002 char *buf;
3003 u8 *bin;
3004 int num;
3005 int err = 0;
3006
3007 buf = memdup_user(user_buf, count);
3008 if (IS_ERR(buf))
3009 return buf;
3010
3011 num = count / 2;
3012 bin = kmalloc(num, GFP_KERNEL);
3013 if (!bin) {
3014 err = -EFAULT;
3015 goto out;
3016 }
3017
3018 if (hex2bin(bin, buf, num)) {
3019 rtw89_info(rtwdev, "valid format: H1H2H3...\n");
3020 kfree(bin);
3021 err = -EINVAL;
3022 }
3023
3024 out:
3025 kfree(buf);
3026
3027 return err ? ERR_PTR(err) : bin;
3028 }
3029
rtw89_debug_priv_send_h2c_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)3030 static ssize_t rtw89_debug_priv_send_h2c_set(struct file *filp,
3031 const char __user *user_buf,
3032 size_t count, loff_t *loff)
3033 {
3034 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
3035 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3036 u8 *h2c;
3037 int ret;
3038 u16 h2c_len = count / 2;
3039
3040 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count);
3041 if (IS_ERR(h2c))
3042 return -EFAULT;
3043
3044 ret = rtw89_fw_h2c_raw(rtwdev, h2c, h2c_len);
3045
3046 kfree(h2c);
3047
3048 return ret ? ret : count;
3049 }
3050
3051 static int
rtw89_debug_priv_early_h2c_get(struct seq_file * m,void * v)3052 rtw89_debug_priv_early_h2c_get(struct seq_file *m, void *v)
3053 {
3054 struct rtw89_debugfs_priv *debugfs_priv = m->private;
3055 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3056 struct rtw89_early_h2c *early_h2c;
3057 int seq = 0;
3058
3059 mutex_lock(&rtwdev->mutex);
3060 list_for_each_entry(early_h2c, &rtwdev->early_h2c_list, list)
3061 seq_printf(m, "%d: %*ph\n", ++seq, early_h2c->h2c_len, early_h2c->h2c);
3062 mutex_unlock(&rtwdev->mutex);
3063
3064 return 0;
3065 }
3066
3067 static ssize_t
rtw89_debug_priv_early_h2c_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)3068 rtw89_debug_priv_early_h2c_set(struct file *filp, const char __user *user_buf,
3069 size_t count, loff_t *loff)
3070 {
3071 struct seq_file *m = (struct seq_file *)filp->private_data;
3072 struct rtw89_debugfs_priv *debugfs_priv = m->private;
3073 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3074 struct rtw89_early_h2c *early_h2c;
3075 u8 *h2c;
3076 u16 h2c_len = count / 2;
3077
3078 h2c = rtw89_hex2bin_user(rtwdev, user_buf, count);
3079 if (IS_ERR(h2c))
3080 return -EFAULT;
3081
3082 if (h2c_len >= 2 && h2c[0] == 0x00 && h2c[1] == 0x00) {
3083 kfree(h2c);
3084 rtw89_fw_free_all_early_h2c(rtwdev);
3085 goto out;
3086 }
3087
3088 early_h2c = kmalloc(sizeof(*early_h2c), GFP_KERNEL);
3089 if (!early_h2c) {
3090 kfree(h2c);
3091 return -EFAULT;
3092 }
3093
3094 early_h2c->h2c = h2c;
3095 early_h2c->h2c_len = h2c_len;
3096
3097 mutex_lock(&rtwdev->mutex);
3098 list_add_tail(&early_h2c->list, &rtwdev->early_h2c_list);
3099 mutex_unlock(&rtwdev->mutex);
3100
3101 out:
3102 return count;
3103 }
3104
rtw89_dbg_trigger_ctrl_error(struct rtw89_dev * rtwdev)3105 static int rtw89_dbg_trigger_ctrl_error(struct rtw89_dev *rtwdev)
3106 {
3107 struct rtw89_cpuio_ctrl ctrl_para = {0};
3108 u16 pkt_id;
3109 int ret;
3110
3111 rtw89_leave_ps_mode(rtwdev);
3112
3113 ret = rtw89_mac_dle_buf_req(rtwdev, 0x20, true, &pkt_id);
3114 if (ret)
3115 return ret;
3116
3117 /* intentionally, enqueue two pkt, but has only one pkt id */
3118 ctrl_para.cmd_type = CPUIO_OP_CMD_ENQ_TO_HEAD;
3119 ctrl_para.start_pktid = pkt_id;
3120 ctrl_para.end_pktid = pkt_id;
3121 ctrl_para.pkt_num = 1; /* start from 0 */
3122 ctrl_para.dst_pid = WDE_DLE_PORT_ID_WDRLS;
3123 ctrl_para.dst_qid = WDE_DLE_QUEID_NO_REPORT;
3124
3125 if (rtw89_mac_set_cpuio(rtwdev, &ctrl_para, true))
3126 return -EFAULT;
3127
3128 return 0;
3129 }
3130
3131 static int
rtw89_debug_priv_fw_crash_get(struct seq_file * m,void * v)3132 rtw89_debug_priv_fw_crash_get(struct seq_file *m, void *v)
3133 {
3134 struct rtw89_debugfs_priv *debugfs_priv = m->private;
3135 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3136
3137 seq_printf(m, "%d\n",
3138 test_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags));
3139 return 0;
3140 }
3141
3142 enum rtw89_dbg_crash_simulation_type {
3143 RTW89_DBG_SIM_CPU_EXCEPTION = 1,
3144 RTW89_DBG_SIM_CTRL_ERROR = 2,
3145 };
3146
3147 static ssize_t
rtw89_debug_priv_fw_crash_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)3148 rtw89_debug_priv_fw_crash_set(struct file *filp, const char __user *user_buf,
3149 size_t count, loff_t *loff)
3150 {
3151 struct seq_file *m = (struct seq_file *)filp->private_data;
3152 struct rtw89_debugfs_priv *debugfs_priv = m->private;
3153 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3154 int (*sim)(struct rtw89_dev *rtwdev);
3155 u8 crash_type;
3156 int ret;
3157
3158 ret = kstrtou8_from_user(user_buf, count, 0, &crash_type);
3159 if (ret)
3160 return -EINVAL;
3161
3162 switch (crash_type) {
3163 case RTW89_DBG_SIM_CPU_EXCEPTION:
3164 if (!RTW89_CHK_FW_FEATURE(CRASH_TRIGGER, &rtwdev->fw))
3165 return -EOPNOTSUPP;
3166 sim = rtw89_fw_h2c_trigger_cpu_exception;
3167 break;
3168 case RTW89_DBG_SIM_CTRL_ERROR:
3169 sim = rtw89_dbg_trigger_ctrl_error;
3170 break;
3171 default:
3172 return -EINVAL;
3173 }
3174
3175 mutex_lock(&rtwdev->mutex);
3176 set_bit(RTW89_FLAG_CRASH_SIMULATING, rtwdev->flags);
3177 ret = sim(rtwdev);
3178 mutex_unlock(&rtwdev->mutex);
3179
3180 if (ret)
3181 return ret;
3182
3183 return count;
3184 }
3185
rtw89_debug_priv_btc_info_get(struct seq_file * m,void * v)3186 static int rtw89_debug_priv_btc_info_get(struct seq_file *m, void *v)
3187 {
3188 struct rtw89_debugfs_priv *debugfs_priv = m->private;
3189 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3190
3191 rtw89_btc_dump_info(rtwdev, m);
3192
3193 return 0;
3194 }
3195
rtw89_debug_priv_btc_manual_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)3196 static ssize_t rtw89_debug_priv_btc_manual_set(struct file *filp,
3197 const char __user *user_buf,
3198 size_t count, loff_t *loff)
3199 {
3200 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
3201 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3202 struct rtw89_btc *btc = &rtwdev->btc;
3203 bool btc_manual;
3204 int ret;
3205
3206 ret = kstrtobool_from_user(user_buf, count, &btc_manual);
3207 if (ret)
3208 return ret;
3209
3210 btc->ctrl.manual = btc_manual;
3211
3212 return count;
3213 }
3214
rtw89_debug_fw_log_manual_set(struct file * filp,const char __user * user_buf,size_t count,loff_t * loff)3215 static ssize_t rtw89_debug_fw_log_manual_set(struct file *filp,
3216 const char __user *user_buf,
3217 size_t count, loff_t *loff)
3218 {
3219 struct rtw89_debugfs_priv *debugfs_priv = filp->private_data;
3220 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3221 struct rtw89_fw_log *log = &rtwdev->fw.log;
3222 bool fw_log_manual;
3223
3224 if (kstrtobool_from_user(user_buf, count, &fw_log_manual))
3225 goto out;
3226
3227 mutex_lock(&rtwdev->mutex);
3228 log->enable = fw_log_manual;
3229 if (log->enable)
3230 rtw89_fw_log_prepare(rtwdev);
3231 rtw89_fw_h2c_fw_log(rtwdev, fw_log_manual);
3232 mutex_unlock(&rtwdev->mutex);
3233 out:
3234 return count;
3235 }
3236
rtw89_sta_info_get_iter(void * data,struct ieee80211_sta * sta)3237 static void rtw89_sta_info_get_iter(void *data, struct ieee80211_sta *sta)
3238 {
3239 static const char * const he_gi_str[] = {
3240 [NL80211_RATE_INFO_HE_GI_0_8] = "0.8",
3241 [NL80211_RATE_INFO_HE_GI_1_6] = "1.6",
3242 [NL80211_RATE_INFO_HE_GI_3_2] = "3.2",
3243 };
3244 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
3245 struct rate_info *rate = &rtwsta->ra_report.txrate;
3246 struct ieee80211_rx_status *status = &rtwsta->rx_status;
3247 struct seq_file *m = (struct seq_file *)data;
3248 struct rtw89_dev *rtwdev = rtwsta->rtwdev;
3249 struct rtw89_hal *hal = &rtwdev->hal;
3250 u8 ant_num = hal->ant_diversity ? 2 : rtwdev->chip->rf_path_num;
3251 bool ant_asterisk = hal->tx_path_diversity || hal->ant_diversity;
3252 u8 evm_min, evm_max;
3253 u8 rssi;
3254 u8 snr;
3255 int i;
3256
3257 seq_printf(m, "TX rate [%d]: ", rtwsta->mac_id);
3258
3259 if (rate->flags & RATE_INFO_FLAGS_MCS)
3260 seq_printf(m, "HT MCS-%d%s", rate->mcs,
3261 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : "");
3262 else if (rate->flags & RATE_INFO_FLAGS_VHT_MCS)
3263 seq_printf(m, "VHT %dSS MCS-%d%s", rate->nss, rate->mcs,
3264 rate->flags & RATE_INFO_FLAGS_SHORT_GI ? " SGI" : "");
3265 else if (rate->flags & RATE_INFO_FLAGS_HE_MCS)
3266 seq_printf(m, "HE %dSS MCS-%d GI:%s", rate->nss, rate->mcs,
3267 rate->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ?
3268 he_gi_str[rate->he_gi] : "N/A");
3269 else
3270 seq_printf(m, "Legacy %d", rate->legacy);
3271 seq_printf(m, "%s", rtwsta->ra_report.might_fallback_legacy ? " FB_G" : "");
3272 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(rate->bw));
3273 seq_printf(m, "\t(hw_rate=0x%x)", rtwsta->ra_report.hw_rate);
3274 seq_printf(m, "\t==> agg_wait=%d (%d)\n", rtwsta->max_agg_wait,
3275 sta->deflink.agg.max_rc_amsdu_len);
3276
3277 seq_printf(m, "RX rate [%d]: ", rtwsta->mac_id);
3278
3279 switch (status->encoding) {
3280 case RX_ENC_LEGACY:
3281 seq_printf(m, "Legacy %d", status->rate_idx +
3282 (status->band != NL80211_BAND_2GHZ ? 4 : 0));
3283 break;
3284 case RX_ENC_HT:
3285 seq_printf(m, "HT MCS-%d%s", status->rate_idx,
3286 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : "");
3287 break;
3288 case RX_ENC_VHT:
3289 seq_printf(m, "VHT %dSS MCS-%d%s", status->nss, status->rate_idx,
3290 status->enc_flags & RX_ENC_FLAG_SHORT_GI ? " SGI" : "");
3291 break;
3292 case RX_ENC_HE:
3293 seq_printf(m, "HE %dSS MCS-%d GI:%s", status->nss, status->rate_idx,
3294 status->he_gi <= NL80211_RATE_INFO_HE_GI_3_2 ?
3295 he_gi_str[rate->he_gi] : "N/A");
3296 break;
3297 }
3298 seq_printf(m, " BW:%u", rtw89_rate_info_bw_to_mhz(status->bw));
3299 seq_printf(m, "\t(hw_rate=0x%x)\n", rtwsta->rx_hw_rate);
3300
3301 rssi = ewma_rssi_read(&rtwsta->avg_rssi);
3302 seq_printf(m, "RSSI: %d dBm (raw=%d, prev=%d) [",
3303 RTW89_RSSI_RAW_TO_DBM(rssi), rssi, rtwsta->prev_rssi);
3304 for (i = 0; i < ant_num; i++) {
3305 rssi = ewma_rssi_read(&rtwsta->rssi[i]);
3306 seq_printf(m, "%d%s%s", RTW89_RSSI_RAW_TO_DBM(rssi),
3307 ant_asterisk && (hal->antenna_tx & BIT(i)) ? "*" : "",
3308 i + 1 == ant_num ? "" : ", ");
3309 }
3310 seq_puts(m, "]\n");
3311
3312 seq_puts(m, "EVM: [");
3313 for (i = 0; i < (hal->ant_diversity ? 2 : 1); i++) {
3314 evm_min = ewma_evm_read(&rtwsta->evm_min[i]);
3315 evm_max = ewma_evm_read(&rtwsta->evm_max[i]);
3316
3317 seq_printf(m, "%s(%2u.%02u, %2u.%02u)", i == 0 ? "" : " ",
3318 evm_min >> 2, (evm_min & 0x3) * 25,
3319 evm_max >> 2, (evm_max & 0x3) * 25);
3320 }
3321 seq_puts(m, "]\t");
3322
3323 snr = ewma_snr_read(&rtwsta->avg_snr);
3324 seq_printf(m, "SNR: %u\n", snr);
3325 }
3326
3327 static void
rtw89_debug_append_rx_rate(struct seq_file * m,struct rtw89_pkt_stat * pkt_stat,enum rtw89_hw_rate first_rate,int len)3328 rtw89_debug_append_rx_rate(struct seq_file *m, struct rtw89_pkt_stat *pkt_stat,
3329 enum rtw89_hw_rate first_rate, int len)
3330 {
3331 int i;
3332
3333 for (i = 0; i < len; i++)
3334 seq_printf(m, "%s%u", i == 0 ? "" : ", ",
3335 pkt_stat->rx_rate_cnt[first_rate + i]);
3336 }
3337
3338 #define FIRST_RATE_SAME(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_ ## rate}
3339 #define FIRST_RATE_ENUM(rate) {RTW89_HW_RATE_ ## rate, RTW89_HW_RATE_V1_ ## rate}
3340 #define FIRST_RATE_GEV1(rate) {RTW89_HW_RATE_INVAL, RTW89_HW_RATE_V1_ ## rate}
3341
3342 static const struct rtw89_rx_rate_cnt_info {
3343 enum rtw89_hw_rate first_rate[RTW89_CHIP_GEN_NUM];
3344 int len;
3345 int ext;
3346 const char *rate_mode;
3347 } rtw89_rx_rate_cnt_infos[] = {
3348 {FIRST_RATE_SAME(CCK1), 4, 0, "Legacy:"},
3349 {FIRST_RATE_SAME(OFDM6), 8, 0, "OFDM:"},
3350 {FIRST_RATE_ENUM(MCS0), 8, 0, "HT 0:"},
3351 {FIRST_RATE_ENUM(MCS8), 8, 0, "HT 1:"},
3352 {FIRST_RATE_ENUM(VHT_NSS1_MCS0), 10, 2, "VHT 1SS:"},
3353 {FIRST_RATE_ENUM(VHT_NSS2_MCS0), 10, 2, "VHT 2SS:"},
3354 {FIRST_RATE_ENUM(HE_NSS1_MCS0), 12, 0, "HE 1SS:"},
3355 {FIRST_RATE_ENUM(HE_NSS2_MCS0), 12, 0, "HE 2SS:"},
3356 {FIRST_RATE_GEV1(EHT_NSS1_MCS0), 14, 2, "EHT 1SS:"},
3357 {FIRST_RATE_GEV1(EHT_NSS2_MCS0), 14, 0, "EHT 2SS:"},
3358 };
3359
rtw89_debug_priv_phy_info_get(struct seq_file * m,void * v)3360 static int rtw89_debug_priv_phy_info_get(struct seq_file *m, void *v)
3361 {
3362 struct rtw89_debugfs_priv *debugfs_priv = m->private;
3363 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3364 struct rtw89_traffic_stats *stats = &rtwdev->stats;
3365 struct rtw89_pkt_stat *pkt_stat = &rtwdev->phystat.last_pkt_stat;
3366 const struct rtw89_chip_info *chip = rtwdev->chip;
3367 const struct rtw89_rx_rate_cnt_info *info;
3368 enum rtw89_hw_rate first_rate;
3369 int i;
3370
3371 seq_printf(m, "TP TX: %u [%u] Mbps (lv: %d), RX: %u [%u] Mbps (lv: %d)\n",
3372 stats->tx_throughput, stats->tx_throughput_raw, stats->tx_tfc_lv,
3373 stats->rx_throughput, stats->rx_throughput_raw, stats->rx_tfc_lv);
3374 seq_printf(m, "Beacon: %u, TF: %u\n", pkt_stat->beacon_nr,
3375 stats->rx_tf_periodic);
3376 seq_printf(m, "Avg packet length: TX=%u, RX=%u\n", stats->tx_avg_len,
3377 stats->rx_avg_len);
3378
3379 seq_puts(m, "RX count:\n");
3380
3381 for (i = 0; i < ARRAY_SIZE(rtw89_rx_rate_cnt_infos); i++) {
3382 info = &rtw89_rx_rate_cnt_infos[i];
3383 first_rate = info->first_rate[chip->chip_gen];
3384 if (first_rate >= RTW89_HW_RATE_NR)
3385 continue;
3386
3387 seq_printf(m, "%10s [", info->rate_mode);
3388 rtw89_debug_append_rx_rate(m, pkt_stat,
3389 first_rate, info->len);
3390 if (info->ext) {
3391 seq_puts(m, "][");
3392 rtw89_debug_append_rx_rate(m, pkt_stat,
3393 first_rate + info->len, info->ext);
3394 }
3395 seq_puts(m, "]\n");
3396 }
3397
3398 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_info_get_iter, m);
3399
3400 return 0;
3401 }
3402
rtw89_dump_addr_cam(struct seq_file * m,struct rtw89_addr_cam_entry * addr_cam)3403 static void rtw89_dump_addr_cam(struct seq_file *m,
3404 struct rtw89_addr_cam_entry *addr_cam)
3405 {
3406 struct rtw89_sec_cam_entry *sec_entry;
3407 int i;
3408
3409 seq_printf(m, "\taddr_cam_idx=%u\n", addr_cam->addr_cam_idx);
3410 seq_printf(m, "\t-> bssid_cam_idx=%u\n", addr_cam->bssid_cam_idx);
3411 seq_printf(m, "\tsec_cam_bitmap=%*ph\n", (int)sizeof(addr_cam->sec_cam_map),
3412 addr_cam->sec_cam_map);
3413 for (i = 0; i < RTW89_SEC_CAM_IN_ADDR_CAM; i++) {
3414 sec_entry = addr_cam->sec_entries[i];
3415 if (!sec_entry)
3416 continue;
3417 seq_printf(m, "\tsec[%d]: sec_cam_idx %u", i, sec_entry->sec_cam_idx);
3418 if (sec_entry->ext_key)
3419 seq_printf(m, ", %u", sec_entry->sec_cam_idx + 1);
3420 seq_puts(m, "\n");
3421 }
3422 }
3423
3424 __printf(3, 4)
rtw89_dump_pkt_offload(struct seq_file * m,struct list_head * pkt_list,const char * fmt,...)3425 static void rtw89_dump_pkt_offload(struct seq_file *m, struct list_head *pkt_list,
3426 const char *fmt, ...)
3427 {
3428 struct rtw89_pktofld_info *info;
3429 struct va_format vaf;
3430 va_list args;
3431
3432 if (list_empty(pkt_list))
3433 return;
3434
3435 va_start(args, fmt);
3436 vaf.va = &args;
3437 vaf.fmt = fmt;
3438
3439 seq_printf(m, "%pV", &vaf);
3440
3441 va_end(args);
3442
3443 list_for_each_entry(info, pkt_list, list)
3444 seq_printf(m, "%d ", info->id);
3445
3446 seq_puts(m, "\n");
3447 }
3448
3449 static
rtw89_vif_ids_get_iter(void * data,u8 * mac,struct ieee80211_vif * vif)3450 void rtw89_vif_ids_get_iter(void *data, u8 *mac, struct ieee80211_vif *vif)
3451 {
3452 struct rtw89_vif *rtwvif = (struct rtw89_vif *)vif->drv_priv;
3453 struct seq_file *m = (struct seq_file *)data;
3454 struct rtw89_bssid_cam_entry *bssid_cam = &rtwvif->bssid_cam;
3455
3456 seq_printf(m, "VIF [%d] %pM\n", rtwvif->mac_id, rtwvif->mac_addr);
3457 seq_printf(m, "\tbssid_cam_idx=%u\n", bssid_cam->bssid_cam_idx);
3458 rtw89_dump_addr_cam(m, &rtwvif->addr_cam);
3459 rtw89_dump_pkt_offload(m, &rtwvif->general_pkt_list, "\tpkt_ofld[GENERAL]: ");
3460 }
3461
rtw89_dump_ba_cam(struct seq_file * m,struct rtw89_sta * rtwsta)3462 static void rtw89_dump_ba_cam(struct seq_file *m, struct rtw89_sta *rtwsta)
3463 {
3464 struct rtw89_vif *rtwvif = rtwsta->rtwvif;
3465 struct rtw89_dev *rtwdev = rtwvif->rtwdev;
3466 struct rtw89_ba_cam_entry *entry;
3467 bool first = true;
3468
3469 list_for_each_entry(entry, &rtwsta->ba_cam_list, list) {
3470 if (first) {
3471 seq_puts(m, "\tba_cam ");
3472 first = false;
3473 } else {
3474 seq_puts(m, ", ");
3475 }
3476 seq_printf(m, "tid[%u]=%d", entry->tid,
3477 (int)(entry - rtwdev->cam_info.ba_cam_entry));
3478 }
3479 seq_puts(m, "\n");
3480 }
3481
rtw89_sta_ids_get_iter(void * data,struct ieee80211_sta * sta)3482 static void rtw89_sta_ids_get_iter(void *data, struct ieee80211_sta *sta)
3483 {
3484 struct rtw89_sta *rtwsta = (struct rtw89_sta *)sta->drv_priv;
3485 struct seq_file *m = (struct seq_file *)data;
3486
3487 seq_printf(m, "STA [%d] %pM %s\n", rtwsta->mac_id, sta->addr,
3488 sta->tdls ? "(TDLS)" : "");
3489 rtw89_dump_addr_cam(m, &rtwsta->addr_cam);
3490 rtw89_dump_ba_cam(m, rtwsta);
3491 }
3492
rtw89_debug_priv_stations_get(struct seq_file * m,void * v)3493 static int rtw89_debug_priv_stations_get(struct seq_file *m, void *v)
3494 {
3495 struct rtw89_debugfs_priv *debugfs_priv = m->private;
3496 struct rtw89_dev *rtwdev = debugfs_priv->rtwdev;
3497 struct rtw89_cam_info *cam_info = &rtwdev->cam_info;
3498 u8 idx;
3499
3500 mutex_lock(&rtwdev->mutex);
3501
3502 seq_puts(m, "map:\n");
3503 seq_printf(m, "\tmac_id: %*ph\n", (int)sizeof(rtwdev->mac_id_map),
3504 rtwdev->mac_id_map);
3505 seq_printf(m, "\taddr_cam: %*ph\n", (int)sizeof(cam_info->addr_cam_map),
3506 cam_info->addr_cam_map);
3507 seq_printf(m, "\tbssid_cam: %*ph\n", (int)sizeof(cam_info->bssid_cam_map),
3508 cam_info->bssid_cam_map);
3509 seq_printf(m, "\tsec_cam: %*ph\n", (int)sizeof(cam_info->sec_cam_map),
3510 cam_info->sec_cam_map);
3511 seq_printf(m, "\tba_cam: %*ph\n", (int)sizeof(cam_info->ba_cam_map),
3512 cam_info->ba_cam_map);
3513 seq_printf(m, "\tpkt_ofld: %*ph\n", (int)sizeof(rtwdev->pkt_offload),
3514 rtwdev->pkt_offload);
3515
3516 for (idx = NL80211_BAND_2GHZ; idx < NUM_NL80211_BANDS; idx++) {
3517 if (!(rtwdev->chip->support_bands & BIT(idx)))
3518 continue;
3519 rtw89_dump_pkt_offload(m, &rtwdev->scan_info.pkt_list[idx],
3520 "\t\t[SCAN %u]: ", idx);
3521 }
3522
3523 ieee80211_iterate_active_interfaces_atomic(rtwdev->hw,
3524 IEEE80211_IFACE_ITER_NORMAL, rtw89_vif_ids_get_iter, m);
3525
3526 ieee80211_iterate_stations_atomic(rtwdev->hw, rtw89_sta_ids_get_iter, m);
3527
3528 mutex_unlock(&rtwdev->mutex);
3529
3530 return 0;
3531 }
3532
3533 static struct rtw89_debugfs_priv rtw89_debug_priv_read_reg = {
3534 .cb_read = rtw89_debug_priv_read_reg_get,
3535 .cb_write = rtw89_debug_priv_read_reg_select,
3536 };
3537
3538 static struct rtw89_debugfs_priv rtw89_debug_priv_write_reg = {
3539 .cb_write = rtw89_debug_priv_write_reg_set,
3540 };
3541
3542 static struct rtw89_debugfs_priv rtw89_debug_priv_read_rf = {
3543 .cb_read = rtw89_debug_priv_read_rf_get,
3544 .cb_write = rtw89_debug_priv_read_rf_select,
3545 };
3546
3547 static struct rtw89_debugfs_priv rtw89_debug_priv_write_rf = {
3548 .cb_write = rtw89_debug_priv_write_rf_set,
3549 };
3550
3551 static struct rtw89_debugfs_priv rtw89_debug_priv_rf_reg_dump = {
3552 .cb_read = rtw89_debug_priv_rf_reg_dump_get,
3553 };
3554
3555 static struct rtw89_debugfs_priv rtw89_debug_priv_txpwr_table = {
3556 .cb_read = rtw89_debug_priv_txpwr_table_get,
3557 };
3558
3559 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_reg_dump = {
3560 .cb_read = rtw89_debug_priv_mac_reg_dump_get,
3561 .cb_write = rtw89_debug_priv_mac_reg_dump_select,
3562 };
3563
3564 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_mem_dump = {
3565 .cb_read = rtw89_debug_priv_mac_mem_dump_get,
3566 .cb_write = rtw89_debug_priv_mac_mem_dump_select,
3567 };
3568
3569 static struct rtw89_debugfs_priv rtw89_debug_priv_mac_dbg_port_dump = {
3570 .cb_read = rtw89_debug_priv_mac_dbg_port_dump_get,
3571 .cb_write = rtw89_debug_priv_mac_dbg_port_dump_select,
3572 };
3573
3574 static struct rtw89_debugfs_priv rtw89_debug_priv_send_h2c = {
3575 .cb_write = rtw89_debug_priv_send_h2c_set,
3576 };
3577
3578 static struct rtw89_debugfs_priv rtw89_debug_priv_early_h2c = {
3579 .cb_read = rtw89_debug_priv_early_h2c_get,
3580 .cb_write = rtw89_debug_priv_early_h2c_set,
3581 };
3582
3583 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_crash = {
3584 .cb_read = rtw89_debug_priv_fw_crash_get,
3585 .cb_write = rtw89_debug_priv_fw_crash_set,
3586 };
3587
3588 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_info = {
3589 .cb_read = rtw89_debug_priv_btc_info_get,
3590 };
3591
3592 static struct rtw89_debugfs_priv rtw89_debug_priv_btc_manual = {
3593 .cb_write = rtw89_debug_priv_btc_manual_set,
3594 };
3595
3596 static struct rtw89_debugfs_priv rtw89_debug_priv_fw_log_manual = {
3597 .cb_write = rtw89_debug_fw_log_manual_set,
3598 };
3599
3600 static struct rtw89_debugfs_priv rtw89_debug_priv_phy_info = {
3601 .cb_read = rtw89_debug_priv_phy_info_get,
3602 };
3603
3604 static struct rtw89_debugfs_priv rtw89_debug_priv_stations = {
3605 .cb_read = rtw89_debug_priv_stations_get,
3606 };
3607
3608 #define rtw89_debugfs_add(name, mode, fopname, parent) \
3609 do { \
3610 rtw89_debug_priv_ ##name.rtwdev = rtwdev; \
3611 if (!debugfs_create_file(#name, mode, \
3612 parent, &rtw89_debug_priv_ ##name, \
3613 &file_ops_ ##fopname)) \
3614 pr_debug("Unable to initialize debugfs:%s\n", #name); \
3615 } while (0)
3616
3617 #define rtw89_debugfs_add_w(name) \
3618 rtw89_debugfs_add(name, S_IFREG | 0222, single_w, debugfs_topdir)
3619 #define rtw89_debugfs_add_rw(name) \
3620 rtw89_debugfs_add(name, S_IFREG | 0666, common_rw, debugfs_topdir)
3621 #define rtw89_debugfs_add_r(name) \
3622 rtw89_debugfs_add(name, S_IFREG | 0444, single_r, debugfs_topdir)
3623
rtw89_debugfs_init(struct rtw89_dev * rtwdev)3624 void rtw89_debugfs_init(struct rtw89_dev *rtwdev)
3625 {
3626 struct dentry *debugfs_topdir;
3627
3628 debugfs_topdir = debugfs_create_dir("rtw89",
3629 rtwdev->hw->wiphy->debugfsdir);
3630
3631 rtw89_debugfs_add_rw(read_reg);
3632 rtw89_debugfs_add_w(write_reg);
3633 rtw89_debugfs_add_rw(read_rf);
3634 rtw89_debugfs_add_w(write_rf);
3635 rtw89_debugfs_add_r(rf_reg_dump);
3636 rtw89_debugfs_add_r(txpwr_table);
3637 rtw89_debugfs_add_rw(mac_reg_dump);
3638 rtw89_debugfs_add_rw(mac_mem_dump);
3639 rtw89_debugfs_add_rw(mac_dbg_port_dump);
3640 rtw89_debugfs_add_w(send_h2c);
3641 rtw89_debugfs_add_rw(early_h2c);
3642 rtw89_debugfs_add_rw(fw_crash);
3643 rtw89_debugfs_add_r(btc_info);
3644 rtw89_debugfs_add_w(btc_manual);
3645 rtw89_debugfs_add_w(fw_log_manual);
3646 rtw89_debugfs_add_r(phy_info);
3647 rtw89_debugfs_add_r(stations);
3648 }
3649 #endif
3650
3651 #ifdef CONFIG_RTW89_DEBUGMSG
__rtw89_debug(struct rtw89_dev * rtwdev,enum rtw89_debug_mask mask,const char * fmt,...)3652 void __rtw89_debug(struct rtw89_dev *rtwdev,
3653 enum rtw89_debug_mask mask,
3654 const char *fmt, ...)
3655 {
3656 struct va_format vaf = {
3657 .fmt = fmt,
3658 };
3659
3660 va_list args;
3661
3662 va_start(args, fmt);
3663 vaf.va = &args;
3664
3665 if (rtw89_debug_mask & mask)
3666 dev_printk(KERN_DEBUG, rtwdev->dev, "%pV", &vaf);
3667
3668 va_end(args);
3669 }
3670 EXPORT_SYMBOL(__rtw89_debug);
3671 #endif
3672