xref: /openbmc/u-boot/include/configs/rsk7203.h (revision cf033e04)
1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Configuation settings for the Renesas Technology RSK 7203
4  *
5  * Copyright (C) 2008 Nobuhiro Iwamatsu
6  * Copyright (C) 2008 Renesas Solutions Corp.
7  */
8 
9 #ifndef __RSK7203_H
10 #define __RSK7203_H
11 
12 #define CONFIG_CPU_SH7203	1
13 
14 #define CONFIG_LOADADDR		0x0C100000 /* RSK7203_SDRAM_BASE + 1MB */
15 
16 #define CONFIG_DISPLAY_BOARDINFO
17 #undef	CONFIG_SHOW_BOOT_PROGRESS
18 
19 /* MEMORY */
20 #define RSK7203_SDRAM_BASE	0x0C000000
21 #define RSK7203_FLASH_BASE_1	0x20000000	/* Non cache */
22 #define RSK7203_FLASH_BANK_SIZE	(4 * 1024 * 1024)
23 
24 /* List of legal baudrate settings for this board */
25 #define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }
26 
27 /* SCIF */
28 #define CONFIG_CONS_SCIF0	1
29 
30 #define CONFIG_SYS_MEMTEST_START	RSK7203_SDRAM_BASE
31 #define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + (3 * 1024 * 1024))
32 
33 #define CONFIG_SYS_SDRAM_BASE		RSK7203_SDRAM_BASE
34 #define CONFIG_SYS_SDRAM_SIZE		(32 * 1024 * 1024)
35 
36 #define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 1024 * 1024)
37 #define CONFIG_SYS_MONITOR_BASE	RSK7203_FLASH_BASE_1
38 #define CONFIG_SYS_MONITOR_LEN		(128 * 1024)
39 #define CONFIG_SYS_MALLOC_LEN		(256 * 1024)
40 #define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)
41 
42 /* FLASH */
43 #define CONFIG_SYS_FLASH_CFI_WIDTH FLASH_CFI_16BIT
44 #undef	CONFIG_SYS_FLASH_QUIET_TEST
45 #define CONFIG_SYS_FLASH_EMPTY_INFO	/* print 'E' for empty sector on flinfo */
46 #define CONFIG_SYS_FLASH_BASE		RSK7203_FLASH_BASE_1
47 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_FLASH_BASE }
48 #define CONFIG_SYS_MAX_FLASH_SECT	64
49 #define CONFIG_SYS_MAX_FLASH_BANKS	1
50 
51 #define CONFIG_ENV_SECT_SIZE	(64 * 1024)
52 #define CONFIG_ENV_SIZE		CONFIG_ENV_SECT_SIZE
53 #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
54 #define CONFIG_SYS_FLASH_ERASE_TOUT	12000
55 #define CONFIG_SYS_FLASH_WRITE_TOUT	500
56 
57 /* Board Clock */
58 #define CONFIG_SYS_CLK_FREQ	33333333
59 #define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
60 #define CMT_CLK_DIVIDER	32	/* 8 (default), 32, 128 or 512 */
61 #define CONFIG_SH_CMT_CLK_FREQ (CONFIG_SYS_CLK_FREQ / CMT_CLK_DIVIDER)
62 
63 #endif	/* __RSK7203_H */
64