1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Renesas RCar Gen3 RPC Hyperflash driver
4 *
5 * Copyright (C) 2016 Renesas Electronics Corporation
6 * Copyright (C) 2016 Cogent Embedded, Inc.
7 * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
8 */
9
10 #include <common.h>
11 #include <asm/io.h>
12 #include <clk.h>
13 #include <dm.h>
14 #include <dm/of_access.h>
15 #include <errno.h>
16 #include <fdt_support.h>
17 #include <flash.h>
18 #include <mtd.h>
19 #include <wait_bit.h>
20 #include <mtd/cfi_flash.h>
21
22 #define RPC_CMNCR 0x0000 /* R/W */
23 #define RPC_CMNCR_MD BIT(31)
24 #define RPC_CMNCR_MOIIO0(val) (((val) & 0x3) << 16)
25 #define RPC_CMNCR_MOIIO1(val) (((val) & 0x3) << 18)
26 #define RPC_CMNCR_MOIIO2(val) (((val) & 0x3) << 20)
27 #define RPC_CMNCR_MOIIO3(val) (((val) & 0x3) << 22)
28 #define RPC_CMNCR_MOIIO_HIZ (RPC_CMNCR_MOIIO0(3) | RPC_CMNCR_MOIIO1(3) | \
29 RPC_CMNCR_MOIIO2(3) | RPC_CMNCR_MOIIO3(3))
30 #define RPC_CMNCR_IO0FV(val) (((val) & 0x3) << 8)
31 #define RPC_CMNCR_IO2FV(val) (((val) & 0x3) << 12)
32 #define RPC_CMNCR_IO3FV(val) (((val) & 0x3) << 14)
33 #define RPC_CMNCR_IOFV_HIZ (RPC_CMNCR_IO0FV(3) | RPC_CMNCR_IO2FV(3) | \
34 RPC_CMNCR_IO3FV(3))
35 #define RPC_CMNCR_BSZ(val) (((val) & 0x3) << 0)
36
37 #define RPC_SSLDR 0x0004 /* R/W */
38 #define RPC_SSLDR_SPNDL(d) (((d) & 0x7) << 16)
39 #define RPC_SSLDR_SLNDL(d) (((d) & 0x7) << 8)
40 #define RPC_SSLDR_SCKDL(d) (((d) & 0x7) << 0)
41
42 #define RPC_DRCR 0x000C /* R/W */
43 #define RPC_DRCR_SSLN BIT(24)
44 #define RPC_DRCR_RBURST(v) (((v) & 0x1F) << 16)
45 #define RPC_DRCR_RCF BIT(9)
46 #define RPC_DRCR_RBE BIT(8)
47 #define RPC_DRCR_SSLE BIT(0)
48
49 #define RPC_DRCMR 0x0010 /* R/W */
50 #define RPC_DRCMR_CMD(c) (((c) & 0xFF) << 16)
51 #define RPC_DRCMR_OCMD(c) (((c) & 0xFF) << 0)
52
53 #define RPC_DREAR 0x0014 /* R/W */
54 #define RPC_DREAR_EAV(v) (((v) & 0xFF) << 16)
55 #define RPC_DREAR_EAC(v) (((v) & 0x7) << 0)
56
57 #define RPC_DROPR 0x0018 /* R/W */
58 #define RPC_DROPR_OPD3(o) (((o) & 0xFF) << 24)
59 #define RPC_DROPR_OPD2(o) (((o) & 0xFF) << 16)
60 #define RPC_DROPR_OPD1(o) (((o) & 0xFF) << 8)
61 #define RPC_DROPR_OPD0(o) (((o) & 0xFF) << 0)
62
63 #define RPC_DRENR 0x001C /* R/W */
64 #define RPC_DRENR_CDB(o) (u32)((((o) & 0x3) << 30))
65 #define RPC_DRENR_OCDB(o) (((o) & 0x3) << 28)
66 #define RPC_DRENR_ADB(o) (((o) & 0x3) << 24)
67 #define RPC_DRENR_OPDB(o) (((o) & 0x3) << 20)
68 #define RPC_DRENR_SPIDB(o) (((o) & 0x3) << 16)
69 #define RPC_DRENR_DME BIT(15)
70 #define RPC_DRENR_CDE BIT(14)
71 #define RPC_DRENR_OCDE BIT(12)
72 #define RPC_DRENR_ADE(v) (((v) & 0xF) << 8)
73 #define RPC_DRENR_OPDE(v) (((v) & 0xF) << 4)
74
75 #define RPC_SMCR 0x0020 /* R/W */
76 #define RPC_SMCR_SSLKP BIT(8)
77 #define RPC_SMCR_SPIRE BIT(2)
78 #define RPC_SMCR_SPIWE BIT(1)
79 #define RPC_SMCR_SPIE BIT(0)
80
81 #define RPC_SMCMR 0x0024 /* R/W */
82 #define RPC_SMCMR_CMD(c) (((c) & 0xFF) << 16)
83 #define RPC_SMCMR_OCMD(c) (((c) & 0xFF) << 0)
84
85 #define RPC_SMADR 0x0028 /* R/W */
86 #define RPC_SMOPR 0x002C /* R/W */
87 #define RPC_SMOPR_OPD0(o) (((o) & 0xFF) << 0)
88 #define RPC_SMOPR_OPD1(o) (((o) & 0xFF) << 8)
89 #define RPC_SMOPR_OPD2(o) (((o) & 0xFF) << 16)
90 #define RPC_SMOPR_OPD3(o) (((o) & 0xFF) << 24)
91
92 #define RPC_SMENR 0x0030 /* R/W */
93 #define RPC_SMENR_CDB(o) (((o) & 0x3) << 30)
94 #define RPC_SMENR_OCDB(o) (((o) & 0x3) << 28)
95 #define RPC_SMENR_ADB(o) (((o) & 0x3) << 24)
96 #define RPC_SMENR_OPDB(o) (((o) & 0x3) << 20)
97 #define RPC_SMENR_SPIDB(o) (((o) & 0x3) << 16)
98 #define RPC_SMENR_DME BIT(15)
99 #define RPC_SMENR_CDE BIT(14)
100 #define RPC_SMENR_OCDE BIT(12)
101 #define RPC_SMENR_ADE(v) (((v) & 0xF) << 8)
102 #define RPC_SMENR_OPDE(v) (((v) & 0xF) << 4)
103 #define RPC_SMENR_SPIDE(v) (((v) & 0xF) << 0)
104
105 #define RPC_SMRDR0 0x0038 /* R */
106 #define RPC_SMRDR1 0x003C /* R */
107 #define RPC_SMWDR0 0x0040 /* R/W */
108 #define RPC_SMWDR1 0x0044 /* R/W */
109 #define RPC_CMNSR 0x0048 /* R */
110 #define RPC_CMNSR_SSLF BIT(1)
111 #define RPC_CMNSR_TEND BIT(0)
112
113 #define RPC_DRDMCR 0x0058 /* R/W */
114 #define RPC_DRDMCR_DMCYC(v) (((v) & 0xF) << 0)
115
116 #define RPC_DRDRENR 0x005C /* R/W */
117 #define RPC_DRDRENR_HYPE (0x5 << 12)
118 #define RPC_DRDRENR_ADDRE BIT(8)
119 #define RPC_DRDRENR_OPDRE BIT(4)
120 #define RPC_DRDRENR_DRDRE BIT(0)
121
122 #define RPC_SMDMCR 0x0060 /* R/W */
123 #define RPC_SMDMCR_DMCYC(v) (((v) & 0xF) << 0)
124
125 #define RPC_SMDRENR 0x0064 /* R/W */
126 #define RPC_SMDRENR_HYPE (0x5 << 12)
127 #define RPC_SMDRENR_ADDRE BIT(8)
128 #define RPC_SMDRENR_OPDRE BIT(4)
129 #define RPC_SMDRENR_SPIDRE BIT(0)
130
131 #define RPC_PHYCNT 0x007C /* R/W */
132 #define RPC_PHYCNT_CAL BIT(31)
133 #define PRC_PHYCNT_OCTA_AA BIT(22)
134 #define PRC_PHYCNT_OCTA_SA BIT(23)
135 #define PRC_PHYCNT_EXDS BIT(21)
136 #define RPC_PHYCNT_OCT BIT(20)
137 #define RPC_PHYCNT_WBUF2 BIT(4)
138 #define RPC_PHYCNT_WBUF BIT(2)
139 #define RPC_PHYCNT_MEM(v) (((v) & 0x3) << 0)
140
141 #define RPC_PHYINT 0x0088 /* R/W */
142 #define RPC_PHYINT_RSTEN BIT(18)
143 #define RPC_PHYINT_WPEN BIT(17)
144 #define RPC_PHYINT_INTEN BIT(16)
145 #define RPC_PHYINT_RST BIT(2)
146 #define RPC_PHYINT_WP BIT(1)
147 #define RPC_PHYINT_INT BIT(0)
148
149 #define RPC_WBUF 0x8000 /* R/W size=4/8/16/32/64Bytes */
150 #define RPC_WBUF_SIZE 0x100
151
152 static phys_addr_t rpc_base;
153
154 enum rpc_hf_size {
155 RPC_HF_SIZE_16BIT = RPC_SMENR_SPIDE(0x8),
156 RPC_HF_SIZE_32BIT = RPC_SMENR_SPIDE(0xC),
157 RPC_HF_SIZE_64BIT = RPC_SMENR_SPIDE(0xF),
158 };
159
rpc_hf_wait_tend(void)160 static int rpc_hf_wait_tend(void)
161 {
162 void __iomem *reg = (void __iomem *)rpc_base + RPC_CMNSR;
163 return wait_for_bit_le32(reg, RPC_CMNSR_TEND, true, 1000, 0);
164 }
165
rpc_hf_mode(bool man)166 static int rpc_hf_mode(bool man)
167 {
168 int ret;
169
170 ret = rpc_hf_wait_tend();
171 if (ret)
172 return ret;
173
174 clrsetbits_le32(rpc_base + RPC_PHYCNT,
175 RPC_PHYCNT_WBUF | RPC_PHYCNT_WBUF2 |
176 RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3),
177 RPC_PHYCNT_CAL | RPC_PHYCNT_MEM(3));
178
179 clrsetbits_le32(rpc_base + RPC_CMNCR,
180 RPC_CMNCR_MD | RPC_CMNCR_BSZ(3),
181 RPC_CMNCR_MOIIO_HIZ | RPC_CMNCR_IOFV_HIZ |
182 (man ? RPC_CMNCR_MD : 0) | RPC_CMNCR_BSZ(1));
183
184 if (man)
185 return 0;
186
187 writel(RPC_DRCR_RBURST(0x1F) | RPC_DRCR_RCF | RPC_DRCR_RBE,
188 rpc_base + RPC_DRCR);
189
190 writel(RPC_DRCMR_CMD(0xA0), rpc_base + RPC_DRCMR);
191 writel(RPC_DRENR_CDB(2) | RPC_DRENR_OCDB(2) | RPC_DRENR_ADB(2) |
192 RPC_DRENR_SPIDB(2) | RPC_DRENR_CDE | RPC_DRENR_OCDE |
193 RPC_DRENR_ADE(4), rpc_base + RPC_DRENR);
194 writel(RPC_DRDMCR_DMCYC(0xE), rpc_base + RPC_DRDMCR);
195 writel(RPC_DRDRENR_HYPE | RPC_DRDRENR_ADDRE | RPC_DRDRENR_DRDRE,
196 rpc_base + RPC_DRDRENR);
197
198 /* Dummy read */
199 readl(rpc_base + RPC_DRCR);
200
201 return 0;
202 }
203
rpc_hf_xfer(void * addr,u64 wdata,u64 * rdata,enum rpc_hf_size size,bool write)204 static int rpc_hf_xfer(void *addr, u64 wdata, u64 *rdata,
205 enum rpc_hf_size size, bool write)
206 {
207 int ret;
208 u32 val;
209
210 ret = rpc_hf_mode(1);
211 if (ret)
212 return ret;
213
214 /* Submit HF address, SMCMR CMD[7] ~= CA Bit# 47 (R/nW) */
215 writel(write ? 0 : RPC_SMCMR_CMD(0x80), rpc_base + RPC_SMCMR);
216 writel((uintptr_t)addr >> 1, rpc_base + RPC_SMADR);
217 writel(0x0, rpc_base + RPC_SMOPR);
218
219 writel(RPC_SMDRENR_HYPE | RPC_SMDRENR_ADDRE | RPC_SMDRENR_SPIDRE,
220 rpc_base + RPC_SMDRENR);
221
222 val = RPC_SMENR_CDB(2) | RPC_SMENR_OCDB(2) |
223 RPC_SMENR_ADB(2) | RPC_SMENR_SPIDB(2) |
224 RPC_SMENR_CDE | RPC_SMENR_OCDE | RPC_SMENR_ADE(4) | size;
225
226 if (write) {
227 writel(val, rpc_base + RPC_SMENR);
228
229 if (size == RPC_HF_SIZE_64BIT)
230 writeq(cpu_to_be64(wdata), rpc_base + RPC_SMWDR0);
231 else
232 writel(cpu_to_be32(wdata), rpc_base + RPC_SMWDR0);
233
234 writel(RPC_SMCR_SPIWE | RPC_SMCR_SPIE, rpc_base + RPC_SMCR);
235 } else {
236 val |= RPC_SMENR_DME;
237
238 writel(RPC_SMDMCR_DMCYC(0xE), rpc_base + RPC_SMDMCR);
239
240 writel(val, rpc_base + RPC_SMENR);
241
242 writel(RPC_SMCR_SPIRE | RPC_SMCR_SPIE, rpc_base + RPC_SMCR);
243
244 ret = rpc_hf_wait_tend();
245 if (ret)
246 return ret;
247
248 if (size == RPC_HF_SIZE_64BIT)
249 *rdata = be64_to_cpu(readq(rpc_base + RPC_SMRDR0));
250 else
251 *rdata = be32_to_cpu(readl(rpc_base + RPC_SMRDR0));
252 }
253
254 return rpc_hf_mode(0);
255 }
256
rpc_hf_write_cmd(void * addr,u64 wdata,enum rpc_hf_size size)257 static void rpc_hf_write_cmd(void *addr, u64 wdata, enum rpc_hf_size size)
258 {
259 int ret;
260
261 ret = rpc_hf_xfer(addr, wdata, NULL, size, 1);
262 if (ret)
263 printf("RPC: Write failed, ret=%i\n", ret);
264 }
265
rpc_hf_read_reg(void * addr,enum rpc_hf_size size)266 static u64 rpc_hf_read_reg(void *addr, enum rpc_hf_size size)
267 {
268 u64 rdata = 0;
269 int ret;
270
271 ret = rpc_hf_xfer(addr, 0, &rdata, size, 0);
272 if (ret)
273 printf("RPC: Read failed, ret=%i\n", ret);
274
275 return rdata;
276 }
277
flash_write8(u8 value,void * addr)278 void flash_write8(u8 value, void *addr)
279 {
280 rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_16BIT);
281 }
282
flash_write16(u16 value,void * addr)283 void flash_write16(u16 value, void *addr)
284 {
285 rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_16BIT);
286 }
287
flash_write32(u32 value,void * addr)288 void flash_write32(u32 value, void *addr)
289 {
290 rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_32BIT);
291 }
292
flash_write64(u64 value,void * addr)293 void flash_write64(u64 value, void *addr)
294 {
295 rpc_hf_write_cmd(addr, value, RPC_HF_SIZE_64BIT);
296 }
297
flash_read8(void * addr)298 u8 flash_read8(void *addr)
299 {
300 return rpc_hf_read_reg(addr, RPC_HF_SIZE_16BIT);
301 }
302
flash_read16(void * addr)303 u16 flash_read16(void *addr)
304 {
305 return rpc_hf_read_reg(addr, RPC_HF_SIZE_16BIT);
306 }
307
flash_read32(void * addr)308 u32 flash_read32(void *addr)
309 {
310 return rpc_hf_read_reg(addr, RPC_HF_SIZE_32BIT);
311 }
312
flash_read64(void * addr)313 u64 flash_read64(void *addr)
314 {
315 return rpc_hf_read_reg(addr, RPC_HF_SIZE_64BIT);
316 }
317
rpc_hf_bind(struct udevice * parent)318 static int rpc_hf_bind(struct udevice *parent)
319 {
320 const void *fdt = gd->fdt_blob;
321 ofnode node;
322 int ret, off;
323
324 /*
325 * Check if there are any SPI NOR child nodes, if so, do NOT bind
326 * as this controller will be operated by the QSPI driver instead.
327 */
328 dev_for_each_subnode(node, parent) {
329 off = ofnode_to_offset(node);
330
331 ret = fdt_node_check_compatible(fdt, off, "spi-flash");
332 if (!ret)
333 return -ENODEV;
334
335 ret = fdt_node_check_compatible(fdt, off, "jedec,spi-nor");
336 if (!ret)
337 return -ENODEV;
338 }
339
340 return 0;
341 }
342
rpc_hf_probe(struct udevice * dev)343 static int rpc_hf_probe(struct udevice *dev)
344 {
345 void *blob = (void *)gd->fdt_blob;
346 const fdt32_t *cell;
347 int node = dev_of_offset(dev);
348 int parent, addrc, sizec, len, ret;
349 struct clk clk;
350 phys_addr_t flash_base;
351
352 parent = fdt_parent_offset(blob, node);
353 fdt_support_default_count_cells(blob, parent, &addrc, &sizec);
354 cell = fdt_getprop(blob, node, "reg", &len);
355 if (!cell)
356 return -ENOENT;
357
358 if (addrc != 2 || sizec != 2)
359 return -EINVAL;
360
361
362 ret = clk_get_by_index(dev, 0, &clk);
363 if (ret < 0) {
364 dev_err(dev, "Failed to get RPC clock\n");
365 return ret;
366 }
367
368 ret = clk_enable(&clk);
369 clk_free(&clk);
370 if (ret) {
371 dev_err(dev, "Failed to enable RPC clock\n");
372 return ret;
373 }
374
375 rpc_base = fdt_translate_address(blob, node, cell);
376 flash_base = fdt_translate_address(blob, node, cell + addrc + sizec);
377
378 flash_info[0].dev = dev;
379 flash_info[0].base = flash_base;
380 cfi_flash_num_flash_banks = 1;
381 gd->bd->bi_flashstart = flash_base;
382
383 return 0;
384 }
385
386 static const struct udevice_id rpc_hf_ids[] = {
387 { .compatible = "renesas,rpc" },
388 {}
389 };
390
391 U_BOOT_DRIVER(rpc_hf) = {
392 .name = "rpc_hf",
393 .id = UCLASS_MTD,
394 .of_match = rpc_hf_ids,
395 .bind = rpc_hf_bind,
396 .probe = rpc_hf_probe,
397 };
398