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Searched defs:RISCVCPUClass (Results 1 – 1 of 1) sorted by relevance

/openbmc/qemu/target/riscv/
H A Dcpu.h523 struct RISCVCPUClass { struct
524 CPUClass parent_class;
526 DeviceRealize parent_realize;
527 ResettablePhases parent_phases;
528 uint32_t misa_mxl_max; /* max mxl for this cpu */