1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * H/W layer of ISHTP provider device (ISH)
4  *
5  * Copyright (c) 2014-2016, Intel Corporation.
6  */
7 
8 #ifndef _ISHTP_HW_ISH_H_
9 #define _ISHTP_HW_ISH_H_
10 
11 #include <linux/pci.h>
12 #include <linux/interrupt.h>
13 #include "hw-ish-regs.h"
14 #include "ishtp-dev.h"
15 
16 #define CHV_DEVICE_ID		0x22D8
17 #define BXT_Ax_DEVICE_ID	0x0AA2
18 #define BXT_Bx_DEVICE_ID	0x1AA2
19 #define APL_Ax_DEVICE_ID	0x5AA2
20 #define SPT_Ax_DEVICE_ID	0x9D35
21 #define CNL_Ax_DEVICE_ID	0x9DFC
22 #define GLK_Ax_DEVICE_ID	0x31A2
23 #define CNL_H_DEVICE_ID		0xA37C
24 #define ICL_MOBILE_DEVICE_ID	0x34FC
25 #define SPT_H_DEVICE_ID		0xA135
26 #define CML_LP_DEVICE_ID	0x02FC
27 #define CMP_H_DEVICE_ID		0x06FC
28 #define EHL_Ax_DEVICE_ID	0x4BB3
29 #define TGL_LP_DEVICE_ID	0xA0FC
30 #define TGL_H_DEVICE_ID		0x43FC
31 #define ADL_S_DEVICE_ID		0x7AF8
32 #define ADL_P_DEVICE_ID		0x51FC
33 #define ADL_N_DEVICE_ID		0x54FC
34 #define RPL_S_DEVICE_ID		0x7A78
35 #define MTL_P_DEVICE_ID		0x7E45
36 #define ARL_H_DEVICE_ID		0x7745
37 
38 #define	REVISION_ID_CHT_A0	0x6
39 #define	REVISION_ID_CHT_Ax_SI	0x0
40 #define	REVISION_ID_CHT_Bx_SI	0x10
41 #define	REVISION_ID_CHT_Kx_SI	0x20
42 #define	REVISION_ID_CHT_Dx_SI	0x30
43 #define	REVISION_ID_CHT_B0	0xB0
44 #define	REVISION_ID_SI_MASK	0x70
45 
46 struct ipc_rst_payload_type {
47 	uint16_t	reset_id;
48 	uint16_t	reserved;
49 };
50 
51 struct time_sync_format {
52 	uint8_t ts1_source;
53 	uint8_t ts2_source;
54 	uint16_t reserved;
55 } __packed;
56 
57 struct ipc_time_update_msg {
58 	uint64_t primary_host_time;
59 	struct time_sync_format sync_info;
60 	uint64_t secondary_host_time;
61 } __packed;
62 
63 enum {
64 	HOST_UTC_TIME_USEC = 0,
65 	HOST_SYSTEM_TIME_USEC = 1
66 };
67 
68 struct ish_hw {
69 	void __iomem *mem_addr;
70 };
71 
72 /*
73  * ISH FW status type
74  */
75 enum {
76 	FWSTS_AFTER_RESET		= 0,
77 	FWSTS_WAIT_FOR_HOST		= 4,
78 	FWSTS_START_KERNEL_DMA		= 5,
79 	FWSTS_FW_IS_RUNNING		= 7,
80 	FWSTS_SENSOR_APP_LOADED		= 8,
81 	FWSTS_SENSOR_APP_RUNNING	= 15
82 };
83 
84 #define to_ish_hw(dev) (struct ish_hw *)((dev)->hw)
85 
86 irqreturn_t ish_irq_handler(int irq, void *dev_id);
87 struct ishtp_device *ish_dev_init(struct pci_dev *pdev);
88 int ish_hw_start(struct ishtp_device *dev);
89 void ish_device_disable(struct ishtp_device *dev);
90 int ish_disable_dma(struct ishtp_device *dev);
91 void ish_set_host_ready(struct ishtp_device *dev);
92 
93 #endif /* _ISHTP_HW_ISH_H_ */
94