xref: /openbmc/u-boot/drivers/mtd/nand/raw/vf610_nfc.c (revision 7e40d0a3)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Copyright 2009-2015 Freescale Semiconductor, Inc. and others
4  *
5  * Description: MPC5125, VF610, MCF54418 and Kinetis K70 Nand driver.
6  * Ported to U-Boot by Stefan Agner
7  * Based on RFC driver posted on Kernel Mailing list by Bill Pringlemeir
8  * Jason ported to M54418TWR and MVFA5.
9  * Authors: Stefan Agner <stefan.agner@toradex.com>
10  *          Bill Pringlemeir <bpringlemeir@nbsps.com>
11  *          Shaohui Xie <b21989@freescale.com>
12  *          Jason Jin <Jason.jin@freescale.com>
13  *
14  * Based on original driver mpc5121_nfc.c.
15  *
16  * Limitations:
17  * - Untested on MPC5125 and M54418.
18  * - DMA and pipelining not used.
19  * - 2K pages or less.
20  * - HW ECC: Only 2K page with 64+ OOB.
21  * - HW ECC: Only 24 and 32-bit error correction implemented.
22  */
23 
24 #include <common.h>
25 #include <malloc.h>
26 
27 #include <linux/mtd/mtd.h>
28 #include <linux/mtd/rawnand.h>
29 #include <linux/mtd/partitions.h>
30 
31 #include <nand.h>
32 #include <errno.h>
33 #include <asm/io.h>
34 #if CONFIG_NAND_VF610_NFC_DT
35 #include <dm.h>
36 #include <linux/io.h>
37 #include <linux/ioport.h>
38 #endif
39 
40 /* Register Offsets */
41 #define NFC_FLASH_CMD1			0x3F00
42 #define NFC_FLASH_CMD2			0x3F04
43 #define NFC_COL_ADDR			0x3F08
44 #define NFC_ROW_ADDR			0x3F0c
45 #define NFC_ROW_ADDR_INC		0x3F14
46 #define NFC_FLASH_STATUS1		0x3F18
47 #define NFC_FLASH_STATUS2		0x3F1c
48 #define NFC_CACHE_SWAP			0x3F28
49 #define NFC_SECTOR_SIZE			0x3F2c
50 #define NFC_FLASH_CONFIG		0x3F30
51 #define NFC_IRQ_STATUS			0x3F38
52 
53 /* Addresses for NFC MAIN RAM BUFFER areas */
54 #define NFC_MAIN_AREA(n)		((n) *  0x1000)
55 
56 #define PAGE_2K				0x0800
57 #define OOB_64				0x0040
58 #define OOB_MAX				0x0100
59 
60 /*
61  * NFC_CMD2[CODE] values. See section:
62  *  - 31.4.7 Flash Command Code Description, Vybrid manual
63  *  - 23.8.6 Flash Command Sequencer, MPC5125 manual
64  *
65  * Briefly these are bitmasks of controller cycles.
66  */
67 #define READ_PAGE_CMD_CODE		0x7EE0
68 #define READ_ONFI_PARAM_CMD_CODE	0x4860
69 #define PROGRAM_PAGE_CMD_CODE		0x7FC0
70 #define ERASE_CMD_CODE			0x4EC0
71 #define READ_ID_CMD_CODE		0x4804
72 #define RESET_CMD_CODE			0x4040
73 #define STATUS_READ_CMD_CODE		0x4068
74 
75 /* NFC ECC mode define */
76 #define ECC_BYPASS			0
77 #define ECC_45_BYTE			6
78 #define ECC_60_BYTE			7
79 
80 /*** Register Mask and bit definitions */
81 
82 /* NFC_FLASH_CMD1 Field */
83 #define CMD_BYTE2_MASK				0xFF000000
84 #define CMD_BYTE2_SHIFT				24
85 
86 /* NFC_FLASH_CM2 Field */
87 #define CMD_BYTE1_MASK				0xFF000000
88 #define CMD_BYTE1_SHIFT				24
89 #define CMD_CODE_MASK				0x00FFFF00
90 #define CMD_CODE_SHIFT				8
91 #define BUFNO_MASK				0x00000006
92 #define BUFNO_SHIFT				1
93 #define START_BIT				(1<<0)
94 
95 /* NFC_COL_ADDR Field */
96 #define COL_ADDR_MASK				0x0000FFFF
97 #define COL_ADDR_SHIFT				0
98 
99 /* NFC_ROW_ADDR Field */
100 #define ROW_ADDR_MASK				0x00FFFFFF
101 #define ROW_ADDR_SHIFT				0
102 #define ROW_ADDR_CHIP_SEL_RB_MASK		0xF0000000
103 #define ROW_ADDR_CHIP_SEL_RB_SHIFT		28
104 #define ROW_ADDR_CHIP_SEL_MASK			0x0F000000
105 #define ROW_ADDR_CHIP_SEL_SHIFT			24
106 
107 /* NFC_FLASH_STATUS2 Field */
108 #define STATUS_BYTE1_MASK			0x000000FF
109 
110 /* NFC_FLASH_CONFIG Field */
111 #define CONFIG_ECC_SRAM_ADDR_MASK		0x7FC00000
112 #define CONFIG_ECC_SRAM_ADDR_SHIFT		22
113 #define CONFIG_ECC_SRAM_REQ_BIT			(1<<21)
114 #define CONFIG_DMA_REQ_BIT			(1<<20)
115 #define CONFIG_ECC_MODE_MASK			0x000E0000
116 #define CONFIG_ECC_MODE_SHIFT			17
117 #define CONFIG_FAST_FLASH_BIT			(1<<16)
118 #define CONFIG_16BIT				(1<<7)
119 #define CONFIG_BOOT_MODE_BIT			(1<<6)
120 #define CONFIG_ADDR_AUTO_INCR_BIT		(1<<5)
121 #define CONFIG_BUFNO_AUTO_INCR_BIT		(1<<4)
122 #define CONFIG_PAGE_CNT_MASK			0xF
123 #define CONFIG_PAGE_CNT_SHIFT			0
124 
125 /* NFC_IRQ_STATUS Field */
126 #define IDLE_IRQ_BIT				(1<<29)
127 #define IDLE_EN_BIT				(1<<20)
128 #define CMD_DONE_CLEAR_BIT			(1<<18)
129 #define IDLE_CLEAR_BIT				(1<<17)
130 
131 #define NFC_TIMEOUT	(1000)
132 
133 /*
134  * ECC status - seems to consume 8 bytes (double word). The documented
135  * status byte is located in the lowest byte of the second word (which is
136  * the 4th or 7th byte depending on endianness).
137  * Calculate an offset to store the ECC status at the end of the buffer.
138  */
139 #define ECC_SRAM_ADDR		(PAGE_2K + OOB_MAX - 8)
140 
141 #define ECC_STATUS		0x4
142 #define ECC_STATUS_MASK		0x80
143 #define ECC_STATUS_ERR_COUNT	0x3F
144 
145 enum vf610_nfc_alt_buf {
146 	ALT_BUF_DATA = 0,
147 	ALT_BUF_ID = 1,
148 	ALT_BUF_STAT = 2,
149 	ALT_BUF_ONFI = 3,
150 };
151 
152 struct vf610_nfc {
153 	struct nand_chip chip;
154 	void __iomem *regs;
155 	uint buf_offset;
156 	int write_sz;
157 	/* Status and ID are in alternate locations. */
158 	enum vf610_nfc_alt_buf alt_buf;
159 };
160 
161 #define mtd_to_nfc(_mtd) nand_get_controller_data(mtd_to_nand(_mtd))
162 
163 #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
164 #define ECC_HW_MODE ECC_45_BYTE
165 
166 static struct nand_ecclayout vf610_nfc_ecc = {
167 	.eccbytes = 45,
168 	.eccpos = {19, 20, 21, 22, 23,
169 		   24, 25, 26, 27, 28, 29, 30, 31,
170 		   32, 33, 34, 35, 36, 37, 38, 39,
171 		   40, 41, 42, 43, 44, 45, 46, 47,
172 		   48, 49, 50, 51, 52, 53, 54, 55,
173 		   56, 57, 58, 59, 60, 61, 62, 63},
174 	.oobfree = {
175 		{.offset = 2,
176 		 .length = 17} }
177 };
178 #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
179 #define ECC_HW_MODE ECC_60_BYTE
180 
181 static struct nand_ecclayout vf610_nfc_ecc = {
182 	.eccbytes = 60,
183 	.eccpos = { 4,  5,  6,  7,  8,  9, 10, 11,
184 		   12, 13, 14, 15, 16, 17, 18, 19,
185 		   20, 21, 22, 23, 24, 25, 26, 27,
186 		   28, 29, 30, 31, 32, 33, 34, 35,
187 		   36, 37, 38, 39, 40, 41, 42, 43,
188 		   44, 45, 46, 47, 48, 49, 50, 51,
189 		   52, 53, 54, 55, 56, 57, 58, 59,
190 		   60, 61, 62, 63 },
191 	.oobfree = {
192 		{.offset = 2,
193 		 .length = 2} }
194 };
195 #endif
196 
vf610_nfc_read(struct mtd_info * mtd,uint reg)197 static inline u32 vf610_nfc_read(struct mtd_info *mtd, uint reg)
198 {
199 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
200 
201 	return readl(nfc->regs + reg);
202 }
203 
vf610_nfc_write(struct mtd_info * mtd,uint reg,u32 val)204 static inline void vf610_nfc_write(struct mtd_info *mtd, uint reg, u32 val)
205 {
206 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
207 
208 	writel(val, nfc->regs + reg);
209 }
210 
vf610_nfc_set(struct mtd_info * mtd,uint reg,u32 bits)211 static inline void vf610_nfc_set(struct mtd_info *mtd, uint reg, u32 bits)
212 {
213 	vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) | bits);
214 }
215 
vf610_nfc_clear(struct mtd_info * mtd,uint reg,u32 bits)216 static inline void vf610_nfc_clear(struct mtd_info *mtd, uint reg, u32 bits)
217 {
218 	vf610_nfc_write(mtd, reg, vf610_nfc_read(mtd, reg) & ~bits);
219 }
220 
vf610_nfc_set_field(struct mtd_info * mtd,u32 reg,u32 mask,u32 shift,u32 val)221 static inline void vf610_nfc_set_field(struct mtd_info *mtd, u32 reg,
222 				       u32 mask, u32 shift, u32 val)
223 {
224 	vf610_nfc_write(mtd, reg,
225 			(vf610_nfc_read(mtd, reg) & (~mask)) | val << shift);
226 }
227 
vf610_nfc_memcpy(void * dst,const void * src,size_t n)228 static inline void vf610_nfc_memcpy(void *dst, const void *src, size_t n)
229 {
230 	/*
231 	 * Use this accessor for the internal SRAM buffers. On the ARM
232 	 * Freescale Vybrid SoC it's known that the driver can treat
233 	 * the SRAM buffer as if it's memory. Other platform might need
234 	 * to treat the buffers differently.
235 	 *
236 	 * For the time being, use memcpy
237 	 */
238 	memcpy(dst, src, n);
239 }
240 
241 /* Clear flags for upcoming command */
vf610_nfc_clear_status(void __iomem * regbase)242 static inline void vf610_nfc_clear_status(void __iomem *regbase)
243 {
244 	void __iomem *reg = regbase + NFC_IRQ_STATUS;
245 	u32 tmp = __raw_readl(reg);
246 	tmp |= CMD_DONE_CLEAR_BIT | IDLE_CLEAR_BIT;
247 	__raw_writel(tmp, reg);
248 }
249 
250 /* Wait for complete operation */
vf610_nfc_done(struct mtd_info * mtd)251 static void vf610_nfc_done(struct mtd_info *mtd)
252 {
253 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
254 	uint start;
255 
256 	/*
257 	 * Barrier is needed after this write. This write need
258 	 * to be done before reading the next register the first
259 	 * time.
260 	 * vf610_nfc_set implicates such a barrier by using writel
261 	 * to write to the register.
262 	 */
263 	vf610_nfc_set(mtd, NFC_FLASH_CMD2, START_BIT);
264 
265 	start = get_timer(0);
266 
267 	while (!(vf610_nfc_read(mtd, NFC_IRQ_STATUS) & IDLE_IRQ_BIT)) {
268 		if (get_timer(start) > NFC_TIMEOUT) {
269 			printf("Timeout while waiting for IDLE.\n");
270 			return;
271 		}
272 	}
273 	vf610_nfc_clear_status(nfc->regs);
274 }
275 
vf610_nfc_get_id(struct mtd_info * mtd,int col)276 static u8 vf610_nfc_get_id(struct mtd_info *mtd, int col)
277 {
278 	u32 flash_id;
279 
280 	if (col < 4) {
281 		flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS1);
282 		flash_id >>= (3 - col) * 8;
283 	} else {
284 		flash_id = vf610_nfc_read(mtd, NFC_FLASH_STATUS2);
285 		flash_id >>= 24;
286 	}
287 
288 	return flash_id & 0xff;
289 }
290 
vf610_nfc_get_status(struct mtd_info * mtd)291 static u8 vf610_nfc_get_status(struct mtd_info *mtd)
292 {
293 	return vf610_nfc_read(mtd, NFC_FLASH_STATUS2) & STATUS_BYTE1_MASK;
294 }
295 
296 /* Single command */
vf610_nfc_send_command(void __iomem * regbase,u32 cmd_byte1,u32 cmd_code)297 static void vf610_nfc_send_command(void __iomem *regbase, u32 cmd_byte1,
298 				   u32 cmd_code)
299 {
300 	void __iomem *reg = regbase + NFC_FLASH_CMD2;
301 	u32 tmp;
302 	vf610_nfc_clear_status(regbase);
303 
304 	tmp = __raw_readl(reg);
305 	tmp &= ~(CMD_BYTE1_MASK | CMD_CODE_MASK | BUFNO_MASK);
306 	tmp |= cmd_byte1 << CMD_BYTE1_SHIFT;
307 	tmp |= cmd_code << CMD_CODE_SHIFT;
308 	__raw_writel(tmp, reg);
309 }
310 
311 /* Two commands */
vf610_nfc_send_commands(void __iomem * regbase,u32 cmd_byte1,u32 cmd_byte2,u32 cmd_code)312 static void vf610_nfc_send_commands(void __iomem *regbase, u32 cmd_byte1,
313 			      u32 cmd_byte2, u32 cmd_code)
314 {
315 	void __iomem *reg = regbase + NFC_FLASH_CMD1;
316 	u32 tmp;
317 	vf610_nfc_send_command(regbase, cmd_byte1, cmd_code);
318 
319 	tmp = __raw_readl(reg);
320 	tmp &= ~CMD_BYTE2_MASK;
321 	tmp |= cmd_byte2 << CMD_BYTE2_SHIFT;
322 	__raw_writel(tmp, reg);
323 }
324 
vf610_nfc_addr_cycle(struct mtd_info * mtd,int column,int page)325 static void vf610_nfc_addr_cycle(struct mtd_info *mtd, int column, int page)
326 {
327 	if (column != -1) {
328 		struct vf610_nfc *nfc = mtd_to_nfc(mtd);
329 		if (nfc->chip.options & NAND_BUSWIDTH_16)
330 			column = column / 2;
331 		vf610_nfc_set_field(mtd, NFC_COL_ADDR, COL_ADDR_MASK,
332 				    COL_ADDR_SHIFT, column);
333 	}
334 	if (page != -1)
335 		vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
336 				    ROW_ADDR_SHIFT, page);
337 }
338 
vf610_nfc_ecc_mode(struct mtd_info * mtd,int ecc_mode)339 static inline void vf610_nfc_ecc_mode(struct mtd_info *mtd, int ecc_mode)
340 {
341 	vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
342 			    CONFIG_ECC_MODE_MASK,
343 			    CONFIG_ECC_MODE_SHIFT, ecc_mode);
344 }
345 
vf610_nfc_transfer_size(void __iomem * regbase,int size)346 static inline void vf610_nfc_transfer_size(void __iomem *regbase, int size)
347 {
348 	__raw_writel(size, regbase + NFC_SECTOR_SIZE);
349 }
350 
351 /* Send command to NAND chip */
vf610_nfc_command(struct mtd_info * mtd,unsigned command,int column,int page)352 static void vf610_nfc_command(struct mtd_info *mtd, unsigned command,
353 			      int column, int page)
354 {
355 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
356 	int trfr_sz = nfc->chip.options & NAND_BUSWIDTH_16 ? 1 : 0;
357 
358 	nfc->buf_offset = max(column, 0);
359 	nfc->alt_buf = ALT_BUF_DATA;
360 
361 	switch (command) {
362 	case NAND_CMD_SEQIN:
363 		/* Use valid column/page from preread... */
364 		vf610_nfc_addr_cycle(mtd, column, page);
365 		nfc->buf_offset = 0;
366 
367 		/*
368 		 * SEQIN => data => PAGEPROG sequence is done by the controller
369 		 * hence we do not need to issue the command here...
370 		 */
371 		return;
372 	case NAND_CMD_PAGEPROG:
373 		trfr_sz += nfc->write_sz;
374 		vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
375 		vf610_nfc_transfer_size(nfc->regs, trfr_sz);
376 		vf610_nfc_send_commands(nfc->regs, NAND_CMD_SEQIN,
377 					command, PROGRAM_PAGE_CMD_CODE);
378 		break;
379 
380 	case NAND_CMD_RESET:
381 		vf610_nfc_transfer_size(nfc->regs, 0);
382 		vf610_nfc_send_command(nfc->regs, command, RESET_CMD_CODE);
383 		break;
384 
385 	case NAND_CMD_READOOB:
386 		trfr_sz += mtd->oobsize;
387 		column = mtd->writesize;
388 		vf610_nfc_transfer_size(nfc->regs, trfr_sz);
389 		vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
390 					NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
391 		vf610_nfc_addr_cycle(mtd, column, page);
392 		vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
393 		break;
394 
395 	case NAND_CMD_READ0:
396 		trfr_sz += mtd->writesize + mtd->oobsize;
397 		vf610_nfc_transfer_size(nfc->regs, trfr_sz);
398 		vf610_nfc_ecc_mode(mtd, ECC_HW_MODE);
399 		vf610_nfc_send_commands(nfc->regs, NAND_CMD_READ0,
400 					NAND_CMD_READSTART, READ_PAGE_CMD_CODE);
401 		vf610_nfc_addr_cycle(mtd, column, page);
402 		break;
403 
404 	case NAND_CMD_PARAM:
405 		nfc->alt_buf = ALT_BUF_ONFI;
406 		trfr_sz = 3 * sizeof(struct nand_onfi_params);
407 		vf610_nfc_transfer_size(nfc->regs, trfr_sz);
408 		vf610_nfc_send_command(nfc->regs, NAND_CMD_PARAM,
409 				       READ_ONFI_PARAM_CMD_CODE);
410 		vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
411 				    ROW_ADDR_SHIFT, column);
412 		vf610_nfc_ecc_mode(mtd, ECC_BYPASS);
413 		break;
414 
415 	case NAND_CMD_ERASE1:
416 		vf610_nfc_transfer_size(nfc->regs, 0);
417 		vf610_nfc_send_commands(nfc->regs, command,
418 					NAND_CMD_ERASE2, ERASE_CMD_CODE);
419 		vf610_nfc_addr_cycle(mtd, column, page);
420 		break;
421 
422 	case NAND_CMD_READID:
423 		nfc->alt_buf = ALT_BUF_ID;
424 		nfc->buf_offset = 0;
425 		vf610_nfc_transfer_size(nfc->regs, 0);
426 		vf610_nfc_send_command(nfc->regs, command, READ_ID_CMD_CODE);
427 		vf610_nfc_set_field(mtd, NFC_ROW_ADDR, ROW_ADDR_MASK,
428 				    ROW_ADDR_SHIFT, column);
429 		break;
430 
431 	case NAND_CMD_STATUS:
432 		nfc->alt_buf = ALT_BUF_STAT;
433 		vf610_nfc_transfer_size(nfc->regs, 0);
434 		vf610_nfc_send_command(nfc->regs, command, STATUS_READ_CMD_CODE);
435 		break;
436 	default:
437 		return;
438 	}
439 
440 	vf610_nfc_done(mtd);
441 
442 	nfc->write_sz = 0;
443 }
444 
445 /* Read data from NFC buffers */
vf610_nfc_read_buf(struct mtd_info * mtd,u_char * buf,int len)446 static void vf610_nfc_read_buf(struct mtd_info *mtd, u_char *buf, int len)
447 {
448 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
449 	uint c = nfc->buf_offset;
450 
451 	/* Alternate buffers are only supported through read_byte */
452 	if (nfc->alt_buf)
453 		return;
454 
455 	vf610_nfc_memcpy(buf, nfc->regs + NFC_MAIN_AREA(0) + c, len);
456 
457 	nfc->buf_offset += len;
458 }
459 
460 /* Write data to NFC buffers */
vf610_nfc_write_buf(struct mtd_info * mtd,const uint8_t * buf,int len)461 static void vf610_nfc_write_buf(struct mtd_info *mtd, const uint8_t *buf,
462 				int len)
463 {
464 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
465 	uint c = nfc->buf_offset;
466 	uint l;
467 
468 	l = min_t(uint, len, mtd->writesize + mtd->oobsize - c);
469 	vf610_nfc_memcpy(nfc->regs + NFC_MAIN_AREA(0) + c, buf, l);
470 
471 	nfc->write_sz += l;
472 	nfc->buf_offset += l;
473 }
474 
475 /* Read byte from NFC buffers */
vf610_nfc_read_byte(struct mtd_info * mtd)476 static uint8_t vf610_nfc_read_byte(struct mtd_info *mtd)
477 {
478 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
479 	u8 tmp;
480 	uint c = nfc->buf_offset;
481 
482 	switch (nfc->alt_buf) {
483 	case ALT_BUF_ID:
484 		tmp = vf610_nfc_get_id(mtd, c);
485 		break;
486 	case ALT_BUF_STAT:
487 		tmp = vf610_nfc_get_status(mtd);
488 		break;
489 #ifdef __LITTLE_ENDIAN
490 	case ALT_BUF_ONFI:
491 		/* Reverse byte since the controller uses big endianness */
492 		c = nfc->buf_offset ^ 0x3;
493 		/* fall-through */
494 #endif
495 	default:
496 		tmp = *((u8 *)(nfc->regs + NFC_MAIN_AREA(0) + c));
497 		break;
498 	}
499 	nfc->buf_offset++;
500 	return tmp;
501 }
502 
503 /* Read word from NFC buffers */
vf610_nfc_read_word(struct mtd_info * mtd)504 static u16 vf610_nfc_read_word(struct mtd_info *mtd)
505 {
506 	u16 tmp;
507 
508 	vf610_nfc_read_buf(mtd, (u_char *)&tmp, sizeof(tmp));
509 	return tmp;
510 }
511 
512 /* If not provided, upper layers apply a fixed delay. */
vf610_nfc_dev_ready(struct mtd_info * mtd)513 static int vf610_nfc_dev_ready(struct mtd_info *mtd)
514 {
515 	/* NFC handles R/B internally; always ready.  */
516 	return 1;
517 }
518 
519 /*
520  * This function supports Vybrid only (MPC5125 would have full RB and four CS)
521  */
vf610_nfc_select_chip(struct mtd_info * mtd,int chip)522 static void vf610_nfc_select_chip(struct mtd_info *mtd, int chip)
523 {
524 #ifdef CONFIG_VF610
525 	u32 tmp = vf610_nfc_read(mtd, NFC_ROW_ADDR);
526 	tmp &= ~(ROW_ADDR_CHIP_SEL_RB_MASK | ROW_ADDR_CHIP_SEL_MASK);
527 
528 	if (chip >= 0) {
529 		tmp |= 1 << ROW_ADDR_CHIP_SEL_RB_SHIFT;
530 		tmp |= (1 << chip) << ROW_ADDR_CHIP_SEL_SHIFT;
531 	}
532 
533 	vf610_nfc_write(mtd, NFC_ROW_ADDR, tmp);
534 #endif
535 }
536 
537 /* Count the number of 0's in buff upto max_bits */
count_written_bits(uint8_t * buff,int size,int max_bits)538 static inline int count_written_bits(uint8_t *buff, int size, int max_bits)
539 {
540 	uint32_t *buff32 = (uint32_t *)buff;
541 	int k, written_bits = 0;
542 
543 	for (k = 0; k < (size / 4); k++) {
544 		written_bits += hweight32(~buff32[k]);
545 		if (written_bits > max_bits)
546 			break;
547 	}
548 
549 	return written_bits;
550 }
551 
vf610_nfc_correct_data(struct mtd_info * mtd,uint8_t * dat,uint8_t * oob,int page)552 static inline int vf610_nfc_correct_data(struct mtd_info *mtd, uint8_t *dat,
553 					 uint8_t *oob, int page)
554 {
555 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
556 	u32 ecc_status_off = NFC_MAIN_AREA(0) + ECC_SRAM_ADDR + ECC_STATUS;
557 	u8 ecc_status;
558 	u8 ecc_count;
559 	int flips;
560 	int flips_threshold = nfc->chip.ecc.strength / 2;
561 
562 	ecc_status = vf610_nfc_read(mtd, ecc_status_off) & 0xff;
563 	ecc_count = ecc_status & ECC_STATUS_ERR_COUNT;
564 
565 	if (!(ecc_status & ECC_STATUS_MASK))
566 		return ecc_count;
567 
568 	/* Read OOB without ECC unit enabled */
569 	vf610_nfc_command(mtd, NAND_CMD_READOOB, 0, page);
570 	vf610_nfc_read_buf(mtd, oob, mtd->oobsize);
571 
572 	/*
573 	 * On an erased page, bit count (including OOB) should be zero or
574 	 * at least less then half of the ECC strength.
575 	 */
576 	flips = count_written_bits(dat, nfc->chip.ecc.size, flips_threshold);
577 	flips += count_written_bits(oob, mtd->oobsize, flips_threshold);
578 
579 	if (unlikely(flips > flips_threshold))
580 		return -EINVAL;
581 
582 	/* Erased page. */
583 	memset(dat, 0xff, nfc->chip.ecc.size);
584 	memset(oob, 0xff, mtd->oobsize);
585 	return flips;
586 }
587 
vf610_nfc_read_page(struct mtd_info * mtd,struct nand_chip * chip,uint8_t * buf,int oob_required,int page)588 static int vf610_nfc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
589 				uint8_t *buf, int oob_required, int page)
590 {
591 	int eccsize = chip->ecc.size;
592 	int stat;
593 
594 	vf610_nfc_read_buf(mtd, buf, eccsize);
595 	if (oob_required)
596 		vf610_nfc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
597 
598 	stat = vf610_nfc_correct_data(mtd, buf, chip->oob_poi, page);
599 
600 	if (stat < 0) {
601 		mtd->ecc_stats.failed++;
602 		return 0;
603 	} else {
604 		mtd->ecc_stats.corrected += stat;
605 		return stat;
606 	}
607 }
608 
609 /*
610  * ECC will be calculated automatically
611  */
vf610_nfc_write_page(struct mtd_info * mtd,struct nand_chip * chip,const uint8_t * buf,int oob_required,int page)612 static int vf610_nfc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
613 			       const uint8_t *buf, int oob_required, int page)
614 {
615 	struct vf610_nfc *nfc = mtd_to_nfc(mtd);
616 
617 	vf610_nfc_write_buf(mtd, buf, mtd->writesize);
618 	if (oob_required)
619 		vf610_nfc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
620 
621 	/* Always write whole page including OOB due to HW ECC */
622 	nfc->write_sz = mtd->writesize + mtd->oobsize;
623 
624 	return 0;
625 }
626 
627 struct vf610_nfc_config {
628 	int hardware_ecc;
629 	int width;
630 	int flash_bbt;
631 };
632 
vf610_nfc_nand_init(int devnum,void __iomem * addr)633 static int vf610_nfc_nand_init(int devnum, void __iomem *addr)
634 {
635 	struct mtd_info *mtd;
636 	struct nand_chip *chip;
637 	struct vf610_nfc *nfc;
638 	int err = 0;
639 	struct vf610_nfc_config cfg = {
640 		.hardware_ecc = 1,
641 #ifdef CONFIG_SYS_NAND_BUSWIDTH_16BIT
642 		.width = 16,
643 #else
644 		.width = 8,
645 #endif
646 		.flash_bbt = 1,
647 	};
648 
649 	nfc = calloc(1, sizeof(*nfc));
650 	if (!nfc) {
651 		printf(KERN_ERR "%s: Memory exhausted!\n", __func__);
652 		return -ENOMEM;
653 	}
654 
655 	chip = &nfc->chip;
656 	nfc->regs = addr;
657 
658 	mtd = nand_to_mtd(chip);
659 	nand_set_controller_data(chip, nfc);
660 
661 	if (cfg.width == 16)
662 		chip->options |= NAND_BUSWIDTH_16;
663 
664 	chip->dev_ready = vf610_nfc_dev_ready;
665 	chip->cmdfunc = vf610_nfc_command;
666 	chip->read_byte = vf610_nfc_read_byte;
667 	chip->read_word = vf610_nfc_read_word;
668 	chip->read_buf = vf610_nfc_read_buf;
669 	chip->write_buf = vf610_nfc_write_buf;
670 	chip->select_chip = vf610_nfc_select_chip;
671 
672 	chip->options |= NAND_NO_SUBPAGE_WRITE;
673 
674 	chip->ecc.size = PAGE_2K;
675 
676 	/* Set configuration register. */
677 	vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
678 	vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_ADDR_AUTO_INCR_BIT);
679 	vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BUFNO_AUTO_INCR_BIT);
680 	vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_BOOT_MODE_BIT);
681 	vf610_nfc_clear(mtd, NFC_FLASH_CONFIG, CONFIG_DMA_REQ_BIT);
682 	vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_FAST_FLASH_BIT);
683 
684 	/* Disable virtual pages, only one elementary transfer unit */
685 	vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG, CONFIG_PAGE_CNT_MASK,
686 			    CONFIG_PAGE_CNT_SHIFT, 1);
687 
688 	/* first scan to find the device and get the page size */
689 	if (nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_DEVICE, NULL)) {
690 		err = -ENXIO;
691 		goto error;
692 	}
693 
694 	if (cfg.width == 16)
695 		vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_16BIT);
696 
697 	/* Bad block options. */
698 	if (cfg.flash_bbt)
699 		chip->bbt_options = NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB |
700 				    NAND_BBT_CREATE;
701 
702 	/* Single buffer only, max 256 OOB minus ECC status */
703 	if (mtd->writesize + mtd->oobsize > PAGE_2K + OOB_MAX - 8) {
704 		dev_err(nfc->dev, "Unsupported flash page size\n");
705 		err = -ENXIO;
706 		goto error;
707 	}
708 
709 	if (cfg.hardware_ecc) {
710 		if (mtd->writesize != PAGE_2K && mtd->oobsize < 64) {
711 			dev_err(nfc->dev, "Unsupported flash with hwecc\n");
712 			err = -ENXIO;
713 			goto error;
714 		}
715 
716 		if (chip->ecc.size != mtd->writesize) {
717 			dev_err(nfc->dev, "ecc size: %d\n", chip->ecc.size);
718 			dev_err(nfc->dev, "Step size needs to be page size\n");
719 			err = -ENXIO;
720 			goto error;
721 		}
722 
723 		/* Current HW ECC layouts only use 64 bytes of OOB */
724 		if (mtd->oobsize > 64)
725 			mtd->oobsize = 64;
726 
727 		/* propagate ecc.layout to mtd_info */
728 		mtd->ecclayout = chip->ecc.layout;
729 		chip->ecc.read_page = vf610_nfc_read_page;
730 		chip->ecc.write_page = vf610_nfc_write_page;
731 		chip->ecc.mode = NAND_ECC_HW;
732 
733 		chip->ecc.size = PAGE_2K;
734 		chip->ecc.layout = &vf610_nfc_ecc;
735 #if defined(CONFIG_SYS_NAND_VF610_NFC_45_ECC_BYTES)
736 		chip->ecc.strength = 24;
737 		chip->ecc.bytes = 45;
738 #elif defined(CONFIG_SYS_NAND_VF610_NFC_60_ECC_BYTES)
739 		chip->ecc.strength = 32;
740 		chip->ecc.bytes = 60;
741 #endif
742 
743 		/* Set ECC_STATUS offset */
744 		vf610_nfc_set_field(mtd, NFC_FLASH_CONFIG,
745 				    CONFIG_ECC_SRAM_ADDR_MASK,
746 				    CONFIG_ECC_SRAM_ADDR_SHIFT,
747 				    ECC_SRAM_ADDR >> 3);
748 
749 		/* Enable ECC status in SRAM */
750 		vf610_nfc_set(mtd, NFC_FLASH_CONFIG, CONFIG_ECC_SRAM_REQ_BIT);
751 	}
752 
753 	/* second phase scan */
754 	err = nand_scan_tail(mtd);
755 	if (err)
756 		return err;
757 
758 	err = nand_register(devnum, mtd);
759 	if (err)
760 		return err;
761 
762 	return 0;
763 
764 error:
765 	return err;
766 }
767 
768 #if CONFIG_NAND_VF610_NFC_DT
769 static const struct udevice_id vf610_nfc_dt_ids[] = {
770 	{
771 		.compatible = "fsl,vf610-nfc",
772 	},
773 	{ /* sentinel */ }
774 };
775 
vf610_nfc_dt_probe(struct udevice * dev)776 static int vf610_nfc_dt_probe(struct udevice *dev)
777 {
778 	struct resource res;
779 	int ret;
780 
781 	ret = dev_read_resource(dev, 0, &res);
782 	if (ret)
783 		return ret;
784 
785 	return vf610_nfc_nand_init(0, devm_ioremap(dev, res.start,
786 						   resource_size(&res)));
787 }
788 
789 U_BOOT_DRIVER(vf610_nfc_dt) = {
790 	.name = "vf610-nfc-dt",
791 	.id = UCLASS_MTD,
792 	.of_match = vf610_nfc_dt_ids,
793 	.probe = vf610_nfc_dt_probe,
794 };
795 
board_nand_init(void)796 void board_nand_init(void)
797 {
798 	struct udevice *dev;
799 	int ret;
800 
801 	ret = uclass_get_device_by_driver(UCLASS_MTD,
802 					  DM_GET_DRIVER(vf610_nfc_dt),
803 					  &dev);
804 	if (ret && ret != -ENODEV)
805 		pr_err("Failed to initialize NAND controller. (error %d)\n",
806 		       ret);
807 }
808 #else
board_nand_init(void)809 void board_nand_init(void)
810 {
811 	int err = vf610_nfc_nand_init(0, (void __iomem *)CONFIG_SYS_NAND_BASE);
812 	if (err)
813 		printf("VF610 NAND init failed (err %d)\n", err);
814 }
815 #endif /* CONFIG_NAND_VF610_NFC_DT */
816