1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Apple SoC pinctrl+GPIO+external IRQ driver
4 *
5 * Copyright (C) The Asahi Linux Contributors
6 * Copyright (C) 2020 Corellium LLC
7 *
8 * Based on: pinctrl-pistachio.c
9 * Copyright (C) 2014 Imagination Technologies Ltd.
10 * Copyright (C) 2014 Google, Inc.
11 */
12
13 #include <dt-bindings/pinctrl/apple.h>
14
15 #include <linux/bitfield.h>
16 #include <linux/bits.h>
17 #include <linux/gpio/driver.h>
18 #include <linux/interrupt.h>
19 #include <linux/irq.h>
20 #include <linux/module.h>
21 #include <linux/of.h>
22 #include <linux/of_irq.h>
23 #include <linux/platform_device.h>
24 #include <linux/regmap.h>
25
26 #include <linux/pinctrl/pinctrl.h>
27 #include <linux/pinctrl/pinmux.h>
28
29 #include "pinctrl-utils.h"
30 #include "core.h"
31 #include "pinmux.h"
32
33 struct apple_gpio_pinctrl {
34 struct device *dev;
35 struct pinctrl_dev *pctldev;
36
37 void __iomem *base;
38 struct regmap *map;
39
40 struct pinctrl_desc pinctrl_desc;
41 struct gpio_chip gpio_chip;
42 u8 irqgrps[];
43 };
44
45 #define REG_GPIO(x) (4 * (x))
46 #define REG_GPIOx_DATA BIT(0)
47 #define REG_GPIOx_MODE GENMASK(3, 1)
48 #define REG_GPIOx_OUT 1
49 #define REG_GPIOx_IN_IRQ_HI 2
50 #define REG_GPIOx_IN_IRQ_LO 3
51 #define REG_GPIOx_IN_IRQ_UP 4
52 #define REG_GPIOx_IN_IRQ_DN 5
53 #define REG_GPIOx_IN_IRQ_ANY 6
54 #define REG_GPIOx_IN_IRQ_OFF 7
55 #define REG_GPIOx_PERIPH GENMASK(6, 5)
56 #define REG_GPIOx_PULL GENMASK(8, 7)
57 #define REG_GPIOx_PULL_OFF 0
58 #define REG_GPIOx_PULL_DOWN 1
59 #define REG_GPIOx_PULL_UP_STRONG 2
60 #define REG_GPIOx_PULL_UP 3
61 #define REG_GPIOx_INPUT_ENABLE BIT(9)
62 #define REG_GPIOx_DRIVE_STRENGTH0 GENMASK(11, 10)
63 #define REG_GPIOx_SCHMITT BIT(15)
64 #define REG_GPIOx_GRP GENMASK(18, 16)
65 #define REG_GPIOx_LOCK BIT(21)
66 #define REG_GPIOx_DRIVE_STRENGTH1 GENMASK(23, 22)
67 #define REG_IRQ(g, x) (0x800 + 0x40 * (g) + 4 * ((x) >> 5))
68
69 struct regmap_config regmap_config = {
70 .reg_bits = 32,
71 .val_bits = 32,
72 .reg_stride = 4,
73 .cache_type = REGCACHE_FLAT,
74 .max_register = 512 * sizeof(u32),
75 .num_reg_defaults_raw = 512,
76 .use_relaxed_mmio = true,
77 .use_raw_spinlock = true,
78 };
79
80 /* No locking needed to mask/unmask IRQs as the interrupt mode is per pin-register. */
apple_gpio_set_reg(struct apple_gpio_pinctrl * pctl,unsigned int pin,u32 mask,u32 value)81 static void apple_gpio_set_reg(struct apple_gpio_pinctrl *pctl,
82 unsigned int pin, u32 mask, u32 value)
83 {
84 regmap_update_bits(pctl->map, REG_GPIO(pin), mask, value);
85 }
86
apple_gpio_get_reg(struct apple_gpio_pinctrl * pctl,unsigned int pin)87 static u32 apple_gpio_get_reg(struct apple_gpio_pinctrl *pctl,
88 unsigned int pin)
89 {
90 int ret;
91 u32 val;
92
93 ret = regmap_read(pctl->map, REG_GPIO(pin), &val);
94 if (ret)
95 return 0;
96
97 return val;
98 }
99
100 /* Pin controller functions */
101
apple_gpio_dt_node_to_map(struct pinctrl_dev * pctldev,struct device_node * node,struct pinctrl_map ** map,unsigned * num_maps)102 static int apple_gpio_dt_node_to_map(struct pinctrl_dev *pctldev,
103 struct device_node *node,
104 struct pinctrl_map **map,
105 unsigned *num_maps)
106 {
107 unsigned reserved_maps;
108 struct apple_gpio_pinctrl *pctl;
109 u32 pinfunc, pin, func;
110 int num_pins, i, ret;
111 const char *group_name;
112 const char *function_name;
113
114 *map = NULL;
115 *num_maps = 0;
116 reserved_maps = 0;
117
118 pctl = pinctrl_dev_get_drvdata(pctldev);
119
120 ret = of_property_count_u32_elems(node, "pinmux");
121 if (ret <= 0) {
122 dev_err(pctl->dev,
123 "missing or empty pinmux property in node %pOFn.\n",
124 node);
125 return ret ? ret : -EINVAL;
126 }
127
128 num_pins = ret;
129
130 ret = pinctrl_utils_reserve_map(pctldev, map, &reserved_maps, num_maps, num_pins);
131 if (ret)
132 return ret;
133
134 for (i = 0; i < num_pins; i++) {
135 ret = of_property_read_u32_index(node, "pinmux", i, &pinfunc);
136 if (ret)
137 goto free_map;
138
139 pin = APPLE_PIN(pinfunc);
140 func = APPLE_FUNC(pinfunc);
141
142 if (func >= pinmux_generic_get_function_count(pctldev)) {
143 ret = -EINVAL;
144 goto free_map;
145 }
146
147 group_name = pinctrl_generic_get_group_name(pctldev, pin);
148 function_name = pinmux_generic_get_function_name(pctl->pctldev, func);
149 ret = pinctrl_utils_add_map_mux(pctl->pctldev, map,
150 &reserved_maps, num_maps,
151 group_name, function_name);
152 if (ret)
153 goto free_map;
154 }
155
156 free_map:
157 if (ret < 0)
158 pinctrl_utils_free_map(pctldev, *map, *num_maps);
159
160 return ret;
161 }
162
163 static const struct pinctrl_ops apple_gpio_pinctrl_ops = {
164 .get_groups_count = pinctrl_generic_get_group_count,
165 .get_group_name = pinctrl_generic_get_group_name,
166 .get_group_pins = pinctrl_generic_get_group_pins,
167 .dt_node_to_map = apple_gpio_dt_node_to_map,
168 .dt_free_map = pinctrl_utils_free_map,
169 };
170
171 /* Pin multiplexer functions */
172
apple_gpio_pinmux_set(struct pinctrl_dev * pctldev,unsigned func,unsigned group)173 static int apple_gpio_pinmux_set(struct pinctrl_dev *pctldev, unsigned func,
174 unsigned group)
175 {
176 struct apple_gpio_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
177
178 apple_gpio_set_reg(
179 pctl, group, REG_GPIOx_PERIPH | REG_GPIOx_INPUT_ENABLE,
180 FIELD_PREP(REG_GPIOx_PERIPH, func) | REG_GPIOx_INPUT_ENABLE);
181
182 return 0;
183 }
184
185 static const struct pinmux_ops apple_gpio_pinmux_ops = {
186 .get_functions_count = pinmux_generic_get_function_count,
187 .get_function_name = pinmux_generic_get_function_name,
188 .get_function_groups = pinmux_generic_get_function_groups,
189 .set_mux = apple_gpio_pinmux_set,
190 .strict = true,
191 };
192
193 /* GPIO chip functions */
194
apple_gpio_get_direction(struct gpio_chip * chip,unsigned int offset)195 static int apple_gpio_get_direction(struct gpio_chip *chip, unsigned int offset)
196 {
197 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
198 unsigned int reg = apple_gpio_get_reg(pctl, offset);
199
200 if (FIELD_GET(REG_GPIOx_MODE, reg) == REG_GPIOx_OUT)
201 return GPIO_LINE_DIRECTION_OUT;
202 return GPIO_LINE_DIRECTION_IN;
203 }
204
apple_gpio_get(struct gpio_chip * chip,unsigned offset)205 static int apple_gpio_get(struct gpio_chip *chip, unsigned offset)
206 {
207 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
208 unsigned int reg = apple_gpio_get_reg(pctl, offset);
209
210 /*
211 * If this is an input GPIO, read the actual value (not the
212 * cached regmap value)
213 */
214 if (FIELD_GET(REG_GPIOx_MODE, reg) != REG_GPIOx_OUT)
215 reg = readl_relaxed(pctl->base + REG_GPIO(offset));
216
217 return !!(reg & REG_GPIOx_DATA);
218 }
219
apple_gpio_set(struct gpio_chip * chip,unsigned int offset,int value)220 static void apple_gpio_set(struct gpio_chip *chip, unsigned int offset, int value)
221 {
222 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
223
224 apple_gpio_set_reg(pctl, offset, REG_GPIOx_DATA, value ? REG_GPIOx_DATA : 0);
225 }
226
apple_gpio_direction_input(struct gpio_chip * chip,unsigned int offset)227 static int apple_gpio_direction_input(struct gpio_chip *chip, unsigned int offset)
228 {
229 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
230
231 apple_gpio_set_reg(pctl, offset,
232 REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA |
233 REG_GPIOx_INPUT_ENABLE,
234 FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF) |
235 REG_GPIOx_INPUT_ENABLE);
236 return 0;
237 }
238
apple_gpio_direction_output(struct gpio_chip * chip,unsigned int offset,int value)239 static int apple_gpio_direction_output(struct gpio_chip *chip,
240 unsigned int offset, int value)
241 {
242 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
243
244 apple_gpio_set_reg(pctl, offset,
245 REG_GPIOx_PERIPH | REG_GPIOx_MODE | REG_GPIOx_DATA,
246 FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_OUT) |
247 (value ? REG_GPIOx_DATA : 0));
248 return 0;
249 }
250
251 /* IRQ chip functions */
252
apple_gpio_irq_ack(struct irq_data * data)253 static void apple_gpio_irq_ack(struct irq_data *data)
254 {
255 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
256 unsigned int irqgrp = FIELD_GET(REG_GPIOx_GRP, apple_gpio_get_reg(pctl, data->hwirq));
257
258 writel(BIT(data->hwirq % 32), pctl->base + REG_IRQ(irqgrp, data->hwirq));
259 }
260
apple_gpio_irq_type(unsigned int type)261 static unsigned int apple_gpio_irq_type(unsigned int type)
262 {
263 switch (type & IRQ_TYPE_SENSE_MASK) {
264 case IRQ_TYPE_EDGE_RISING:
265 return REG_GPIOx_IN_IRQ_UP;
266 case IRQ_TYPE_EDGE_FALLING:
267 return REG_GPIOx_IN_IRQ_DN;
268 case IRQ_TYPE_EDGE_BOTH:
269 return REG_GPIOx_IN_IRQ_ANY;
270 case IRQ_TYPE_LEVEL_HIGH:
271 return REG_GPIOx_IN_IRQ_HI;
272 case IRQ_TYPE_LEVEL_LOW:
273 return REG_GPIOx_IN_IRQ_LO;
274 default:
275 return REG_GPIOx_IN_IRQ_OFF;
276 }
277 }
278
apple_gpio_irq_mask(struct irq_data * data)279 static void apple_gpio_irq_mask(struct irq_data *data)
280 {
281 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
282 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(gc);
283
284 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
285 FIELD_PREP(REG_GPIOx_MODE, REG_GPIOx_IN_IRQ_OFF));
286 gpiochip_disable_irq(gc, data->hwirq);
287 }
288
apple_gpio_irq_unmask(struct irq_data * data)289 static void apple_gpio_irq_unmask(struct irq_data *data)
290 {
291 struct gpio_chip *gc = irq_data_get_irq_chip_data(data);
292 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(gc);
293 unsigned int irqtype = apple_gpio_irq_type(irqd_get_trigger_type(data));
294
295 gpiochip_enable_irq(gc, data->hwirq);
296 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
297 FIELD_PREP(REG_GPIOx_MODE, irqtype));
298 }
299
apple_gpio_irq_startup(struct irq_data * data)300 static unsigned int apple_gpio_irq_startup(struct irq_data *data)
301 {
302 struct gpio_chip *chip = irq_data_get_irq_chip_data(data);
303 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(chip);
304
305 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_GRP,
306 FIELD_PREP(REG_GPIOx_GRP, 0));
307
308 apple_gpio_direction_input(chip, data->hwirq);
309 apple_gpio_irq_unmask(data);
310
311 return 0;
312 }
313
apple_gpio_irq_set_type(struct irq_data * data,unsigned int type)314 static int apple_gpio_irq_set_type(struct irq_data *data, unsigned int type)
315 {
316 struct apple_gpio_pinctrl *pctl = gpiochip_get_data(irq_data_get_irq_chip_data(data));
317 unsigned int irqtype = apple_gpio_irq_type(type);
318
319 if (irqtype == REG_GPIOx_IN_IRQ_OFF)
320 return -EINVAL;
321
322 apple_gpio_set_reg(pctl, data->hwirq, REG_GPIOx_MODE,
323 FIELD_PREP(REG_GPIOx_MODE, irqtype));
324
325 if (type & IRQ_TYPE_LEVEL_MASK)
326 irq_set_handler_locked(data, handle_level_irq);
327 else
328 irq_set_handler_locked(data, handle_edge_irq);
329 return 0;
330 }
331
apple_gpio_irq_handler(struct irq_desc * desc)332 static void apple_gpio_irq_handler(struct irq_desc *desc)
333 {
334 struct irq_chip *chip = irq_desc_get_chip(desc);
335 u8 *grpp = irq_desc_get_handler_data(desc);
336 struct apple_gpio_pinctrl *pctl;
337 unsigned int pinh, pinl;
338 unsigned long pending;
339 struct gpio_chip *gc;
340
341 pctl = container_of(grpp - *grpp, typeof(*pctl), irqgrps[0]);
342 gc = &pctl->gpio_chip;
343
344 chained_irq_enter(chip, desc);
345 for (pinh = 0; pinh < gc->ngpio; pinh += 32) {
346 pending = readl_relaxed(pctl->base + REG_IRQ(*grpp, pinh));
347 for_each_set_bit(pinl, &pending, 32)
348 generic_handle_domain_irq(gc->irq.domain, pinh + pinl);
349 }
350 chained_irq_exit(chip, desc);
351 }
352
353 static const struct irq_chip apple_gpio_irqchip = {
354 .name = "Apple-GPIO",
355 .irq_startup = apple_gpio_irq_startup,
356 .irq_ack = apple_gpio_irq_ack,
357 .irq_mask = apple_gpio_irq_mask,
358 .irq_unmask = apple_gpio_irq_unmask,
359 .irq_set_type = apple_gpio_irq_set_type,
360 .flags = IRQCHIP_IMMUTABLE,
361 GPIOCHIP_IRQ_RESOURCE_HELPERS,
362 };
363
364 /* Probe & register */
365
apple_gpio_register(struct apple_gpio_pinctrl * pctl)366 static int apple_gpio_register(struct apple_gpio_pinctrl *pctl)
367 {
368 struct gpio_irq_chip *girq = &pctl->gpio_chip.irq;
369 void **irq_data = NULL;
370 int ret;
371
372 pctl->gpio_chip.label = dev_name(pctl->dev);
373 pctl->gpio_chip.request = gpiochip_generic_request;
374 pctl->gpio_chip.free = gpiochip_generic_free;
375 pctl->gpio_chip.get_direction = apple_gpio_get_direction;
376 pctl->gpio_chip.direction_input = apple_gpio_direction_input;
377 pctl->gpio_chip.direction_output = apple_gpio_direction_output;
378 pctl->gpio_chip.get = apple_gpio_get;
379 pctl->gpio_chip.set = apple_gpio_set;
380 pctl->gpio_chip.base = -1;
381 pctl->gpio_chip.ngpio = pctl->pinctrl_desc.npins;
382 pctl->gpio_chip.parent = pctl->dev;
383
384 if (girq->num_parents) {
385 int i;
386
387 gpio_irq_chip_set_chip(girq, &apple_gpio_irqchip);
388 girq->parent_handler = apple_gpio_irq_handler;
389
390 girq->parents = kmalloc_array(girq->num_parents,
391 sizeof(*girq->parents),
392 GFP_KERNEL);
393 irq_data = kmalloc_array(girq->num_parents, sizeof(*irq_data),
394 GFP_KERNEL);
395 if (!girq->parents || !irq_data) {
396 ret = -ENOMEM;
397 goto out_free_irq_data;
398 }
399
400 for (i = 0; i < girq->num_parents; i++) {
401 ret = platform_get_irq(to_platform_device(pctl->dev), i);
402 if (ret < 0)
403 goto out_free_irq_data;
404
405 girq->parents[i] = ret;
406 pctl->irqgrps[i] = i;
407 irq_data[i] = &pctl->irqgrps[i];
408 }
409
410 girq->parent_handler_data_array = irq_data;
411 girq->per_parent_data = true;
412 girq->default_type = IRQ_TYPE_NONE;
413 girq->handler = handle_level_irq;
414 }
415
416 ret = devm_gpiochip_add_data(pctl->dev, &pctl->gpio_chip, pctl);
417
418 out_free_irq_data:
419 kfree(girq->parents);
420 kfree(irq_data);
421
422 return ret;
423 }
424
apple_gpio_pinctrl_probe(struct platform_device * pdev)425 static int apple_gpio_pinctrl_probe(struct platform_device *pdev)
426 {
427 struct apple_gpio_pinctrl *pctl;
428 struct pinctrl_pin_desc *pins;
429 unsigned int npins;
430 const char **pin_names;
431 unsigned int *pin_nums;
432 static const char* pinmux_functions[] = {
433 "gpio", "periph1", "periph2", "periph3"
434 };
435 unsigned int i, nirqs = 0;
436 int res;
437
438 if (of_property_read_bool(pdev->dev.of_node, "interrupt-controller")) {
439 res = platform_irq_count(pdev);
440 if (res > 0)
441 nirqs = res;
442 }
443
444 pctl = devm_kzalloc(&pdev->dev, struct_size(pctl, irqgrps, nirqs),
445 GFP_KERNEL);
446 if (!pctl)
447 return -ENOMEM;
448 pctl->dev = &pdev->dev;
449 pctl->gpio_chip.irq.num_parents = nirqs;
450 dev_set_drvdata(&pdev->dev, pctl);
451
452 if (of_property_read_u32(pdev->dev.of_node, "apple,npins", &npins))
453 return dev_err_probe(&pdev->dev, -EINVAL,
454 "apple,npins property not found\n");
455
456 pins = devm_kmalloc_array(&pdev->dev, npins, sizeof(pins[0]),
457 GFP_KERNEL);
458 pin_names = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_names[0]),
459 GFP_KERNEL);
460 pin_nums = devm_kmalloc_array(&pdev->dev, npins, sizeof(pin_nums[0]),
461 GFP_KERNEL);
462 if (!pins || !pin_names || !pin_nums)
463 return -ENOMEM;
464
465 pctl->base = devm_platform_ioremap_resource(pdev, 0);
466 if (IS_ERR(pctl->base))
467 return PTR_ERR(pctl->base);
468
469 pctl->map = devm_regmap_init_mmio(&pdev->dev, pctl->base, ®map_config);
470 if (IS_ERR(pctl->map))
471 return dev_err_probe(&pdev->dev, PTR_ERR(pctl->map),
472 "Failed to create regmap\n");
473
474 for (i = 0; i < npins; i++) {
475 pins[i].number = i;
476 pins[i].name = devm_kasprintf(&pdev->dev, GFP_KERNEL, "PIN%u", i);
477 if (!pins[i].name)
478 return -ENOMEM;
479
480 pins[i].drv_data = pctl;
481 pin_names[i] = pins[i].name;
482 pin_nums[i] = i;
483 }
484
485 pctl->pinctrl_desc.name = dev_name(pctl->dev);
486 pctl->pinctrl_desc.pins = pins;
487 pctl->pinctrl_desc.npins = npins;
488 pctl->pinctrl_desc.pctlops = &apple_gpio_pinctrl_ops;
489 pctl->pinctrl_desc.pmxops = &apple_gpio_pinmux_ops;
490
491 pctl->pctldev = devm_pinctrl_register(&pdev->dev, &pctl->pinctrl_desc, pctl);
492 if (IS_ERR(pctl->pctldev))
493 return dev_err_probe(&pdev->dev, PTR_ERR(pctl->pctldev),
494 "Failed to register pinctrl device.\n");
495
496 for (i = 0; i < npins; i++) {
497 res = pinctrl_generic_add_group(pctl->pctldev, pins[i].name,
498 pin_nums + i, 1, pctl);
499 if (res < 0)
500 return dev_err_probe(pctl->dev, res,
501 "Failed to register group");
502 }
503
504 for (i = 0; i < ARRAY_SIZE(pinmux_functions); ++i) {
505 res = pinmux_generic_add_function(pctl->pctldev, pinmux_functions[i],
506 pin_names, npins, pctl);
507 if (res < 0)
508 return dev_err_probe(pctl->dev, res,
509 "Failed to register function.");
510 }
511
512 return apple_gpio_register(pctl);
513 }
514
515 static const struct of_device_id apple_gpio_pinctrl_of_match[] = {
516 { .compatible = "apple,pinctrl", },
517 { }
518 };
519 MODULE_DEVICE_TABLE(of, apple_gpio_pinctrl_of_match);
520
521 static struct platform_driver apple_gpio_pinctrl_driver = {
522 .driver = {
523 .name = "apple-gpio-pinctrl",
524 .of_match_table = apple_gpio_pinctrl_of_match,
525 .suppress_bind_attrs = true,
526 },
527 .probe = apple_gpio_pinctrl_probe,
528 };
529 module_platform_driver(apple_gpio_pinctrl_driver);
530
531 MODULE_DESCRIPTION("Apple pinctrl/GPIO driver");
532 MODULE_AUTHOR("Stan Skowronek <stan@corellium.com>");
533 MODULE_AUTHOR("Joey Gouly <joey.gouly@arm.com>");
534 MODULE_LICENSE("GPL v2");
535