xref: /openbmc/linux/sound/soc/fsl/fsl_asrc.h (revision be7bd03f)
1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * fsl_asrc.h - Freescale ASRC ALSA SoC header file
4  *
5  * Copyright (C) 2014 Freescale Semiconductor, Inc.
6  *
7  * Author: Nicolin Chen <nicoleotsuka@gmail.com>
8  */
9 
10 #ifndef _FSL_ASRC_H
11 #define _FSL_ASRC_H
12 
13 #include  "fsl_asrc_common.h"
14 
15 #define ASRC_DMA_BUFFER_NUM		2
16 #define ASRC_INPUTFIFO_THRESHOLD	32
17 #define ASRC_OUTPUTFIFO_THRESHOLD	32
18 #define ASRC_FIFO_THRESHOLD_MIN		0
19 #define ASRC_FIFO_THRESHOLD_MAX		63
20 #define ASRC_DMA_BUFFER_SIZE		(1024 * 48 * 4)
21 #define ASRC_MAX_BUFFER_SIZE		(1024 * 48)
22 #define ASRC_OUTPUT_LAST_SAMPLE		8
23 
24 #define IDEAL_RATIO_RATE		1000000
25 
26 #define REG_ASRCTR			0x00
27 #define REG_ASRIER			0x04
28 #define REG_ASRCNCR			0x0C
29 #define REG_ASRCFG			0x10
30 #define REG_ASRCSR			0x14
31 
32 #define REG_ASRCDR1			0x18
33 #define REG_ASRCDR2			0x1C
34 #define REG_ASRCDR(i)			((i < 2) ? REG_ASRCDR1 : REG_ASRCDR2)
35 
36 #define REG_ASRSTR			0x20
37 #define REG_ASRRA			0x24
38 #define REG_ASRRB			0x28
39 #define REG_ASRRC			0x2C
40 #define REG_ASRPM1			0x40
41 #define REG_ASRPM2			0x44
42 #define REG_ASRPM3			0x48
43 #define REG_ASRPM4			0x4C
44 #define REG_ASRPM5			0x50
45 #define REG_ASRTFR1			0x54
46 #define REG_ASRCCR			0x5C
47 
48 #define REG_ASRDIA			0x60
49 #define REG_ASRDOA			0x64
50 #define REG_ASRDIB			0x68
51 #define REG_ASRDOB			0x6C
52 #define REG_ASRDIC			0x70
53 #define REG_ASRDOC			0x74
54 #define REG_ASRDI(i)			(REG_ASRDIA + (i << 3))
55 #define REG_ASRDO(i)			(REG_ASRDOA + (i << 3))
56 #define REG_ASRDx(x, i)			((x) == IN ? REG_ASRDI(i) : REG_ASRDO(i))
57 
58 #define REG_ASRIDRHA			0x80
59 #define REG_ASRIDRLA			0x84
60 #define REG_ASRIDRHB			0x88
61 #define REG_ASRIDRLB			0x8C
62 #define REG_ASRIDRHC			0x90
63 #define REG_ASRIDRLC			0x94
64 #define REG_ASRIDRH(i)			(REG_ASRIDRHA + (i << 3))
65 #define REG_ASRIDRL(i)			(REG_ASRIDRLA + (i << 3))
66 
67 #define REG_ASR76K			0x98
68 #define REG_ASR56K			0x9C
69 
70 #define REG_ASRMCRA			0xA0
71 #define REG_ASRFSTA			0xA4
72 #define REG_ASRMCRB			0xA8
73 #define REG_ASRFSTB			0xAC
74 #define REG_ASRMCRC			0xB0
75 #define REG_ASRFSTC			0xB4
76 #define REG_ASRMCR(i)			(REG_ASRMCRA + (i << 3))
77 #define REG_ASRFST(i)			(REG_ASRFSTA + (i << 3))
78 
79 #define REG_ASRMCR1A			0xC0
80 #define REG_ASRMCR1B			0xC4
81 #define REG_ASRMCR1C			0xC8
82 #define REG_ASRMCR1(i)			(REG_ASRMCR1A + (i << 2))
83 
84 
85 /* REG0 0x00 REG_ASRCTR */
86 #define ASRCTR_ATSi_SHIFT(i)		(20 + i)
87 #define ASRCTR_ATSi_MASK(i)		(1 << ASRCTR_ATSi_SHIFT(i))
88 #define ASRCTR_ATS(i)			(1 << ASRCTR_ATSi_SHIFT(i))
89 #define ASRCTR_USRi_SHIFT(i)		(14 + (i << 1))
90 #define ASRCTR_USRi_MASK(i)		(1 << ASRCTR_USRi_SHIFT(i))
91 #define ASRCTR_USR(i)			(1 << ASRCTR_USRi_SHIFT(i))
92 #define ASRCTR_IDRi_SHIFT(i)		(13 + (i << 1))
93 #define ASRCTR_IDRi_MASK(i)		(1 << ASRCTR_IDRi_SHIFT(i))
94 #define ASRCTR_IDR(i)			(1 << ASRCTR_IDRi_SHIFT(i))
95 #define ASRCTR_SRST_SHIFT		4
96 #define ASRCTR_SRST_MASK		(1 << ASRCTR_SRST_SHIFT)
97 #define ASRCTR_SRST			(1 << ASRCTR_SRST_SHIFT)
98 #define ASRCTR_ASRCEi_SHIFT(i)		(1 + i)
99 #define ASRCTR_ASRCEi_MASK(i)		(1 << ASRCTR_ASRCEi_SHIFT(i))
100 #define ASRCTR_ASRCE(i)			(1 << ASRCTR_ASRCEi_SHIFT(i))
101 #define ASRCTR_ASRCEi_ALL_MASK		(0x7 << ASRCTR_ASRCEi_SHIFT(0))
102 #define ASRCTR_ASRCEN_SHIFT		0
103 #define ASRCTR_ASRCEN_MASK		(1 << ASRCTR_ASRCEN_SHIFT)
104 #define ASRCTR_ASRCEN			(1 << ASRCTR_ASRCEN_SHIFT)
105 
106 /* REG1 0x04 REG_ASRIER */
107 #define ASRIER_AFPWE_SHIFT		7
108 #define ASRIER_AFPWE_MASK		(1 << ASRIER_AFPWE_SHIFT)
109 #define ASRIER_AFPWE			(1 << ASRIER_AFPWE_SHIFT)
110 #define ASRIER_AOLIE_SHIFT		6
111 #define ASRIER_AOLIE_MASK		(1 << ASRIER_AOLIE_SHIFT)
112 #define ASRIER_AOLIE			(1 << ASRIER_AOLIE_SHIFT)
113 #define ASRIER_ADOEi_SHIFT(i)		(3 + i)
114 #define ASRIER_ADOEi_MASK(i)		(1 << ASRIER_ADOEi_SHIFT(i))
115 #define ASRIER_ADOE(i)			(1 << ASRIER_ADOEi_SHIFT(i))
116 #define ASRIER_ADIEi_SHIFT(i)		(0 + i)
117 #define ASRIER_ADIEi_MASK(i)		(1 << ASRIER_ADIEi_SHIFT(i))
118 #define ASRIER_ADIE(i)			(1 << ASRIER_ADIEi_SHIFT(i))
119 
120 /* REG2 0x0C REG_ASRCNCR */
121 #define ASRCNCR_ANCi_SHIFT(i, b)	(b * i)
122 #define ASRCNCR_ANCi_MASK(i, b)		(((1 << b) - 1) << ASRCNCR_ANCi_SHIFT(i, b))
123 #define ASRCNCR_ANCi(i, v, b)		((v << ASRCNCR_ANCi_SHIFT(i, b)) & ASRCNCR_ANCi_MASK(i, b))
124 
125 /* REG3 0x10 REG_ASRCFG */
126 #define ASRCFG_INIRQi_SHIFT(i)		(21 + i)
127 #define ASRCFG_INIRQi_MASK(i)		(1 << ASRCFG_INIRQi_SHIFT(i))
128 #define ASRCFG_INIRQi			(1 << ASRCFG_INIRQi_SHIFT(i))
129 #define ASRCFG_NDPRi_SHIFT(i)		(18 + i)
130 #define ASRCFG_NDPRi_MASK(i)		(1 << ASRCFG_NDPRi_SHIFT(i))
131 #define ASRCFG_NDPRi_ALL_SHIFT		18
132 #define ASRCFG_NDPRi_ALL_MASK		(7 << ASRCFG_NDPRi_ALL_SHIFT)
133 #define ASRCFG_NDPRi			(1 << ASRCFG_NDPRi_SHIFT(i))
134 #define ASRCFG_POSTMODi_SHIFT(i)	(8 + (i << 2))
135 #define ASRCFG_POSTMODi_WIDTH		2
136 #define ASRCFG_POSTMODi_MASK(i)		(((1 << ASRCFG_POSTMODi_WIDTH) - 1) << ASRCFG_POSTMODi_SHIFT(i))
137 #define ASRCFG_POSTMODi_ALL_MASK	(ASRCFG_POSTMODi_MASK(0) | ASRCFG_POSTMODi_MASK(1) | ASRCFG_POSTMODi_MASK(2))
138 #define ASRCFG_POSTMOD(i, v)		((v) << ASRCFG_POSTMODi_SHIFT(i))
139 #define ASRCFG_POSTMODi_UP(i)		(0 << ASRCFG_POSTMODi_SHIFT(i))
140 #define ASRCFG_POSTMODi_DCON(i)		(1 << ASRCFG_POSTMODi_SHIFT(i))
141 #define ASRCFG_POSTMODi_DOWN(i)		(2 << ASRCFG_POSTMODi_SHIFT(i))
142 #define ASRCFG_PREMODi_SHIFT(i)		(6 + (i << 2))
143 #define ASRCFG_PREMODi_WIDTH		2
144 #define ASRCFG_PREMODi_MASK(i)		(((1 << ASRCFG_PREMODi_WIDTH) - 1) << ASRCFG_PREMODi_SHIFT(i))
145 #define ASRCFG_PREMODi_ALL_MASK		(ASRCFG_PREMODi_MASK(0) | ASRCFG_PREMODi_MASK(1) | ASRCFG_PREMODi_MASK(2))
146 #define ASRCFG_PREMOD(i, v)		((v) << ASRCFG_PREMODi_SHIFT(i))
147 #define ASRCFG_PREMODi_UP(i)		(0 << ASRCFG_PREMODi_SHIFT(i))
148 #define ASRCFG_PREMODi_DCON(i)		(1 << ASRCFG_PREMODi_SHIFT(i))
149 #define ASRCFG_PREMODi_DOWN(i)		(2 << ASRCFG_PREMODi_SHIFT(i))
150 #define ASRCFG_PREMODi_BYPASS(i)	(3 << ASRCFG_PREMODi_SHIFT(i))
151 
152 /* REG4 0x14 REG_ASRCSR */
153 #define ASRCSR_AxCSi_WIDTH		4
154 #define ASRCSR_AxCSi_MASK		((1 << ASRCSR_AxCSi_WIDTH) - 1)
155 #define ASRCSR_AOCSi_SHIFT(i)		(12 + (i << 2))
156 #define ASRCSR_AOCSi_MASK(i)		(((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AOCSi_SHIFT(i))
157 #define ASRCSR_AOCS(i, v)		((v) << ASRCSR_AOCSi_SHIFT(i))
158 #define ASRCSR_AICSi_SHIFT(i)		(i << 2)
159 #define ASRCSR_AICSi_MASK(i)		(((1 << ASRCSR_AxCSi_WIDTH) - 1) << ASRCSR_AICSi_SHIFT(i))
160 #define ASRCSR_AICS(i, v)		((v) << ASRCSR_AICSi_SHIFT(i))
161 
162 /* REG5&6 0x18 & 0x1C REG_ASRCDR1 & ASRCDR2 */
163 #define ASRCDRi_AxCPi_WIDTH		3
164 #define ASRCDRi_AICPi_SHIFT(i)		(0 + (i % 2) * 6)
165 #define ASRCDRi_AICPi_MASK(i)		(((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICPi_SHIFT(i))
166 #define ASRCDRi_AICP(i, v)		((v) << ASRCDRi_AICPi_SHIFT(i))
167 #define ASRCDRi_AICDi_SHIFT(i)		(3 + (i % 2) * 6)
168 #define ASRCDRi_AICDi_MASK(i)		(((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AICDi_SHIFT(i))
169 #define ASRCDRi_AICD(i, v)		((v) << ASRCDRi_AICDi_SHIFT(i))
170 #define ASRCDRi_AOCPi_SHIFT(i)		((i < 2) ? 12 + i * 6 : 6)
171 #define ASRCDRi_AOCPi_MASK(i)		(((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCPi_SHIFT(i))
172 #define ASRCDRi_AOCP(i, v)		((v) << ASRCDRi_AOCPi_SHIFT(i))
173 #define ASRCDRi_AOCDi_SHIFT(i)		((i < 2) ? 15 + i * 6 : 9)
174 #define ASRCDRi_AOCDi_MASK(i)		(((1 << ASRCDRi_AxCPi_WIDTH) - 1) << ASRCDRi_AOCDi_SHIFT(i))
175 #define ASRCDRi_AOCD(i, v)		((v) << ASRCDRi_AOCDi_SHIFT(i))
176 
177 /* REG7 0x20 REG_ASRSTR */
178 #define ASRSTR_DSLCNT_SHIFT		21
179 #define ASRSTR_DSLCNT_MASK		(1 << ASRSTR_DSLCNT_SHIFT)
180 #define ASRSTR_DSLCNT			(1 << ASRSTR_DSLCNT_SHIFT)
181 #define ASRSTR_ATQOL_SHIFT		20
182 #define ASRSTR_ATQOL_MASK		(1 << ASRSTR_ATQOL_SHIFT)
183 #define ASRSTR_ATQOL			(1 << ASRSTR_ATQOL_SHIFT)
184 #define ASRSTR_AOOLi_SHIFT(i)		(17 + i)
185 #define ASRSTR_AOOLi_MASK(i)		(1 << ASRSTR_AOOLi_SHIFT(i))
186 #define ASRSTR_AOOL(i)			(1 << ASRSTR_AOOLi_SHIFT(i))
187 #define ASRSTR_AIOLi_SHIFT(i)		(14 + i)
188 #define ASRSTR_AIOLi_MASK(i)		(1 << ASRSTR_AIOLi_SHIFT(i))
189 #define ASRSTR_AIOL(i)			(1 << ASRSTR_AIOLi_SHIFT(i))
190 #define ASRSTR_AODOi_SHIFT(i)		(11 + i)
191 #define ASRSTR_AODOi_MASK(i)		(1 << ASRSTR_AODOi_SHIFT(i))
192 #define ASRSTR_AODO(i)			(1 << ASRSTR_AODOi_SHIFT(i))
193 #define ASRSTR_AIDUi_SHIFT(i)		(8 + i)
194 #define ASRSTR_AIDUi_MASK(i)		(1 << ASRSTR_AIDUi_SHIFT(i))
195 #define ASRSTR_AIDU(i)			(1 << ASRSTR_AIDUi_SHIFT(i))
196 #define ASRSTR_FPWT_SHIFT		7
197 #define ASRSTR_FPWT_MASK		(1 << ASRSTR_FPWT_SHIFT)
198 #define ASRSTR_FPWT			(1 << ASRSTR_FPWT_SHIFT)
199 #define ASRSTR_AOLE_SHIFT		6
200 #define ASRSTR_AOLE_MASK		(1 << ASRSTR_AOLE_SHIFT)
201 #define ASRSTR_AOLE			(1 << ASRSTR_AOLE_SHIFT)
202 #define ASRSTR_AODEi_SHIFT(i)		(3 + i)
203 #define ASRSTR_AODFi_MASK(i)		(1 << ASRSTR_AODEi_SHIFT(i))
204 #define ASRSTR_AODF(i)			(1 << ASRSTR_AODEi_SHIFT(i))
205 #define ASRSTR_AIDEi_SHIFT(i)		(0 + i)
206 #define ASRSTR_AIDEi_MASK(i)		(1 << ASRSTR_AIDEi_SHIFT(i))
207 #define ASRSTR_AIDE(i)			(1 << ASRSTR_AIDEi_SHIFT(i))
208 
209 /* REG10 0x54 REG_ASRTFR1 */
210 #define ASRTFR1_TF_BASE_WIDTH		7
211 #define ASRTFR1_TF_BASE_SHIFT		6
212 #define ASRTFR1_TF_BASE_MASK		(((1 << ASRTFR1_TF_BASE_WIDTH) - 1) << ASRTFR1_TF_BASE_SHIFT)
213 #define ASRTFR1_TF_BASE(i)		((i) << ASRTFR1_TF_BASE_SHIFT)
214 
215 /*
216  * REG22 0xA0 REG_ASRMCRA
217  * REG24 0xA8 REG_ASRMCRB
218  * REG26 0xB0 REG_ASRMCRC
219  */
220 #define ASRMCRi_ZEROBUFi_SHIFT		23
221 #define ASRMCRi_ZEROBUFi_MASK		(1 << ASRMCRi_ZEROBUFi_SHIFT)
222 #define ASRMCRi_ZEROBUFi		(1 << ASRMCRi_ZEROBUFi_SHIFT)
223 #define ASRMCRi_EXTTHRSHi_SHIFT		22
224 #define ASRMCRi_EXTTHRSHi_MASK		(1 << ASRMCRi_EXTTHRSHi_SHIFT)
225 #define ASRMCRi_EXTTHRSHi		(1 << ASRMCRi_EXTTHRSHi_SHIFT)
226 #define ASRMCRi_BUFSTALLi_SHIFT		21
227 #define ASRMCRi_BUFSTALLi_MASK		(1 << ASRMCRi_BUFSTALLi_SHIFT)
228 #define ASRMCRi_BUFSTALLi		(1 << ASRMCRi_BUFSTALLi_SHIFT)
229 #define ASRMCRi_BYPASSPOLYi_SHIFT	20
230 #define ASRMCRi_BYPASSPOLYi_MASK	(1 << ASRMCRi_BYPASSPOLYi_SHIFT)
231 #define ASRMCRi_BYPASSPOLYi		(1 << ASRMCRi_BYPASSPOLYi_SHIFT)
232 #define ASRMCRi_OUTFIFO_THRESHOLD_WIDTH	6
233 #define ASRMCRi_OUTFIFO_THRESHOLD_SHIFT	12
234 #define ASRMCRi_OUTFIFO_THRESHOLD_MASK	(((1 << ASRMCRi_OUTFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT)
235 #define ASRMCRi_OUTFIFO_THRESHOLD(v)	(((v) << ASRMCRi_OUTFIFO_THRESHOLD_SHIFT) & ASRMCRi_OUTFIFO_THRESHOLD_MASK)
236 #define ASRMCRi_RSYNIFi_SHIFT		11
237 #define ASRMCRi_RSYNIFi_MASK		(1 << ASRMCRi_RSYNIFi_SHIFT)
238 #define ASRMCRi_RSYNIFi			(1 << ASRMCRi_RSYNIFi_SHIFT)
239 #define ASRMCRi_RSYNOFi_SHIFT		10
240 #define ASRMCRi_RSYNOFi_MASK		(1 << ASRMCRi_RSYNOFi_SHIFT)
241 #define ASRMCRi_RSYNOFi			(1 << ASRMCRi_RSYNOFi_SHIFT)
242 #define ASRMCRi_INFIFO_THRESHOLD_WIDTH	6
243 #define ASRMCRi_INFIFO_THRESHOLD_SHIFT	0
244 #define ASRMCRi_INFIFO_THRESHOLD_MASK	(((1 << ASRMCRi_INFIFO_THRESHOLD_WIDTH) - 1) << ASRMCRi_INFIFO_THRESHOLD_SHIFT)
245 #define ASRMCRi_INFIFO_THRESHOLD(v)	(((v) << ASRMCRi_INFIFO_THRESHOLD_SHIFT) & ASRMCRi_INFIFO_THRESHOLD_MASK)
246 
247 /*
248  * REG23 0xA4 REG_ASRFSTA
249  * REG25 0xAC REG_ASRFSTB
250  * REG27 0xB4 REG_ASRFSTC
251  */
252 #define ASRFSTi_OAFi_SHIFT		23
253 #define ASRFSTi_OAFi_MASK		(1 << ASRFSTi_OAFi_SHIFT)
254 #define ASRFSTi_OAFi			(1 << ASRFSTi_OAFi_SHIFT)
255 #define ASRFSTi_OUTPUT_FIFO_WIDTH	7
256 #define ASRFSTi_OUTPUT_FIFO_SHIFT	12
257 #define ASRFSTi_OUTPUT_FIFO_MASK	(((1 << ASRFSTi_OUTPUT_FIFO_WIDTH) - 1) << ASRFSTi_OUTPUT_FIFO_SHIFT)
258 #define ASRFSTi_IAEi_SHIFT		11
259 #define ASRFSTi_IAEi_MASK		(1 << ASRFSTi_IAEi_SHIFT)
260 #define ASRFSTi_IAEi			(1 << ASRFSTi_IAEi_SHIFT)
261 #define ASRFSTi_INPUT_FIFO_WIDTH	7
262 #define ASRFSTi_INPUT_FIFO_SHIFT	0
263 #define ASRFSTi_INPUT_FIFO_MASK		((1 << ASRFSTi_INPUT_FIFO_WIDTH) - 1)
264 
265 /* REG28 0xC0 & 0xC4 & 0xC8 REG_ASRMCR1i */
266 #define ASRMCR1i_IWD_WIDTH		3
267 #define ASRMCR1i_IWD_SHIFT		9
268 #define ASRMCR1i_IWD_MASK		(((1 << ASRMCR1i_IWD_WIDTH) - 1) << ASRMCR1i_IWD_SHIFT)
269 #define ASRMCR1i_IWD(v)			((v) << ASRMCR1i_IWD_SHIFT)
270 #define ASRMCR1i_IMSB_SHIFT		8
271 #define ASRMCR1i_IMSB_MASK		(1 << ASRMCR1i_IMSB_SHIFT)
272 #define ASRMCR1i_IMSB_MSB		(1 << ASRMCR1i_IMSB_SHIFT)
273 #define ASRMCR1i_IMSB_LSB		(0 << ASRMCR1i_IMSB_SHIFT)
274 #define ASRMCR1i_OMSB_SHIFT		2
275 #define ASRMCR1i_OMSB_MASK		(1 << ASRMCR1i_OMSB_SHIFT)
276 #define ASRMCR1i_OMSB_MSB		(1 << ASRMCR1i_OMSB_SHIFT)
277 #define ASRMCR1i_OMSB_LSB		(0 << ASRMCR1i_OMSB_SHIFT)
278 #define ASRMCR1i_OSGN_SHIFT		1
279 #define ASRMCR1i_OSGN_MASK		(1 << ASRMCR1i_OSGN_SHIFT)
280 #define ASRMCR1i_OSGN			(1 << ASRMCR1i_OSGN_SHIFT)
281 #define ASRMCR1i_OW16_SHIFT		0
282 #define ASRMCR1i_OW16_MASK		(1 << ASRMCR1i_OW16_SHIFT)
283 #define ASRMCR1i_OW16(v)		((v) << ASRMCR1i_OW16_SHIFT)
284 
285 #define ASRC_PAIR_MAX_NUM	(ASRC_PAIR_C + 1)
286 
287 enum asrc_inclk {
288 	INCLK_NONE = 0x03,
289 	INCLK_ESAI_RX = 0x00,
290 	INCLK_SSI1_RX = 0x01,
291 	INCLK_SSI2_RX = 0x02,
292 	INCLK_SSI3_RX = 0x07,
293 	INCLK_SPDIF_RX = 0x04,
294 	INCLK_MLB_CLK = 0x05,
295 	INCLK_PAD = 0x06,
296 	INCLK_ESAI_TX = 0x08,
297 	INCLK_SSI1_TX = 0x09,
298 	INCLK_SSI2_TX = 0x0a,
299 	INCLK_SSI3_TX = 0x0b,
300 	INCLK_SPDIF_TX = 0x0c,
301 	INCLK_ASRCK1_CLK = 0x0f,
302 
303 	/* clocks for imx8 */
304 	INCLK_AUD_PLL_DIV_CLK0 = 0x10,
305 	INCLK_AUD_PLL_DIV_CLK1 = 0x11,
306 	INCLK_AUD_CLK0         = 0x12,
307 	INCLK_AUD_CLK1         = 0x13,
308 	INCLK_ESAI0_RX_CLK     = 0x14,
309 	INCLK_ESAI0_TX_CLK     = 0x15,
310 	INCLK_SPDIF0_RX        = 0x16,
311 	INCLK_SPDIF1_RX        = 0x17,
312 	INCLK_SAI0_RX_BCLK     = 0x18,
313 	INCLK_SAI0_TX_BCLK     = 0x19,
314 	INCLK_SAI1_RX_BCLK     = 0x1a,
315 	INCLK_SAI1_TX_BCLK     = 0x1b,
316 	INCLK_SAI2_RX_BCLK     = 0x1c,
317 	INCLK_SAI3_RX_BCLK     = 0x1d,
318 	INCLK_ASRC0_MUX_CLK    = 0x1e,
319 
320 	INCLK_ESAI1_RX_CLK     = 0x20,
321 	INCLK_ESAI1_TX_CLK     = 0x21,
322 	INCLK_SAI6_TX_BCLK     = 0x22,
323 	INCLK_HDMI_RX_SAI0_RX_BCLK     = 0x24,
324 	INCLK_HDMI_TX_SAI0_TX_BCLK     = 0x25,
325 };
326 
327 enum asrc_outclk {
328 	OUTCLK_NONE = 0x03,
329 	OUTCLK_ESAI_TX = 0x00,
330 	OUTCLK_SSI1_TX = 0x01,
331 	OUTCLK_SSI2_TX = 0x02,
332 	OUTCLK_SSI3_TX = 0x07,
333 	OUTCLK_SPDIF_TX = 0x04,
334 	OUTCLK_MLB_CLK = 0x05,
335 	OUTCLK_PAD = 0x06,
336 	OUTCLK_ESAI_RX = 0x08,
337 	OUTCLK_SSI1_RX = 0x09,
338 	OUTCLK_SSI2_RX = 0x0a,
339 	OUTCLK_SSI3_RX = 0x0b,
340 	OUTCLK_SPDIF_RX = 0x0c,
341 	OUTCLK_ASRCK1_CLK = 0x0f,
342 
343 	/* clocks for imx8 */
344 	OUTCLK_AUD_PLL_DIV_CLK0 = 0x10,
345 	OUTCLK_AUD_PLL_DIV_CLK1 = 0x11,
346 	OUTCLK_AUD_CLK0         = 0x12,
347 	OUTCLK_AUD_CLK1         = 0x13,
348 	OUTCLK_ESAI0_RX_CLK     = 0x14,
349 	OUTCLK_ESAI0_TX_CLK     = 0x15,
350 	OUTCLK_SPDIF0_RX        = 0x16,
351 	OUTCLK_SPDIF1_RX        = 0x17,
352 	OUTCLK_SAI0_RX_BCLK     = 0x18,
353 	OUTCLK_SAI0_TX_BCLK     = 0x19,
354 	OUTCLK_SAI1_RX_BCLK     = 0x1a,
355 	OUTCLK_SAI1_TX_BCLK     = 0x1b,
356 	OUTCLK_SAI2_RX_BCLK     = 0x1c,
357 	OUTCLK_SAI3_RX_BCLK     = 0x1d,
358 	OUTCLK_ASRCO_MUX_CLK    = 0x1e,
359 
360 	OUTCLK_ESAI1_RX_CLK     = 0x20,
361 	OUTCLK_ESAI1_TX_CLK     = 0x21,
362 	OUTCLK_SAI6_TX_BCLK     = 0x22,
363 	OUTCLK_HDMI_RX_SAI0_RX_BCLK     = 0x24,
364 	OUTCLK_HDMI_TX_SAI0_TX_BCLK     = 0x25,
365 };
366 
367 #define ASRC_CLK_MAX_NUM	16
368 #define ASRC_CLK_MAP_LEN	0x30
369 
370 enum asrc_word_width {
371 	ASRC_WIDTH_24_BIT = 0,
372 	ASRC_WIDTH_16_BIT = 1,
373 	ASRC_WIDTH_8_BIT = 2,
374 };
375 
376 struct asrc_config {
377 	enum asrc_pair_index pair;
378 	unsigned int channel_num;
379 	unsigned int buffer_num;
380 	unsigned int dma_buffer_size;
381 	unsigned int input_sample_rate;
382 	unsigned int output_sample_rate;
383 	snd_pcm_format_t input_format;
384 	snd_pcm_format_t output_format;
385 	enum asrc_inclk inclk;
386 	enum asrc_outclk outclk;
387 };
388 
389 struct asrc_req {
390 	unsigned int chn_num;
391 	enum asrc_pair_index index;
392 };
393 
394 struct asrc_querybuf {
395 	unsigned int buffer_index;
396 	unsigned int input_length;
397 	unsigned int output_length;
398 	unsigned long input_offset;
399 	unsigned long output_offset;
400 };
401 
402 struct asrc_convert_buffer {
403 	void *input_buffer_vaddr;
404 	void *output_buffer_vaddr;
405 	unsigned int input_buffer_length;
406 	unsigned int output_buffer_length;
407 };
408 
409 struct asrc_status_flags {
410 	enum asrc_pair_index index;
411 	unsigned int overload_error;
412 };
413 
414 enum asrc_error_status {
415 	ASRC_TASK_Q_OVERLOAD		= 0x01,
416 	ASRC_OUTPUT_TASK_OVERLOAD	= 0x02,
417 	ASRC_INPUT_TASK_OVERLOAD	= 0x04,
418 	ASRC_OUTPUT_BUFFER_OVERFLOW	= 0x08,
419 	ASRC_INPUT_BUFFER_UNDERRUN	= 0x10,
420 };
421 
422 struct dma_block {
423 	dma_addr_t dma_paddr;
424 	void *dma_vaddr;
425 	unsigned int length;
426 };
427 
428 /**
429  * fsl_asrc_soc_data: soc specific data
430  *
431  * @use_edma: using edma as dma device or not
432  * @channel_bits: width of ASRCNCR register for each pair
433  */
434 struct fsl_asrc_soc_data {
435 	bool use_edma;
436 	unsigned int channel_bits;
437 };
438 
439 /**
440  * fsl_asrc_pair_priv: ASRC Pair private data
441  *
442  * @config: configuration profile
443  */
444 struct fsl_asrc_pair_priv {
445 	struct asrc_config *config;
446 };
447 
448 /**
449  * fsl_asrc_priv: ASRC private data
450  *
451  * @asrck_clk: clock sources to driver ASRC internal logic
452  * @soc: soc specific data
453  * @clk_map: clock map for input/output clock
454  * @regcache_cfg: store register value of REG_ASRCFG
455  */
456 struct fsl_asrc_priv {
457 	struct clk *asrck_clk[ASRC_CLK_MAX_NUM];
458 	const struct fsl_asrc_soc_data *soc;
459 	unsigned char *clk_map[2];
460 
461 	u32 regcache_cfg;
462 };
463 
464 #endif /* _FSL_ASRC_H */
465