1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2014 Freescale Semiconductor, Inc. 4 */ 5 6 #ifndef __MX6SX_RDC_H__ 7 #define __MX6SX_RDC_H__ 8 9 #define RDC_SEMA_PROC_ID 2 /* The processor ID for main CPU */ 10 11 enum { 12 RDC_PER_PWM1 = 0, 13 RDC_PER_PWM2, 14 RDC_PER_PWM3, 15 RDC_PER_PWM4, 16 RDC_PER_CAN1, 17 RDC_PER_CAN2, 18 RDC_PER_GPT, 19 RDC_PER_GPIO1, 20 RDC_PER_GPIO2, 21 RDC_PER_GPIO3, 22 RDC_PER_GPIO4, 23 RDC_PER_GPIO5, 24 RDC_PER_GPIO6, 25 RDC_PER_GPIO7, 26 RDC_PER_KPP, 27 RDC_PER_WDOG1, 28 RDC_PER_WODG2, 29 RDC_PER_CCM, 30 RDC_PER_ANATOPDIG, 31 RDC_PER_SNVSHP, 32 RDC_PER_EPIT1, 33 RDC_PER_EPIT2, 34 RDC_PER_SRC, 35 RDC_PER_GPC, 36 RDC_PER_IOMUXC, 37 RDC_PER_IOMUXCGPR, 38 RDC_PER_CANFD1, 39 RDC_PER_SDMA, 40 RDC_PER_CANFD2, 41 RDC_PER_SEMA1, 42 RDC_PER_SEMA2, 43 RDC_PER_RDC, 44 RDC_PER_AIPSTZ1_GE1, 45 RDC_PER_AIPSTZ2_GE2, 46 RDC_PER_USBO2H_PL301, 47 RDC_PER_USBO2H_USB, 48 RDC_PER_ENET1, 49 RDC_PER_MLB25, 50 RDC_PER_USDHC1, 51 RDC_PER_USDHC2, 52 RDC_PER_USDHC3, 53 RDC_PER_USDHC4, 54 RDC_PER_I2C1, 55 RDC_PER_I2C2, 56 RDC_PER_I2C3, 57 RDC_PER_ROMCP, 58 RDC_PER_MMDC, 59 RDC_PER_ENET2, 60 RDC_PER_EIM, 61 RDC_PER_OCOTP, 62 RDC_PER_CSU, 63 RDC_PER_PERFMON1, 64 RDC_PER_PERFMON2, 65 RDC_PER_AXIMON, 66 RDC_PER_TZASC1, 67 RDC_PER_SAI1, 68 RDC_PER_AUDMUX, 69 RDC_PER_SAI2, 70 RDC_PER_QSPI1, 71 RDC_PER_QSPI2, 72 RDC_PER_UART2, 73 RDC_PER_UART3, 74 RDC_PER_UART4, 75 RDC_PER_UART5, 76 RDC_PER_I2C4, 77 RDC_PER_QOSC, 78 RDC_PER_CAAM, 79 RDC_PER_DAP, 80 RDC_PER_ADC1, 81 RDC_PER_ADC2, 82 RDC_PER_WDOG3, 83 RDC_PER_ECSPI5, 84 RDC_PER_SEMA4, 85 RDC_PER_MUPORT1, 86 RDC_PER_CANFD_CPU, 87 RDC_PER_MUPORT2, 88 RDC_PER_UART6, 89 RDC_PER_PWM5, 90 RDC_PER_PWM6, 91 RDC_PER_PWM7, 92 RDC_PER_PWM8, 93 RDC_PER_AIPSTZ3_GE0, 94 RDC_PER_AIPSTZ3_GE1, 95 RDC_PER_RESERVED1, 96 RDC_PER_SPDIF, 97 RDC_PER_ECSPI1, 98 RDC_PER_ECSPI2, 99 RDC_PER_ECSPI3, 100 RDC_PER_ECSPI4, 101 RDC_PER_RESERVED2, 102 RDC_PER_RESERVED3, 103 RDC_PER_UART1, 104 RDC_PER_ESAI, 105 RDC_PER_SSI1, 106 RDC_PER_SSI2, 107 RDC_PER_SSI3, 108 RDC_PER_ASRC, 109 RDC_PER_RESERVED4, 110 RDC_PER_SPBA_MA, 111 RDC_PER_GIS, 112 RDC_PER_DCIC1, 113 RDC_PER_DCIC2, 114 RDC_PER_CSI1, 115 RDC_PER_PXP, 116 RDC_PER_CSI2, 117 RDC_PER_LCDIF1, 118 RDC_PER_LCDIF2, 119 RDC_PER_VADC, 120 RDC_PER_VDEC, 121 RDC_PER_SPBA_DISPLAYMIX, 122 }; 123 124 enum { 125 RDC_MA_A9_L2CACHE = 0, 126 RDC_MA_M4, 127 RDC_MA_GPU, 128 RDC_MA_CSI1, 129 RDC_MA_CSI2, 130 RDC_MA_LCDIF1, 131 RDC_MA_LCDIF2, 132 RDC_MA_PXP, 133 RDC_MA_PCIE_CTRL, 134 RDC_MA_DAP, 135 RDC_MA_CAAM, 136 RDC_MA_SDMA_PERI, 137 RDC_MA_SDMA_BURST, 138 RDC_MA_APBHDMA, 139 RDC_MA_RAWNAND, 140 RDC_MA_USDHC1, 141 RDC_MA_USDHC2, 142 RDC_MA_USDHC3, 143 RDC_MA_USDHC4, 144 RDC_MA_USB, 145 RDC_MA_MLB, 146 RDC_MA_TEST, 147 RDC_MA_ENET1_TX, 148 RDC_MA_ENET1_RX, 149 RDC_MA_ENET2_TX, 150 RDC_MA_ENET2_RX, 151 RDC_MA_SDMA, 152 }; 153 154 #endif /* __MX6SX_RDC_H__*/ 155