1 /*
2 * STM32F405 SoC
3 *
4 * Copyright (c) 2014 Alistair Francis <alistair@alistair23.me>
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a copy
7 * of this software and associated documentation files (the "Software"), to deal
8 * in the Software without restriction, including without limitation the rights
9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
10 * copies of the Software, and to permit persons to whom the Software is
11 * furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice shall be included in
14 * all copies or substantial portions of the Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
22 * THE SOFTWARE.
23 */
24
25 #include "qemu/osdep.h"
26 #include "qapi/error.h"
27 #include "exec/address-spaces.h"
28 #include "sysemu/sysemu.h"
29 #include "hw/arm/stm32f405_soc.h"
30 #include "hw/qdev-clock.h"
31 #include "hw/misc/unimp.h"
32
33 #define RCC_ADDR 0x40023800
34 #define SYSCFG_ADD 0x40013800
35 static const uint32_t usart_addr[] = { 0x40011000, 0x40004400, 0x40004800,
36 0x40004C00, 0x40005000, 0x40011400,
37 0x40007800, 0x40007C00 };
38 /* At the moment only Timer 2 to 5 are modelled */
39 static const uint32_t timer_addr[] = { 0x40000000, 0x40000400,
40 0x40000800, 0x40000C00 };
41 static const uint32_t adc_addr[] = { 0x40012000, 0x40012100, 0x40012200,
42 0x40012300, 0x40012400, 0x40012500 };
43 static const uint32_t spi_addr[] = { 0x40013000, 0x40003800, 0x40003C00,
44 0x40013400, 0x40015000, 0x40015400 };
45 #define EXTI_ADDR 0x40013C00
46
47 #define SYSCFG_IRQ 71
48 static const int usart_irq[] = { 37, 38, 39, 52, 53, 71, 82, 83 };
49 static const int timer_irq[] = { 28, 29, 30, 50 };
50 #define ADC_IRQ 18
51 static const int spi_irq[] = { 35, 36, 51, 0, 0, 0 };
52 static const int exti_irq[] = { 6, 7, 8, 9, 10, 23, 23, 23, 23, 23, 40,
53 40, 40, 40, 40, 40} ;
54
55
stm32f405_soc_initfn(Object * obj)56 static void stm32f405_soc_initfn(Object *obj)
57 {
58 STM32F405State *s = STM32F405_SOC(obj);
59 int i;
60
61 object_initialize_child(obj, "armv7m", &s->armv7m, TYPE_ARMV7M);
62
63 object_initialize_child(obj, "rcc", &s->rcc, TYPE_STM32_RCC);
64
65 object_initialize_child(obj, "syscfg", &s->syscfg, TYPE_STM32F4XX_SYSCFG);
66
67 for (i = 0; i < STM_NUM_USARTS; i++) {
68 object_initialize_child(obj, "usart[*]", &s->usart[i],
69 TYPE_STM32F2XX_USART);
70 }
71
72 for (i = 0; i < STM_NUM_TIMERS; i++) {
73 object_initialize_child(obj, "timer[*]", &s->timer[i],
74 TYPE_STM32F2XX_TIMER);
75 }
76
77 for (i = 0; i < STM_NUM_ADCS; i++) {
78 object_initialize_child(obj, "adc[*]", &s->adc[i], TYPE_STM32F2XX_ADC);
79 }
80
81 for (i = 0; i < STM_NUM_SPIS; i++) {
82 object_initialize_child(obj, "spi[*]", &s->spi[i], TYPE_STM32F2XX_SPI);
83 }
84
85 object_initialize_child(obj, "exti", &s->exti, TYPE_STM32F4XX_EXTI);
86
87 s->sysclk = qdev_init_clock_in(DEVICE(s), "sysclk", NULL, NULL, 0);
88 s->refclk = qdev_init_clock_in(DEVICE(s), "refclk", NULL, NULL, 0);
89 }
90
stm32f405_soc_realize(DeviceState * dev_soc,Error ** errp)91 static void stm32f405_soc_realize(DeviceState *dev_soc, Error **errp)
92 {
93 STM32F405State *s = STM32F405_SOC(dev_soc);
94 MemoryRegion *system_memory = get_system_memory();
95 DeviceState *dev, *armv7m;
96 SysBusDevice *busdev;
97 Error *err = NULL;
98 int i;
99
100 /*
101 * We use s->refclk internally and only define it with qdev_init_clock_in()
102 * so it is correctly parented and not leaked on an init/deinit; it is not
103 * intended as an externally exposed clock.
104 */
105 if (clock_has_source(s->refclk)) {
106 error_setg(errp, "refclk clock must not be wired up by the board code");
107 return;
108 }
109
110 if (!clock_has_source(s->sysclk)) {
111 error_setg(errp, "sysclk clock must be wired up by the board code");
112 return;
113 }
114
115 /*
116 * TODO: ideally we should model the SoC RCC and its ability to
117 * change the sysclk frequency and define different sysclk sources.
118 */
119
120 /* The refclk always runs at frequency HCLK / 8 */
121 clock_set_mul_div(s->refclk, 8, 1);
122 clock_set_source(s->refclk, s->sysclk);
123
124 memory_region_init_rom(&s->flash, OBJECT(dev_soc), "STM32F405.flash",
125 FLASH_SIZE, &err);
126 if (err != NULL) {
127 error_propagate(errp, err);
128 return;
129 }
130 memory_region_init_alias(&s->flash_alias, OBJECT(dev_soc),
131 "STM32F405.flash.alias", &s->flash, 0,
132 FLASH_SIZE);
133
134 memory_region_add_subregion(system_memory, FLASH_BASE_ADDRESS, &s->flash);
135 memory_region_add_subregion(system_memory, 0, &s->flash_alias);
136
137 memory_region_init_ram(&s->sram, NULL, "STM32F405.sram", SRAM_SIZE,
138 &err);
139 if (err != NULL) {
140 error_propagate(errp, err);
141 return;
142 }
143 memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, &s->sram);
144
145 memory_region_init_ram(&s->ccm, NULL, "STM32F405.ccm", CCM_SIZE,
146 &err);
147 if (err != NULL) {
148 error_propagate(errp, err);
149 return;
150 }
151 memory_region_add_subregion(system_memory, CCM_BASE_ADDRESS, &s->ccm);
152
153 armv7m = DEVICE(&s->armv7m);
154 qdev_prop_set_uint32(armv7m, "num-irq", 96);
155 qdev_prop_set_uint8(armv7m, "num-prio-bits", 4);
156 qdev_prop_set_string(armv7m, "cpu-type", ARM_CPU_TYPE_NAME("cortex-m4"));
157 qdev_prop_set_bit(armv7m, "enable-bitband", true);
158 qdev_connect_clock_in(armv7m, "cpuclk", s->sysclk);
159 qdev_connect_clock_in(armv7m, "refclk", s->refclk);
160 object_property_set_link(OBJECT(&s->armv7m), "memory",
161 OBJECT(system_memory), &error_abort);
162 if (!sysbus_realize(SYS_BUS_DEVICE(&s->armv7m), errp)) {
163 return;
164 }
165
166 /* Reset and clock controller */
167 dev = DEVICE(&s->rcc);
168 if (!sysbus_realize(SYS_BUS_DEVICE(&s->rcc), errp)) {
169 return;
170 }
171 busdev = SYS_BUS_DEVICE(dev);
172 sysbus_mmio_map(busdev, 0, RCC_ADDR);
173
174 /* System configuration controller */
175 dev = DEVICE(&s->syscfg);
176 if (!sysbus_realize(SYS_BUS_DEVICE(&s->syscfg), errp)) {
177 return;
178 }
179 busdev = SYS_BUS_DEVICE(dev);
180 sysbus_mmio_map(busdev, 0, SYSCFG_ADD);
181 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, SYSCFG_IRQ));
182
183 /* Attach UART (uses USART registers) and USART controllers */
184 for (i = 0; i < STM_NUM_USARTS; i++) {
185 dev = DEVICE(&(s->usart[i]));
186 qdev_prop_set_chr(dev, "chardev", serial_hd(i));
187 if (!sysbus_realize(SYS_BUS_DEVICE(&s->usart[i]), errp)) {
188 return;
189 }
190 busdev = SYS_BUS_DEVICE(dev);
191 sysbus_mmio_map(busdev, 0, usart_addr[i]);
192 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, usart_irq[i]));
193 }
194
195 /* Timer 2 to 5 */
196 for (i = 0; i < STM_NUM_TIMERS; i++) {
197 dev = DEVICE(&(s->timer[i]));
198 qdev_prop_set_uint64(dev, "clock-frequency", 1000000000);
199 if (!sysbus_realize(SYS_BUS_DEVICE(&s->timer[i]), errp)) {
200 return;
201 }
202 busdev = SYS_BUS_DEVICE(dev);
203 sysbus_mmio_map(busdev, 0, timer_addr[i]);
204 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, timer_irq[i]));
205 }
206
207 /* ADC device, the IRQs are ORed together */
208 if (!object_initialize_child_with_props(OBJECT(s), "adc-orirq",
209 &s->adc_irqs, sizeof(s->adc_irqs),
210 TYPE_OR_IRQ, errp, NULL)) {
211 return;
212 }
213 object_property_set_int(OBJECT(&s->adc_irqs), "num-lines", STM_NUM_ADCS,
214 &error_abort);
215 if (!qdev_realize(DEVICE(&s->adc_irqs), NULL, errp)) {
216 return;
217 }
218 qdev_connect_gpio_out(DEVICE(&s->adc_irqs), 0,
219 qdev_get_gpio_in(armv7m, ADC_IRQ));
220
221 for (i = 0; i < STM_NUM_ADCS; i++) {
222 dev = DEVICE(&(s->adc[i]));
223 if (!sysbus_realize(SYS_BUS_DEVICE(&s->adc[i]), errp)) {
224 return;
225 }
226 busdev = SYS_BUS_DEVICE(dev);
227 sysbus_mmio_map(busdev, 0, adc_addr[i]);
228 sysbus_connect_irq(busdev, 0,
229 qdev_get_gpio_in(DEVICE(&s->adc_irqs), i));
230 }
231
232 /* SPI devices */
233 for (i = 0; i < STM_NUM_SPIS; i++) {
234 dev = DEVICE(&(s->spi[i]));
235 if (!sysbus_realize(SYS_BUS_DEVICE(&s->spi[i]), errp)) {
236 return;
237 }
238 busdev = SYS_BUS_DEVICE(dev);
239 sysbus_mmio_map(busdev, 0, spi_addr[i]);
240 sysbus_connect_irq(busdev, 0, qdev_get_gpio_in(armv7m, spi_irq[i]));
241 }
242
243 /* EXTI device */
244 dev = DEVICE(&s->exti);
245 if (!sysbus_realize(SYS_BUS_DEVICE(&s->exti), errp)) {
246 return;
247 }
248 busdev = SYS_BUS_DEVICE(dev);
249 sysbus_mmio_map(busdev, 0, EXTI_ADDR);
250 for (i = 0; i < 16; i++) {
251 sysbus_connect_irq(busdev, i, qdev_get_gpio_in(armv7m, exti_irq[i]));
252 }
253 for (i = 0; i < 16; i++) {
254 qdev_connect_gpio_out(DEVICE(&s->syscfg), i, qdev_get_gpio_in(dev, i));
255 }
256
257 create_unimplemented_device("timer[7]", 0x40001400, 0x400);
258 create_unimplemented_device("timer[12]", 0x40001800, 0x400);
259 create_unimplemented_device("timer[6]", 0x40001000, 0x400);
260 create_unimplemented_device("timer[13]", 0x40001C00, 0x400);
261 create_unimplemented_device("timer[14]", 0x40002000, 0x400);
262 create_unimplemented_device("RTC and BKP", 0x40002800, 0x400);
263 create_unimplemented_device("WWDG", 0x40002C00, 0x400);
264 create_unimplemented_device("IWDG", 0x40003000, 0x400);
265 create_unimplemented_device("I2S2ext", 0x40003000, 0x400);
266 create_unimplemented_device("I2S3ext", 0x40004000, 0x400);
267 create_unimplemented_device("I2C1", 0x40005400, 0x400);
268 create_unimplemented_device("I2C2", 0x40005800, 0x400);
269 create_unimplemented_device("I2C3", 0x40005C00, 0x400);
270 create_unimplemented_device("CAN1", 0x40006400, 0x400);
271 create_unimplemented_device("CAN2", 0x40006800, 0x400);
272 create_unimplemented_device("PWR", 0x40007000, 0x400);
273 create_unimplemented_device("DAC", 0x40007400, 0x400);
274 create_unimplemented_device("timer[1]", 0x40010000, 0x400);
275 create_unimplemented_device("timer[8]", 0x40010400, 0x400);
276 create_unimplemented_device("SDIO", 0x40012C00, 0x400);
277 create_unimplemented_device("timer[9]", 0x40014000, 0x400);
278 create_unimplemented_device("timer[10]", 0x40014400, 0x400);
279 create_unimplemented_device("timer[11]", 0x40014800, 0x400);
280 create_unimplemented_device("GPIOA", 0x40020000, 0x400);
281 create_unimplemented_device("GPIOB", 0x40020400, 0x400);
282 create_unimplemented_device("GPIOC", 0x40020800, 0x400);
283 create_unimplemented_device("GPIOD", 0x40020C00, 0x400);
284 create_unimplemented_device("GPIOE", 0x40021000, 0x400);
285 create_unimplemented_device("GPIOF", 0x40021400, 0x400);
286 create_unimplemented_device("GPIOG", 0x40021800, 0x400);
287 create_unimplemented_device("GPIOH", 0x40021C00, 0x400);
288 create_unimplemented_device("GPIOI", 0x40022000, 0x400);
289 create_unimplemented_device("CRC", 0x40023000, 0x400);
290 create_unimplemented_device("Flash Int", 0x40023C00, 0x400);
291 create_unimplemented_device("BKPSRAM", 0x40024000, 0x400);
292 create_unimplemented_device("DMA1", 0x40026000, 0x400);
293 create_unimplemented_device("DMA2", 0x40026400, 0x400);
294 create_unimplemented_device("Ethernet", 0x40028000, 0x1400);
295 create_unimplemented_device("USB OTG HS", 0x40040000, 0x30000);
296 create_unimplemented_device("USB OTG FS", 0x50000000, 0x31000);
297 create_unimplemented_device("DCMI", 0x50050000, 0x400);
298 create_unimplemented_device("RNG", 0x50060800, 0x400);
299 }
300
stm32f405_soc_class_init(ObjectClass * klass,void * data)301 static void stm32f405_soc_class_init(ObjectClass *klass, void *data)
302 {
303 DeviceClass *dc = DEVICE_CLASS(klass);
304
305 dc->realize = stm32f405_soc_realize;
306 /* No vmstate or reset required: device has no internal state */
307 }
308
309 static const TypeInfo stm32f405_soc_info = {
310 .name = TYPE_STM32F405_SOC,
311 .parent = TYPE_SYS_BUS_DEVICE,
312 .instance_size = sizeof(STM32F405State),
313 .instance_init = stm32f405_soc_initfn,
314 .class_init = stm32f405_soc_class_init,
315 };
316
stm32f405_soc_types(void)317 static void stm32f405_soc_types(void)
318 {
319 type_register_static(&stm32f405_soc_info);
320 }
321
322 type_init(stm32f405_soc_types)
323