1 // SPDX-License-Identifier: GPL-2.0+
2 /* Renesas R-Car CAN FD device driver
3 *
4 * Copyright (C) 2015 Renesas Electronics Corp.
5 */
6
7 /* The R-Car CAN FD controller can operate in either one of the below two modes
8 * - CAN FD only mode
9 * - Classical CAN (CAN 2.0) only mode
10 *
11 * This driver puts the controller in CAN FD only mode by default. In this
12 * mode, the controller acts as a CAN FD node that can also interoperate with
13 * CAN 2.0 nodes.
14 *
15 * To switch the controller to Classical CAN (CAN 2.0) only mode, add
16 * "renesas,no-can-fd" optional property to the device tree node. A h/w reset is
17 * also required to switch modes.
18 *
19 * Note: The h/w manual register naming convention is clumsy and not acceptable
20 * to use as it is in the driver. However, those names are added as comments
21 * wherever it is modified to a readable name.
22 */
23
24 #include <linux/bitmap.h>
25 #include <linux/bitops.h>
26 #include <linux/can/dev.h>
27 #include <linux/clk.h>
28 #include <linux/errno.h>
29 #include <linux/ethtool.h>
30 #include <linux/interrupt.h>
31 #include <linux/iopoll.h>
32 #include <linux/kernel.h>
33 #include <linux/module.h>
34 #include <linux/moduleparam.h>
35 #include <linux/netdevice.h>
36 #include <linux/of.h>
37 #include <linux/phy/phy.h>
38 #include <linux/platform_device.h>
39 #include <linux/reset.h>
40 #include <linux/types.h>
41
42 #define RCANFD_DRV_NAME "rcar_canfd"
43
44 /* Global register bits */
45
46 /* RSCFDnCFDGRMCFG */
47 #define RCANFD_GRMCFG_RCMC BIT(0)
48
49 /* RSCFDnCFDGCFG / RSCFDnGCFG */
50 #define RCANFD_GCFG_EEFE BIT(6)
51 #define RCANFD_GCFG_CMPOC BIT(5) /* CAN FD only */
52 #define RCANFD_GCFG_DCS BIT(4)
53 #define RCANFD_GCFG_DCE BIT(1)
54 #define RCANFD_GCFG_TPRI BIT(0)
55
56 /* RSCFDnCFDGCTR / RSCFDnGCTR */
57 #define RCANFD_GCTR_TSRST BIT(16)
58 #define RCANFD_GCTR_CFMPOFIE BIT(11) /* CAN FD only */
59 #define RCANFD_GCTR_THLEIE BIT(10)
60 #define RCANFD_GCTR_MEIE BIT(9)
61 #define RCANFD_GCTR_DEIE BIT(8)
62 #define RCANFD_GCTR_GSLPR BIT(2)
63 #define RCANFD_GCTR_GMDC_MASK (0x3)
64 #define RCANFD_GCTR_GMDC_GOPM (0x0)
65 #define RCANFD_GCTR_GMDC_GRESET (0x1)
66 #define RCANFD_GCTR_GMDC_GTEST (0x2)
67
68 /* RSCFDnCFDGSTS / RSCFDnGSTS */
69 #define RCANFD_GSTS_GRAMINIT BIT(3)
70 #define RCANFD_GSTS_GSLPSTS BIT(2)
71 #define RCANFD_GSTS_GHLTSTS BIT(1)
72 #define RCANFD_GSTS_GRSTSTS BIT(0)
73 /* Non-operational status */
74 #define RCANFD_GSTS_GNOPM (BIT(0) | BIT(1) | BIT(2) | BIT(3))
75
76 /* RSCFDnCFDGERFL / RSCFDnGERFL */
77 #define RCANFD_GERFL_EEF0_7 GENMASK(23, 16)
78 #define RCANFD_GERFL_EEF(ch) BIT(16 + (ch))
79 #define RCANFD_GERFL_CMPOF BIT(3) /* CAN FD only */
80 #define RCANFD_GERFL_THLES BIT(2)
81 #define RCANFD_GERFL_MES BIT(1)
82 #define RCANFD_GERFL_DEF BIT(0)
83
84 #define RCANFD_GERFL_ERR(gpriv, x) \
85 ((x) & (reg_gen4(gpriv, RCANFD_GERFL_EEF0_7, \
86 RCANFD_GERFL_EEF(0) | RCANFD_GERFL_EEF(1)) | \
87 RCANFD_GERFL_MES | \
88 ((gpriv)->fdmode ? RCANFD_GERFL_CMPOF : 0)))
89
90 /* AFL Rx rules registers */
91
92 /* RSCFDnCFDGAFLCFG0 / RSCFDnGAFLCFG0 */
93 #define RCANFD_GAFLCFG_SETRNC(gpriv, n, x) \
94 (((x) & reg_gen4(gpriv, 0x1ff, 0xff)) << \
95 (reg_gen4(gpriv, 16, 24) - ((n) & 1) * reg_gen4(gpriv, 16, 8)))
96
97 #define RCANFD_GAFLCFG_GETRNC(gpriv, n, x) \
98 (((x) >> (reg_gen4(gpriv, 16, 24) - ((n) & 1) * reg_gen4(gpriv, 16, 8))) & \
99 reg_gen4(gpriv, 0x1ff, 0xff))
100
101 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
102 #define RCANFD_GAFLECTR_AFLDAE BIT(8)
103 #define RCANFD_GAFLECTR_AFLPN(gpriv, x) ((x) & reg_gen4(gpriv, 0x7f, 0x1f))
104
105 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
106 #define RCANFD_GAFLID_GAFLLB BIT(29)
107
108 /* RSCFDnCFDGAFLP1_j / RSCFDnGAFLP1_j */
109 #define RCANFD_GAFLP1_GAFLFDP(x) (1 << (x))
110
111 /* Channel register bits */
112
113 /* RSCFDnCmCFG - Classical CAN only */
114 #define RCANFD_CFG_SJW(x) (((x) & 0x3) << 24)
115 #define RCANFD_CFG_TSEG2(x) (((x) & 0x7) << 20)
116 #define RCANFD_CFG_TSEG1(x) (((x) & 0xf) << 16)
117 #define RCANFD_CFG_BRP(x) (((x) & 0x3ff) << 0)
118
119 /* RSCFDnCFDCmNCFG - CAN FD only */
120 #define RCANFD_NCFG_NTSEG2(gpriv, x) \
121 (((x) & reg_gen4(gpriv, 0x7f, 0x1f)) << reg_gen4(gpriv, 25, 24))
122
123 #define RCANFD_NCFG_NTSEG1(gpriv, x) \
124 (((x) & reg_gen4(gpriv, 0xff, 0x7f)) << reg_gen4(gpriv, 17, 16))
125
126 #define RCANFD_NCFG_NSJW(gpriv, x) \
127 (((x) & reg_gen4(gpriv, 0x7f, 0x1f)) << reg_gen4(gpriv, 10, 11))
128
129 #define RCANFD_NCFG_NBRP(x) (((x) & 0x3ff) << 0)
130
131 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
132 #define RCANFD_CCTR_CTME BIT(24)
133 #define RCANFD_CCTR_ERRD BIT(23)
134 #define RCANFD_CCTR_BOM_MASK (0x3 << 21)
135 #define RCANFD_CCTR_BOM_ISO (0x0 << 21)
136 #define RCANFD_CCTR_BOM_BENTRY (0x1 << 21)
137 #define RCANFD_CCTR_BOM_BEND (0x2 << 21)
138 #define RCANFD_CCTR_TDCVFIE BIT(19)
139 #define RCANFD_CCTR_SOCOIE BIT(18)
140 #define RCANFD_CCTR_EOCOIE BIT(17)
141 #define RCANFD_CCTR_TAIE BIT(16)
142 #define RCANFD_CCTR_ALIE BIT(15)
143 #define RCANFD_CCTR_BLIE BIT(14)
144 #define RCANFD_CCTR_OLIE BIT(13)
145 #define RCANFD_CCTR_BORIE BIT(12)
146 #define RCANFD_CCTR_BOEIE BIT(11)
147 #define RCANFD_CCTR_EPIE BIT(10)
148 #define RCANFD_CCTR_EWIE BIT(9)
149 #define RCANFD_CCTR_BEIE BIT(8)
150 #define RCANFD_CCTR_CSLPR BIT(2)
151 #define RCANFD_CCTR_CHMDC_MASK (0x3)
152 #define RCANFD_CCTR_CHDMC_COPM (0x0)
153 #define RCANFD_CCTR_CHDMC_CRESET (0x1)
154 #define RCANFD_CCTR_CHDMC_CHLT (0x2)
155
156 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
157 #define RCANFD_CSTS_COMSTS BIT(7)
158 #define RCANFD_CSTS_RECSTS BIT(6)
159 #define RCANFD_CSTS_TRMSTS BIT(5)
160 #define RCANFD_CSTS_BOSTS BIT(4)
161 #define RCANFD_CSTS_EPSTS BIT(3)
162 #define RCANFD_CSTS_SLPSTS BIT(2)
163 #define RCANFD_CSTS_HLTSTS BIT(1)
164 #define RCANFD_CSTS_CRSTSTS BIT(0)
165
166 #define RCANFD_CSTS_TECCNT(x) (((x) >> 24) & 0xff)
167 #define RCANFD_CSTS_RECCNT(x) (((x) >> 16) & 0xff)
168
169 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
170 #define RCANFD_CERFL_ADERR BIT(14)
171 #define RCANFD_CERFL_B0ERR BIT(13)
172 #define RCANFD_CERFL_B1ERR BIT(12)
173 #define RCANFD_CERFL_CERR BIT(11)
174 #define RCANFD_CERFL_AERR BIT(10)
175 #define RCANFD_CERFL_FERR BIT(9)
176 #define RCANFD_CERFL_SERR BIT(8)
177 #define RCANFD_CERFL_ALF BIT(7)
178 #define RCANFD_CERFL_BLF BIT(6)
179 #define RCANFD_CERFL_OVLF BIT(5)
180 #define RCANFD_CERFL_BORF BIT(4)
181 #define RCANFD_CERFL_BOEF BIT(3)
182 #define RCANFD_CERFL_EPF BIT(2)
183 #define RCANFD_CERFL_EWF BIT(1)
184 #define RCANFD_CERFL_BEF BIT(0)
185
186 #define RCANFD_CERFL_ERR(x) ((x) & (0x7fff)) /* above bits 14:0 */
187
188 /* RSCFDnCFDCmDCFG */
189 #define RCANFD_DCFG_DSJW(gpriv, x) (((x) & reg_gen4(gpriv, 0xf, 0x7)) << 24)
190
191 #define RCANFD_DCFG_DTSEG2(gpriv, x) \
192 (((x) & reg_gen4(gpriv, 0x0f, 0x7)) << reg_gen4(gpriv, 16, 20))
193
194 #define RCANFD_DCFG_DTSEG1(gpriv, x) \
195 (((x) & reg_gen4(gpriv, 0x1f, 0xf)) << reg_gen4(gpriv, 8, 16))
196
197 #define RCANFD_DCFG_DBRP(x) (((x) & 0xff) << 0)
198
199 /* RSCFDnCFDCmFDCFG */
200 #define RCANFD_GEN4_FDCFG_CLOE BIT(30)
201 #define RCANFD_GEN4_FDCFG_FDOE BIT(28)
202 #define RCANFD_FDCFG_TDCE BIT(9)
203 #define RCANFD_FDCFG_TDCOC BIT(8)
204 #define RCANFD_FDCFG_TDCO(x) (((x) & 0x7f) >> 16)
205
206 /* RSCFDnCFDRFCCx */
207 #define RCANFD_RFCC_RFIM BIT(12)
208 #define RCANFD_RFCC_RFDC(x) (((x) & 0x7) << 8)
209 #define RCANFD_RFCC_RFPLS(x) (((x) & 0x7) << 4)
210 #define RCANFD_RFCC_RFIE BIT(1)
211 #define RCANFD_RFCC_RFE BIT(0)
212
213 /* RSCFDnCFDRFSTSx */
214 #define RCANFD_RFSTS_RFIF BIT(3)
215 #define RCANFD_RFSTS_RFMLT BIT(2)
216 #define RCANFD_RFSTS_RFFLL BIT(1)
217 #define RCANFD_RFSTS_RFEMP BIT(0)
218
219 /* RSCFDnCFDRFIDx */
220 #define RCANFD_RFID_RFIDE BIT(31)
221 #define RCANFD_RFID_RFRTR BIT(30)
222
223 /* RSCFDnCFDRFPTRx */
224 #define RCANFD_RFPTR_RFDLC(x) (((x) >> 28) & 0xf)
225 #define RCANFD_RFPTR_RFPTR(x) (((x) >> 16) & 0xfff)
226 #define RCANFD_RFPTR_RFTS(x) (((x) >> 0) & 0xffff)
227
228 /* RSCFDnCFDRFFDSTSx */
229 #define RCANFD_RFFDSTS_RFFDF BIT(2)
230 #define RCANFD_RFFDSTS_RFBRS BIT(1)
231 #define RCANFD_RFFDSTS_RFESI BIT(0)
232
233 /* Common FIFO bits */
234
235 /* RSCFDnCFDCFCCk */
236 #define RCANFD_CFCC_CFTML(gpriv, x) \
237 (((x) & reg_gen4(gpriv, 0x1f, 0xf)) << reg_gen4(gpriv, 16, 20))
238 #define RCANFD_CFCC_CFM(gpriv, x) (((x) & 0x3) << reg_gen4(gpriv, 8, 16))
239 #define RCANFD_CFCC_CFIM BIT(12)
240 #define RCANFD_CFCC_CFDC(gpriv, x) (((x) & 0x7) << reg_gen4(gpriv, 21, 8))
241 #define RCANFD_CFCC_CFPLS(x) (((x) & 0x7) << 4)
242 #define RCANFD_CFCC_CFTXIE BIT(2)
243 #define RCANFD_CFCC_CFE BIT(0)
244
245 /* RSCFDnCFDCFSTSk */
246 #define RCANFD_CFSTS_CFMC(x) (((x) >> 8) & 0xff)
247 #define RCANFD_CFSTS_CFTXIF BIT(4)
248 #define RCANFD_CFSTS_CFMLT BIT(2)
249 #define RCANFD_CFSTS_CFFLL BIT(1)
250 #define RCANFD_CFSTS_CFEMP BIT(0)
251
252 /* RSCFDnCFDCFIDk */
253 #define RCANFD_CFID_CFIDE BIT(31)
254 #define RCANFD_CFID_CFRTR BIT(30)
255 #define RCANFD_CFID_CFID_MASK(x) ((x) & 0x1fffffff)
256
257 /* RSCFDnCFDCFPTRk */
258 #define RCANFD_CFPTR_CFDLC(x) (((x) & 0xf) << 28)
259 #define RCANFD_CFPTR_CFPTR(x) (((x) & 0xfff) << 16)
260 #define RCANFD_CFPTR_CFTS(x) (((x) & 0xff) << 0)
261
262 /* RSCFDnCFDCFFDCSTSk */
263 #define RCANFD_CFFDCSTS_CFFDF BIT(2)
264 #define RCANFD_CFFDCSTS_CFBRS BIT(1)
265 #define RCANFD_CFFDCSTS_CFESI BIT(0)
266
267 /* This controller supports either Classical CAN only mode or CAN FD only mode.
268 * These modes are supported in two separate set of register maps & names.
269 * However, some of the register offsets are common for both modes. Those
270 * offsets are listed below as Common registers.
271 *
272 * The CAN FD only mode specific registers & Classical CAN only mode specific
273 * registers are listed separately. Their register names starts with
274 * RCANFD_F_xxx & RCANFD_C_xxx respectively.
275 */
276
277 /* Common registers */
278
279 /* RSCFDnCFDCmNCFG / RSCFDnCmCFG */
280 #define RCANFD_CCFG(m) (0x0000 + (0x10 * (m)))
281 /* RSCFDnCFDCmCTR / RSCFDnCmCTR */
282 #define RCANFD_CCTR(m) (0x0004 + (0x10 * (m)))
283 /* RSCFDnCFDCmSTS / RSCFDnCmSTS */
284 #define RCANFD_CSTS(m) (0x0008 + (0x10 * (m)))
285 /* RSCFDnCFDCmERFL / RSCFDnCmERFL */
286 #define RCANFD_CERFL(m) (0x000C + (0x10 * (m)))
287
288 /* RSCFDnCFDGCFG / RSCFDnGCFG */
289 #define RCANFD_GCFG (0x0084)
290 /* RSCFDnCFDGCTR / RSCFDnGCTR */
291 #define RCANFD_GCTR (0x0088)
292 /* RSCFDnCFDGCTS / RSCFDnGCTS */
293 #define RCANFD_GSTS (0x008c)
294 /* RSCFDnCFDGERFL / RSCFDnGERFL */
295 #define RCANFD_GERFL (0x0090)
296 /* RSCFDnCFDGTSC / RSCFDnGTSC */
297 #define RCANFD_GTSC (0x0094)
298 /* RSCFDnCFDGAFLECTR / RSCFDnGAFLECTR */
299 #define RCANFD_GAFLECTR (0x0098)
300 /* RSCFDnCFDGAFLCFG / RSCFDnGAFLCFG */
301 #define RCANFD_GAFLCFG(ch) (0x009c + (0x04 * ((ch) / 2)))
302 /* RSCFDnCFDRMNB / RSCFDnRMNB */
303 #define RCANFD_RMNB (0x00a4)
304 /* RSCFDnCFDRMND / RSCFDnRMND */
305 #define RCANFD_RMND(y) (0x00a8 + (0x04 * (y)))
306
307 /* RSCFDnCFDRFCCx / RSCFDnRFCCx */
308 #define RCANFD_RFCC(gpriv, x) (reg_gen4(gpriv, 0x00c0, 0x00b8) + (0x04 * (x)))
309 /* RSCFDnCFDRFSTSx / RSCFDnRFSTSx */
310 #define RCANFD_RFSTS(gpriv, x) (RCANFD_RFCC(gpriv, x) + 0x20)
311 /* RSCFDnCFDRFPCTRx / RSCFDnRFPCTRx */
312 #define RCANFD_RFPCTR(gpriv, x) (RCANFD_RFCC(gpriv, x) + 0x40)
313
314 /* Common FIFO Control registers */
315
316 /* RSCFDnCFDCFCCx / RSCFDnCFCCx */
317 #define RCANFD_CFCC(gpriv, ch, idx) \
318 (reg_gen4(gpriv, 0x0120, 0x0118) + (0x0c * (ch)) + (0x04 * (idx)))
319 /* RSCFDnCFDCFSTSx / RSCFDnCFSTSx */
320 #define RCANFD_CFSTS(gpriv, ch, idx) \
321 (reg_gen4(gpriv, 0x01e0, 0x0178) + (0x0c * (ch)) + (0x04 * (idx)))
322 /* RSCFDnCFDCFPCTRx / RSCFDnCFPCTRx */
323 #define RCANFD_CFPCTR(gpriv, ch, idx) \
324 (reg_gen4(gpriv, 0x0240, 0x01d8) + (0x0c * (ch)) + (0x04 * (idx)))
325
326 /* RSCFDnCFDFESTS / RSCFDnFESTS */
327 #define RCANFD_FESTS (0x0238)
328 /* RSCFDnCFDFFSTS / RSCFDnFFSTS */
329 #define RCANFD_FFSTS (0x023c)
330 /* RSCFDnCFDFMSTS / RSCFDnFMSTS */
331 #define RCANFD_FMSTS (0x0240)
332 /* RSCFDnCFDRFISTS / RSCFDnRFISTS */
333 #define RCANFD_RFISTS (0x0244)
334 /* RSCFDnCFDCFRISTS / RSCFDnCFRISTS */
335 #define RCANFD_CFRISTS (0x0248)
336 /* RSCFDnCFDCFTISTS / RSCFDnCFTISTS */
337 #define RCANFD_CFTISTS (0x024c)
338
339 /* RSCFDnCFDTMCp / RSCFDnTMCp */
340 #define RCANFD_TMC(p) (0x0250 + (0x01 * (p)))
341 /* RSCFDnCFDTMSTSp / RSCFDnTMSTSp */
342 #define RCANFD_TMSTS(p) (0x02d0 + (0x01 * (p)))
343
344 /* RSCFDnCFDTMTRSTSp / RSCFDnTMTRSTSp */
345 #define RCANFD_TMTRSTS(y) (0x0350 + (0x04 * (y)))
346 /* RSCFDnCFDTMTARSTSp / RSCFDnTMTARSTSp */
347 #define RCANFD_TMTARSTS(y) (0x0360 + (0x04 * (y)))
348 /* RSCFDnCFDTMTCSTSp / RSCFDnTMTCSTSp */
349 #define RCANFD_TMTCSTS(y) (0x0370 + (0x04 * (y)))
350 /* RSCFDnCFDTMTASTSp / RSCFDnTMTASTSp */
351 #define RCANFD_TMTASTS(y) (0x0380 + (0x04 * (y)))
352 /* RSCFDnCFDTMIECy / RSCFDnTMIECy */
353 #define RCANFD_TMIEC(y) (0x0390 + (0x04 * (y)))
354
355 /* RSCFDnCFDTXQCCm / RSCFDnTXQCCm */
356 #define RCANFD_TXQCC(m) (0x03a0 + (0x04 * (m)))
357 /* RSCFDnCFDTXQSTSm / RSCFDnTXQSTSm */
358 #define RCANFD_TXQSTS(m) (0x03c0 + (0x04 * (m)))
359 /* RSCFDnCFDTXQPCTRm / RSCFDnTXQPCTRm */
360 #define RCANFD_TXQPCTR(m) (0x03e0 + (0x04 * (m)))
361
362 /* RSCFDnCFDTHLCCm / RSCFDnTHLCCm */
363 #define RCANFD_THLCC(m) (0x0400 + (0x04 * (m)))
364 /* RSCFDnCFDTHLSTSm / RSCFDnTHLSTSm */
365 #define RCANFD_THLSTS(m) (0x0420 + (0x04 * (m)))
366 /* RSCFDnCFDTHLPCTRm / RSCFDnTHLPCTRm */
367 #define RCANFD_THLPCTR(m) (0x0440 + (0x04 * (m)))
368
369 /* RSCFDnCFDGTINTSTS0 / RSCFDnGTINTSTS0 */
370 #define RCANFD_GTINTSTS0 (0x0460)
371 /* RSCFDnCFDGTINTSTS1 / RSCFDnGTINTSTS1 */
372 #define RCANFD_GTINTSTS1 (0x0464)
373 /* RSCFDnCFDGTSTCFG / RSCFDnGTSTCFG */
374 #define RCANFD_GTSTCFG (0x0468)
375 /* RSCFDnCFDGTSTCTR / RSCFDnGTSTCTR */
376 #define RCANFD_GTSTCTR (0x046c)
377 /* RSCFDnCFDGLOCKK / RSCFDnGLOCKK */
378 #define RCANFD_GLOCKK (0x047c)
379 /* RSCFDnCFDGRMCFG */
380 #define RCANFD_GRMCFG (0x04fc)
381
382 /* RSCFDnCFDGAFLIDj / RSCFDnGAFLIDj */
383 #define RCANFD_GAFLID(offset, j) ((offset) + (0x10 * (j)))
384 /* RSCFDnCFDGAFLMj / RSCFDnGAFLMj */
385 #define RCANFD_GAFLM(offset, j) ((offset) + 0x04 + (0x10 * (j)))
386 /* RSCFDnCFDGAFLP0j / RSCFDnGAFLP0j */
387 #define RCANFD_GAFLP0(offset, j) ((offset) + 0x08 + (0x10 * (j)))
388 /* RSCFDnCFDGAFLP1j / RSCFDnGAFLP1j */
389 #define RCANFD_GAFLP1(offset, j) ((offset) + 0x0c + (0x10 * (j)))
390
391 /* Classical CAN only mode register map */
392
393 /* RSCFDnGAFLXXXj offset */
394 #define RCANFD_C_GAFL_OFFSET (0x0500)
395
396 /* RSCFDnRMXXXq -> RCANFD_C_RMXXX(q) */
397 #define RCANFD_C_RMID(q) (0x0600 + (0x10 * (q)))
398 #define RCANFD_C_RMPTR(q) (0x0604 + (0x10 * (q)))
399 #define RCANFD_C_RMDF0(q) (0x0608 + (0x10 * (q)))
400 #define RCANFD_C_RMDF1(q) (0x060c + (0x10 * (q)))
401
402 /* RSCFDnRFXXx -> RCANFD_C_RFXX(x) */
403 #define RCANFD_C_RFOFFSET (0x0e00)
404 #define RCANFD_C_RFID(x) (RCANFD_C_RFOFFSET + (0x10 * (x)))
405 #define RCANFD_C_RFPTR(x) (RCANFD_C_RFOFFSET + 0x04 + (0x10 * (x)))
406 #define RCANFD_C_RFDF(x, df) \
407 (RCANFD_C_RFOFFSET + 0x08 + (0x10 * (x)) + (0x04 * (df)))
408
409 /* RSCFDnCFXXk -> RCANFD_C_CFXX(ch, k) */
410 #define RCANFD_C_CFOFFSET (0x0e80)
411
412 #define RCANFD_C_CFID(ch, idx) \
413 (RCANFD_C_CFOFFSET + (0x30 * (ch)) + (0x10 * (idx)))
414
415 #define RCANFD_C_CFPTR(ch, idx) \
416 (RCANFD_C_CFOFFSET + 0x04 + (0x30 * (ch)) + (0x10 * (idx)))
417
418 #define RCANFD_C_CFDF(ch, idx, df) \
419 (RCANFD_C_CFOFFSET + 0x08 + (0x30 * (ch)) + (0x10 * (idx)) + (0x04 * (df)))
420
421 /* RSCFDnTMXXp -> RCANFD_C_TMXX(p) */
422 #define RCANFD_C_TMID(p) (0x1000 + (0x10 * (p)))
423 #define RCANFD_C_TMPTR(p) (0x1004 + (0x10 * (p)))
424 #define RCANFD_C_TMDF0(p) (0x1008 + (0x10 * (p)))
425 #define RCANFD_C_TMDF1(p) (0x100c + (0x10 * (p)))
426
427 /* RSCFDnTHLACCm */
428 #define RCANFD_C_THLACC(m) (0x1800 + (0x04 * (m)))
429 /* RSCFDnRPGACCr */
430 #define RCANFD_C_RPGACC(r) (0x1900 + (0x04 * (r)))
431
432 /* R-Car Gen4 Classical and CAN FD mode specific register map */
433 #define RCANFD_GEN4_FDCFG(m) (0x1404 + (0x20 * (m)))
434
435 #define RCANFD_GEN4_GAFL_OFFSET (0x1800)
436
437 /* CAN FD mode specific register map */
438
439 /* RSCFDnCFDCmXXX -> RCANFD_F_XXX(m) */
440 #define RCANFD_F_DCFG(gpriv, m) (reg_gen4(gpriv, 0x1400, 0x0500) + (0x20 * (m)))
441 #define RCANFD_F_CFDCFG(m) (0x0504 + (0x20 * (m)))
442 #define RCANFD_F_CFDCTR(m) (0x0508 + (0x20 * (m)))
443 #define RCANFD_F_CFDSTS(m) (0x050c + (0x20 * (m)))
444 #define RCANFD_F_CFDCRC(m) (0x0510 + (0x20 * (m)))
445
446 /* RSCFDnCFDGAFLXXXj offset */
447 #define RCANFD_F_GAFL_OFFSET (0x1000)
448
449 /* RSCFDnCFDRMXXXq -> RCANFD_F_RMXXX(q) */
450 #define RCANFD_F_RMID(q) (0x2000 + (0x20 * (q)))
451 #define RCANFD_F_RMPTR(q) (0x2004 + (0x20 * (q)))
452 #define RCANFD_F_RMFDSTS(q) (0x2008 + (0x20 * (q)))
453 #define RCANFD_F_RMDF(q, b) (0x200c + (0x04 * (b)) + (0x20 * (q)))
454
455 /* RSCFDnCFDRFXXx -> RCANFD_F_RFXX(x) */
456 #define RCANFD_F_RFOFFSET(gpriv) reg_gen4(gpriv, 0x6000, 0x3000)
457 #define RCANFD_F_RFID(gpriv, x) (RCANFD_F_RFOFFSET(gpriv) + (0x80 * (x)))
458 #define RCANFD_F_RFPTR(gpriv, x) (RCANFD_F_RFOFFSET(gpriv) + 0x04 + (0x80 * (x)))
459 #define RCANFD_F_RFFDSTS(gpriv, x) (RCANFD_F_RFOFFSET(gpriv) + 0x08 + (0x80 * (x)))
460 #define RCANFD_F_RFDF(gpriv, x, df) \
461 (RCANFD_F_RFOFFSET(gpriv) + 0x0c + (0x80 * (x)) + (0x04 * (df)))
462
463 /* RSCFDnCFDCFXXk -> RCANFD_F_CFXX(ch, k) */
464 #define RCANFD_F_CFOFFSET(gpriv) reg_gen4(gpriv, 0x6400, 0x3400)
465
466 #define RCANFD_F_CFID(gpriv, ch, idx) \
467 (RCANFD_F_CFOFFSET(gpriv) + (0x180 * (ch)) + (0x80 * (idx)))
468
469 #define RCANFD_F_CFPTR(gpriv, ch, idx) \
470 (RCANFD_F_CFOFFSET(gpriv) + 0x04 + (0x180 * (ch)) + (0x80 * (idx)))
471
472 #define RCANFD_F_CFFDCSTS(gpriv, ch, idx) \
473 (RCANFD_F_CFOFFSET(gpriv) + 0x08 + (0x180 * (ch)) + (0x80 * (idx)))
474
475 #define RCANFD_F_CFDF(gpriv, ch, idx, df) \
476 (RCANFD_F_CFOFFSET(gpriv) + 0x0c + (0x180 * (ch)) + (0x80 * (idx)) + \
477 (0x04 * (df)))
478
479 /* RSCFDnCFDTMXXp -> RCANFD_F_TMXX(p) */
480 #define RCANFD_F_TMID(p) (0x4000 + (0x20 * (p)))
481 #define RCANFD_F_TMPTR(p) (0x4004 + (0x20 * (p)))
482 #define RCANFD_F_TMFDCTR(p) (0x4008 + (0x20 * (p)))
483 #define RCANFD_F_TMDF(p, b) (0x400c + (0x20 * (p)) + (0x04 * (b)))
484
485 /* RSCFDnCFDTHLACCm */
486 #define RCANFD_F_THLACC(m) (0x6000 + (0x04 * (m)))
487 /* RSCFDnCFDRPGACCr */
488 #define RCANFD_F_RPGACC(r) (0x6400 + (0x04 * (r)))
489
490 /* Constants */
491 #define RCANFD_FIFO_DEPTH 8 /* Tx FIFO depth */
492 #define RCANFD_NAPI_WEIGHT 8 /* Rx poll quota */
493
494 #define RCANFD_NUM_CHANNELS 8 /* Eight channels max */
495 #define RCANFD_CHANNELS_MASK BIT((RCANFD_NUM_CHANNELS) - 1)
496
497 #define RCANFD_GAFL_PAGENUM(entry) ((entry) / 16)
498 #define RCANFD_CHANNEL_NUMRULES 1 /* only one rule per channel */
499
500 /* Rx FIFO is a global resource of the controller. There are 8 such FIFOs
501 * available. Each channel gets a dedicated Rx FIFO (i.e.) the channel
502 * number is added to RFFIFO index.
503 */
504 #define RCANFD_RFFIFO_IDX 0
505
506 /* Tx/Rx or Common FIFO is a per channel resource. Each channel has 3 Common
507 * FIFOs dedicated to them. Use the first (index 0) FIFO out of the 3 for Tx.
508 */
509 #define RCANFD_CFFIFO_IDX 0
510
511 /* fCAN clock select register settings */
512 enum rcar_canfd_fcanclk {
513 RCANFD_CANFDCLK = 0, /* CANFD clock */
514 RCANFD_EXTCLK, /* Externally input clock */
515 };
516
517 struct rcar_canfd_global;
518
519 struct rcar_canfd_hw_info {
520 u8 max_channels;
521 u8 postdiv;
522 /* hardware features */
523 unsigned shared_global_irqs:1; /* Has shared global irqs */
524 unsigned multi_channel_irqs:1; /* Has multiple channel irqs */
525 };
526
527 /* Channel priv data */
528 struct rcar_canfd_channel {
529 struct can_priv can; /* Must be the first member */
530 struct net_device *ndev;
531 struct rcar_canfd_global *gpriv; /* Controller reference */
532 void __iomem *base; /* Register base address */
533 struct phy *transceiver; /* Optional transceiver */
534 struct napi_struct napi;
535 u32 tx_head; /* Incremented on xmit */
536 u32 tx_tail; /* Incremented on xmit done */
537 u32 channel; /* Channel number */
538 spinlock_t tx_lock; /* To protect tx path */
539 };
540
541 /* Global priv data */
542 struct rcar_canfd_global {
543 struct rcar_canfd_channel *ch[RCANFD_NUM_CHANNELS];
544 void __iomem *base; /* Register base address */
545 struct platform_device *pdev; /* Respective platform device */
546 struct clk *clkp; /* Peripheral clock */
547 struct clk *can_clk; /* fCAN clock */
548 enum rcar_canfd_fcanclk fcan; /* CANFD or Ext clock */
549 unsigned long channels_mask; /* Enabled channels mask */
550 bool fdmode; /* CAN FD or Classical CAN only mode */
551 struct reset_control *rstc1;
552 struct reset_control *rstc2;
553 const struct rcar_canfd_hw_info *info;
554 };
555
556 /* CAN FD mode nominal rate constants */
557 static const struct can_bittiming_const rcar_canfd_nom_bittiming_const = {
558 .name = RCANFD_DRV_NAME,
559 .tseg1_min = 2,
560 .tseg1_max = 128,
561 .tseg2_min = 2,
562 .tseg2_max = 32,
563 .sjw_max = 32,
564 .brp_min = 1,
565 .brp_max = 1024,
566 .brp_inc = 1,
567 };
568
569 /* CAN FD mode data rate constants */
570 static const struct can_bittiming_const rcar_canfd_data_bittiming_const = {
571 .name = RCANFD_DRV_NAME,
572 .tseg1_min = 2,
573 .tseg1_max = 16,
574 .tseg2_min = 2,
575 .tseg2_max = 8,
576 .sjw_max = 8,
577 .brp_min = 1,
578 .brp_max = 256,
579 .brp_inc = 1,
580 };
581
582 /* Classical CAN mode bitrate constants */
583 static const struct can_bittiming_const rcar_canfd_bittiming_const = {
584 .name = RCANFD_DRV_NAME,
585 .tseg1_min = 4,
586 .tseg1_max = 16,
587 .tseg2_min = 2,
588 .tseg2_max = 8,
589 .sjw_max = 4,
590 .brp_min = 1,
591 .brp_max = 1024,
592 .brp_inc = 1,
593 };
594
595 static const struct rcar_canfd_hw_info rcar_gen3_hw_info = {
596 .max_channels = 2,
597 .postdiv = 2,
598 .shared_global_irqs = 1,
599 };
600
601 static const struct rcar_canfd_hw_info rcar_gen4_hw_info = {
602 .max_channels = 8,
603 .postdiv = 2,
604 .shared_global_irqs = 1,
605 };
606
607 static const struct rcar_canfd_hw_info rzg2l_hw_info = {
608 .max_channels = 2,
609 .postdiv = 1,
610 .multi_channel_irqs = 1,
611 };
612
613 /* Helper functions */
is_gen4(struct rcar_canfd_global * gpriv)614 static inline bool is_gen4(struct rcar_canfd_global *gpriv)
615 {
616 return gpriv->info == &rcar_gen4_hw_info;
617 }
618
reg_gen4(struct rcar_canfd_global * gpriv,u32 gen4,u32 not_gen4)619 static inline u32 reg_gen4(struct rcar_canfd_global *gpriv,
620 u32 gen4, u32 not_gen4)
621 {
622 return is_gen4(gpriv) ? gen4 : not_gen4;
623 }
624
rcar_canfd_update(u32 mask,u32 val,u32 __iomem * reg)625 static inline void rcar_canfd_update(u32 mask, u32 val, u32 __iomem *reg)
626 {
627 u32 data = readl(reg);
628
629 data &= ~mask;
630 data |= (val & mask);
631 writel(data, reg);
632 }
633
rcar_canfd_read(void __iomem * base,u32 offset)634 static inline u32 rcar_canfd_read(void __iomem *base, u32 offset)
635 {
636 return readl(base + (offset));
637 }
638
rcar_canfd_write(void __iomem * base,u32 offset,u32 val)639 static inline void rcar_canfd_write(void __iomem *base, u32 offset, u32 val)
640 {
641 writel(val, base + (offset));
642 }
643
rcar_canfd_set_bit(void __iomem * base,u32 reg,u32 val)644 static void rcar_canfd_set_bit(void __iomem *base, u32 reg, u32 val)
645 {
646 rcar_canfd_update(val, val, base + (reg));
647 }
648
rcar_canfd_clear_bit(void __iomem * base,u32 reg,u32 val)649 static void rcar_canfd_clear_bit(void __iomem *base, u32 reg, u32 val)
650 {
651 rcar_canfd_update(val, 0, base + (reg));
652 }
653
rcar_canfd_update_bit(void __iomem * base,u32 reg,u32 mask,u32 val)654 static void rcar_canfd_update_bit(void __iomem *base, u32 reg,
655 u32 mask, u32 val)
656 {
657 rcar_canfd_update(mask, val, base + (reg));
658 }
659
rcar_canfd_get_data(struct rcar_canfd_channel * priv,struct canfd_frame * cf,u32 off)660 static void rcar_canfd_get_data(struct rcar_canfd_channel *priv,
661 struct canfd_frame *cf, u32 off)
662 {
663 u32 i, lwords;
664
665 lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
666 for (i = 0; i < lwords; i++)
667 *((u32 *)cf->data + i) =
668 rcar_canfd_read(priv->base, off + (i * sizeof(u32)));
669 }
670
rcar_canfd_put_data(struct rcar_canfd_channel * priv,struct canfd_frame * cf,u32 off)671 static void rcar_canfd_put_data(struct rcar_canfd_channel *priv,
672 struct canfd_frame *cf, u32 off)
673 {
674 u32 i, lwords;
675
676 lwords = DIV_ROUND_UP(cf->len, sizeof(u32));
677 for (i = 0; i < lwords; i++)
678 rcar_canfd_write(priv->base, off + (i * sizeof(u32)),
679 *((u32 *)cf->data + i));
680 }
681
rcar_canfd_tx_failure_cleanup(struct net_device * ndev)682 static void rcar_canfd_tx_failure_cleanup(struct net_device *ndev)
683 {
684 u32 i;
685
686 for (i = 0; i < RCANFD_FIFO_DEPTH; i++)
687 can_free_echo_skb(ndev, i, NULL);
688 }
689
rcar_canfd_set_mode(struct rcar_canfd_global * gpriv)690 static void rcar_canfd_set_mode(struct rcar_canfd_global *gpriv)
691 {
692 if (is_gen4(gpriv)) {
693 u32 ch, val = gpriv->fdmode ? RCANFD_GEN4_FDCFG_FDOE
694 : RCANFD_GEN4_FDCFG_CLOE;
695
696 for_each_set_bit(ch, &gpriv->channels_mask,
697 gpriv->info->max_channels)
698 rcar_canfd_set_bit(gpriv->base, RCANFD_GEN4_FDCFG(ch),
699 val);
700 } else {
701 if (gpriv->fdmode)
702 rcar_canfd_set_bit(gpriv->base, RCANFD_GRMCFG,
703 RCANFD_GRMCFG_RCMC);
704 else
705 rcar_canfd_clear_bit(gpriv->base, RCANFD_GRMCFG,
706 RCANFD_GRMCFG_RCMC);
707 }
708 }
709
rcar_canfd_reset_controller(struct rcar_canfd_global * gpriv)710 static int rcar_canfd_reset_controller(struct rcar_canfd_global *gpriv)
711 {
712 u32 sts, ch;
713 int err;
714
715 /* Check RAMINIT flag as CAN RAM initialization takes place
716 * after the MCU reset
717 */
718 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
719 !(sts & RCANFD_GSTS_GRAMINIT), 2, 500000);
720 if (err) {
721 dev_dbg(&gpriv->pdev->dev, "global raminit failed\n");
722 return err;
723 }
724
725 /* Transition to Global Reset mode */
726 rcar_canfd_clear_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
727 rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR,
728 RCANFD_GCTR_GMDC_MASK, RCANFD_GCTR_GMDC_GRESET);
729
730 /* Ensure Global reset mode */
731 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
732 (sts & RCANFD_GSTS_GRSTSTS), 2, 500000);
733 if (err) {
734 dev_dbg(&gpriv->pdev->dev, "global reset failed\n");
735 return err;
736 }
737
738 /* Reset Global error flags */
739 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0x0);
740
741 /* Set the controller into appropriate mode */
742 rcar_canfd_set_mode(gpriv);
743
744 /* Transition all Channels to reset mode */
745 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
746 rcar_canfd_clear_bit(gpriv->base,
747 RCANFD_CCTR(ch), RCANFD_CCTR_CSLPR);
748
749 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
750 RCANFD_CCTR_CHMDC_MASK,
751 RCANFD_CCTR_CHDMC_CRESET);
752
753 /* Ensure Channel reset mode */
754 err = readl_poll_timeout((gpriv->base + RCANFD_CSTS(ch)), sts,
755 (sts & RCANFD_CSTS_CRSTSTS),
756 2, 500000);
757 if (err) {
758 dev_dbg(&gpriv->pdev->dev,
759 "channel %u reset failed\n", ch);
760 return err;
761 }
762 }
763 return 0;
764 }
765
rcar_canfd_configure_controller(struct rcar_canfd_global * gpriv)766 static void rcar_canfd_configure_controller(struct rcar_canfd_global *gpriv)
767 {
768 u32 cfg, ch;
769
770 /* Global configuration settings */
771
772 /* ECC Error flag Enable */
773 cfg = RCANFD_GCFG_EEFE;
774
775 if (gpriv->fdmode)
776 /* Truncate payload to configured message size RFPLS */
777 cfg |= RCANFD_GCFG_CMPOC;
778
779 /* Set External Clock if selected */
780 if (gpriv->fcan != RCANFD_CANFDCLK)
781 cfg |= RCANFD_GCFG_DCS;
782
783 rcar_canfd_set_bit(gpriv->base, RCANFD_GCFG, cfg);
784
785 /* Channel configuration settings */
786 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
787 rcar_canfd_set_bit(gpriv->base, RCANFD_CCTR(ch),
788 RCANFD_CCTR_ERRD);
789 rcar_canfd_update_bit(gpriv->base, RCANFD_CCTR(ch),
790 RCANFD_CCTR_BOM_MASK,
791 RCANFD_CCTR_BOM_BENTRY);
792 }
793 }
794
rcar_canfd_configure_afl_rules(struct rcar_canfd_global * gpriv,u32 ch,u32 rule_entry)795 static void rcar_canfd_configure_afl_rules(struct rcar_canfd_global *gpriv,
796 u32 ch, u32 rule_entry)
797 {
798 int offset, page, num_rules = RCANFD_CHANNEL_NUMRULES;
799 u32 rule_entry_index = rule_entry % 16;
800 u32 ridx = ch + RCANFD_RFFIFO_IDX;
801
802 /* Enable write access to entry */
803 page = RCANFD_GAFL_PAGENUM(rule_entry);
804 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLECTR,
805 (RCANFD_GAFLECTR_AFLPN(gpriv, page) |
806 RCANFD_GAFLECTR_AFLDAE));
807
808 /* Write number of rules for channel */
809 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLCFG(ch),
810 RCANFD_GAFLCFG_SETRNC(gpriv, ch, num_rules));
811 if (is_gen4(gpriv))
812 offset = RCANFD_GEN4_GAFL_OFFSET;
813 else if (gpriv->fdmode)
814 offset = RCANFD_F_GAFL_OFFSET;
815 else
816 offset = RCANFD_C_GAFL_OFFSET;
817
818 /* Accept all IDs */
819 rcar_canfd_write(gpriv->base, RCANFD_GAFLID(offset, rule_entry_index), 0);
820 /* IDE or RTR is not considered for matching */
821 rcar_canfd_write(gpriv->base, RCANFD_GAFLM(offset, rule_entry_index), 0);
822 /* Any data length accepted */
823 rcar_canfd_write(gpriv->base, RCANFD_GAFLP0(offset, rule_entry_index), 0);
824 /* Place the msg in corresponding Rx FIFO entry */
825 rcar_canfd_set_bit(gpriv->base, RCANFD_GAFLP1(offset, rule_entry_index),
826 RCANFD_GAFLP1_GAFLFDP(ridx));
827
828 /* Disable write access to page */
829 rcar_canfd_clear_bit(gpriv->base,
830 RCANFD_GAFLECTR, RCANFD_GAFLECTR_AFLDAE);
831 }
832
rcar_canfd_configure_rx(struct rcar_canfd_global * gpriv,u32 ch)833 static void rcar_canfd_configure_rx(struct rcar_canfd_global *gpriv, u32 ch)
834 {
835 /* Rx FIFO is used for reception */
836 u32 cfg;
837 u16 rfdc, rfpls;
838
839 /* Select Rx FIFO based on channel */
840 u32 ridx = ch + RCANFD_RFFIFO_IDX;
841
842 rfdc = 2; /* b010 - 8 messages Rx FIFO depth */
843 if (gpriv->fdmode)
844 rfpls = 7; /* b111 - Max 64 bytes payload */
845 else
846 rfpls = 0; /* b000 - Max 8 bytes payload */
847
848 cfg = (RCANFD_RFCC_RFIM | RCANFD_RFCC_RFDC(rfdc) |
849 RCANFD_RFCC_RFPLS(rfpls) | RCANFD_RFCC_RFIE);
850 rcar_canfd_write(gpriv->base, RCANFD_RFCC(gpriv, ridx), cfg);
851 }
852
rcar_canfd_configure_tx(struct rcar_canfd_global * gpriv,u32 ch)853 static void rcar_canfd_configure_tx(struct rcar_canfd_global *gpriv, u32 ch)
854 {
855 /* Tx/Rx(Common) FIFO configured in Tx mode is
856 * used for transmission
857 *
858 * Each channel has 3 Common FIFO dedicated to them.
859 * Use the 1st (index 0) out of 3
860 */
861 u32 cfg;
862 u16 cftml, cfm, cfdc, cfpls;
863
864 cftml = 0; /* 0th buffer */
865 cfm = 1; /* b01 - Transmit mode */
866 cfdc = 2; /* b010 - 8 messages Tx FIFO depth */
867 if (gpriv->fdmode)
868 cfpls = 7; /* b111 - Max 64 bytes payload */
869 else
870 cfpls = 0; /* b000 - Max 8 bytes payload */
871
872 cfg = (RCANFD_CFCC_CFTML(gpriv, cftml) | RCANFD_CFCC_CFM(gpriv, cfm) |
873 RCANFD_CFCC_CFIM | RCANFD_CFCC_CFDC(gpriv, cfdc) |
874 RCANFD_CFCC_CFPLS(cfpls) | RCANFD_CFCC_CFTXIE);
875 rcar_canfd_write(gpriv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX), cfg);
876
877 if (gpriv->fdmode)
878 /* Clear FD mode specific control/status register */
879 rcar_canfd_write(gpriv->base,
880 RCANFD_F_CFFDCSTS(gpriv, ch, RCANFD_CFFIFO_IDX), 0);
881 }
882
rcar_canfd_enable_global_interrupts(struct rcar_canfd_global * gpriv)883 static void rcar_canfd_enable_global_interrupts(struct rcar_canfd_global *gpriv)
884 {
885 u32 ctr;
886
887 /* Clear any stray error interrupt flags */
888 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
889
890 /* Global interrupts setup */
891 ctr = RCANFD_GCTR_MEIE;
892 if (gpriv->fdmode)
893 ctr |= RCANFD_GCTR_CFMPOFIE;
894
895 rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, ctr);
896 }
897
rcar_canfd_disable_global_interrupts(struct rcar_canfd_global * gpriv)898 static void rcar_canfd_disable_global_interrupts(struct rcar_canfd_global
899 *gpriv)
900 {
901 /* Disable all interrupts */
902 rcar_canfd_write(gpriv->base, RCANFD_GCTR, 0);
903
904 /* Clear any stray error interrupt flags */
905 rcar_canfd_write(gpriv->base, RCANFD_GERFL, 0);
906 }
907
rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel * priv)908 static void rcar_canfd_enable_channel_interrupts(struct rcar_canfd_channel
909 *priv)
910 {
911 u32 ctr, ch = priv->channel;
912
913 /* Clear any stray error flags */
914 rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
915
916 /* Channel interrupts setup */
917 ctr = (RCANFD_CCTR_TAIE |
918 RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
919 RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
920 RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
921 RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
922 rcar_canfd_set_bit(priv->base, RCANFD_CCTR(ch), ctr);
923 }
924
rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel * priv)925 static void rcar_canfd_disable_channel_interrupts(struct rcar_canfd_channel
926 *priv)
927 {
928 u32 ctr, ch = priv->channel;
929
930 ctr = (RCANFD_CCTR_TAIE |
931 RCANFD_CCTR_ALIE | RCANFD_CCTR_BLIE |
932 RCANFD_CCTR_OLIE | RCANFD_CCTR_BORIE |
933 RCANFD_CCTR_BOEIE | RCANFD_CCTR_EPIE |
934 RCANFD_CCTR_EWIE | RCANFD_CCTR_BEIE);
935 rcar_canfd_clear_bit(priv->base, RCANFD_CCTR(ch), ctr);
936
937 /* Clear any stray error flags */
938 rcar_canfd_write(priv->base, RCANFD_CERFL(ch), 0);
939 }
940
rcar_canfd_global_error(struct net_device * ndev)941 static void rcar_canfd_global_error(struct net_device *ndev)
942 {
943 struct rcar_canfd_channel *priv = netdev_priv(ndev);
944 struct rcar_canfd_global *gpriv = priv->gpriv;
945 struct net_device_stats *stats = &ndev->stats;
946 u32 ch = priv->channel;
947 u32 gerfl, sts;
948 u32 ridx = ch + RCANFD_RFFIFO_IDX;
949
950 gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
951 if (gerfl & RCANFD_GERFL_EEF(ch)) {
952 netdev_dbg(ndev, "Ch%u: ECC Error flag\n", ch);
953 stats->tx_dropped++;
954 }
955 if (gerfl & RCANFD_GERFL_MES) {
956 sts = rcar_canfd_read(priv->base,
957 RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
958 if (sts & RCANFD_CFSTS_CFMLT) {
959 netdev_dbg(ndev, "Tx Message Lost flag\n");
960 stats->tx_dropped++;
961 rcar_canfd_write(priv->base,
962 RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX),
963 sts & ~RCANFD_CFSTS_CFMLT);
964 }
965
966 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
967 if (sts & RCANFD_RFSTS_RFMLT) {
968 netdev_dbg(ndev, "Rx Message Lost flag\n");
969 stats->rx_dropped++;
970 rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx),
971 sts & ~RCANFD_RFSTS_RFMLT);
972 }
973 }
974 if (gpriv->fdmode && gerfl & RCANFD_GERFL_CMPOF) {
975 /* Message Lost flag will be set for respective channel
976 * when this condition happens with counters and flags
977 * already updated.
978 */
979 netdev_dbg(ndev, "global payload overflow interrupt\n");
980 }
981
982 /* Clear all global error interrupts. Only affected channels bits
983 * get cleared
984 */
985 rcar_canfd_write(priv->base, RCANFD_GERFL, 0);
986 }
987
rcar_canfd_error(struct net_device * ndev,u32 cerfl,u16 txerr,u16 rxerr)988 static void rcar_canfd_error(struct net_device *ndev, u32 cerfl,
989 u16 txerr, u16 rxerr)
990 {
991 struct rcar_canfd_channel *priv = netdev_priv(ndev);
992 struct net_device_stats *stats = &ndev->stats;
993 struct can_frame *cf;
994 struct sk_buff *skb;
995 u32 ch = priv->channel;
996
997 netdev_dbg(ndev, "ch erfl %x txerr %u rxerr %u\n", cerfl, txerr, rxerr);
998
999 /* Propagate the error condition to the CAN stack */
1000 skb = alloc_can_err_skb(ndev, &cf);
1001 if (!skb) {
1002 stats->rx_dropped++;
1003 return;
1004 }
1005
1006 /* Channel error interrupts */
1007 if (cerfl & RCANFD_CERFL_BEF) {
1008 netdev_dbg(ndev, "Bus error\n");
1009 cf->can_id |= CAN_ERR_BUSERROR | CAN_ERR_PROT;
1010 cf->data[2] = CAN_ERR_PROT_UNSPEC;
1011 priv->can.can_stats.bus_error++;
1012 }
1013 if (cerfl & RCANFD_CERFL_ADERR) {
1014 netdev_dbg(ndev, "ACK Delimiter Error\n");
1015 stats->tx_errors++;
1016 cf->data[3] |= CAN_ERR_PROT_LOC_ACK_DEL;
1017 }
1018 if (cerfl & RCANFD_CERFL_B0ERR) {
1019 netdev_dbg(ndev, "Bit Error (dominant)\n");
1020 stats->tx_errors++;
1021 cf->data[2] |= CAN_ERR_PROT_BIT0;
1022 }
1023 if (cerfl & RCANFD_CERFL_B1ERR) {
1024 netdev_dbg(ndev, "Bit Error (recessive)\n");
1025 stats->tx_errors++;
1026 cf->data[2] |= CAN_ERR_PROT_BIT1;
1027 }
1028 if (cerfl & RCANFD_CERFL_CERR) {
1029 netdev_dbg(ndev, "CRC Error\n");
1030 stats->rx_errors++;
1031 cf->data[3] |= CAN_ERR_PROT_LOC_CRC_SEQ;
1032 }
1033 if (cerfl & RCANFD_CERFL_AERR) {
1034 netdev_dbg(ndev, "ACK Error\n");
1035 stats->tx_errors++;
1036 cf->can_id |= CAN_ERR_ACK;
1037 cf->data[3] |= CAN_ERR_PROT_LOC_ACK;
1038 }
1039 if (cerfl & RCANFD_CERFL_FERR) {
1040 netdev_dbg(ndev, "Form Error\n");
1041 stats->rx_errors++;
1042 cf->data[2] |= CAN_ERR_PROT_FORM;
1043 }
1044 if (cerfl & RCANFD_CERFL_SERR) {
1045 netdev_dbg(ndev, "Stuff Error\n");
1046 stats->rx_errors++;
1047 cf->data[2] |= CAN_ERR_PROT_STUFF;
1048 }
1049 if (cerfl & RCANFD_CERFL_ALF) {
1050 netdev_dbg(ndev, "Arbitration lost Error\n");
1051 priv->can.can_stats.arbitration_lost++;
1052 cf->can_id |= CAN_ERR_LOSTARB;
1053 cf->data[0] |= CAN_ERR_LOSTARB_UNSPEC;
1054 }
1055 if (cerfl & RCANFD_CERFL_BLF) {
1056 netdev_dbg(ndev, "Bus Lock Error\n");
1057 stats->rx_errors++;
1058 cf->can_id |= CAN_ERR_BUSERROR;
1059 }
1060 if (cerfl & RCANFD_CERFL_EWF) {
1061 netdev_dbg(ndev, "Error warning interrupt\n");
1062 priv->can.state = CAN_STATE_ERROR_WARNING;
1063 priv->can.can_stats.error_warning++;
1064 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
1065 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_WARNING :
1066 CAN_ERR_CRTL_RX_WARNING;
1067 cf->data[6] = txerr;
1068 cf->data[7] = rxerr;
1069 }
1070 if (cerfl & RCANFD_CERFL_EPF) {
1071 netdev_dbg(ndev, "Error passive interrupt\n");
1072 priv->can.state = CAN_STATE_ERROR_PASSIVE;
1073 priv->can.can_stats.error_passive++;
1074 cf->can_id |= CAN_ERR_CRTL | CAN_ERR_CNT;
1075 cf->data[1] = txerr > rxerr ? CAN_ERR_CRTL_TX_PASSIVE :
1076 CAN_ERR_CRTL_RX_PASSIVE;
1077 cf->data[6] = txerr;
1078 cf->data[7] = rxerr;
1079 }
1080 if (cerfl & RCANFD_CERFL_BOEF) {
1081 netdev_dbg(ndev, "Bus-off entry interrupt\n");
1082 rcar_canfd_tx_failure_cleanup(ndev);
1083 priv->can.state = CAN_STATE_BUS_OFF;
1084 priv->can.can_stats.bus_off++;
1085 can_bus_off(ndev);
1086 cf->can_id |= CAN_ERR_BUSOFF;
1087 }
1088 if (cerfl & RCANFD_CERFL_OVLF) {
1089 netdev_dbg(ndev,
1090 "Overload Frame Transmission error interrupt\n");
1091 stats->tx_errors++;
1092 cf->can_id |= CAN_ERR_PROT;
1093 cf->data[2] |= CAN_ERR_PROT_OVERLOAD;
1094 }
1095
1096 /* Clear channel error interrupts that are handled */
1097 rcar_canfd_write(priv->base, RCANFD_CERFL(ch),
1098 RCANFD_CERFL_ERR(~cerfl));
1099 netif_rx(skb);
1100 }
1101
rcar_canfd_tx_done(struct net_device * ndev)1102 static void rcar_canfd_tx_done(struct net_device *ndev)
1103 {
1104 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1105 struct rcar_canfd_global *gpriv = priv->gpriv;
1106 struct net_device_stats *stats = &ndev->stats;
1107 u32 sts;
1108 unsigned long flags;
1109 u32 ch = priv->channel;
1110
1111 do {
1112 u8 unsent, sent;
1113
1114 sent = priv->tx_tail % RCANFD_FIFO_DEPTH;
1115 stats->tx_packets++;
1116 stats->tx_bytes += can_get_echo_skb(ndev, sent, NULL);
1117
1118 spin_lock_irqsave(&priv->tx_lock, flags);
1119 priv->tx_tail++;
1120 sts = rcar_canfd_read(priv->base,
1121 RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
1122 unsent = RCANFD_CFSTS_CFMC(sts);
1123
1124 /* Wake producer only when there is room */
1125 if (unsent != RCANFD_FIFO_DEPTH)
1126 netif_wake_queue(ndev);
1127
1128 if (priv->tx_head - priv->tx_tail <= unsent) {
1129 spin_unlock_irqrestore(&priv->tx_lock, flags);
1130 break;
1131 }
1132 spin_unlock_irqrestore(&priv->tx_lock, flags);
1133
1134 } while (1);
1135
1136 /* Clear interrupt */
1137 rcar_canfd_write(priv->base, RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX),
1138 sts & ~RCANFD_CFSTS_CFTXIF);
1139 }
1140
rcar_canfd_handle_global_err(struct rcar_canfd_global * gpriv,u32 ch)1141 static void rcar_canfd_handle_global_err(struct rcar_canfd_global *gpriv, u32 ch)
1142 {
1143 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1144 struct net_device *ndev = priv->ndev;
1145 u32 gerfl;
1146
1147 /* Handle global error interrupts */
1148 gerfl = rcar_canfd_read(priv->base, RCANFD_GERFL);
1149 if (unlikely(RCANFD_GERFL_ERR(gpriv, gerfl)))
1150 rcar_canfd_global_error(ndev);
1151 }
1152
rcar_canfd_global_err_interrupt(int irq,void * dev_id)1153 static irqreturn_t rcar_canfd_global_err_interrupt(int irq, void *dev_id)
1154 {
1155 struct rcar_canfd_global *gpriv = dev_id;
1156 u32 ch;
1157
1158 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
1159 rcar_canfd_handle_global_err(gpriv, ch);
1160
1161 return IRQ_HANDLED;
1162 }
1163
rcar_canfd_handle_global_receive(struct rcar_canfd_global * gpriv,u32 ch)1164 static void rcar_canfd_handle_global_receive(struct rcar_canfd_global *gpriv, u32 ch)
1165 {
1166 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1167 u32 ridx = ch + RCANFD_RFFIFO_IDX;
1168 u32 sts, cc;
1169
1170 /* Handle Rx interrupts */
1171 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1172 cc = rcar_canfd_read(priv->base, RCANFD_RFCC(gpriv, ridx));
1173 if (likely(sts & RCANFD_RFSTS_RFIF &&
1174 cc & RCANFD_RFCC_RFIE)) {
1175 if (napi_schedule_prep(&priv->napi)) {
1176 /* Disable Rx FIFO interrupts */
1177 rcar_canfd_clear_bit(priv->base,
1178 RCANFD_RFCC(gpriv, ridx),
1179 RCANFD_RFCC_RFIE);
1180 __napi_schedule(&priv->napi);
1181 }
1182 }
1183 }
1184
rcar_canfd_global_receive_fifo_interrupt(int irq,void * dev_id)1185 static irqreturn_t rcar_canfd_global_receive_fifo_interrupt(int irq, void *dev_id)
1186 {
1187 struct rcar_canfd_global *gpriv = dev_id;
1188 u32 ch;
1189
1190 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels)
1191 rcar_canfd_handle_global_receive(gpriv, ch);
1192
1193 return IRQ_HANDLED;
1194 }
1195
rcar_canfd_global_interrupt(int irq,void * dev_id)1196 static irqreturn_t rcar_canfd_global_interrupt(int irq, void *dev_id)
1197 {
1198 struct rcar_canfd_global *gpriv = dev_id;
1199 u32 ch;
1200
1201 /* Global error interrupts still indicate a condition specific
1202 * to a channel. RxFIFO interrupt is a global interrupt.
1203 */
1204 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
1205 rcar_canfd_handle_global_err(gpriv, ch);
1206 rcar_canfd_handle_global_receive(gpriv, ch);
1207 }
1208 return IRQ_HANDLED;
1209 }
1210
rcar_canfd_state_change(struct net_device * ndev,u16 txerr,u16 rxerr)1211 static void rcar_canfd_state_change(struct net_device *ndev,
1212 u16 txerr, u16 rxerr)
1213 {
1214 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1215 struct net_device_stats *stats = &ndev->stats;
1216 enum can_state rx_state, tx_state, state = priv->can.state;
1217 struct can_frame *cf;
1218 struct sk_buff *skb;
1219
1220 /* Handle transition from error to normal states */
1221 if (txerr < 96 && rxerr < 96)
1222 state = CAN_STATE_ERROR_ACTIVE;
1223 else if (txerr < 128 && rxerr < 128)
1224 state = CAN_STATE_ERROR_WARNING;
1225
1226 if (state != priv->can.state) {
1227 netdev_dbg(ndev, "state: new %d, old %d: txerr %u, rxerr %u\n",
1228 state, priv->can.state, txerr, rxerr);
1229 skb = alloc_can_err_skb(ndev, &cf);
1230 if (!skb) {
1231 stats->rx_dropped++;
1232 return;
1233 }
1234 tx_state = txerr >= rxerr ? state : 0;
1235 rx_state = txerr <= rxerr ? state : 0;
1236
1237 can_change_state(ndev, cf, tx_state, rx_state);
1238 netif_rx(skb);
1239 }
1240 }
1241
rcar_canfd_handle_channel_tx(struct rcar_canfd_global * gpriv,u32 ch)1242 static void rcar_canfd_handle_channel_tx(struct rcar_canfd_global *gpriv, u32 ch)
1243 {
1244 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1245 struct net_device *ndev = priv->ndev;
1246 u32 sts;
1247
1248 /* Handle Tx interrupts */
1249 sts = rcar_canfd_read(priv->base,
1250 RCANFD_CFSTS(gpriv, ch, RCANFD_CFFIFO_IDX));
1251 if (likely(sts & RCANFD_CFSTS_CFTXIF))
1252 rcar_canfd_tx_done(ndev);
1253 }
1254
rcar_canfd_channel_tx_interrupt(int irq,void * dev_id)1255 static irqreturn_t rcar_canfd_channel_tx_interrupt(int irq, void *dev_id)
1256 {
1257 struct rcar_canfd_channel *priv = dev_id;
1258
1259 rcar_canfd_handle_channel_tx(priv->gpriv, priv->channel);
1260
1261 return IRQ_HANDLED;
1262 }
1263
rcar_canfd_handle_channel_err(struct rcar_canfd_global * gpriv,u32 ch)1264 static void rcar_canfd_handle_channel_err(struct rcar_canfd_global *gpriv, u32 ch)
1265 {
1266 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1267 struct net_device *ndev = priv->ndev;
1268 u16 txerr, rxerr;
1269 u32 sts, cerfl;
1270
1271 /* Handle channel error interrupts */
1272 cerfl = rcar_canfd_read(priv->base, RCANFD_CERFL(ch));
1273 sts = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1274 txerr = RCANFD_CSTS_TECCNT(sts);
1275 rxerr = RCANFD_CSTS_RECCNT(sts);
1276 if (unlikely(RCANFD_CERFL_ERR(cerfl)))
1277 rcar_canfd_error(ndev, cerfl, txerr, rxerr);
1278
1279 /* Handle state change to lower states */
1280 if (unlikely(priv->can.state != CAN_STATE_ERROR_ACTIVE &&
1281 priv->can.state != CAN_STATE_BUS_OFF))
1282 rcar_canfd_state_change(ndev, txerr, rxerr);
1283 }
1284
rcar_canfd_channel_err_interrupt(int irq,void * dev_id)1285 static irqreturn_t rcar_canfd_channel_err_interrupt(int irq, void *dev_id)
1286 {
1287 struct rcar_canfd_channel *priv = dev_id;
1288
1289 rcar_canfd_handle_channel_err(priv->gpriv, priv->channel);
1290
1291 return IRQ_HANDLED;
1292 }
1293
rcar_canfd_channel_interrupt(int irq,void * dev_id)1294 static irqreturn_t rcar_canfd_channel_interrupt(int irq, void *dev_id)
1295 {
1296 struct rcar_canfd_global *gpriv = dev_id;
1297 u32 ch;
1298
1299 /* Common FIFO is a per channel resource */
1300 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
1301 rcar_canfd_handle_channel_err(gpriv, ch);
1302 rcar_canfd_handle_channel_tx(gpriv, ch);
1303 }
1304
1305 return IRQ_HANDLED;
1306 }
1307
rcar_canfd_set_bittiming(struct net_device * dev)1308 static void rcar_canfd_set_bittiming(struct net_device *dev)
1309 {
1310 struct rcar_canfd_channel *priv = netdev_priv(dev);
1311 struct rcar_canfd_global *gpriv = priv->gpriv;
1312 const struct can_bittiming *bt = &priv->can.bittiming;
1313 const struct can_bittiming *dbt = &priv->can.data_bittiming;
1314 u16 brp, sjw, tseg1, tseg2;
1315 u32 cfg;
1316 u32 ch = priv->channel;
1317
1318 /* Nominal bit timing settings */
1319 brp = bt->brp - 1;
1320 sjw = bt->sjw - 1;
1321 tseg1 = bt->prop_seg + bt->phase_seg1 - 1;
1322 tseg2 = bt->phase_seg2 - 1;
1323
1324 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1325 /* CAN FD only mode */
1326 cfg = (RCANFD_NCFG_NTSEG1(gpriv, tseg1) | RCANFD_NCFG_NBRP(brp) |
1327 RCANFD_NCFG_NSJW(gpriv, sjw) | RCANFD_NCFG_NTSEG2(gpriv, tseg2));
1328
1329 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1330 netdev_dbg(priv->ndev, "nrate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1331 brp, sjw, tseg1, tseg2);
1332
1333 /* Data bit timing settings */
1334 brp = dbt->brp - 1;
1335 sjw = dbt->sjw - 1;
1336 tseg1 = dbt->prop_seg + dbt->phase_seg1 - 1;
1337 tseg2 = dbt->phase_seg2 - 1;
1338
1339 cfg = (RCANFD_DCFG_DTSEG1(gpriv, tseg1) | RCANFD_DCFG_DBRP(brp) |
1340 RCANFD_DCFG_DSJW(gpriv, sjw) | RCANFD_DCFG_DTSEG2(gpriv, tseg2));
1341
1342 rcar_canfd_write(priv->base, RCANFD_F_DCFG(gpriv, ch), cfg);
1343 netdev_dbg(priv->ndev, "drate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1344 brp, sjw, tseg1, tseg2);
1345 } else {
1346 /* Classical CAN only mode */
1347 if (is_gen4(gpriv)) {
1348 cfg = (RCANFD_NCFG_NTSEG1(gpriv, tseg1) |
1349 RCANFD_NCFG_NBRP(brp) |
1350 RCANFD_NCFG_NSJW(gpriv, sjw) |
1351 RCANFD_NCFG_NTSEG2(gpriv, tseg2));
1352 } else {
1353 cfg = (RCANFD_CFG_TSEG1(tseg1) |
1354 RCANFD_CFG_BRP(brp) |
1355 RCANFD_CFG_SJW(sjw) |
1356 RCANFD_CFG_TSEG2(tseg2));
1357 }
1358
1359 rcar_canfd_write(priv->base, RCANFD_CCFG(ch), cfg);
1360 netdev_dbg(priv->ndev,
1361 "rate: brp %u, sjw %u, tseg1 %u, tseg2 %u\n",
1362 brp, sjw, tseg1, tseg2);
1363 }
1364 }
1365
rcar_canfd_start(struct net_device * ndev)1366 static int rcar_canfd_start(struct net_device *ndev)
1367 {
1368 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1369 struct rcar_canfd_global *gpriv = priv->gpriv;
1370 int err = -EOPNOTSUPP;
1371 u32 sts, ch = priv->channel;
1372 u32 ridx = ch + RCANFD_RFFIFO_IDX;
1373
1374 rcar_canfd_set_bittiming(ndev);
1375
1376 rcar_canfd_enable_channel_interrupts(priv);
1377
1378 /* Set channel to Operational mode */
1379 rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1380 RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_COPM);
1381
1382 /* Verify channel mode change */
1383 err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1384 (sts & RCANFD_CSTS_COMSTS), 2, 500000);
1385 if (err) {
1386 netdev_err(ndev, "channel %u communication state failed\n", ch);
1387 goto fail_mode_change;
1388 }
1389
1390 /* Enable Common & Rx FIFO */
1391 rcar_canfd_set_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX),
1392 RCANFD_CFCC_CFE);
1393 rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE);
1394
1395 priv->can.state = CAN_STATE_ERROR_ACTIVE;
1396 return 0;
1397
1398 fail_mode_change:
1399 rcar_canfd_disable_channel_interrupts(priv);
1400 return err;
1401 }
1402
rcar_canfd_open(struct net_device * ndev)1403 static int rcar_canfd_open(struct net_device *ndev)
1404 {
1405 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1406 struct rcar_canfd_global *gpriv = priv->gpriv;
1407 int err;
1408
1409 err = phy_power_on(priv->transceiver);
1410 if (err) {
1411 netdev_err(ndev, "failed to power on PHY: %pe\n", ERR_PTR(err));
1412 return err;
1413 }
1414
1415 /* Peripheral clock is already enabled in probe */
1416 err = clk_prepare_enable(gpriv->can_clk);
1417 if (err) {
1418 netdev_err(ndev, "failed to enable CAN clock: %pe\n", ERR_PTR(err));
1419 goto out_phy;
1420 }
1421
1422 err = open_candev(ndev);
1423 if (err) {
1424 netdev_err(ndev, "open_candev() failed: %pe\n", ERR_PTR(err));
1425 goto out_can_clock;
1426 }
1427
1428 napi_enable(&priv->napi);
1429 err = rcar_canfd_start(ndev);
1430 if (err)
1431 goto out_close;
1432 netif_start_queue(ndev);
1433 return 0;
1434 out_close:
1435 napi_disable(&priv->napi);
1436 close_candev(ndev);
1437 out_can_clock:
1438 clk_disable_unprepare(gpriv->can_clk);
1439 out_phy:
1440 phy_power_off(priv->transceiver);
1441 return err;
1442 }
1443
rcar_canfd_stop(struct net_device * ndev)1444 static void rcar_canfd_stop(struct net_device *ndev)
1445 {
1446 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1447 struct rcar_canfd_global *gpriv = priv->gpriv;
1448 int err;
1449 u32 sts, ch = priv->channel;
1450 u32 ridx = ch + RCANFD_RFFIFO_IDX;
1451
1452 /* Transition to channel reset mode */
1453 rcar_canfd_update_bit(priv->base, RCANFD_CCTR(ch),
1454 RCANFD_CCTR_CHMDC_MASK, RCANFD_CCTR_CHDMC_CRESET);
1455
1456 /* Check Channel reset mode */
1457 err = readl_poll_timeout((priv->base + RCANFD_CSTS(ch)), sts,
1458 (sts & RCANFD_CSTS_CRSTSTS), 2, 500000);
1459 if (err)
1460 netdev_err(ndev, "channel %u reset failed\n", ch);
1461
1462 rcar_canfd_disable_channel_interrupts(priv);
1463
1464 /* Disable Common & Rx FIFO */
1465 rcar_canfd_clear_bit(priv->base, RCANFD_CFCC(gpriv, ch, RCANFD_CFFIFO_IDX),
1466 RCANFD_CFCC_CFE);
1467 rcar_canfd_clear_bit(priv->base, RCANFD_RFCC(gpriv, ridx), RCANFD_RFCC_RFE);
1468
1469 /* Set the state as STOPPED */
1470 priv->can.state = CAN_STATE_STOPPED;
1471 }
1472
rcar_canfd_close(struct net_device * ndev)1473 static int rcar_canfd_close(struct net_device *ndev)
1474 {
1475 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1476 struct rcar_canfd_global *gpriv = priv->gpriv;
1477
1478 netif_stop_queue(ndev);
1479 rcar_canfd_stop(ndev);
1480 napi_disable(&priv->napi);
1481 clk_disable_unprepare(gpriv->can_clk);
1482 close_candev(ndev);
1483 phy_power_off(priv->transceiver);
1484 return 0;
1485 }
1486
rcar_canfd_start_xmit(struct sk_buff * skb,struct net_device * ndev)1487 static netdev_tx_t rcar_canfd_start_xmit(struct sk_buff *skb,
1488 struct net_device *ndev)
1489 {
1490 struct rcar_canfd_channel *priv = netdev_priv(ndev);
1491 struct rcar_canfd_global *gpriv = priv->gpriv;
1492 struct canfd_frame *cf = (struct canfd_frame *)skb->data;
1493 u32 sts = 0, id, dlc;
1494 unsigned long flags;
1495 u32 ch = priv->channel;
1496
1497 if (can_dev_dropped_skb(ndev, skb))
1498 return NETDEV_TX_OK;
1499
1500 if (cf->can_id & CAN_EFF_FLAG) {
1501 id = cf->can_id & CAN_EFF_MASK;
1502 id |= RCANFD_CFID_CFIDE;
1503 } else {
1504 id = cf->can_id & CAN_SFF_MASK;
1505 }
1506
1507 if (cf->can_id & CAN_RTR_FLAG)
1508 id |= RCANFD_CFID_CFRTR;
1509
1510 dlc = RCANFD_CFPTR_CFDLC(can_fd_len2dlc(cf->len));
1511
1512 if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || is_gen4(gpriv)) {
1513 rcar_canfd_write(priv->base,
1514 RCANFD_F_CFID(gpriv, ch, RCANFD_CFFIFO_IDX), id);
1515 rcar_canfd_write(priv->base,
1516 RCANFD_F_CFPTR(gpriv, ch, RCANFD_CFFIFO_IDX), dlc);
1517
1518 if (can_is_canfd_skb(skb)) {
1519 /* CAN FD frame format */
1520 sts |= RCANFD_CFFDCSTS_CFFDF;
1521 if (cf->flags & CANFD_BRS)
1522 sts |= RCANFD_CFFDCSTS_CFBRS;
1523
1524 if (priv->can.state == CAN_STATE_ERROR_PASSIVE)
1525 sts |= RCANFD_CFFDCSTS_CFESI;
1526 }
1527
1528 rcar_canfd_write(priv->base,
1529 RCANFD_F_CFFDCSTS(gpriv, ch, RCANFD_CFFIFO_IDX), sts);
1530
1531 rcar_canfd_put_data(priv, cf,
1532 RCANFD_F_CFDF(gpriv, ch, RCANFD_CFFIFO_IDX, 0));
1533 } else {
1534 rcar_canfd_write(priv->base,
1535 RCANFD_C_CFID(ch, RCANFD_CFFIFO_IDX), id);
1536 rcar_canfd_write(priv->base,
1537 RCANFD_C_CFPTR(ch, RCANFD_CFFIFO_IDX), dlc);
1538 rcar_canfd_put_data(priv, cf,
1539 RCANFD_C_CFDF(ch, RCANFD_CFFIFO_IDX, 0));
1540 }
1541
1542 can_put_echo_skb(skb, ndev, priv->tx_head % RCANFD_FIFO_DEPTH, 0);
1543
1544 spin_lock_irqsave(&priv->tx_lock, flags);
1545 priv->tx_head++;
1546
1547 /* Stop the queue if we've filled all FIFO entries */
1548 if (priv->tx_head - priv->tx_tail >= RCANFD_FIFO_DEPTH)
1549 netif_stop_queue(ndev);
1550
1551 /* Start Tx: Write 0xff to CFPC to increment the CPU-side
1552 * pointer for the Common FIFO
1553 */
1554 rcar_canfd_write(priv->base,
1555 RCANFD_CFPCTR(gpriv, ch, RCANFD_CFFIFO_IDX), 0xff);
1556
1557 spin_unlock_irqrestore(&priv->tx_lock, flags);
1558 return NETDEV_TX_OK;
1559 }
1560
rcar_canfd_rx_pkt(struct rcar_canfd_channel * priv)1561 static void rcar_canfd_rx_pkt(struct rcar_canfd_channel *priv)
1562 {
1563 struct net_device_stats *stats = &priv->ndev->stats;
1564 struct rcar_canfd_global *gpriv = priv->gpriv;
1565 struct canfd_frame *cf;
1566 struct sk_buff *skb;
1567 u32 sts = 0, id, dlc;
1568 u32 ch = priv->channel;
1569 u32 ridx = ch + RCANFD_RFFIFO_IDX;
1570
1571 if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) || is_gen4(gpriv)) {
1572 id = rcar_canfd_read(priv->base, RCANFD_F_RFID(gpriv, ridx));
1573 dlc = rcar_canfd_read(priv->base, RCANFD_F_RFPTR(gpriv, ridx));
1574
1575 sts = rcar_canfd_read(priv->base, RCANFD_F_RFFDSTS(gpriv, ridx));
1576
1577 if ((priv->can.ctrlmode & CAN_CTRLMODE_FD) &&
1578 sts & RCANFD_RFFDSTS_RFFDF)
1579 skb = alloc_canfd_skb(priv->ndev, &cf);
1580 else
1581 skb = alloc_can_skb(priv->ndev,
1582 (struct can_frame **)&cf);
1583 } else {
1584 id = rcar_canfd_read(priv->base, RCANFD_C_RFID(ridx));
1585 dlc = rcar_canfd_read(priv->base, RCANFD_C_RFPTR(ridx));
1586 skb = alloc_can_skb(priv->ndev, (struct can_frame **)&cf);
1587 }
1588
1589 if (!skb) {
1590 stats->rx_dropped++;
1591 return;
1592 }
1593
1594 if (id & RCANFD_RFID_RFIDE)
1595 cf->can_id = (id & CAN_EFF_MASK) | CAN_EFF_FLAG;
1596 else
1597 cf->can_id = id & CAN_SFF_MASK;
1598
1599 if (priv->can.ctrlmode & CAN_CTRLMODE_FD) {
1600 if (sts & RCANFD_RFFDSTS_RFFDF)
1601 cf->len = can_fd_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1602 else
1603 cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1604
1605 if (sts & RCANFD_RFFDSTS_RFESI) {
1606 cf->flags |= CANFD_ESI;
1607 netdev_dbg(priv->ndev, "ESI Error\n");
1608 }
1609
1610 if (!(sts & RCANFD_RFFDSTS_RFFDF) && (id & RCANFD_RFID_RFRTR)) {
1611 cf->can_id |= CAN_RTR_FLAG;
1612 } else {
1613 if (sts & RCANFD_RFFDSTS_RFBRS)
1614 cf->flags |= CANFD_BRS;
1615
1616 rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(gpriv, ridx, 0));
1617 }
1618 } else {
1619 cf->len = can_cc_dlc2len(RCANFD_RFPTR_RFDLC(dlc));
1620 if (id & RCANFD_RFID_RFRTR)
1621 cf->can_id |= CAN_RTR_FLAG;
1622 else if (is_gen4(gpriv))
1623 rcar_canfd_get_data(priv, cf, RCANFD_F_RFDF(gpriv, ridx, 0));
1624 else
1625 rcar_canfd_get_data(priv, cf, RCANFD_C_RFDF(ridx, 0));
1626 }
1627
1628 /* Write 0xff to RFPC to increment the CPU-side
1629 * pointer of the Rx FIFO
1630 */
1631 rcar_canfd_write(priv->base, RCANFD_RFPCTR(gpriv, ridx), 0xff);
1632
1633 if (!(cf->can_id & CAN_RTR_FLAG))
1634 stats->rx_bytes += cf->len;
1635 stats->rx_packets++;
1636 netif_receive_skb(skb);
1637 }
1638
rcar_canfd_rx_poll(struct napi_struct * napi,int quota)1639 static int rcar_canfd_rx_poll(struct napi_struct *napi, int quota)
1640 {
1641 struct rcar_canfd_channel *priv =
1642 container_of(napi, struct rcar_canfd_channel, napi);
1643 struct rcar_canfd_global *gpriv = priv->gpriv;
1644 int num_pkts;
1645 u32 sts;
1646 u32 ch = priv->channel;
1647 u32 ridx = ch + RCANFD_RFFIFO_IDX;
1648
1649 for (num_pkts = 0; num_pkts < quota; num_pkts++) {
1650 sts = rcar_canfd_read(priv->base, RCANFD_RFSTS(gpriv, ridx));
1651 /* Check FIFO empty condition */
1652 if (sts & RCANFD_RFSTS_RFEMP)
1653 break;
1654
1655 rcar_canfd_rx_pkt(priv);
1656
1657 /* Clear interrupt bit */
1658 if (sts & RCANFD_RFSTS_RFIF)
1659 rcar_canfd_write(priv->base, RCANFD_RFSTS(gpriv, ridx),
1660 sts & ~RCANFD_RFSTS_RFIF);
1661 }
1662
1663 /* All packets processed */
1664 if (num_pkts < quota) {
1665 if (napi_complete_done(napi, num_pkts)) {
1666 /* Enable Rx FIFO interrupts */
1667 rcar_canfd_set_bit(priv->base, RCANFD_RFCC(gpriv, ridx),
1668 RCANFD_RFCC_RFIE);
1669 }
1670 }
1671 return num_pkts;
1672 }
1673
rcar_canfd_do_set_mode(struct net_device * ndev,enum can_mode mode)1674 static int rcar_canfd_do_set_mode(struct net_device *ndev, enum can_mode mode)
1675 {
1676 int err;
1677
1678 switch (mode) {
1679 case CAN_MODE_START:
1680 err = rcar_canfd_start(ndev);
1681 if (err)
1682 return err;
1683 netif_wake_queue(ndev);
1684 return 0;
1685 default:
1686 return -EOPNOTSUPP;
1687 }
1688 }
1689
rcar_canfd_get_berr_counter(const struct net_device * dev,struct can_berr_counter * bec)1690 static int rcar_canfd_get_berr_counter(const struct net_device *dev,
1691 struct can_berr_counter *bec)
1692 {
1693 struct rcar_canfd_channel *priv = netdev_priv(dev);
1694 u32 val, ch = priv->channel;
1695
1696 /* Peripheral clock is already enabled in probe */
1697 val = rcar_canfd_read(priv->base, RCANFD_CSTS(ch));
1698 bec->txerr = RCANFD_CSTS_TECCNT(val);
1699 bec->rxerr = RCANFD_CSTS_RECCNT(val);
1700 return 0;
1701 }
1702
1703 static const struct net_device_ops rcar_canfd_netdev_ops = {
1704 .ndo_open = rcar_canfd_open,
1705 .ndo_stop = rcar_canfd_close,
1706 .ndo_start_xmit = rcar_canfd_start_xmit,
1707 .ndo_change_mtu = can_change_mtu,
1708 };
1709
1710 static const struct ethtool_ops rcar_canfd_ethtool_ops = {
1711 .get_ts_info = ethtool_op_get_ts_info,
1712 };
1713
rcar_canfd_channel_probe(struct rcar_canfd_global * gpriv,u32 ch,u32 fcan_freq,struct phy * transceiver)1714 static int rcar_canfd_channel_probe(struct rcar_canfd_global *gpriv, u32 ch,
1715 u32 fcan_freq, struct phy *transceiver)
1716 {
1717 const struct rcar_canfd_hw_info *info = gpriv->info;
1718 struct platform_device *pdev = gpriv->pdev;
1719 struct device *dev = &pdev->dev;
1720 struct rcar_canfd_channel *priv;
1721 struct net_device *ndev;
1722 int err = -ENODEV;
1723
1724 ndev = alloc_candev(sizeof(*priv), RCANFD_FIFO_DEPTH);
1725 if (!ndev)
1726 return -ENOMEM;
1727
1728 priv = netdev_priv(ndev);
1729
1730 ndev->netdev_ops = &rcar_canfd_netdev_ops;
1731 ndev->ethtool_ops = &rcar_canfd_ethtool_ops;
1732 ndev->flags |= IFF_ECHO;
1733 priv->ndev = ndev;
1734 priv->base = gpriv->base;
1735 priv->transceiver = transceiver;
1736 priv->channel = ch;
1737 priv->gpriv = gpriv;
1738 if (transceiver)
1739 priv->can.bitrate_max = transceiver->attrs.max_link_rate;
1740 priv->can.clock.freq = fcan_freq;
1741 dev_info(dev, "can_clk rate is %u\n", priv->can.clock.freq);
1742
1743 if (info->multi_channel_irqs) {
1744 char *irq_name;
1745 int err_irq;
1746 int tx_irq;
1747
1748 err_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_err" : "ch1_err");
1749 if (err_irq < 0) {
1750 err = err_irq;
1751 goto fail;
1752 }
1753
1754 tx_irq = platform_get_irq_byname(pdev, ch == 0 ? "ch0_trx" : "ch1_trx");
1755 if (tx_irq < 0) {
1756 err = tx_irq;
1757 goto fail;
1758 }
1759
1760 irq_name = devm_kasprintf(dev, GFP_KERNEL, "canfd.ch%d_err",
1761 ch);
1762 if (!irq_name) {
1763 err = -ENOMEM;
1764 goto fail;
1765 }
1766 err = devm_request_irq(dev, err_irq,
1767 rcar_canfd_channel_err_interrupt, 0,
1768 irq_name, priv);
1769 if (err) {
1770 dev_err(dev, "devm_request_irq CH Err %d failed: %pe\n",
1771 err_irq, ERR_PTR(err));
1772 goto fail;
1773 }
1774 irq_name = devm_kasprintf(dev, GFP_KERNEL, "canfd.ch%d_trx",
1775 ch);
1776 if (!irq_name) {
1777 err = -ENOMEM;
1778 goto fail;
1779 }
1780 err = devm_request_irq(dev, tx_irq,
1781 rcar_canfd_channel_tx_interrupt, 0,
1782 irq_name, priv);
1783 if (err) {
1784 dev_err(dev, "devm_request_irq Tx %d failed: %pe\n",
1785 tx_irq, ERR_PTR(err));
1786 goto fail;
1787 }
1788 }
1789
1790 if (gpriv->fdmode) {
1791 priv->can.bittiming_const = &rcar_canfd_nom_bittiming_const;
1792 priv->can.data_bittiming_const =
1793 &rcar_canfd_data_bittiming_const;
1794
1795 /* Controller starts in CAN FD only mode */
1796 err = can_set_static_ctrlmode(ndev, CAN_CTRLMODE_FD);
1797 if (err)
1798 goto fail;
1799 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1800 } else {
1801 /* Controller starts in Classical CAN only mode */
1802 priv->can.bittiming_const = &rcar_canfd_bittiming_const;
1803 priv->can.ctrlmode_supported = CAN_CTRLMODE_BERR_REPORTING;
1804 }
1805
1806 priv->can.do_set_mode = rcar_canfd_do_set_mode;
1807 priv->can.do_get_berr_counter = rcar_canfd_get_berr_counter;
1808 SET_NETDEV_DEV(ndev, dev);
1809
1810 netif_napi_add_weight(ndev, &priv->napi, rcar_canfd_rx_poll,
1811 RCANFD_NAPI_WEIGHT);
1812 spin_lock_init(&priv->tx_lock);
1813 gpriv->ch[priv->channel] = priv;
1814 err = register_candev(ndev);
1815 if (err) {
1816 dev_err(dev, "register_candev() failed: %pe\n", ERR_PTR(err));
1817 goto fail_candev;
1818 }
1819 dev_info(dev, "device registered (channel %u)\n", priv->channel);
1820 return 0;
1821
1822 fail_candev:
1823 netif_napi_del(&priv->napi);
1824 fail:
1825 free_candev(ndev);
1826 return err;
1827 }
1828
rcar_canfd_channel_remove(struct rcar_canfd_global * gpriv,u32 ch)1829 static void rcar_canfd_channel_remove(struct rcar_canfd_global *gpriv, u32 ch)
1830 {
1831 struct rcar_canfd_channel *priv = gpriv->ch[ch];
1832
1833 if (priv) {
1834 unregister_candev(priv->ndev);
1835 netif_napi_del(&priv->napi);
1836 free_candev(priv->ndev);
1837 }
1838 }
1839
rcar_canfd_probe(struct platform_device * pdev)1840 static int rcar_canfd_probe(struct platform_device *pdev)
1841 {
1842 struct phy *transceivers[RCANFD_NUM_CHANNELS] = { NULL, };
1843 const struct rcar_canfd_hw_info *info;
1844 struct device *dev = &pdev->dev;
1845 void __iomem *addr;
1846 u32 sts, ch, fcan_freq;
1847 struct rcar_canfd_global *gpriv;
1848 struct device_node *of_child;
1849 unsigned long channels_mask = 0;
1850 int err, ch_irq, g_irq;
1851 int g_err_irq, g_recc_irq;
1852 u32 rule_entry = 0;
1853 bool fdmode = true; /* CAN FD only mode - default */
1854 char name[9] = "channelX";
1855 int i;
1856
1857 info = of_device_get_match_data(dev);
1858
1859 if (of_property_read_bool(dev->of_node, "renesas,no-can-fd"))
1860 fdmode = false; /* Classical CAN only mode */
1861
1862 for (i = 0; i < info->max_channels; ++i) {
1863 name[7] = '0' + i;
1864 of_child = of_get_child_by_name(dev->of_node, name);
1865 if (of_child && of_device_is_available(of_child)) {
1866 channels_mask |= BIT(i);
1867 transceivers[i] = devm_of_phy_optional_get(dev,
1868 of_child, NULL);
1869 }
1870 of_node_put(of_child);
1871 if (IS_ERR(transceivers[i]))
1872 return PTR_ERR(transceivers[i]);
1873 }
1874
1875 if (info->shared_global_irqs) {
1876 ch_irq = platform_get_irq_byname_optional(pdev, "ch_int");
1877 if (ch_irq < 0) {
1878 /* For backward compatibility get irq by index */
1879 ch_irq = platform_get_irq(pdev, 0);
1880 if (ch_irq < 0)
1881 return ch_irq;
1882 }
1883
1884 g_irq = platform_get_irq_byname_optional(pdev, "g_int");
1885 if (g_irq < 0) {
1886 /* For backward compatibility get irq by index */
1887 g_irq = platform_get_irq(pdev, 1);
1888 if (g_irq < 0)
1889 return g_irq;
1890 }
1891 } else {
1892 g_err_irq = platform_get_irq_byname(pdev, "g_err");
1893 if (g_err_irq < 0)
1894 return g_err_irq;
1895
1896 g_recc_irq = platform_get_irq_byname(pdev, "g_recc");
1897 if (g_recc_irq < 0)
1898 return g_recc_irq;
1899 }
1900
1901 /* Global controller context */
1902 gpriv = devm_kzalloc(dev, sizeof(*gpriv), GFP_KERNEL);
1903 if (!gpriv)
1904 return -ENOMEM;
1905
1906 gpriv->pdev = pdev;
1907 gpriv->channels_mask = channels_mask;
1908 gpriv->fdmode = fdmode;
1909 gpriv->info = info;
1910
1911 gpriv->rstc1 = devm_reset_control_get_optional_exclusive(dev, "rstp_n");
1912 if (IS_ERR(gpriv->rstc1))
1913 return dev_err_probe(dev, PTR_ERR(gpriv->rstc1),
1914 "failed to get rstp_n\n");
1915
1916 gpriv->rstc2 = devm_reset_control_get_optional_exclusive(dev, "rstc_n");
1917 if (IS_ERR(gpriv->rstc2))
1918 return dev_err_probe(dev, PTR_ERR(gpriv->rstc2),
1919 "failed to get rstc_n\n");
1920
1921 /* Peripheral clock */
1922 gpriv->clkp = devm_clk_get(dev, "fck");
1923 if (IS_ERR(gpriv->clkp))
1924 return dev_err_probe(dev, PTR_ERR(gpriv->clkp),
1925 "cannot get peripheral clock\n");
1926
1927 /* fCAN clock: Pick External clock. If not available fallback to
1928 * CANFD clock
1929 */
1930 gpriv->can_clk = devm_clk_get(dev, "can_clk");
1931 if (IS_ERR(gpriv->can_clk) || (clk_get_rate(gpriv->can_clk) == 0)) {
1932 gpriv->can_clk = devm_clk_get(dev, "canfd");
1933 if (IS_ERR(gpriv->can_clk))
1934 return dev_err_probe(dev, PTR_ERR(gpriv->can_clk),
1935 "cannot get canfd clock\n");
1936
1937 gpriv->fcan = RCANFD_CANFDCLK;
1938
1939 } else {
1940 gpriv->fcan = RCANFD_EXTCLK;
1941 }
1942 fcan_freq = clk_get_rate(gpriv->can_clk);
1943
1944 if (gpriv->fcan == RCANFD_CANFDCLK)
1945 /* CANFD clock is further divided by (1/2) within the IP */
1946 fcan_freq /= info->postdiv;
1947
1948 addr = devm_platform_ioremap_resource(pdev, 0);
1949 if (IS_ERR(addr)) {
1950 err = PTR_ERR(addr);
1951 goto fail_dev;
1952 }
1953 gpriv->base = addr;
1954
1955 /* Request IRQ that's common for both channels */
1956 if (info->shared_global_irqs) {
1957 err = devm_request_irq(dev, ch_irq,
1958 rcar_canfd_channel_interrupt, 0,
1959 "canfd.ch_int", gpriv);
1960 if (err) {
1961 dev_err(dev, "devm_request_irq %d failed: %pe\n",
1962 ch_irq, ERR_PTR(err));
1963 goto fail_dev;
1964 }
1965
1966 err = devm_request_irq(dev, g_irq, rcar_canfd_global_interrupt,
1967 0, "canfd.g_int", gpriv);
1968 if (err) {
1969 dev_err(dev, "devm_request_irq %d failed: %pe\n",
1970 g_irq, ERR_PTR(err));
1971 goto fail_dev;
1972 }
1973 } else {
1974 err = devm_request_irq(dev, g_recc_irq,
1975 rcar_canfd_global_receive_fifo_interrupt, 0,
1976 "canfd.g_recc", gpriv);
1977
1978 if (err) {
1979 dev_err(dev, "devm_request_irq %d failed: %pe\n",
1980 g_recc_irq, ERR_PTR(err));
1981 goto fail_dev;
1982 }
1983
1984 err = devm_request_irq(dev, g_err_irq,
1985 rcar_canfd_global_err_interrupt, 0,
1986 "canfd.g_err", gpriv);
1987 if (err) {
1988 dev_err(dev, "devm_request_irq %d failed: %pe\n",
1989 g_err_irq, ERR_PTR(err));
1990 goto fail_dev;
1991 }
1992 }
1993
1994 err = reset_control_reset(gpriv->rstc1);
1995 if (err)
1996 goto fail_dev;
1997 err = reset_control_reset(gpriv->rstc2);
1998 if (err) {
1999 reset_control_assert(gpriv->rstc1);
2000 goto fail_dev;
2001 }
2002
2003 /* Enable peripheral clock for register access */
2004 err = clk_prepare_enable(gpriv->clkp);
2005 if (err) {
2006 dev_err(dev, "failed to enable peripheral clock: %pe\n",
2007 ERR_PTR(err));
2008 goto fail_reset;
2009 }
2010
2011 err = rcar_canfd_reset_controller(gpriv);
2012 if (err) {
2013 dev_err(dev, "reset controller failed: %pe\n", ERR_PTR(err));
2014 goto fail_clk;
2015 }
2016
2017 /* Controller in Global reset & Channel reset mode */
2018 rcar_canfd_configure_controller(gpriv);
2019
2020 /* Configure per channel attributes */
2021 for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels) {
2022 /* Configure Channel's Rx fifo */
2023 rcar_canfd_configure_rx(gpriv, ch);
2024
2025 /* Configure Channel's Tx (Common) fifo */
2026 rcar_canfd_configure_tx(gpriv, ch);
2027
2028 /* Configure receive rules */
2029 rcar_canfd_configure_afl_rules(gpriv, ch, rule_entry);
2030 rule_entry += RCANFD_CHANNEL_NUMRULES;
2031 }
2032
2033 /* Configure common interrupts */
2034 rcar_canfd_enable_global_interrupts(gpriv);
2035
2036 /* Start Global operation mode */
2037 rcar_canfd_update_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GMDC_MASK,
2038 RCANFD_GCTR_GMDC_GOPM);
2039
2040 /* Verify mode change */
2041 err = readl_poll_timeout((gpriv->base + RCANFD_GSTS), sts,
2042 !(sts & RCANFD_GSTS_GNOPM), 2, 500000);
2043 if (err) {
2044 dev_err(dev, "global operational mode failed\n");
2045 goto fail_mode;
2046 }
2047
2048 for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels) {
2049 err = rcar_canfd_channel_probe(gpriv, ch, fcan_freq,
2050 transceivers[ch]);
2051 if (err)
2052 goto fail_channel;
2053 }
2054
2055 platform_set_drvdata(pdev, gpriv);
2056 dev_info(dev, "global operational state (clk %d, fdmode %d)\n",
2057 gpriv->fcan, gpriv->fdmode);
2058 return 0;
2059
2060 fail_channel:
2061 for_each_set_bit(ch, &gpriv->channels_mask, info->max_channels)
2062 rcar_canfd_channel_remove(gpriv, ch);
2063 fail_mode:
2064 rcar_canfd_disable_global_interrupts(gpriv);
2065 fail_clk:
2066 clk_disable_unprepare(gpriv->clkp);
2067 fail_reset:
2068 reset_control_assert(gpriv->rstc1);
2069 reset_control_assert(gpriv->rstc2);
2070 fail_dev:
2071 return err;
2072 }
2073
rcar_canfd_remove(struct platform_device * pdev)2074 static void rcar_canfd_remove(struct platform_device *pdev)
2075 {
2076 struct rcar_canfd_global *gpriv = platform_get_drvdata(pdev);
2077 u32 ch;
2078
2079 rcar_canfd_reset_controller(gpriv);
2080 rcar_canfd_disable_global_interrupts(gpriv);
2081
2082 for_each_set_bit(ch, &gpriv->channels_mask, gpriv->info->max_channels) {
2083 rcar_canfd_disable_channel_interrupts(gpriv->ch[ch]);
2084 rcar_canfd_channel_remove(gpriv, ch);
2085 }
2086
2087 /* Enter global sleep mode */
2088 rcar_canfd_set_bit(gpriv->base, RCANFD_GCTR, RCANFD_GCTR_GSLPR);
2089 clk_disable_unprepare(gpriv->clkp);
2090 reset_control_assert(gpriv->rstc1);
2091 reset_control_assert(gpriv->rstc2);
2092 }
2093
rcar_canfd_suspend(struct device * dev)2094 static int __maybe_unused rcar_canfd_suspend(struct device *dev)
2095 {
2096 return 0;
2097 }
2098
rcar_canfd_resume(struct device * dev)2099 static int __maybe_unused rcar_canfd_resume(struct device *dev)
2100 {
2101 return 0;
2102 }
2103
2104 static SIMPLE_DEV_PM_OPS(rcar_canfd_pm_ops, rcar_canfd_suspend,
2105 rcar_canfd_resume);
2106
2107 static const __maybe_unused struct of_device_id rcar_canfd_of_table[] = {
2108 { .compatible = "renesas,r8a779a0-canfd", .data = &rcar_gen4_hw_info },
2109 { .compatible = "renesas,rcar-gen3-canfd", .data = &rcar_gen3_hw_info },
2110 { .compatible = "renesas,rcar-gen4-canfd", .data = &rcar_gen4_hw_info },
2111 { .compatible = "renesas,rzg2l-canfd", .data = &rzg2l_hw_info },
2112 { }
2113 };
2114
2115 MODULE_DEVICE_TABLE(of, rcar_canfd_of_table);
2116
2117 static struct platform_driver rcar_canfd_driver = {
2118 .driver = {
2119 .name = RCANFD_DRV_NAME,
2120 .of_match_table = of_match_ptr(rcar_canfd_of_table),
2121 .pm = &rcar_canfd_pm_ops,
2122 },
2123 .probe = rcar_canfd_probe,
2124 .remove_new = rcar_canfd_remove,
2125 };
2126
2127 module_platform_driver(rcar_canfd_driver);
2128
2129 MODULE_AUTHOR("Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>");
2130 MODULE_LICENSE("GPL");
2131 MODULE_DESCRIPTION("CAN FD driver for Renesas R-Car SoC");
2132 MODULE_ALIAS("platform:" RCANFD_DRV_NAME);
2133