1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Definitions for the new Marvell Yukon / SysKonnect driver.
4  */
5 #ifndef _SKGE_H
6 #define _SKGE_H
7 #include <linux/interrupt.h>
8 
9 /* PCI config registers */
10 #define PCI_DEV_REG1	0x40
11 #define  PCI_PHY_COMA	0x8000000
12 #define  PCI_VIO	0x2000000
13 
14 #define PCI_DEV_REG2	0x44
15 #define  PCI_VPD_ROM_SZ	7L<<14	/* VPD ROM size 0=256, 1=512, ... */
16 #define  PCI_REV_DESC	1<<2	/* Reverse Descriptor bytes */
17 
18 enum csr_regs {
19 	B0_RAP	= 0x0000,
20 	B0_CTST	= 0x0004,
21 	B0_LED	= 0x0006,
22 	B0_POWER_CTRL	= 0x0007,
23 	B0_ISRC	= 0x0008,
24 	B0_IMSK	= 0x000c,
25 	B0_HWE_ISRC	= 0x0010,
26 	B0_HWE_IMSK	= 0x0014,
27 	B0_SP_ISRC	= 0x0018,
28 	B0_XM1_IMSK	= 0x0020,
29 	B0_XM1_ISRC	= 0x0028,
30 	B0_XM1_PHY_ADDR	= 0x0030,
31 	B0_XM1_PHY_DATA	= 0x0034,
32 	B0_XM2_IMSK	= 0x0040,
33 	B0_XM2_ISRC	= 0x0048,
34 	B0_XM2_PHY_ADDR	= 0x0050,
35 	B0_XM2_PHY_DATA	= 0x0054,
36 	B0_R1_CSR	= 0x0060,
37 	B0_R2_CSR	= 0x0064,
38 	B0_XS1_CSR	= 0x0068,
39 	B0_XA1_CSR	= 0x006c,
40 	B0_XS2_CSR	= 0x0070,
41 	B0_XA2_CSR	= 0x0074,
42 
43 	B2_MAC_1	= 0x0100,
44 	B2_MAC_2	= 0x0108,
45 	B2_MAC_3	= 0x0110,
46 	B2_CONN_TYP	= 0x0118,
47 	B2_PMD_TYP	= 0x0119,
48 	B2_MAC_CFG	= 0x011a,
49 	B2_CHIP_ID	= 0x011b,
50 	B2_E_0		= 0x011c,
51 	B2_E_1		= 0x011d,
52 	B2_E_2		= 0x011e,
53 	B2_E_3		= 0x011f,
54 	B2_FAR		= 0x0120,
55 	B2_FDP		= 0x0124,
56 	B2_LD_CTRL	= 0x0128,
57 	B2_LD_TEST	= 0x0129,
58 	B2_TI_INI	= 0x0130,
59 	B2_TI_VAL	= 0x0134,
60 	B2_TI_CTRL	= 0x0138,
61 	B2_TI_TEST	= 0x0139,
62 	B2_IRQM_INI	= 0x0140,
63 	B2_IRQM_VAL	= 0x0144,
64 	B2_IRQM_CTRL	= 0x0148,
65 	B2_IRQM_TEST	= 0x0149,
66 	B2_IRQM_MSK	= 0x014c,
67 	B2_IRQM_HWE_MSK	= 0x0150,
68 	B2_TST_CTRL1	= 0x0158,
69 	B2_TST_CTRL2	= 0x0159,
70 	B2_GP_IO	= 0x015c,
71 	B2_I2C_CTRL	= 0x0160,
72 	B2_I2C_DATA	= 0x0164,
73 	B2_I2C_IRQ	= 0x0168,
74 	B2_I2C_SW	= 0x016c,
75 	B2_BSC_INI	= 0x0170,
76 	B2_BSC_VAL	= 0x0174,
77 	B2_BSC_CTRL	= 0x0178,
78 	B2_BSC_STAT	= 0x0179,
79 	B2_BSC_TST	= 0x017a,
80 
81 	B3_RAM_ADDR	= 0x0180,
82 	B3_RAM_DATA_LO	= 0x0184,
83 	B3_RAM_DATA_HI	= 0x0188,
84 	B3_RI_WTO_R1	= 0x0190,
85 	B3_RI_WTO_XA1	= 0x0191,
86 	B3_RI_WTO_XS1	= 0x0192,
87 	B3_RI_RTO_R1	= 0x0193,
88 	B3_RI_RTO_XA1	= 0x0194,
89 	B3_RI_RTO_XS1	= 0x0195,
90 	B3_RI_WTO_R2	= 0x0196,
91 	B3_RI_WTO_XA2	= 0x0197,
92 	B3_RI_WTO_XS2	= 0x0198,
93 	B3_RI_RTO_R2	= 0x0199,
94 	B3_RI_RTO_XA2	= 0x019a,
95 	B3_RI_RTO_XS2	= 0x019b,
96 	B3_RI_TO_VAL	= 0x019c,
97 	B3_RI_CTRL	= 0x01a0,
98 	B3_RI_TEST	= 0x01a2,
99 	B3_MA_TOINI_RX1	= 0x01b0,
100 	B3_MA_TOINI_RX2	= 0x01b1,
101 	B3_MA_TOINI_TX1	= 0x01b2,
102 	B3_MA_TOINI_TX2	= 0x01b3,
103 	B3_MA_TOVAL_RX1	= 0x01b4,
104 	B3_MA_TOVAL_RX2	= 0x01b5,
105 	B3_MA_TOVAL_TX1	= 0x01b6,
106 	B3_MA_TOVAL_TX2	= 0x01b7,
107 	B3_MA_TO_CTRL	= 0x01b8,
108 	B3_MA_TO_TEST	= 0x01ba,
109 	B3_MA_RCINI_RX1	= 0x01c0,
110 	B3_MA_RCINI_RX2	= 0x01c1,
111 	B3_MA_RCINI_TX1	= 0x01c2,
112 	B3_MA_RCINI_TX2	= 0x01c3,
113 	B3_MA_RCVAL_RX1	= 0x01c4,
114 	B3_MA_RCVAL_RX2	= 0x01c5,
115 	B3_MA_RCVAL_TX1	= 0x01c6,
116 	B3_MA_RCVAL_TX2	= 0x01c7,
117 	B3_MA_RC_CTRL	= 0x01c8,
118 	B3_MA_RC_TEST	= 0x01ca,
119 	B3_PA_TOINI_RX1	= 0x01d0,
120 	B3_PA_TOINI_RX2	= 0x01d4,
121 	B3_PA_TOINI_TX1	= 0x01d8,
122 	B3_PA_TOINI_TX2	= 0x01dc,
123 	B3_PA_TOVAL_RX1	= 0x01e0,
124 	B3_PA_TOVAL_RX2	= 0x01e4,
125 	B3_PA_TOVAL_TX1	= 0x01e8,
126 	B3_PA_TOVAL_TX2	= 0x01ec,
127 	B3_PA_CTRL	= 0x01f0,
128 	B3_PA_TEST	= 0x01f2,
129 };
130 
131 /*	B0_CTST			16 bit	Control/Status register */
132 enum {
133 	CS_CLK_RUN_HOT	= 1<<13,/* CLK_RUN hot m. (YUKON-Lite only) */
134 	CS_CLK_RUN_RST	= 1<<12,/* CLK_RUN reset  (YUKON-Lite only) */
135 	CS_CLK_RUN_ENA	= 1<<11,/* CLK_RUN enable (YUKON-Lite only) */
136 	CS_VAUX_AVAIL	= 1<<10,/* VAUX available (YUKON only) */
137 	CS_BUS_CLOCK	= 1<<9,	/* Bus Clock 0/1 = 33/66 MHz */
138 	CS_BUS_SLOT_SZ	= 1<<8,	/* Slot Size 0/1 = 32/64 bit slot */
139 	CS_ST_SW_IRQ	= 1<<7,	/* Set IRQ SW Request */
140 	CS_CL_SW_IRQ	= 1<<6,	/* Clear IRQ SW Request */
141 	CS_STOP_DONE	= 1<<5,	/* Stop Master is finished */
142 	CS_STOP_MAST	= 1<<4,	/* Command Bit to stop the master */
143 	CS_MRST_CLR	= 1<<3,	/* Clear Master reset	*/
144 	CS_MRST_SET	= 1<<2,	/* Set Master reset	*/
145 	CS_RST_CLR	= 1<<1,	/* Clear Software reset	*/
146 	CS_RST_SET	= 1,	/* Set   Software reset	*/
147 
148 /*	B0_LED			 8 Bit	LED register */
149 /* Bit  7.. 2:	reserved */
150 	LED_STAT_ON	= 1<<1,	/* Status LED on	*/
151 	LED_STAT_OFF	= 1,		/* Status LED off	*/
152 
153 /*	B0_POWER_CTRL	 8 Bit	Power Control reg (YUKON only) */
154 	PC_VAUX_ENA	= 1<<7,	/* Switch VAUX Enable  */
155 	PC_VAUX_DIS	= 1<<6,	/* Switch VAUX Disable */
156 	PC_VCC_ENA	= 1<<5,	/* Switch VCC Enable  */
157 	PC_VCC_DIS	= 1<<4,	/* Switch VCC Disable */
158 	PC_VAUX_ON	= 1<<3,	/* Switch VAUX On  */
159 	PC_VAUX_OFF	= 1<<2,	/* Switch VAUX Off */
160 	PC_VCC_ON	= 1<<1,	/* Switch VCC On  */
161 	PC_VCC_OFF	= 1<<0,	/* Switch VCC Off */
162 };
163 
164 /*	B2_IRQM_MSK 	32 bit	IRQ Moderation Mask */
165 enum {
166 	IS_ALL_MSK	= 0xbffffffful,	/* All Interrupt bits */
167 	IS_HW_ERR	= 1<<31,	/* Interrupt HW Error */
168 					/* Bit 30:	reserved */
169 	IS_PA_TO_RX1	= 1<<29,	/* Packet Arb Timeout Rx1 */
170 	IS_PA_TO_RX2	= 1<<28,	/* Packet Arb Timeout Rx2 */
171 	IS_PA_TO_TX1	= 1<<27,	/* Packet Arb Timeout Tx1 */
172 	IS_PA_TO_TX2	= 1<<26,	/* Packet Arb Timeout Tx2 */
173 	IS_I2C_READY	= 1<<25,	/* IRQ on end of I2C Tx */
174 	IS_IRQ_SW	= 1<<24,	/* SW forced IRQ	*/
175 	IS_EXT_REG	= 1<<23,	/* IRQ from LM80 or PHY (GENESIS only) */
176 					/* IRQ from PHY (YUKON only) */
177 	IS_TIMINT	= 1<<22,	/* IRQ from Timer	*/
178 	IS_MAC1		= 1<<21,	/* IRQ from MAC 1	*/
179 	IS_LNK_SYNC_M1	= 1<<20,	/* Link Sync Cnt wrap MAC 1 */
180 	IS_MAC2		= 1<<19,	/* IRQ from MAC 2	*/
181 	IS_LNK_SYNC_M2	= 1<<18,	/* Link Sync Cnt wrap MAC 2 */
182 /* Receive Queue 1 */
183 	IS_R1_B		= 1<<17,	/* Q_R1 End of Buffer */
184 	IS_R1_F		= 1<<16,	/* Q_R1 End of Frame */
185 	IS_R1_C		= 1<<15,	/* Q_R1 Encoding Error */
186 /* Receive Queue 2 */
187 	IS_R2_B		= 1<<14,	/* Q_R2 End of Buffer */
188 	IS_R2_F		= 1<<13,	/* Q_R2 End of Frame */
189 	IS_R2_C		= 1<<12,	/* Q_R2 Encoding Error */
190 /* Synchronous Transmit Queue 1 */
191 	IS_XS1_B	= 1<<11,	/* Q_XS1 End of Buffer */
192 	IS_XS1_F	= 1<<10,	/* Q_XS1 End of Frame */
193 	IS_XS1_C	= 1<<9,		/* Q_XS1 Encoding Error */
194 /* Asynchronous Transmit Queue 1 */
195 	IS_XA1_B	= 1<<8,		/* Q_XA1 End of Buffer */
196 	IS_XA1_F	= 1<<7,		/* Q_XA1 End of Frame */
197 	IS_XA1_C	= 1<<6,		/* Q_XA1 Encoding Error */
198 /* Synchronous Transmit Queue 2 */
199 	IS_XS2_B	= 1<<5,		/* Q_XS2 End of Buffer */
200 	IS_XS2_F	= 1<<4,		/* Q_XS2 End of Frame */
201 	IS_XS2_C	= 1<<3,		/* Q_XS2 Encoding Error */
202 /* Asynchronous Transmit Queue 2 */
203 	IS_XA2_B	= 1<<2,		/* Q_XA2 End of Buffer */
204 	IS_XA2_F	= 1<<1,		/* Q_XA2 End of Frame */
205 	IS_XA2_C	= 1<<0,		/* Q_XA2 Encoding Error */
206 
207 	IS_TO_PORT1	= IS_PA_TO_RX1 | IS_PA_TO_TX1,
208 	IS_TO_PORT2	= IS_PA_TO_RX2 | IS_PA_TO_TX2,
209 
210 	IS_PORT_1	= IS_XA1_F| IS_R1_F | IS_TO_PORT1 | IS_MAC1,
211 	IS_PORT_2	= IS_XA2_F| IS_R2_F | IS_TO_PORT2 | IS_MAC2,
212 };
213 
214 
215 /*	B2_IRQM_HWE_MSK	32 bit	IRQ Moderation HW Error Mask */
216 enum {
217 	IS_IRQ_TIST_OV	= 1<<13, /* Time Stamp Timer Overflow (YUKON only) */
218 	IS_IRQ_SENSOR	= 1<<12, /* IRQ from Sensor (YUKON only) */
219 	IS_IRQ_MST_ERR	= 1<<11, /* IRQ master error detected */
220 	IS_IRQ_STAT	= 1<<10, /* IRQ status exception */
221 	IS_NO_STAT_M1	= 1<<9,	/* No Rx Status from MAC 1 */
222 	IS_NO_STAT_M2	= 1<<8,	/* No Rx Status from MAC 2 */
223 	IS_NO_TIST_M1	= 1<<7,	/* No Time Stamp from MAC 1 */
224 	IS_NO_TIST_M2	= 1<<6,	/* No Time Stamp from MAC 2 */
225 	IS_RAM_RD_PAR	= 1<<5,	/* RAM Read  Parity Error */
226 	IS_RAM_WR_PAR	= 1<<4,	/* RAM Write Parity Error */
227 	IS_M1_PAR_ERR	= 1<<3,	/* MAC 1 Parity Error */
228 	IS_M2_PAR_ERR	= 1<<2,	/* MAC 2 Parity Error */
229 	IS_R1_PAR_ERR	= 1<<1,	/* Queue R1 Parity Error */
230 	IS_R2_PAR_ERR	= 1<<0,	/* Queue R2 Parity Error */
231 
232 	IS_ERR_MSK	= IS_IRQ_MST_ERR | IS_IRQ_STAT
233 			| IS_RAM_RD_PAR | IS_RAM_WR_PAR
234 			| IS_M1_PAR_ERR | IS_M2_PAR_ERR
235 			| IS_R1_PAR_ERR | IS_R2_PAR_ERR,
236 };
237 
238 /*	B2_TST_CTRL1	 8 bit	Test Control Register 1 */
239 enum {
240 	TST_FRC_DPERR_MR = 1<<7, /* force DATAPERR on MST RD */
241 	TST_FRC_DPERR_MW = 1<<6, /* force DATAPERR on MST WR */
242 	TST_FRC_DPERR_TR = 1<<5, /* force DATAPERR on TRG RD */
243 	TST_FRC_DPERR_TW = 1<<4, /* force DATAPERR on TRG WR */
244 	TST_FRC_APERR_M	 = 1<<3, /* force ADDRPERR on MST */
245 	TST_FRC_APERR_T	 = 1<<2, /* force ADDRPERR on TRG */
246 	TST_CFG_WRITE_ON = 1<<1, /* Enable  Config Reg WR */
247 	TST_CFG_WRITE_OFF= 1<<0, /* Disable Config Reg WR */
248 };
249 
250 /*	B2_MAC_CFG		 8 bit	MAC Configuration / Chip Revision */
251 enum {
252 	CFG_CHIP_R_MSK	  = 0xf<<4,	/* Bit 7.. 4: Chip Revision */
253 					/* Bit 3.. 2:	reserved */
254 	CFG_DIS_M2_CLK	  = 1<<1,	/* Disable Clock for 2nd MAC */
255 	CFG_SNG_MAC	  = 1<<0,	/* MAC Config: 0=2 MACs / 1=1 MAC*/
256 };
257 
258 /*	B2_CHIP_ID		 8 bit 	Chip Identification Number */
259 enum {
260 	CHIP_ID_GENESIS	   = 0x0a, /* Chip ID for GENESIS */
261 	CHIP_ID_YUKON	   = 0xb0, /* Chip ID for YUKON */
262 	CHIP_ID_YUKON_LITE = 0xb1, /* Chip ID for YUKON-Lite (Rev. A1-A3) */
263 	CHIP_ID_YUKON_LP   = 0xb2, /* Chip ID for YUKON-LP */
264 	CHIP_ID_YUKON_XL   = 0xb3, /* Chip ID for YUKON-2 XL */
265 	CHIP_ID_YUKON_EC   = 0xb6, /* Chip ID for YUKON-2 EC */
266 	CHIP_ID_YUKON_FE   = 0xb7, /* Chip ID for YUKON-2 FE */
267 
268 	CHIP_REV_YU_LITE_A1  = 3,	/* Chip Rev. for YUKON-Lite A1,A2 */
269 	CHIP_REV_YU_LITE_A3  = 7,	/* Chip Rev. for YUKON-Lite A3 */
270 };
271 
272 /*	B2_TI_CTRL		 8 bit	Timer control */
273 /*	B2_IRQM_CTRL	 8 bit	IRQ Moderation Timer Control */
274 enum {
275 	TIM_START	= 1<<2,	/* Start Timer */
276 	TIM_STOP	= 1<<1,	/* Stop  Timer */
277 	TIM_CLR_IRQ	= 1<<0,	/* Clear Timer IRQ (!IRQM) */
278 };
279 
280 /*	B2_TI_TEST		 8 Bit	Timer Test */
281 /*	B2_IRQM_TEST	 8 bit	IRQ Moderation Timer Test */
282 /*	B28_DPT_TST		 8 bit	Descriptor Poll Timer Test Reg */
283 enum {
284 	TIM_T_ON	= 1<<2,	/* Test mode on */
285 	TIM_T_OFF	= 1<<1,	/* Test mode off */
286 	TIM_T_STEP	= 1<<0,	/* Test step */
287 };
288 
289 /*	B2_GP_IO		32 bit	General Purpose I/O Register */
290 enum {
291 	GP_DIR_9 = 1<<25, /* IO_9 direct, 0=In/1=Out */
292 	GP_DIR_8 = 1<<24, /* IO_8 direct, 0=In/1=Out */
293 	GP_DIR_7 = 1<<23, /* IO_7 direct, 0=In/1=Out */
294 	GP_DIR_6 = 1<<22, /* IO_6 direct, 0=In/1=Out */
295 	GP_DIR_5 = 1<<21, /* IO_5 direct, 0=In/1=Out */
296 	GP_DIR_4 = 1<<20, /* IO_4 direct, 0=In/1=Out */
297 	GP_DIR_3 = 1<<19, /* IO_3 direct, 0=In/1=Out */
298 	GP_DIR_2 = 1<<18, /* IO_2 direct, 0=In/1=Out */
299 	GP_DIR_1 = 1<<17, /* IO_1 direct, 0=In/1=Out */
300 	GP_DIR_0 = 1<<16, /* IO_0 direct, 0=In/1=Out */
301 
302 	GP_IO_9	= 1<<9,	/* IO_9 pin */
303 	GP_IO_8	= 1<<8,	/* IO_8 pin */
304 	GP_IO_7	= 1<<7,	/* IO_7 pin */
305 	GP_IO_6	= 1<<6,	/* IO_6 pin */
306 	GP_IO_5	= 1<<5,	/* IO_5 pin */
307 	GP_IO_4	= 1<<4,	/* IO_4 pin */
308 	GP_IO_3	= 1<<3,	/* IO_3 pin */
309 	GP_IO_2	= 1<<2,	/* IO_2 pin */
310 	GP_IO_1	= 1<<1,	/* IO_1 pin */
311 	GP_IO_0	= 1<<0,	/* IO_0 pin */
312 };
313 
314 /* Descriptor Bit Definition */
315 /*	TxCtrl		Transmit Buffer Control Field */
316 /*	RxCtrl		Receive  Buffer Control Field */
317 enum {
318 	BMU_OWN		= 1<<31, /* OWN bit: 0=host/1=BMU */
319 	BMU_STF		= 1<<30, /* Start of Frame */
320 	BMU_EOF		= 1<<29, /* End of Frame */
321 	BMU_IRQ_EOB	= 1<<28, /* Req "End of Buffer" IRQ */
322 	BMU_IRQ_EOF	= 1<<27, /* Req "End of Frame" IRQ */
323 				/* TxCtrl specific bits */
324 	BMU_STFWD	= 1<<26, /* (Tx)	Store & Forward Frame */
325 	BMU_NO_FCS	= 1<<25, /* (Tx) Disable MAC FCS (CRC) generation */
326 	BMU_SW	= 1<<24, /* (Tx)	1 bit res. for SW use */
327 				/* RxCtrl specific bits */
328 	BMU_DEV_0	= 1<<26, /* (Rx)	Transfer data to Dev0 */
329 	BMU_STAT_VAL	= 1<<25, /* (Rx)	Rx Status Valid */
330 	BMU_TIST_VAL	= 1<<24, /* (Rx)	Rx TimeStamp Valid */
331 			/* Bit 23..16:	BMU Check Opcodes */
332 	BMU_CHECK	= 0x55<<16, /* Default BMU check */
333 	BMU_TCP_CHECK	= 0x56<<16, /* Descr with TCP ext */
334 	BMU_UDP_CHECK	= 0x57<<16, /* Descr with UDP ext (YUKON only) */
335 	BMU_BBC		= 0xffffL, /* Bit 15.. 0:	Buffer Byte Counter */
336 };
337 
338 /*	B2_BSC_CTRL		 8 bit	Blink Source Counter Control */
339 enum {
340 	 BSC_START	= 1<<1,	/* Start Blink Source Counter */
341 	 BSC_STOP	= 1<<0,	/* Stop  Blink Source Counter */
342 };
343 
344 /*	B2_BSC_STAT		 8 bit	Blink Source Counter Status */
345 enum {
346 	BSC_SRC		= 1<<0,	/* Blink Source, 0=Off / 1=On */
347 };
348 
349 /*	B2_BSC_TST		16 bit	Blink Source Counter Test Reg */
350 enum {
351 	BSC_T_ON	= 1<<2,	/* Test mode on */
352 	BSC_T_OFF	= 1<<1,	/* Test mode off */
353 	BSC_T_STEP	= 1<<0,	/* Test step */
354 };
355 
356 /*	B3_RAM_ADDR		32 bit	RAM Address, to read or write */
357 					/* Bit 31..19:	reserved */
358 #define RAM_ADR_RAN	0x0007ffffL	/* Bit 18.. 0:	RAM Address Range */
359 /* RAM Interface Registers */
360 
361 /*	B3_RI_CTRL		16 bit	RAM Iface Control Register */
362 enum {
363 	RI_CLR_RD_PERR	= 1<<9,	/* Clear IRQ RAM Read Parity Err */
364 	RI_CLR_WR_PERR	= 1<<8,	/* Clear IRQ RAM Write Parity Err*/
365 
366 	RI_RST_CLR	= 1<<1,	/* Clear RAM Interface Reset */
367 	RI_RST_SET	= 1<<0,	/* Set   RAM Interface Reset */
368 };
369 
370 /* MAC Arbiter Registers */
371 /*	B3_MA_TO_CTRL	16 bit	MAC Arbiter Timeout Ctrl Reg */
372 enum {
373 	MA_FOE_ON	= 1<<3,	/* XMAC Fast Output Enable ON */
374 	MA_FOE_OFF	= 1<<2,	/* XMAC Fast Output Enable OFF */
375 	MA_RST_CLR	= 1<<1,	/* Clear MAC Arbiter Reset */
376 	MA_RST_SET	= 1<<0,	/* Set   MAC Arbiter Reset */
377 
378 };
379 
380 /* Timeout values */
381 #define SK_MAC_TO_53	72		/* MAC arbiter timeout */
382 #define SK_PKT_TO_53	0x2000		/* Packet arbiter timeout */
383 #define SK_PKT_TO_MAX	0xffff		/* Maximum value */
384 #define SK_RI_TO_53	36		/* RAM interface timeout */
385 
386 /* Packet Arbiter Registers */
387 /*	B3_PA_CTRL		16 bit	Packet Arbiter Ctrl Register */
388 enum {
389 	PA_CLR_TO_TX2	= 1<<13,/* Clear IRQ Packet Timeout TX2 */
390 	PA_CLR_TO_TX1	= 1<<12,/* Clear IRQ Packet Timeout TX1 */
391 	PA_CLR_TO_RX2	= 1<<11,/* Clear IRQ Packet Timeout RX2 */
392 	PA_CLR_TO_RX1	= 1<<10,/* Clear IRQ Packet Timeout RX1 */
393 	PA_ENA_TO_TX2	= 1<<9,	/* Enable  Timeout Timer TX2 */
394 	PA_DIS_TO_TX2	= 1<<8,	/* Disable Timeout Timer TX2 */
395 	PA_ENA_TO_TX1	= 1<<7,	/* Enable  Timeout Timer TX1 */
396 	PA_DIS_TO_TX1	= 1<<6,	/* Disable Timeout Timer TX1 */
397 	PA_ENA_TO_RX2	= 1<<5,	/* Enable  Timeout Timer RX2 */
398 	PA_DIS_TO_RX2	= 1<<4,	/* Disable Timeout Timer RX2 */
399 	PA_ENA_TO_RX1	= 1<<3,	/* Enable  Timeout Timer RX1 */
400 	PA_DIS_TO_RX1	= 1<<2,	/* Disable Timeout Timer RX1 */
401 	PA_RST_CLR	= 1<<1,	/* Clear MAC Arbiter Reset */
402 	PA_RST_SET	= 1<<0,	/* Set   MAC Arbiter Reset */
403 };
404 
405 #define PA_ENA_TO_ALL	(PA_ENA_TO_RX1 | PA_ENA_TO_RX2 |\
406 						PA_ENA_TO_TX1 | PA_ENA_TO_TX2)
407 
408 
409 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
410 /*	TXA_ITI_INI		32 bit	Tx Arb Interval Timer Init Val */
411 /*	TXA_ITI_VAL		32 bit	Tx Arb Interval Timer Value */
412 /*	TXA_LIM_INI		32 bit	Tx Arb Limit Counter Init Val */
413 /*	TXA_LIM_VAL		32 bit	Tx Arb Limit Counter Value */
414 
415 #define TXA_MAX_VAL	0x00ffffffUL	/* Bit 23.. 0:	Max TXA Timer/Cnt Val */
416 
417 /*	TXA_CTRL		 8 bit	Tx Arbiter Control Register */
418 enum {
419 	TXA_ENA_FSYNC	= 1<<7,	/* Enable  force of sync Tx queue */
420 	TXA_DIS_FSYNC	= 1<<6,	/* Disable force of sync Tx queue */
421 	TXA_ENA_ALLOC	= 1<<5,	/* Enable  alloc of free bandwidth */
422 	TXA_DIS_ALLOC	= 1<<4,	/* Disable alloc of free bandwidth */
423 	TXA_START_RC	= 1<<3,	/* Start sync Rate Control */
424 	TXA_STOP_RC	= 1<<2,	/* Stop  sync Rate Control */
425 	TXA_ENA_ARB	= 1<<1,	/* Enable  Tx Arbiter */
426 	TXA_DIS_ARB	= 1<<0,	/* Disable Tx Arbiter */
427 };
428 
429 /*
430  *	Bank 4 - 5
431  */
432 /* Transmit Arbiter Registers MAC 1 and 2, use SK_REG() to access */
433 enum {
434 	TXA_ITI_INI	= 0x0200,/* 32 bit	Tx Arb Interval Timer Init Val*/
435 	TXA_ITI_VAL	= 0x0204,/* 32 bit	Tx Arb Interval Timer Value */
436 	TXA_LIM_INI	= 0x0208,/* 32 bit	Tx Arb Limit Counter Init Val */
437 	TXA_LIM_VAL	= 0x020c,/* 32 bit	Tx Arb Limit Counter Value */
438 	TXA_CTRL	= 0x0210,/*  8 bit	Tx Arbiter Control Register */
439 	TXA_TEST	= 0x0211,/*  8 bit	Tx Arbiter Test Register */
440 	TXA_STAT	= 0x0212,/*  8 bit	Tx Arbiter Status Register */
441 };
442 
443 
444 enum {
445 	B6_EXT_REG	= 0x0300,/* External registers (GENESIS only) */
446 	B7_CFG_SPC	= 0x0380,/* copy of the Configuration register */
447 	B8_RQ1_REGS	= 0x0400,/* Receive Queue 1 */
448 	B8_RQ2_REGS	= 0x0480,/* Receive Queue 2 */
449 	B8_TS1_REGS	= 0x0600,/* Transmit sync queue 1 */
450 	B8_TA1_REGS	= 0x0680,/* Transmit async queue 1 */
451 	B8_TS2_REGS	= 0x0700,/* Transmit sync queue 2 */
452 	B8_TA2_REGS	= 0x0780,/* Transmit sync queue 2 */
453 	B16_RAM_REGS	= 0x0800,/* RAM Buffer Registers */
454 };
455 
456 /* Queue Register Offsets, use Q_ADDR() to access */
457 enum {
458 	B8_Q_REGS = 0x0400, /* base of Queue registers */
459 	Q_D	= 0x00,	/* 8*32	bit	Current Descriptor */
460 	Q_DA_L	= 0x20,	/* 32 bit	Current Descriptor Address Low dWord */
461 	Q_DA_H	= 0x24,	/* 32 bit	Current Descriptor Address High dWord */
462 	Q_AC_L	= 0x28,	/* 32 bit	Current Address Counter Low dWord */
463 	Q_AC_H	= 0x2c,	/* 32 bit	Current Address Counter High dWord */
464 	Q_BC	= 0x30,	/* 32 bit	Current Byte Counter */
465 	Q_CSR	= 0x34,	/* 32 bit	BMU Control/Status Register */
466 	Q_F	= 0x38,	/* 32 bit	Flag Register */
467 	Q_T1	= 0x3c,	/* 32 bit	Test Register 1 */
468 	Q_T1_TR	= 0x3c,	/*  8 bit	Test Register 1 Transfer SM */
469 	Q_T1_WR	= 0x3d,	/*  8 bit	Test Register 1 Write Descriptor SM */
470 	Q_T1_RD	= 0x3e,	/*  8 bit	Test Register 1 Read Descriptor SM */
471 	Q_T1_SV	= 0x3f,	/*  8 bit	Test Register 1 Supervisor SM */
472 	Q_T2	= 0x40,	/* 32 bit	Test Register 2	*/
473 	Q_T3	= 0x44,	/* 32 bit	Test Register 3	*/
474 
475 };
476 #define Q_ADDR(reg, offs) (B8_Q_REGS + (reg) + (offs))
477 
478 /* RAM Buffer Register Offsets */
479 enum {
480 
481 	RB_START= 0x00,/* 32 bit	RAM Buffer Start Address */
482 	RB_END	= 0x04,/* 32 bit	RAM Buffer End Address */
483 	RB_WP	= 0x08,/* 32 bit	RAM Buffer Write Pointer */
484 	RB_RP	= 0x0c,/* 32 bit	RAM Buffer Read Pointer */
485 	RB_RX_UTPP= 0x10,/* 32 bit	Rx Upper Threshold, Pause Packet */
486 	RB_RX_LTPP= 0x14,/* 32 bit	Rx Lower Threshold, Pause Packet */
487 	RB_RX_UTHP= 0x18,/* 32 bit	Rx Upper Threshold, High Prio */
488 	RB_RX_LTHP= 0x1c,/* 32 bit	Rx Lower Threshold, High Prio */
489 	/* 0x10 - 0x1f:	reserved at Tx RAM Buffer Registers */
490 	RB_PC	= 0x20,/* 32 bit	RAM Buffer Packet Counter */
491 	RB_LEV	= 0x24,/* 32 bit	RAM Buffer Level Register */
492 	RB_CTRL	= 0x28,/* 32 bit	RAM Buffer Control Register */
493 	RB_TST1	= 0x29,/*  8 bit	RAM Buffer Test Register 1 */
494 	RB_TST2	= 0x2a,/*  8 bit	RAM Buffer Test Register 2 */
495 };
496 
497 /* Receive and Transmit Queues */
498 enum {
499 	Q_R1	= 0x0000,	/* Receive Queue 1 */
500 	Q_R2	= 0x0080,	/* Receive Queue 2 */
501 	Q_XS1	= 0x0200,	/* Synchronous Transmit Queue 1 */
502 	Q_XA1	= 0x0280,	/* Asynchronous Transmit Queue 1 */
503 	Q_XS2	= 0x0300,	/* Synchronous Transmit Queue 2 */
504 	Q_XA2	= 0x0380,	/* Asynchronous Transmit Queue 2 */
505 };
506 
507 /* Different MAC Types */
508 enum {
509 	SK_MAC_XMAC =	0,	/* Xaqti XMAC II */
510 	SK_MAC_GMAC =	1,	/* Marvell GMAC */
511 };
512 
513 /* Different PHY Types */
514 enum {
515 	SK_PHY_XMAC	= 0,/* integrated in XMAC II */
516 	SK_PHY_BCOM	= 1,/* Broadcom BCM5400 */
517 	SK_PHY_LONE	= 2,/* Level One LXT1000  [not supported]*/
518 	SK_PHY_NAT	= 3,/* National DP83891  [not supported] */
519 	SK_PHY_MARV_COPPER= 4,/* Marvell 88E1011S */
520 	SK_PHY_MARV_FIBER = 5,/* Marvell 88E1011S working on fiber */
521 };
522 
523 /* PHY addresses (bits 12..8 of PHY address reg) */
524 enum {
525 	PHY_ADDR_XMAC	= 0<<8,
526 	PHY_ADDR_BCOM	= 1<<8,
527 
528 /* GPHY address (bits 15..11 of SMI control reg) */
529 	PHY_ADDR_MARV	= 0,
530 };
531 
532 #define RB_ADDR(offs, queue) ((u16)B16_RAM_REGS + (u16)(queue) + (offs))
533 
534 /* Receive MAC FIFO, Receive LED, and Link_Sync regs (GENESIS only) */
535 enum {
536 	RX_MFF_EA	= 0x0c00,/* 32 bit	Receive MAC FIFO End Address */
537 	RX_MFF_WP	= 0x0c04,/* 32 bit	Receive MAC FIFO Write Pointer */
538 
539 	RX_MFF_RP	= 0x0c0c,/* 32 bit	Receive MAC FIFO Read Pointer */
540 	RX_MFF_PC	= 0x0c10,/* 32 bit	Receive MAC FIFO Packet Cnt */
541 	RX_MFF_LEV	= 0x0c14,/* 32 bit	Receive MAC FIFO Level */
542 	RX_MFF_CTRL1	= 0x0c18,/* 16 bit	Receive MAC FIFO Control Reg 1*/
543 	RX_MFF_STAT_TO	= 0x0c1a,/*  8 bit	Receive MAC Status Timeout */
544 	RX_MFF_TIST_TO	= 0x0c1b,/*  8 bit	Receive MAC Time Stamp Timeout */
545 	RX_MFF_CTRL2	= 0x0c1c,/*  8 bit	Receive MAC FIFO Control Reg 2*/
546 	RX_MFF_TST1	= 0x0c1d,/*  8 bit	Receive MAC FIFO Test Reg 1 */
547 	RX_MFF_TST2	= 0x0c1e,/*  8 bit	Receive MAC FIFO Test Reg 2 */
548 
549 	RX_LED_INI	= 0x0c20,/* 32 bit	Receive LED Cnt Init Value */
550 	RX_LED_VAL	= 0x0c24,/* 32 bit	Receive LED Cnt Current Value */
551 	RX_LED_CTRL	= 0x0c28,/*  8 bit	Receive LED Cnt Control Reg */
552 	RX_LED_TST	= 0x0c29,/*  8 bit	Receive LED Cnt Test Register */
553 
554 	LNK_SYNC_INI	= 0x0c30,/* 32 bit	Link Sync Cnt Init Value */
555 	LNK_SYNC_VAL	= 0x0c34,/* 32 bit	Link Sync Cnt Current Value */
556 	LNK_SYNC_CTRL	= 0x0c38,/*  8 bit	Link Sync Cnt Control Register */
557 	LNK_SYNC_TST	= 0x0c39,/*  8 bit	Link Sync Cnt Test Register */
558 	LNK_LED_REG	= 0x0c3c,/*  8 bit	Link LED Register */
559 };
560 
561 /* Receive and Transmit MAC FIFO Registers (GENESIS only) */
562 /*	RX_MFF_CTRL1	16 bit	Receive MAC FIFO Control Reg 1 */
563 enum {
564 	MFF_ENA_RDY_PAT	= 1<<13,	/* Enable  Ready Patch */
565 	MFF_DIS_RDY_PAT	= 1<<12,	/* Disable Ready Patch */
566 	MFF_ENA_TIM_PAT	= 1<<11,	/* Enable  Timing Patch */
567 	MFF_DIS_TIM_PAT	= 1<<10,	/* Disable Timing Patch */
568 	MFF_ENA_ALM_FUL	= 1<<9,	/* Enable  AlmostFull Sign */
569 	MFF_DIS_ALM_FUL	= 1<<8,	/* Disable AlmostFull Sign */
570 	MFF_ENA_PAUSE	= 1<<7,	/* Enable  Pause Signaling */
571 	MFF_DIS_PAUSE	= 1<<6,	/* Disable Pause Signaling */
572 	MFF_ENA_FLUSH	= 1<<5,	/* Enable  Frame Flushing */
573 	MFF_DIS_FLUSH	= 1<<4,	/* Disable Frame Flushing */
574 	MFF_ENA_TIST	= 1<<3,	/* Enable  Time Stamp Gener */
575 	MFF_DIS_TIST	= 1<<2,	/* Disable Time Stamp Gener */
576 	MFF_CLR_INTIST	= 1<<1,	/* Clear IRQ No Time Stamp */
577 	MFF_CLR_INSTAT	= 1<<0,	/* Clear IRQ No Status */
578 	MFF_RX_CTRL_DEF = MFF_ENA_TIM_PAT,
579 };
580 
581 /*	TX_MFF_CTRL1	16 bit	Transmit MAC FIFO Control Reg 1 */
582 enum {
583 	MFF_CLR_PERR	= 1<<15, /* Clear Parity Error IRQ */
584 
585 	MFF_ENA_PKT_REC	= 1<<13, /* Enable  Packet Recovery */
586 	MFF_DIS_PKT_REC	= 1<<12, /* Disable Packet Recovery */
587 
588 	MFF_ENA_W4E	= 1<<7,	/* Enable  Wait for Empty */
589 	MFF_DIS_W4E	= 1<<6,	/* Disable Wait for Empty */
590 
591 	MFF_ENA_LOOPB	= 1<<3,	/* Enable  Loopback */
592 	MFF_DIS_LOOPB	= 1<<2,	/* Disable Loopback */
593 	MFF_CLR_MAC_RST	= 1<<1,	/* Clear XMAC Reset */
594 	MFF_SET_MAC_RST	= 1<<0,	/* Set   XMAC Reset */
595 
596 	MFF_TX_CTRL_DEF	 = MFF_ENA_PKT_REC | (u16) MFF_ENA_TIM_PAT | MFF_ENA_FLUSH,
597 };
598 
599 
600 /*	RX_MFF_TST2	 	 8 bit	Receive MAC FIFO Test Register 2 */
601 /*	TX_MFF_TST2	 	 8 bit	Transmit MAC FIFO Test Register 2 */
602 enum {
603 	MFF_WSP_T_ON	= 1<<6,	/* Tx: Write Shadow Ptr TestOn */
604 	MFF_WSP_T_OFF	= 1<<5,	/* Tx: Write Shadow Ptr TstOff */
605 	MFF_WSP_INC	= 1<<4,	/* Tx: Write Shadow Ptr Increment */
606 	MFF_PC_DEC	= 1<<3,	/* Packet Counter Decrement */
607 	MFF_PC_T_ON	= 1<<2,	/* Packet Counter Test On */
608 	MFF_PC_T_OFF	= 1<<1,	/* Packet Counter Test Off */
609 	MFF_PC_INC	= 1<<0,	/* Packet Counter Increment */
610 };
611 
612 /*	RX_MFF_TST1	 	 8 bit	Receive MAC FIFO Test Register 1 */
613 /*	TX_MFF_TST1	 	 8 bit	Transmit MAC FIFO Test Register 1 */
614 enum {
615 	MFF_WP_T_ON	= 1<<6,	/* Write Pointer Test On */
616 	MFF_WP_T_OFF	= 1<<5,	/* Write Pointer Test Off */
617 	MFF_WP_INC	= 1<<4,	/* Write Pointer Increm */
618 
619 	MFF_RP_T_ON	= 1<<2,	/* Read Pointer Test On */
620 	MFF_RP_T_OFF	= 1<<1,	/* Read Pointer Test Off */
621 	MFF_RP_DEC	= 1<<0,	/* Read Pointer Decrement */
622 };
623 
624 /*	RX_MFF_CTRL2	 8 bit	Receive MAC FIFO Control Reg 2 */
625 /*	TX_MFF_CTRL2	 8 bit	Transmit MAC FIFO Control Reg 2 */
626 enum {
627 	MFF_ENA_OP_MD	= 1<<3,	/* Enable  Operation Mode */
628 	MFF_DIS_OP_MD	= 1<<2,	/* Disable Operation Mode */
629 	MFF_RST_CLR	= 1<<1,	/* Clear MAC FIFO Reset */
630 	MFF_RST_SET	= 1<<0,	/* Set   MAC FIFO Reset */
631 };
632 
633 
634 /*	Link LED Counter Registers (GENESIS only) */
635 
636 /*	RX_LED_CTRL		 8 bit	Receive LED Cnt Control Reg */
637 /*	TX_LED_CTRL		 8 bit	Transmit LED Cnt Control Reg */
638 /*	LNK_SYNC_CTRL	 8 bit	Link Sync Cnt Control Register */
639 enum {
640 	LED_START	= 1<<2,	/* Start Timer */
641 	LED_STOP	= 1<<1,	/* Stop Timer */
642 	LED_STATE	= 1<<0,	/* Rx/Tx: LED State, 1=LED on */
643 };
644 
645 /*	RX_LED_TST		 8 bit	Receive LED Cnt Test Register */
646 /*	TX_LED_TST		 8 bit	Transmit LED Cnt Test Register */
647 /*	LNK_SYNC_TST	 8 bit	Link Sync Cnt Test Register */
648 enum {
649 	LED_T_ON	= 1<<2,	/* LED Counter Test mode On */
650 	LED_T_OFF	= 1<<1,	/* LED Counter Test mode Off */
651 	LED_T_STEP	= 1<<0,	/* LED Counter Step */
652 };
653 
654 /*	LNK_LED_REG	 	 8 bit	Link LED Register */
655 enum {
656 	LED_BLK_ON	= 1<<5,	/* Link LED Blinking On */
657 	LED_BLK_OFF	= 1<<4,	/* Link LED Blinking Off */
658 	LED_SYNC_ON	= 1<<3,	/* Use Sync Wire to switch LED */
659 	LED_SYNC_OFF	= 1<<2,	/* Disable Sync Wire Input */
660 	LED_REG_ON	= 1<<1,	/* switch LED on */
661 	LED_REG_OFF	= 1<<0,	/* switch LED off */
662 };
663 
664 /* Receive GMAC FIFO (YUKON) */
665 enum {
666 	RX_GMF_EA	= 0x0c40,/* 32 bit	Rx GMAC FIFO End Address */
667 	RX_GMF_AF_THR	= 0x0c44,/* 32 bit	Rx GMAC FIFO Almost Full Thresh. */
668 	RX_GMF_CTRL_T	= 0x0c48,/* 32 bit	Rx GMAC FIFO Control/Test */
669 	RX_GMF_FL_MSK	= 0x0c4c,/* 32 bit	Rx GMAC FIFO Flush Mask */
670 	RX_GMF_FL_THR	= 0x0c50,/* 32 bit	Rx GMAC FIFO Flush Threshold */
671 	RX_GMF_WP	= 0x0c60,/* 32 bit	Rx GMAC FIFO Write Pointer */
672 	RX_GMF_WLEV	= 0x0c68,/* 32 bit	Rx GMAC FIFO Write Level */
673 	RX_GMF_RP	= 0x0c70,/* 32 bit	Rx GMAC FIFO Read Pointer */
674 	RX_GMF_RLEV	= 0x0c78,/* 32 bit	Rx GMAC FIFO Read Level */
675 };
676 
677 
678 /*	TXA_TEST		 8 bit	Tx Arbiter Test Register */
679 enum {
680 	TXA_INT_T_ON	= 1<<5,	/* Tx Arb Interval Timer Test On */
681 	TXA_INT_T_OFF	= 1<<4,	/* Tx Arb Interval Timer Test Off */
682 	TXA_INT_T_STEP	= 1<<3,	/* Tx Arb Interval Timer Step */
683 	TXA_LIM_T_ON	= 1<<2,	/* Tx Arb Limit Timer Test On */
684 	TXA_LIM_T_OFF	= 1<<1,	/* Tx Arb Limit Timer Test Off */
685 	TXA_LIM_T_STEP	= 1<<0,	/* Tx Arb Limit Timer Step */
686 };
687 
688 /*	TXA_STAT		 8 bit	Tx Arbiter Status Register */
689 enum {
690 	TXA_PRIO_XS	= 1<<0,	/* sync queue has prio to send */
691 };
692 
693 
694 /*	Q_BC			32 bit	Current Byte Counter */
695 
696 /* BMU Control Status Registers */
697 /*	B0_R1_CSR		32 bit	BMU Ctrl/Stat Rx Queue 1 */
698 /*	B0_R2_CSR		32 bit	BMU Ctrl/Stat Rx Queue 2 */
699 /*	B0_XA1_CSR		32 bit	BMU Ctrl/Stat Sync Tx Queue 1 */
700 /*	B0_XS1_CSR		32 bit	BMU Ctrl/Stat Async Tx Queue 1 */
701 /*	B0_XA2_CSR		32 bit	BMU Ctrl/Stat Sync Tx Queue 2 */
702 /*	B0_XS2_CSR		32 bit	BMU Ctrl/Stat Async Tx Queue 2 */
703 /*	Q_CSR			32 bit	BMU Control/Status Register */
704 
705 enum {
706 	CSR_SV_IDLE	= 1<<24,	/* BMU SM Idle */
707 
708 	CSR_DESC_CLR	= 1<<21,	/* Clear Reset for Descr */
709 	CSR_DESC_SET	= 1<<20,	/* Set   Reset for Descr */
710 	CSR_FIFO_CLR	= 1<<19,	/* Clear Reset for FIFO */
711 	CSR_FIFO_SET	= 1<<18,	/* Set   Reset for FIFO */
712 	CSR_HPI_RUN	= 1<<17,	/* Release HPI SM */
713 	CSR_HPI_RST	= 1<<16,	/* Reset   HPI SM to Idle */
714 	CSR_SV_RUN	= 1<<15,	/* Release Supervisor SM */
715 	CSR_SV_RST	= 1<<14,	/* Reset   Supervisor SM */
716 	CSR_DREAD_RUN	= 1<<13,	/* Release Descr Read SM */
717 	CSR_DREAD_RST	= 1<<12,	/* Reset   Descr Read SM */
718 	CSR_DWRITE_RUN	= 1<<11,	/* Release Descr Write SM */
719 	CSR_DWRITE_RST	= 1<<10,	/* Reset   Descr Write SM */
720 	CSR_TRANS_RUN	= 1<<9,		/* Release Transfer SM */
721 	CSR_TRANS_RST	= 1<<8,		/* Reset   Transfer SM */
722 	CSR_ENA_POL	= 1<<7,		/* Enable  Descr Polling */
723 	CSR_DIS_POL	= 1<<6,		/* Disable Descr Polling */
724 	CSR_STOP	= 1<<5,		/* Stop  Rx/Tx Queue */
725 	CSR_START	= 1<<4,		/* Start Rx/Tx Queue */
726 	CSR_IRQ_CL_P	= 1<<3,		/* (Rx)	Clear Parity IRQ */
727 	CSR_IRQ_CL_B	= 1<<2,		/* Clear EOB IRQ */
728 	CSR_IRQ_CL_F	= 1<<1,		/* Clear EOF IRQ */
729 	CSR_IRQ_CL_C	= 1<<0,		/* Clear ERR IRQ */
730 };
731 
732 #define CSR_SET_RESET	(CSR_DESC_SET | CSR_FIFO_SET | CSR_HPI_RST |\
733 			CSR_SV_RST | CSR_DREAD_RST | CSR_DWRITE_RST |\
734 			CSR_TRANS_RST)
735 #define CSR_CLR_RESET	(CSR_DESC_CLR | CSR_FIFO_CLR | CSR_HPI_RUN |\
736 			CSR_SV_RUN | CSR_DREAD_RUN | CSR_DWRITE_RUN |\
737 			CSR_TRANS_RUN)
738 
739 /*	Q_F				32 bit	Flag Register */
740 enum {
741 	F_ALM_FULL	= 1<<27,	/* Rx FIFO: almost full */
742 	F_EMPTY		= 1<<27,	/* Tx FIFO: empty flag */
743 	F_FIFO_EOF	= 1<<26,	/* Tag (EOF Flag) bit in FIFO */
744 	F_WM_REACHED	= 1<<25,	/* Watermark reached */
745 
746 	F_FIFO_LEVEL	= 0x1fL<<16,	/* Bit 23..16:	# of Qwords in FIFO */
747 	F_WATER_MARK	= 0x0007ffL,	/* Bit 10.. 0:	Watermark */
748 };
749 
750 /* RAM Buffer Register Offsets, use RB_ADDR(Queue, Offs) to access */
751 /*	RB_START		32 bit	RAM Buffer Start Address */
752 /*	RB_END			32 bit	RAM Buffer End Address */
753 /*	RB_WP			32 bit	RAM Buffer Write Pointer */
754 /*	RB_RP			32 bit	RAM Buffer Read Pointer */
755 /*	RB_RX_UTPP		32 bit	Rx Upper Threshold, Pause Pack */
756 /*	RB_RX_LTPP		32 bit	Rx Lower Threshold, Pause Pack */
757 /*	RB_RX_UTHP		32 bit	Rx Upper Threshold, High Prio */
758 /*	RB_RX_LTHP		32 bit	Rx Lower Threshold, High Prio */
759 /*	RB_PC			32 bit	RAM Buffer Packet Counter */
760 /*	RB_LEV			32 bit	RAM Buffer Level Register */
761 
762 #define RB_MSK	0x0007ffff	/* Bit 18.. 0:	RAM Buffer Pointer Bits */
763 /*	RB_TST2			 8 bit	RAM Buffer Test Register 2 */
764 /*	RB_TST1			 8 bit	RAM Buffer Test Register 1 */
765 
766 /*	RB_CTRL			 8 bit	RAM Buffer Control Register */
767 enum {
768 	RB_ENA_STFWD	= 1<<5,	/* Enable  Store & Forward */
769 	RB_DIS_STFWD	= 1<<4,	/* Disable Store & Forward */
770 	RB_ENA_OP_MD	= 1<<3,	/* Enable  Operation Mode */
771 	RB_DIS_OP_MD	= 1<<2,	/* Disable Operation Mode */
772 	RB_RST_CLR	= 1<<1,	/* Clear RAM Buf STM Reset */
773 	RB_RST_SET	= 1<<0,	/* Set   RAM Buf STM Reset */
774 };
775 
776 /* Transmit MAC FIFO and Transmit LED Registers (GENESIS only), */
777 enum {
778 	TX_MFF_EA	= 0x0d00,/* 32 bit	Transmit MAC FIFO End Address */
779 	TX_MFF_WP	= 0x0d04,/* 32 bit	Transmit MAC FIFO WR Pointer */
780 	TX_MFF_WSP	= 0x0d08,/* 32 bit	Transmit MAC FIFO WR Shadow Ptr */
781 	TX_MFF_RP	= 0x0d0c,/* 32 bit	Transmit MAC FIFO RD Pointer */
782 	TX_MFF_PC	= 0x0d10,/* 32 bit	Transmit MAC FIFO Packet Cnt */
783 	TX_MFF_LEV	= 0x0d14,/* 32 bit	Transmit MAC FIFO Level */
784 	TX_MFF_CTRL1	= 0x0d18,/* 16 bit	Transmit MAC FIFO Ctrl Reg 1 */
785 	TX_MFF_WAF	= 0x0d1a,/*  8 bit	Transmit MAC Wait after flush */
786 
787 	TX_MFF_CTRL2	= 0x0d1c,/*  8 bit	Transmit MAC FIFO Ctrl Reg 2 */
788 	TX_MFF_TST1	= 0x0d1d,/*  8 bit	Transmit MAC FIFO Test Reg 1 */
789 	TX_MFF_TST2	= 0x0d1e,/*  8 bit	Transmit MAC FIFO Test Reg 2 */
790 
791 	TX_LED_INI	= 0x0d20,/* 32 bit	Transmit LED Cnt Init Value */
792 	TX_LED_VAL	= 0x0d24,/* 32 bit	Transmit LED Cnt Current Val */
793 	TX_LED_CTRL	= 0x0d28,/*  8 bit	Transmit LED Cnt Control Reg */
794 	TX_LED_TST	= 0x0d29,/*  8 bit	Transmit LED Cnt Test Reg */
795 };
796 
797 /* Counter and Timer constants, for a host clock of 62.5 MHz */
798 #define SK_XMIT_DUR		0x002faf08UL	/*  50 ms */
799 #define SK_BLK_DUR		0x01dcd650UL	/* 500 ms */
800 
801 #define SK_DPOLL_DEF	0x00ee6b28UL	/* 250 ms at 62.5 MHz */
802 
803 #define SK_DPOLL_MAX	0x00ffffffUL	/* 268 ms at 62.5 MHz */
804 					/* 215 ms at 78.12 MHz */
805 
806 #define SK_FACT_62		100	/* is given in percent */
807 #define SK_FACT_53		 85     /* on GENESIS:	53.12 MHz */
808 #define SK_FACT_78		125	/* on YUKON:	78.12 MHz */
809 
810 
811 /* Transmit GMAC FIFO (YUKON only) */
812 enum {
813 	TX_GMF_EA	= 0x0d40,/* 32 bit	Tx GMAC FIFO End Address */
814 	TX_GMF_AE_THR	= 0x0d44,/* 32 bit	Tx GMAC FIFO Almost Empty Thresh.*/
815 	TX_GMF_CTRL_T	= 0x0d48,/* 32 bit	Tx GMAC FIFO Control/Test */
816 
817 	TX_GMF_WP	= 0x0d60,/* 32 bit 	Tx GMAC FIFO Write Pointer */
818 	TX_GMF_WSP	= 0x0d64,/* 32 bit 	Tx GMAC FIFO Write Shadow Ptr. */
819 	TX_GMF_WLEV	= 0x0d68,/* 32 bit 	Tx GMAC FIFO Write Level */
820 
821 	TX_GMF_RP	= 0x0d70,/* 32 bit 	Tx GMAC FIFO Read Pointer */
822 	TX_GMF_RSTP	= 0x0d74,/* 32 bit 	Tx GMAC FIFO Restart Pointer */
823 	TX_GMF_RLEV	= 0x0d78,/* 32 bit 	Tx GMAC FIFO Read Level */
824 
825 	/* Descriptor Poll Timer Registers */
826 	B28_DPT_INI	= 0x0e00,/* 24 bit	Descriptor Poll Timer Init Val */
827 	B28_DPT_VAL	= 0x0e04,/* 24 bit	Descriptor Poll Timer Curr Val */
828 	B28_DPT_CTRL	= 0x0e08,/*  8 bit	Descriptor Poll Timer Ctrl Reg */
829 
830 	B28_DPT_TST	= 0x0e0a,/*  8 bit	Descriptor Poll Timer Test Reg */
831 
832 	/* Time Stamp Timer Registers (YUKON only) */
833 	GMAC_TI_ST_VAL	= 0x0e14,/* 32 bit	Time Stamp Timer Curr Val */
834 	GMAC_TI_ST_CTRL	= 0x0e18,/*  8 bit	Time Stamp Timer Ctrl Reg */
835 	GMAC_TI_ST_TST	= 0x0e1a,/*  8 bit	Time Stamp Timer Test Reg */
836 };
837 
838 
839 enum {
840 	LINKLED_OFF 	     = 0x01,
841 	LINKLED_ON  	     = 0x02,
842 	LINKLED_LINKSYNC_OFF = 0x04,
843 	LINKLED_LINKSYNC_ON  = 0x08,
844 	LINKLED_BLINK_OFF    = 0x10,
845 	LINKLED_BLINK_ON     = 0x20,
846 };
847 
848 /* GMAC and GPHY Control Registers (YUKON only) */
849 enum {
850 	GMAC_CTRL	= 0x0f00,/* 32 bit	GMAC Control Reg */
851 	GPHY_CTRL	= 0x0f04,/* 32 bit	GPHY Control Reg */
852 	GMAC_IRQ_SRC	= 0x0f08,/*  8 bit	GMAC Interrupt Source Reg */
853 	GMAC_IRQ_MSK	= 0x0f0c,/*  8 bit	GMAC Interrupt Mask Reg */
854 	GMAC_LINK_CTRL	= 0x0f10,/* 16 bit	Link Control Reg */
855 
856 /* Wake-up Frame Pattern Match Control Registers (YUKON only) */
857 
858 	WOL_REG_OFFS	= 0x20,/* HW-Bug: Address is + 0x20 against spec. */
859 
860 	WOL_CTRL_STAT	= 0x0f20,/* 16 bit	WOL Control/Status Reg */
861 	WOL_MATCH_CTL	= 0x0f22,/*  8 bit	WOL Match Control Reg */
862 	WOL_MATCH_RES	= 0x0f23,/*  8 bit	WOL Match Result Reg */
863 	WOL_MAC_ADDR	= 0x0f24,/* 32 bit	WOL MAC Address */
864 	WOL_PATT_RPTR	= 0x0f2c,/*  8 bit	WOL Pattern Read Pointer */
865 
866 /* WOL Pattern Length Registers (YUKON only) */
867 
868 	WOL_PATT_LEN_LO	= 0x0f30,/* 32 bit	WOL Pattern Length 3..0 */
869 	WOL_PATT_LEN_HI	= 0x0f34,/* 24 bit	WOL Pattern Length 6..4 */
870 
871 /* WOL Pattern Counter Registers (YUKON only) */
872 
873 	WOL_PATT_CNT_0	= 0x0f38,/* 32 bit	WOL Pattern Counter 3..0 */
874 	WOL_PATT_CNT_4	= 0x0f3c,/* 24 bit	WOL Pattern Counter 6..4 */
875 };
876 #define WOL_REGS(port, x)	(x + (port)*0x80)
877 
878 enum {
879 	WOL_PATT_RAM_1	= 0x1000,/*  WOL Pattern RAM Link 1 */
880 	WOL_PATT_RAM_2	= 0x1400,/*  WOL Pattern RAM Link 2 */
881 };
882 #define WOL_PATT_RAM_BASE(port)	(WOL_PATT_RAM_1 + (port)*0x400)
883 
884 enum {
885 	BASE_XMAC_1	= 0x2000,/* XMAC 1 registers */
886 	BASE_GMAC_1	= 0x2800,/* GMAC 1 registers */
887 	BASE_XMAC_2	= 0x3000,/* XMAC 2 registers */
888 	BASE_GMAC_2	= 0x3800,/* GMAC 2 registers */
889 };
890 
891 /*
892  * Receive Frame Status Encoding
893  */
894 enum {
895 	XMR_FS_LEN	= 0x3fff<<18,	/* Bit 31..18:	Rx Frame Length */
896 	XMR_FS_LEN_SHIFT = 18,
897 	XMR_FS_2L_VLAN	= 1<<17, /* Bit 17:	tagged wh 2Lev VLAN ID*/
898 	XMR_FS_1_VLAN	= 1<<16, /* Bit 16:	tagged wh 1ev VLAN ID*/
899 	XMR_FS_BC	= 1<<15, /* Bit 15:	Broadcast Frame */
900 	XMR_FS_MC	= 1<<14, /* Bit 14:	Multicast Frame */
901 	XMR_FS_UC	= 1<<13, /* Bit 13:	Unicast Frame */
902 
903 	XMR_FS_BURST	= 1<<11, /* Bit 11:	Burst Mode */
904 	XMR_FS_CEX_ERR	= 1<<10, /* Bit 10:	Carrier Ext. Error */
905 	XMR_FS_802_3	= 1<<9, /* Bit  9:	802.3 Frame */
906 	XMR_FS_COL_ERR	= 1<<8, /* Bit  8:	Collision Error */
907 	XMR_FS_CAR_ERR	= 1<<7, /* Bit  7:	Carrier Event Error */
908 	XMR_FS_LEN_ERR	= 1<<6, /* Bit  6:	In-Range Length Error */
909 	XMR_FS_FRA_ERR	= 1<<5, /* Bit  5:	Framing Error */
910 	XMR_FS_RUNT	= 1<<4, /* Bit  4:	Runt Frame */
911 	XMR_FS_LNG_ERR	= 1<<3, /* Bit  3:	Giant (Jumbo) Frame */
912 	XMR_FS_FCS_ERR	= 1<<2, /* Bit  2:	Frame Check Sequ Err */
913 	XMR_FS_ERR	= 1<<1, /* Bit  1:	Frame Error */
914 	XMR_FS_MCTRL	= 1<<0, /* Bit  0:	MAC Control Packet */
915 
916 /*
917  * XMR_FS_ERR will be set if
918  *	XMR_FS_FCS_ERR, XMR_FS_LNG_ERR, XMR_FS_RUNT,
919  *	XMR_FS_FRA_ERR, XMR_FS_LEN_ERR, or XMR_FS_CEX_ERR
920  * is set. XMR_FS_LNG_ERR and XMR_FS_LEN_ERR will issue
921  * XMR_FS_ERR unless the corresponding bit in the Receive Command
922  * Register is set.
923  */
924 };
925 
926 /*
927 ,* XMAC-PHY Registers, indirect addressed over the XMAC
928  */
929 enum {
930 	PHY_XMAC_CTRL		= 0x00,/* 16 bit r/w	PHY Control Register */
931 	PHY_XMAC_STAT		= 0x01,/* 16 bit r/w	PHY Status Register */
932 	PHY_XMAC_ID0		= 0x02,/* 16 bit r/o	PHY ID0 Register */
933 	PHY_XMAC_ID1		= 0x03,/* 16 bit r/o	PHY ID1 Register */
934 	PHY_XMAC_AUNE_ADV	= 0x04,/* 16 bit r/w	Auto-Neg. Advertisement */
935 	PHY_XMAC_AUNE_LP	= 0x05,/* 16 bit r/o	Link Partner Abi Reg */
936 	PHY_XMAC_AUNE_EXP	= 0x06,/* 16 bit r/o	Auto-Neg. Expansion Reg */
937 	PHY_XMAC_NEPG		= 0x07,/* 16 bit r/w	Next Page Register */
938 	PHY_XMAC_NEPG_LP	= 0x08,/* 16 bit r/o	Next Page Link Partner */
939 
940 	PHY_XMAC_EXT_STAT	= 0x0f,/* 16 bit r/o	Ext Status Register */
941 	PHY_XMAC_RES_ABI	= 0x10,/* 16 bit r/o	PHY Resolved Ability */
942 };
943 /*
944  * Broadcom-PHY Registers, indirect addressed over XMAC
945  */
946 enum {
947 	PHY_BCOM_CTRL		= 0x00,/* 16 bit r/w	PHY Control Register */
948 	PHY_BCOM_STAT		= 0x01,/* 16 bit r/o	PHY Status Register */
949 	PHY_BCOM_ID0		= 0x02,/* 16 bit r/o	PHY ID0 Register */
950 	PHY_BCOM_ID1		= 0x03,/* 16 bit r/o	PHY ID1 Register */
951 	PHY_BCOM_AUNE_ADV	= 0x04,/* 16 bit r/w	Auto-Neg. Advertisement */
952 	PHY_BCOM_AUNE_LP	= 0x05,/* 16 bit r/o	Link Part Ability Reg */
953 	PHY_BCOM_AUNE_EXP	= 0x06,/* 16 bit r/o	Auto-Neg. Expansion Reg */
954 	PHY_BCOM_NEPG		= 0x07,/* 16 bit r/w	Next Page Register */
955 	PHY_BCOM_NEPG_LP	= 0x08,/* 16 bit r/o	Next Page Link Partner */
956 	/* Broadcom-specific registers */
957 	PHY_BCOM_1000T_CTRL	= 0x09,/* 16 bit r/w	1000Base-T Control Reg */
958 	PHY_BCOM_1000T_STAT	= 0x0a,/* 16 bit r/o	1000Base-T Status Reg */
959 	PHY_BCOM_EXT_STAT	= 0x0f,/* 16 bit r/o	Extended Status Reg */
960 	PHY_BCOM_P_EXT_CTRL	= 0x10,/* 16 bit r/w	PHY Extended Ctrl Reg */
961 	PHY_BCOM_P_EXT_STAT	= 0x11,/* 16 bit r/o	PHY Extended Stat Reg */
962 	PHY_BCOM_RE_CTR		= 0x12,/* 16 bit r/w	Receive Error Counter */
963 	PHY_BCOM_FC_CTR		= 0x13,/* 16 bit r/w	False Carrier Sense Cnt */
964 	PHY_BCOM_RNO_CTR	= 0x14,/* 16 bit r/w	Receiver NOT_OK Cnt */
965 
966 	PHY_BCOM_AUX_CTRL	= 0x18,/* 16 bit r/w	Auxiliary Control Reg */
967 	PHY_BCOM_AUX_STAT	= 0x19,/* 16 bit r/o	Auxiliary Stat Summary */
968 	PHY_BCOM_INT_STAT	= 0x1a,/* 16 bit r/o	Interrupt Status Reg */
969 	PHY_BCOM_INT_MASK	= 0x1b,/* 16 bit r/w	Interrupt Mask Reg */
970 };
971 
972 /*
973  * Marvel-PHY Registers, indirect addressed over GMAC
974  */
975 enum {
976 	PHY_MARV_CTRL		= 0x00,/* 16 bit r/w	PHY Control Register */
977 	PHY_MARV_STAT		= 0x01,/* 16 bit r/o	PHY Status Register */
978 	PHY_MARV_ID0		= 0x02,/* 16 bit r/o	PHY ID0 Register */
979 	PHY_MARV_ID1		= 0x03,/* 16 bit r/o	PHY ID1 Register */
980 	PHY_MARV_AUNE_ADV	= 0x04,/* 16 bit r/w	Auto-Neg. Advertisement */
981 	PHY_MARV_AUNE_LP	= 0x05,/* 16 bit r/o	Link Part Ability Reg */
982 	PHY_MARV_AUNE_EXP	= 0x06,/* 16 bit r/o	Auto-Neg. Expansion Reg */
983 	PHY_MARV_NEPG		= 0x07,/* 16 bit r/w	Next Page Register */
984 	PHY_MARV_NEPG_LP	= 0x08,/* 16 bit r/o	Next Page Link Partner */
985 	/* Marvel-specific registers */
986 	PHY_MARV_1000T_CTRL	= 0x09,/* 16 bit r/w	1000Base-T Control Reg */
987 	PHY_MARV_1000T_STAT	= 0x0a,/* 16 bit r/o	1000Base-T Status Reg */
988 	PHY_MARV_EXT_STAT	= 0x0f,/* 16 bit r/o	Extended Status Reg */
989 	PHY_MARV_PHY_CTRL	= 0x10,/* 16 bit r/w	PHY Specific Ctrl Reg */
990 	PHY_MARV_PHY_STAT	= 0x11,/* 16 bit r/o	PHY Specific Stat Reg */
991 	PHY_MARV_INT_MASK	= 0x12,/* 16 bit r/w	Interrupt Mask Reg */
992 	PHY_MARV_INT_STAT	= 0x13,/* 16 bit r/o	Interrupt Status Reg */
993 	PHY_MARV_EXT_CTRL	= 0x14,/* 16 bit r/w	Ext. PHY Specific Ctrl */
994 	PHY_MARV_RXE_CNT	= 0x15,/* 16 bit r/w	Receive Error Counter */
995 	PHY_MARV_EXT_ADR	= 0x16,/* 16 bit r/w	Ext. Ad. for Cable Diag. */
996 	PHY_MARV_PORT_IRQ	= 0x17,/* 16 bit r/o	Port 0 IRQ (88E1111 only) */
997 	PHY_MARV_LED_CTRL	= 0x18,/* 16 bit r/w	LED Control Reg */
998 	PHY_MARV_LED_OVER	= 0x19,/* 16 bit r/w	Manual LED Override Reg */
999 	PHY_MARV_EXT_CTRL_2	= 0x1a,/* 16 bit r/w	Ext. PHY Specific Ctrl 2 */
1000 	PHY_MARV_EXT_P_STAT	= 0x1b,/* 16 bit r/w	Ext. PHY Spec. Stat Reg */
1001 	PHY_MARV_CABLE_DIAG	= 0x1c,/* 16 bit r/o	Cable Diagnostic Reg */
1002 	PHY_MARV_PAGE_ADDR	= 0x1d,/* 16 bit r/w	Extended Page Address Reg */
1003 	PHY_MARV_PAGE_DATA	= 0x1e,/* 16 bit r/w	Extended Page Data Reg */
1004 
1005 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1006 	PHY_MARV_FE_LED_PAR	= 0x16,/* 16 bit r/w	LED Parallel Select Reg. */
1007 	PHY_MARV_FE_LED_SER	= 0x17,/* 16 bit r/w	LED Stream Select S. LED */
1008 	PHY_MARV_FE_VCT_TX	= 0x1a,/* 16 bit r/w	VCT Reg. for TXP/N Pins */
1009 	PHY_MARV_FE_VCT_RX	= 0x1b,/* 16 bit r/o	VCT Reg. for RXP/N Pins */
1010 	PHY_MARV_FE_SPEC_2	= 0x1c,/* 16 bit r/w	Specific Control Reg. 2 */
1011 };
1012 
1013 enum {
1014 	PHY_CT_RESET	= 1<<15, /* Bit 15: (sc)	clear all PHY related regs */
1015 	PHY_CT_LOOP	= 1<<14, /* Bit 14:	enable Loopback over PHY */
1016 	PHY_CT_SPS_LSB	= 1<<13, /* Bit 13:	Speed select, lower bit */
1017 	PHY_CT_ANE	= 1<<12, /* Bit 12:	Auto-Negotiation Enabled */
1018 	PHY_CT_PDOWN	= 1<<11, /* Bit 11:	Power Down Mode */
1019 	PHY_CT_ISOL	= 1<<10, /* Bit 10:	Isolate Mode */
1020 	PHY_CT_RE_CFG	= 1<<9, /* Bit  9:	(sc) Restart Auto-Negotiation */
1021 	PHY_CT_DUP_MD	= 1<<8, /* Bit  8:	Duplex Mode */
1022 	PHY_CT_COL_TST	= 1<<7, /* Bit  7:	Collision Test enabled */
1023 	PHY_CT_SPS_MSB	= 1<<6, /* Bit  6:	Speed select, upper bit */
1024 };
1025 
1026 enum {
1027 	PHY_CT_SP1000	= PHY_CT_SPS_MSB, /* enable speed of 1000 Mbps */
1028 	PHY_CT_SP100	= PHY_CT_SPS_LSB, /* enable speed of  100 Mbps */
1029 	PHY_CT_SP10	= 0,		  /* enable speed of   10 Mbps */
1030 };
1031 
1032 enum {
1033 	PHY_ST_EXT_ST	= 1<<8, /* Bit  8:	Extended Status Present */
1034 
1035 	PHY_ST_PRE_SUP	= 1<<6, /* Bit  6:	Preamble Suppression */
1036 	PHY_ST_AN_OVER	= 1<<5, /* Bit  5:	Auto-Negotiation Over */
1037 	PHY_ST_REM_FLT	= 1<<4, /* Bit  4:	Remote Fault Condition Occurred */
1038 	PHY_ST_AN_CAP	= 1<<3, /* Bit  3:	Auto-Negotiation Capability */
1039 	PHY_ST_LSYNC	= 1<<2, /* Bit  2:	Link Synchronized */
1040 	PHY_ST_JAB_DET	= 1<<1, /* Bit  1:	Jabber Detected */
1041 	PHY_ST_EXT_REG	= 1<<0, /* Bit  0:	Extended Register available */
1042 };
1043 
1044 enum {
1045 	PHY_I1_OUI_MSK	= 0x3f<<10, /* Bit 15..10:	Organization Unique ID */
1046 	PHY_I1_MOD_NUM	= 0x3f<<4, /* Bit  9.. 4:	Model Number */
1047 	PHY_I1_REV_MSK	= 0xf, /* Bit  3.. 0:	Revision Number */
1048 };
1049 
1050 /* different Broadcom PHY Ids */
1051 enum {
1052 	PHY_BCOM_ID1_A1	= 0x6041,
1053 	PHY_BCOM_ID1_B2 = 0x6043,
1054 	PHY_BCOM_ID1_C0	= 0x6044,
1055 	PHY_BCOM_ID1_C5	= 0x6047,
1056 };
1057 
1058 /* different Marvell PHY Ids */
1059 enum {
1060 	PHY_MARV_ID0_VAL= 0x0141, /* Marvell Unique Identifier */
1061 	PHY_MARV_ID1_B0	= 0x0C23, /* Yukon (PHY 88E1011) */
1062 	PHY_MARV_ID1_B2	= 0x0C25, /* Yukon-Plus (PHY 88E1011) */
1063 	PHY_MARV_ID1_C2	= 0x0CC2, /* Yukon-EC (PHY 88E1111) */
1064 	PHY_MARV_ID1_Y2	= 0x0C91, /* Yukon-2 (PHY 88E1112) */
1065 };
1066 
1067 /* Advertisement register bits */
1068 enum {
1069 	PHY_AN_NXT_PG	= 1<<15, /* Bit 15:	Request Next Page */
1070 	PHY_AN_ACK	= 1<<14, /* Bit 14:	(ro) Acknowledge Received */
1071 	PHY_AN_RF	= 1<<13, /* Bit 13:	Remote Fault Bits */
1072 
1073 	PHY_AN_PAUSE_ASYM = 1<<11,/* Bit 11:	Try for asymmetric */
1074 	PHY_AN_PAUSE_CAP = 1<<10, /* Bit 10:	Try for pause */
1075 	PHY_AN_100BASE4	= 1<<9, /* Bit 9:	Try for 100mbps 4k packets */
1076 	PHY_AN_100FULL	= 1<<8, /* Bit 8:	Try for 100mbps full-duplex */
1077 	PHY_AN_100HALF	= 1<<7, /* Bit 7:	Try for 100mbps half-duplex */
1078 	PHY_AN_10FULL	= 1<<6, /* Bit 6:	Try for 10mbps full-duplex */
1079 	PHY_AN_10HALF	= 1<<5, /* Bit 5:	Try for 10mbps half-duplex */
1080 	PHY_AN_CSMA	= 1<<0, /* Bit 0:	Only selector supported */
1081 	PHY_AN_SEL	= 0x1f, /* Bit 4..0:	Selector Field, 00001=Ethernet*/
1082 	PHY_AN_FULL	= PHY_AN_100FULL | PHY_AN_10FULL | PHY_AN_CSMA,
1083 	PHY_AN_ALL	= PHY_AN_10HALF | PHY_AN_10FULL |
1084 		  	  PHY_AN_100HALF | PHY_AN_100FULL,
1085 };
1086 
1087 /* Xmac Specific */
1088 enum {
1089 	PHY_X_AN_NXT_PG	= 1<<15, /* Bit 15:	Request Next Page */
1090 	PHY_X_AN_ACK	= 1<<14, /* Bit 14:	(ro) Acknowledge Received */
1091 	PHY_X_AN_RFB	= 3<<12,/* Bit 13..12:	Remote Fault Bits */
1092 
1093 	PHY_X_AN_PAUSE	= 3<<7,/* Bit  8.. 7:	Pause Bits */
1094 	PHY_X_AN_HD	= 1<<6, /* Bit  6:	Half Duplex */
1095 	PHY_X_AN_FD	= 1<<5, /* Bit  5:	Full Duplex */
1096 };
1097 
1098 /* Pause Bits (PHY_X_AN_PAUSE and PHY_X_RS_PAUSE) encoding */
1099 enum {
1100 	PHY_X_P_NO_PAUSE= 0<<7,/* Bit  8..7:	no Pause Mode */
1101 	PHY_X_P_SYM_MD	= 1<<7, /* Bit  8..7:	symmetric Pause Mode */
1102 	PHY_X_P_ASYM_MD	= 2<<7,/* Bit  8..7:	asymmetric Pause Mode */
1103 	PHY_X_P_BOTH_MD	= 3<<7,/* Bit  8..7:	both Pause Mode */
1104 };
1105 
1106 
1107 /*****  PHY_XMAC_EXT_STAT	16 bit r/w	Extended Status Register *****/
1108 enum {
1109 	PHY_X_EX_FD	= 1<<15, /* Bit 15:	Device Supports Full Duplex */
1110 	PHY_X_EX_HD	= 1<<14, /* Bit 14:	Device Supports Half Duplex */
1111 };
1112 
1113 /*****  PHY_XMAC_RES_ABI	16 bit r/o	PHY Resolved Ability *****/
1114 enum {
1115 	PHY_X_RS_PAUSE	= 3<<7,	/* Bit  8..7:	selected Pause Mode */
1116 	PHY_X_RS_HD	= 1<<6,	/* Bit  6:	Half Duplex Mode selected */
1117 	PHY_X_RS_FD	= 1<<5,	/* Bit  5:	Full Duplex Mode selected */
1118 	PHY_X_RS_ABLMIS = 1<<4,	/* Bit  4:	duplex or pause cap mismatch */
1119 	PHY_X_RS_PAUMIS = 1<<3,	/* Bit  3:	pause capability mismatch */
1120 };
1121 
1122 /* Remote Fault Bits (PHY_X_AN_RFB) encoding */
1123 enum {
1124 	X_RFB_OK	= 0<<12,/* Bit 13..12	No errors, Link OK */
1125 	X_RFB_LF	= 1<<12,/* Bit 13..12	Link Failure */
1126 	X_RFB_OFF	= 2<<12,/* Bit 13..12	Offline */
1127 	X_RFB_AN_ERR	= 3<<12,/* Bit 13..12	Auto-Negotiation Error */
1128 };
1129 
1130 /* Broadcom-Specific */
1131 /*****  PHY_BCOM_1000T_CTRL	16 bit r/w	1000Base-T Control Reg *****/
1132 enum {
1133 	PHY_B_1000C_TEST	= 7<<13,/* Bit 15..13:	Test Modes */
1134 	PHY_B_1000C_MSE	= 1<<12, /* Bit 12:	Master/Slave Enable */
1135 	PHY_B_1000C_MSC	= 1<<11, /* Bit 11:	M/S Configuration */
1136 	PHY_B_1000C_RD	= 1<<10, /* Bit 10:	Repeater/DTE */
1137 	PHY_B_1000C_AFD	= 1<<9, /* Bit  9:	Advertise Full Duplex */
1138 	PHY_B_1000C_AHD	= 1<<8, /* Bit  8:	Advertise Half Duplex */
1139 };
1140 
1141 /*****  PHY_BCOM_1000T_STAT	16 bit r/o	1000Base-T Status Reg *****/
1142 /*****  PHY_MARV_1000T_STAT	16 bit r/o	1000Base-T Status Reg *****/
1143 enum {
1144 	PHY_B_1000S_MSF	= 1<<15, /* Bit 15:	Master/Slave Fault */
1145 	PHY_B_1000S_MSR	= 1<<14, /* Bit 14:	Master/Slave Result */
1146 	PHY_B_1000S_LRS	= 1<<13, /* Bit 13:	Local Receiver Status */
1147 	PHY_B_1000S_RRS	= 1<<12, /* Bit 12:	Remote Receiver Status */
1148 	PHY_B_1000S_LP_FD	= 1<<11, /* Bit 11:	Link Partner can FD */
1149 	PHY_B_1000S_LP_HD	= 1<<10, /* Bit 10:	Link Partner can HD */
1150 									/* Bit  9..8:	reserved */
1151 	PHY_B_1000S_IEC	= 0xff, /* Bit  7..0:	Idle Error Count */
1152 };
1153 
1154 /*****  PHY_BCOM_EXT_STAT	16 bit r/o	Extended Status Register *****/
1155 enum {
1156 	PHY_B_ES_X_FD_CAP	= 1<<15, /* Bit 15:	1000Base-X FD capable */
1157 	PHY_B_ES_X_HD_CAP	= 1<<14, /* Bit 14:	1000Base-X HD capable */
1158 	PHY_B_ES_T_FD_CAP	= 1<<13, /* Bit 13:	1000Base-T FD capable */
1159 	PHY_B_ES_T_HD_CAP	= 1<<12, /* Bit 12:	1000Base-T HD capable */
1160 };
1161 
1162 /*****  PHY_BCOM_P_EXT_CTRL	16 bit r/w	PHY Extended Control Reg *****/
1163 enum {
1164 	PHY_B_PEC_MAC_PHY	= 1<<15, /* Bit 15:	10BIT/GMI-Interface */
1165 	PHY_B_PEC_DIS_CROSS	= 1<<14, /* Bit 14:	Disable MDI Crossover */
1166 	PHY_B_PEC_TX_DIS	= 1<<13, /* Bit 13:	Tx output Disabled */
1167 	PHY_B_PEC_INT_DIS	= 1<<12, /* Bit 12:	Interrupts Disabled */
1168 	PHY_B_PEC_F_INT	= 1<<11, /* Bit 11:	Force Interrupt */
1169 	PHY_B_PEC_BY_45	= 1<<10, /* Bit 10:	Bypass 4B5B-Decoder */
1170 	PHY_B_PEC_BY_SCR	= 1<<9, /* Bit  9:	Bypass Scrambler */
1171 	PHY_B_PEC_BY_MLT3	= 1<<8, /* Bit  8:	Bypass MLT3 Encoder */
1172 	PHY_B_PEC_BY_RXA	= 1<<7, /* Bit  7:	Bypass Rx Alignm. */
1173 	PHY_B_PEC_RES_SCR	= 1<<6, /* Bit  6:	Reset Scrambler */
1174 	PHY_B_PEC_EN_LTR	= 1<<5, /* Bit  5:	Ena LED Traffic Mode */
1175 	PHY_B_PEC_LED_ON	= 1<<4, /* Bit  4:	Force LED's on */
1176 	PHY_B_PEC_LED_OFF	= 1<<3, /* Bit  3:	Force LED's off */
1177 	PHY_B_PEC_EX_IPG	= 1<<2, /* Bit  2:	Extend Tx IPG Mode */
1178 	PHY_B_PEC_3_LED	= 1<<1, /* Bit  1:	Three Link LED mode */
1179 	PHY_B_PEC_HIGH_LA	= 1<<0, /* Bit  0:	GMII FIFO Elasticy */
1180 };
1181 
1182 /*****  PHY_BCOM_P_EXT_STAT	16 bit r/o	PHY Extended Status Reg *****/
1183 enum {
1184 	PHY_B_PES_CROSS_STAT	= 1<<13, /* Bit 13:	MDI Crossover Status */
1185 	PHY_B_PES_INT_STAT	= 1<<12, /* Bit 12:	Interrupt Status */
1186 	PHY_B_PES_RRS	= 1<<11, /* Bit 11:	Remote Receiver Stat. */
1187 	PHY_B_PES_LRS	= 1<<10, /* Bit 10:	Local Receiver Stat. */
1188 	PHY_B_PES_LOCKED	= 1<<9, /* Bit  9:	Locked */
1189 	PHY_B_PES_LS	= 1<<8, /* Bit  8:	Link Status */
1190 	PHY_B_PES_RF	= 1<<7, /* Bit  7:	Remote Fault */
1191 	PHY_B_PES_CE_ER	= 1<<6, /* Bit  6:	Carrier Ext Error */
1192 	PHY_B_PES_BAD_SSD	= 1<<5, /* Bit  5:	Bad SSD */
1193 	PHY_B_PES_BAD_ESD	= 1<<4, /* Bit  4:	Bad ESD */
1194 	PHY_B_PES_RX_ER	= 1<<3, /* Bit  3:	Receive Error */
1195 	PHY_B_PES_TX_ER	= 1<<2, /* Bit  2:	Transmit Error */
1196 	PHY_B_PES_LOCK_ER	= 1<<1, /* Bit  1:	Lock Error */
1197 	PHY_B_PES_MLT3_ER	= 1<<0, /* Bit  0:	MLT3 code Error */
1198 };
1199 
1200 /*  PHY_BCOM_AUNE_ADV	16 bit r/w	Auto-Negotiation Advertisement *****/
1201 /*  PHY_BCOM_AUNE_LP	16 bit r/o	Link Partner Ability Reg *****/
1202 enum {
1203 	PHY_B_AN_RF	= 1<<13, /* Bit 13:	Remote Fault */
1204 
1205 	PHY_B_AN_ASP	= 1<<11, /* Bit 11:	Asymmetric Pause */
1206 	PHY_B_AN_PC	= 1<<10, /* Bit 10:	Pause Capable */
1207 };
1208 
1209 
1210 /*****  PHY_BCOM_FC_CTR		16 bit r/w	False Carrier Counter *****/
1211 enum {
1212 	PHY_B_FC_CTR	= 0xff, /* Bit  7..0:	False Carrier Counter */
1213 
1214 /*****  PHY_BCOM_RNO_CTR	16 bit r/w	Receive NOT_OK Counter *****/
1215 	PHY_B_RC_LOC_MSK	= 0xff00, /* Bit 15..8:	Local Rx NOT_OK cnt */
1216 	PHY_B_RC_REM_MSK	= 0x00ff, /* Bit  7..0:	Remote Rx NOT_OK cnt */
1217 
1218 /*****  PHY_BCOM_AUX_CTRL	16 bit r/w	Auxiliary Control Reg *****/
1219 	PHY_B_AC_L_SQE		= 1<<15, /* Bit 15:	Low Squelch */
1220 	PHY_B_AC_LONG_PACK	= 1<<14, /* Bit 14:	Rx Long Packets */
1221 	PHY_B_AC_ER_CTRL	= 3<<12,/* Bit 13..12:	Edgerate Control */
1222 									/* Bit 11:	reserved */
1223 	PHY_B_AC_TX_TST	= 1<<10, /* Bit 10:	Tx test bit, always 1 */
1224 									/* Bit  9.. 8:	reserved */
1225 	PHY_B_AC_DIS_PRF	= 1<<7, /* Bit  7:	dis part resp filter */
1226 									/* Bit  6:	reserved */
1227 	PHY_B_AC_DIS_PM	= 1<<5, /* Bit  5:	dis power management */
1228 									/* Bit  4:	reserved */
1229 	PHY_B_AC_DIAG	= 1<<3, /* Bit  3:	Diagnostic Mode */
1230 };
1231 
1232 /*****  PHY_BCOM_AUX_STAT	16 bit r/o	Auxiliary Status Reg *****/
1233 enum {
1234 	PHY_B_AS_AN_C	= 1<<15, /* Bit 15:	AutoNeg complete */
1235 	PHY_B_AS_AN_CA	= 1<<14, /* Bit 14:	AN Complete Ack */
1236 	PHY_B_AS_ANACK_D	= 1<<13, /* Bit 13:	AN Ack Detect */
1237 	PHY_B_AS_ANAB_D	= 1<<12, /* Bit 12:	AN Ability Detect */
1238 	PHY_B_AS_NPW	= 1<<11, /* Bit 11:	AN Next Page Wait */
1239 	PHY_B_AS_AN_RES_MSK	= 7<<8,/* Bit 10..8:	AN HDC */
1240 	PHY_B_AS_PDF	= 1<<7, /* Bit  7:	Parallel Detect. Fault */
1241 	PHY_B_AS_RF	= 1<<6, /* Bit  6:	Remote Fault */
1242 	PHY_B_AS_ANP_R	= 1<<5, /* Bit  5:	AN Page Received */
1243 	PHY_B_AS_LP_ANAB	= 1<<4, /* Bit  4:	LP AN Ability */
1244 	PHY_B_AS_LP_NPAB	= 1<<3, /* Bit  3:	LP Next Page Ability */
1245 	PHY_B_AS_LS	= 1<<2, /* Bit  2:	Link Status */
1246 	PHY_B_AS_PRR	= 1<<1, /* Bit  1:	Pause Resolution-Rx */
1247 	PHY_B_AS_PRT	= 1<<0, /* Bit  0:	Pause Resolution-Tx */
1248 };
1249 #define PHY_B_AS_PAUSE_MSK	(PHY_B_AS_PRR | PHY_B_AS_PRT)
1250 
1251 /*****  PHY_BCOM_INT_STAT	16 bit r/o	Interrupt Status Reg *****/
1252 /*****  PHY_BCOM_INT_MASK	16 bit r/w	Interrupt Mask Reg *****/
1253 enum {
1254 	PHY_B_IS_PSE	= 1<<14, /* Bit 14:	Pair Swap Error */
1255 	PHY_B_IS_MDXI_SC	= 1<<13, /* Bit 13:	MDIX Status Change */
1256 	PHY_B_IS_HCT	= 1<<12, /* Bit 12:	counter above 32k */
1257 	PHY_B_IS_LCT	= 1<<11, /* Bit 11:	counter above 128 */
1258 	PHY_B_IS_AN_PR	= 1<<10, /* Bit 10:	Page Received */
1259 	PHY_B_IS_NO_HDCL	= 1<<9, /* Bit  9:	No HCD Link */
1260 	PHY_B_IS_NO_HDC	= 1<<8, /* Bit  8:	No HCD */
1261 	PHY_B_IS_NEG_USHDC	= 1<<7, /* Bit  7:	Negotiated Unsup. HCD */
1262 	PHY_B_IS_SCR_S_ER	= 1<<6, /* Bit  6:	Scrambler Sync Error */
1263 	PHY_B_IS_RRS_CHANGE	= 1<<5, /* Bit  5:	Remote Rx Stat Change */
1264 	PHY_B_IS_LRS_CHANGE	= 1<<4, /* Bit  4:	Local Rx Stat Change */
1265 	PHY_B_IS_DUP_CHANGE	= 1<<3, /* Bit  3:	Duplex Mode Change */
1266 	PHY_B_IS_LSP_CHANGE	= 1<<2, /* Bit  2:	Link Speed Change */
1267 	PHY_B_IS_LST_CHANGE	= 1<<1, /* Bit  1:	Link Status Changed */
1268 	PHY_B_IS_CRC_ER	= 1<<0, /* Bit  0:	CRC Error */
1269 };
1270 #define PHY_B_DEF_MSK	\
1271 	(~(PHY_B_IS_PSE | PHY_B_IS_AN_PR | PHY_B_IS_DUP_CHANGE | \
1272 	    PHY_B_IS_LSP_CHANGE | PHY_B_IS_LST_CHANGE))
1273 
1274 /* Pause Bits (PHY_B_AN_ASP and PHY_B_AN_PC) encoding */
1275 enum {
1276 	PHY_B_P_NO_PAUSE	= 0<<10,/* Bit 11..10:	no Pause Mode */
1277 	PHY_B_P_SYM_MD	= 1<<10, /* Bit 11..10:	symmetric Pause Mode */
1278 	PHY_B_P_ASYM_MD	= 2<<10,/* Bit 11..10:	asymmetric Pause Mode */
1279 	PHY_B_P_BOTH_MD	= 3<<10,/* Bit 11..10:	both Pause Mode */
1280 };
1281 /*
1282  * Resolved Duplex mode and Capabilities (Aux Status Summary Reg)
1283  */
1284 enum {
1285 	PHY_B_RES_1000FD	= 7<<8,/* Bit 10..8:	1000Base-T Full Dup. */
1286 	PHY_B_RES_1000HD	= 6<<8,/* Bit 10..8:	1000Base-T Half Dup. */
1287 };
1288 
1289 /** Marvell-Specific */
1290 enum {
1291 	PHY_M_AN_NXT_PG	= 1<<15, /* Request Next Page */
1292 	PHY_M_AN_ACK	= 1<<14, /* (ro)	Acknowledge Received */
1293 	PHY_M_AN_RF	= 1<<13, /* Remote Fault */
1294 
1295 	PHY_M_AN_ASP	= 1<<11, /* Asymmetric Pause */
1296 	PHY_M_AN_PC	= 1<<10, /* MAC Pause implemented */
1297 	PHY_M_AN_100_T4	= 1<<9, /* Not cap. 100Base-T4 (always 0) */
1298 	PHY_M_AN_100_FD	= 1<<8, /* Advertise 100Base-TX Full Duplex */
1299 	PHY_M_AN_100_HD	= 1<<7, /* Advertise 100Base-TX Half Duplex */
1300 	PHY_M_AN_10_FD	= 1<<6, /* Advertise 10Base-TX Full Duplex */
1301 	PHY_M_AN_10_HD	= 1<<5, /* Advertise 10Base-TX Half Duplex */
1302 	PHY_M_AN_SEL_MSK =0x1f<<4,	/* Bit  4.. 0: Selector Field Mask */
1303 };
1304 
1305 /* special defines for FIBER (88E1011S only) */
1306 enum {
1307 	PHY_M_AN_ASP_X		= 1<<8, /* Asymmetric Pause */
1308 	PHY_M_AN_PC_X		= 1<<7, /* MAC Pause implemented */
1309 	PHY_M_AN_1000X_AHD	= 1<<6, /* Advertise 10000Base-X Half Duplex */
1310 	PHY_M_AN_1000X_AFD	= 1<<5, /* Advertise 10000Base-X Full Duplex */
1311 };
1312 
1313 /* Pause Bits (PHY_M_AN_ASP_X and PHY_M_AN_PC_X) encoding */
1314 enum {
1315 	PHY_M_P_NO_PAUSE_X	= 0<<7,/* Bit  8.. 7:	no Pause Mode */
1316 	PHY_M_P_SYM_MD_X	= 1<<7, /* Bit  8.. 7:	symmetric Pause Mode */
1317 	PHY_M_P_ASYM_MD_X	= 2<<7,/* Bit  8.. 7:	asymmetric Pause Mode */
1318 	PHY_M_P_BOTH_MD_X	= 3<<7,/* Bit  8.. 7:	both Pause Mode */
1319 };
1320 
1321 /*****  PHY_MARV_1000T_CTRL	16 bit r/w	1000Base-T Control Reg *****/
1322 enum {
1323 	PHY_M_1000C_TEST= 7<<13,/* Bit 15..13:	Test Modes */
1324 	PHY_M_1000C_MSE	= 1<<12, /* Manual Master/Slave Enable */
1325 	PHY_M_1000C_MSC	= 1<<11, /* M/S Configuration (1=Master) */
1326 	PHY_M_1000C_MPD	= 1<<10, /* Multi-Port Device */
1327 	PHY_M_1000C_AFD	= 1<<9, /* Advertise Full Duplex */
1328 	PHY_M_1000C_AHD	= 1<<8, /* Advertise Half Duplex */
1329 };
1330 
1331 /*****  PHY_MARV_PHY_CTRL	16 bit r/w	PHY Specific Ctrl Reg *****/
1332 enum {
1333 	PHY_M_PC_TX_FFD_MSK	= 3<<14,/* Bit 15..14: Tx FIFO Depth Mask */
1334 	PHY_M_PC_RX_FFD_MSK	= 3<<12,/* Bit 13..12: Rx FIFO Depth Mask */
1335 	PHY_M_PC_ASS_CRS_TX	= 1<<11, /* Assert CRS on Transmit */
1336 	PHY_M_PC_FL_GOOD	= 1<<10, /* Force Link Good */
1337 	PHY_M_PC_EN_DET_MSK	= 3<<8,/* Bit  9.. 8: Energy Detect Mask */
1338 	PHY_M_PC_ENA_EXT_D	= 1<<7, /* Enable Ext. Distance (10BT) */
1339 	PHY_M_PC_MDIX_MSK	= 3<<5,/* Bit  6.. 5: MDI/MDIX Config. Mask */
1340 	PHY_M_PC_DIS_125CLK	= 1<<4, /* Disable 125 CLK */
1341 	PHY_M_PC_MAC_POW_UP	= 1<<3, /* MAC Power up */
1342 	PHY_M_PC_SQE_T_ENA	= 1<<2, /* SQE Test Enabled */
1343 	PHY_M_PC_POL_R_DIS	= 1<<1, /* Polarity Reversal Disabled */
1344 	PHY_M_PC_DIS_JABBER	= 1<<0, /* Disable Jabber */
1345 };
1346 
1347 enum {
1348 	PHY_M_PC_EN_DET		= 2<<8,	/* Energy Detect (Mode 1) */
1349 	PHY_M_PC_EN_DET_PLUS	= 3<<8, /* Energy Detect Plus (Mode 2) */
1350 };
1351 
1352 enum {
1353 	PHY_M_PC_MAN_MDI	= 0, /* 00 = Manual MDI configuration */
1354 	PHY_M_PC_MAN_MDIX	= 1, /* 01 = Manual MDIX configuration */
1355 	PHY_M_PC_ENA_AUTO	= 3, /* 11 = Enable Automatic Crossover */
1356 };
1357 
1358 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1359 enum {
1360 	PHY_M_PC_ENA_DTE_DT	= 1<<15, /* Enable Data Terminal Equ. (DTE) Detect */
1361 	PHY_M_PC_ENA_ENE_DT	= 1<<14, /* Enable Energy Detect (sense & pulse) */
1362 	PHY_M_PC_DIS_NLP_CK	= 1<<13, /* Disable Normal Link Puls (NLP) Check */
1363 	PHY_M_PC_ENA_LIP_NP	= 1<<12, /* Enable Link Partner Next Page Reg. */
1364 	PHY_M_PC_DIS_NLP_GN	= 1<<11, /* Disable Normal Link Puls Generation */
1365 
1366 	PHY_M_PC_DIS_SCRAMB	= 1<<9, /* Disable Scrambler */
1367 	PHY_M_PC_DIS_FEFI	= 1<<8, /* Disable Far End Fault Indic. (FEFI) */
1368 
1369 	PHY_M_PC_SH_TP_SEL	= 1<<6, /* Shielded Twisted Pair Select */
1370 	PHY_M_PC_RX_FD_MSK	= 3<<2,/* Bit  3.. 2: Rx FIFO Depth Mask */
1371 };
1372 
1373 /*****  PHY_MARV_PHY_STAT	16 bit r/o	PHY Specific Status Reg *****/
1374 enum {
1375 	PHY_M_PS_SPEED_MSK	= 3<<14, /* Bit 15..14: Speed Mask */
1376 	PHY_M_PS_SPEED_1000	= 1<<15, /*		10 = 1000 Mbps */
1377 	PHY_M_PS_SPEED_100	= 1<<14, /*		01 =  100 Mbps */
1378 	PHY_M_PS_SPEED_10	= 0,	 /*		00 =   10 Mbps */
1379 	PHY_M_PS_FULL_DUP	= 1<<13, /* Full Duplex */
1380 	PHY_M_PS_PAGE_REC	= 1<<12, /* Page Received */
1381 	PHY_M_PS_SPDUP_RES	= 1<<11, /* Speed & Duplex Resolved */
1382 	PHY_M_PS_LINK_UP	= 1<<10, /* Link Up */
1383 	PHY_M_PS_CABLE_MSK	= 7<<7,  /* Bit  9.. 7: Cable Length Mask */
1384 	PHY_M_PS_MDI_X_STAT	= 1<<6,  /* MDI Crossover Stat (1=MDIX) */
1385 	PHY_M_PS_DOWNS_STAT	= 1<<5,  /* Downshift Status (1=downsh.) */
1386 	PHY_M_PS_ENDET_STAT	= 1<<4,  /* Energy Detect Status (1=act) */
1387 	PHY_M_PS_TX_P_EN	= 1<<3,  /* Tx Pause Enabled */
1388 	PHY_M_PS_RX_P_EN	= 1<<2,  /* Rx Pause Enabled */
1389 	PHY_M_PS_POL_REV	= 1<<1,  /* Polarity Reversed */
1390 	PHY_M_PS_JABBER		= 1<<0,  /* Jabber */
1391 };
1392 
1393 #define PHY_M_PS_PAUSE_MSK	(PHY_M_PS_TX_P_EN | PHY_M_PS_RX_P_EN)
1394 
1395 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1396 enum {
1397 	PHY_M_PS_DTE_DETECT	= 1<<15, /* Data Terminal Equipment (DTE) Detected */
1398 	PHY_M_PS_RES_SPEED	= 1<<14, /* Resolved Speed (1=100 Mbps, 0=10 Mbps */
1399 };
1400 
1401 enum {
1402 	PHY_M_IS_AN_ERROR	= 1<<15, /* Auto-Negotiation Error */
1403 	PHY_M_IS_LSP_CHANGE	= 1<<14, /* Link Speed Changed */
1404 	PHY_M_IS_DUP_CHANGE	= 1<<13, /* Duplex Mode Changed */
1405 	PHY_M_IS_AN_PR		= 1<<12, /* Page Received */
1406 	PHY_M_IS_AN_COMPL	= 1<<11, /* Auto-Negotiation Completed */
1407 	PHY_M_IS_LST_CHANGE	= 1<<10, /* Link Status Changed */
1408 	PHY_M_IS_SYMB_ERROR	= 1<<9, /* Symbol Error */
1409 	PHY_M_IS_FALSE_CARR	= 1<<8, /* False Carrier */
1410 	PHY_M_IS_FIFO_ERROR	= 1<<7, /* FIFO Overflow/Underrun Error */
1411 	PHY_M_IS_MDI_CHANGE	= 1<<6, /* MDI Crossover Changed */
1412 	PHY_M_IS_DOWNSH_DET	= 1<<5, /* Downshift Detected */
1413 	PHY_M_IS_END_CHANGE	= 1<<4, /* Energy Detect Changed */
1414 
1415 	PHY_M_IS_DTE_CHANGE	= 1<<2, /* DTE Power Det. Status Changed */
1416 	PHY_M_IS_POL_CHANGE	= 1<<1, /* Polarity Changed */
1417 	PHY_M_IS_JABBER		= 1<<0, /* Jabber */
1418 
1419 	PHY_M_IS_DEF_MSK	= PHY_M_IS_AN_ERROR | PHY_M_IS_LSP_CHANGE |
1420 				  PHY_M_IS_LST_CHANGE | PHY_M_IS_FIFO_ERROR,
1421 
1422 	PHY_M_IS_AN_MSK		= PHY_M_IS_AN_ERROR | PHY_M_IS_AN_COMPL,
1423 };
1424 
1425 /*****  PHY_MARV_EXT_CTRL	16 bit r/w	Ext. PHY Specific Ctrl *****/
1426 enum {
1427 	PHY_M_EC_ENA_BC_EXT = 1<<15, /* Enable Block Carr. Ext. (88E1111 only) */
1428 	PHY_M_EC_ENA_LIN_LB = 1<<14, /* Enable Line Loopback (88E1111 only) */
1429 
1430 	PHY_M_EC_DIS_LINK_P = 1<<12, /* Disable Link Pulses (88E1111 only) */
1431 	PHY_M_EC_M_DSC_MSK  = 3<<10, /* Bit 11..10:	Master Downshift Counter */
1432 					/* (88E1011 only) */
1433 	PHY_M_EC_S_DSC_MSK  = 3<<8,  /* Bit  9.. 8:	Slave  Downshift Counter */
1434 				       /* (88E1011 only) */
1435 	PHY_M_EC_M_DSC_MSK2  = 7<<9, /* Bit 11.. 9:	Master Downshift Counter */
1436 					/* (88E1111 only) */
1437 	PHY_M_EC_DOWN_S_ENA  = 1<<8, /* Downshift Enable (88E1111 only) */
1438 					/* !!! Errata in spec. (1 = disable) */
1439 	PHY_M_EC_RX_TIM_CT   = 1<<7, /* RGMII Rx Timing Control*/
1440 	PHY_M_EC_MAC_S_MSK   = 7<<4, /* Bit  6.. 4:	Def. MAC interface speed */
1441 	PHY_M_EC_FIB_AN_ENA  = 1<<3, /* Fiber Auto-Neg. Enable (88E1011S only) */
1442 	PHY_M_EC_DTE_D_ENA   = 1<<2, /* DTE Detect Enable (88E1111 only) */
1443 	PHY_M_EC_TX_TIM_CT   = 1<<1, /* RGMII Tx Timing Control */
1444 	PHY_M_EC_TRANS_DIS   = 1<<0, /* Transmitter Disable (88E1111 only) */};
1445 
1446 #define PHY_M_EC_M_DSC(x)	((u16)(x)<<10) /* 00=1x; 01=2x; 10=3x; 11=4x */
1447 #define PHY_M_EC_S_DSC(x)	((u16)(x)<<8) /* 00=dis; 01=1x; 10=2x; 11=3x */
1448 #define PHY_M_EC_MAC_S(x)	((u16)(x)<<4) /* 01X=0; 110=2.5; 111=25 (MHz) */
1449 
1450 #define PHY_M_EC_M_DSC_2(x)	((u16)(x)<<9) /* 000=1x; 001=2x; 010=3x; 011=4x */
1451 											/* 100=5x; 101=6x; 110=7x; 111=8x */
1452 enum {
1453 	MAC_TX_CLK_0_MHZ	= 2,
1454 	MAC_TX_CLK_2_5_MHZ	= 6,
1455 	MAC_TX_CLK_25_MHZ 	= 7,
1456 };
1457 
1458 /*****  PHY_MARV_LED_CTRL	16 bit r/w	LED Control Reg *****/
1459 enum {
1460 	PHY_M_LEDC_DIS_LED	= 1<<15, /* Disable LED */
1461 	PHY_M_LEDC_PULS_MSK	= 7<<12,/* Bit 14..12: Pulse Stretch Mask */
1462 	PHY_M_LEDC_F_INT	= 1<<11, /* Force Interrupt */
1463 	PHY_M_LEDC_BL_R_MSK	= 7<<8,/* Bit 10.. 8: Blink Rate Mask */
1464 	PHY_M_LEDC_DP_C_LSB	= 1<<7, /* Duplex Control (LSB, 88E1111 only) */
1465 	PHY_M_LEDC_TX_C_LSB	= 1<<6, /* Tx Control (LSB, 88E1111 only) */
1466 	PHY_M_LEDC_LK_C_MSK	= 7<<3,/* Bit  5.. 3: Link Control Mask */
1467 					/* (88E1111 only) */
1468 };
1469 #define PHY_M_LED_PULS_DUR(x)	(((u16)(x)<<12) & PHY_M_LEDC_PULS_MSK)
1470 #define PHY_M_LED_BLINK_RT(x)	(((u16)(x)<<8) & PHY_M_LEDC_BL_R_MSK)
1471 
1472 enum {
1473 	PHY_M_LEDC_LINK_MSK	= 3<<3, /* Bit  4.. 3: Link Control Mask */
1474 					/* (88E1011 only) */
1475 	PHY_M_LEDC_DP_CTRL	= 1<<2, /* Duplex Control */
1476 	PHY_M_LEDC_DP_C_MSB	= 1<<2, /* Duplex Control (MSB, 88E1111 only) */
1477 	PHY_M_LEDC_RX_CTRL	= 1<<1, /* Rx Activity / Link */
1478 	PHY_M_LEDC_TX_CTRL	= 1<<0, /* Tx Activity / Link */
1479 	PHY_M_LEDC_TX_C_MSB	= 1<<0, /* Tx Control (MSB, 88E1111 only) */
1480 };
1481 
1482 enum {
1483 	PULS_NO_STR	= 0, /* no pulse stretching */
1484 	PULS_21MS	= 1, /* 21 ms to 42 ms */
1485 	PULS_42MS	= 2, /* 42 ms to 84 ms */
1486 	PULS_84MS	= 3, /* 84 ms to 170 ms */
1487 	PULS_170MS	= 4, /* 170 ms to 340 ms */
1488 	PULS_340MS	= 5, /* 340 ms to 670 ms */
1489 	PULS_670MS	= 6, /* 670 ms to 1.3 s */
1490 	PULS_1300MS	= 7, /* 1.3 s to 2.7 s */
1491 };
1492 
1493 
1494 enum {
1495 	BLINK_42MS	= 0, /* 42 ms */
1496 	BLINK_84MS	= 1, /* 84 ms */
1497 	BLINK_170MS	= 2, /* 170 ms */
1498 	BLINK_340MS	= 3, /* 340 ms */
1499 	BLINK_670MS	= 4, /* 670 ms */
1500 };
1501 
1502 /*****  PHY_MARV_LED_OVER	16 bit r/w	Manual LED Override Reg *****/
1503 #define PHY_M_LED_MO_SGMII(x)	((x)<<14) /* Bit 15..14:  SGMII AN Timer */
1504 										/* Bit 13..12:	reserved */
1505 #define PHY_M_LED_MO_DUP(x)	((x)<<10) /* Bit 11..10:  Duplex */
1506 #define PHY_M_LED_MO_10(x)	((x)<<8) /* Bit  9.. 8:  Link 10 */
1507 #define PHY_M_LED_MO_100(x)	((x)<<6) /* Bit  7.. 6:  Link 100 */
1508 #define PHY_M_LED_MO_1000(x)	((x)<<4) /* Bit  5.. 4:  Link 1000 */
1509 #define PHY_M_LED_MO_RX(x)	((x)<<2) /* Bit  3.. 2:  Rx */
1510 #define PHY_M_LED_MO_TX(x)	((x)<<0) /* Bit  1.. 0:  Tx */
1511 
1512 enum {
1513 	MO_LED_NORM	= 0,
1514 	MO_LED_BLINK	= 1,
1515 	MO_LED_OFF	= 2,
1516 	MO_LED_ON	= 3,
1517 };
1518 
1519 /*****  PHY_MARV_EXT_CTRL_2	16 bit r/w	Ext. PHY Specific Ctrl 2 *****/
1520 enum {
1521 	PHY_M_EC2_FI_IMPED	= 1<<6, /* Fiber Input  Impedance */
1522 	PHY_M_EC2_FO_IMPED	= 1<<5, /* Fiber Output Impedance */
1523 	PHY_M_EC2_FO_M_CLK	= 1<<4, /* Fiber Mode Clock Enable */
1524 	PHY_M_EC2_FO_BOOST	= 1<<3, /* Fiber Output Boost */
1525 	PHY_M_EC2_FO_AM_MSK	= 7, /* Bit  2.. 0:	Fiber Output Amplitude */
1526 };
1527 
1528 /*****  PHY_MARV_EXT_P_STAT 16 bit r/w	Ext. PHY Specific Status *****/
1529 enum {
1530 	PHY_M_FC_AUTO_SEL	= 1<<15, /* Fiber/Copper Auto Sel. Dis. */
1531 	PHY_M_FC_AN_REG_ACC	= 1<<14, /* Fiber/Copper AN Reg. Access */
1532 	PHY_M_FC_RESOLUTION	= 1<<13, /* Fiber/Copper Resolution */
1533 	PHY_M_SER_IF_AN_BP	= 1<<12, /* Ser. IF AN Bypass Enable */
1534 	PHY_M_SER_IF_BP_ST	= 1<<11, /* Ser. IF AN Bypass Status */
1535 	PHY_M_IRQ_POLARITY	= 1<<10, /* IRQ polarity */
1536 	PHY_M_DIS_AUT_MED	= 1<<9, /* Disable Aut. Medium Reg. Selection */
1537 									/* (88E1111 only) */
1538 								/* Bit  9.. 4: reserved (88E1011 only) */
1539 	PHY_M_UNDOC1	= 1<<7, /* undocumented bit !! */
1540 	PHY_M_DTE_POW_STAT	= 1<<4, /* DTE Power Status (88E1111 only) */
1541 	PHY_M_MODE_MASK	= 0xf, /* Bit  3.. 0: copy of HWCFG MODE[3:0] */
1542 };
1543 
1544 /*****  PHY_MARV_CABLE_DIAG	16 bit r/o	Cable Diagnostic Reg *****/
1545 enum {
1546 	PHY_M_CABD_ENA_TEST	= 1<<15, /* Enable Test (Page 0) */
1547 	PHY_M_CABD_DIS_WAIT	= 1<<15, /* Disable Waiting Period (Page 1) */
1548 					/* (88E1111 only) */
1549 	PHY_M_CABD_STAT_MSK	= 3<<13, /* Bit 14..13: Status Mask */
1550 	PHY_M_CABD_AMPL_MSK	= 0x1f<<8, /* Bit 12.. 8: Amplitude Mask */
1551 					/* (88E1111 only) */
1552 	PHY_M_CABD_DIST_MSK	= 0xff, /* Bit  7.. 0: Distance Mask */
1553 };
1554 
1555 /* values for Cable Diagnostic Status (11=fail; 00=OK; 10=open; 01=short) */
1556 enum {
1557 	CABD_STAT_NORMAL= 0,
1558 	CABD_STAT_SHORT	= 1,
1559 	CABD_STAT_OPEN	= 2,
1560 	CABD_STAT_FAIL	= 3,
1561 };
1562 
1563 /* for 10/100 Fast Ethernet PHY (88E3082 only) */
1564 /*****  PHY_MARV_FE_LED_PAR		16 bit r/w	LED Parallel Select Reg. *****/
1565 									/* Bit 15..12: reserved (used internally) */
1566 enum {
1567 	PHY_M_FELP_LED2_MSK = 0xf<<8,	/* Bit 11.. 8: LED2 Mask (LINK) */
1568 	PHY_M_FELP_LED1_MSK = 0xf<<4,	/* Bit  7.. 4: LED1 Mask (ACT) */
1569 	PHY_M_FELP_LED0_MSK = 0xf, /* Bit  3.. 0: LED0 Mask (SPEED) */
1570 };
1571 
1572 #define PHY_M_FELP_LED2_CTRL(x)	(((x)<<8) & PHY_M_FELP_LED2_MSK)
1573 #define PHY_M_FELP_LED1_CTRL(x)	(((x)<<4) & PHY_M_FELP_LED1_MSK)
1574 #define PHY_M_FELP_LED0_CTRL(x)	(((x)<<0) & PHY_M_FELP_LED0_MSK)
1575 
1576 enum {
1577 	LED_PAR_CTRL_COLX	= 0x00,
1578 	LED_PAR_CTRL_ERROR	= 0x01,
1579 	LED_PAR_CTRL_DUPLEX	= 0x02,
1580 	LED_PAR_CTRL_DP_COL	= 0x03,
1581 	LED_PAR_CTRL_SPEED	= 0x04,
1582 	LED_PAR_CTRL_LINK	= 0x05,
1583 	LED_PAR_CTRL_TX		= 0x06,
1584 	LED_PAR_CTRL_RX		= 0x07,
1585 	LED_PAR_CTRL_ACT	= 0x08,
1586 	LED_PAR_CTRL_LNK_RX	= 0x09,
1587 	LED_PAR_CTRL_LNK_AC	= 0x0a,
1588 	LED_PAR_CTRL_ACT_BL	= 0x0b,
1589 	LED_PAR_CTRL_TX_BL	= 0x0c,
1590 	LED_PAR_CTRL_RX_BL	= 0x0d,
1591 	LED_PAR_CTRL_COL_BL	= 0x0e,
1592 	LED_PAR_CTRL_INACT	= 0x0f
1593 };
1594 
1595 /*****,PHY_MARV_FE_SPEC_2		16 bit r/w	Specific Control Reg. 2 *****/
1596 enum {
1597 	PHY_M_FESC_DIS_WAIT	= 1<<2, /* Disable TDR Waiting Period */
1598 	PHY_M_FESC_ENA_MCLK	= 1<<1, /* Enable MAC Rx Clock in sleep mode */
1599 	PHY_M_FESC_SEL_CL_A	= 1<<0, /* Select Class A driver (100B-TX) */
1600 };
1601 
1602 
1603 /*****  PHY_MARV_PHY_CTRL (page 3)		16 bit r/w	LED Control Reg. *****/
1604 enum {
1605 	PHY_M_LEDC_LOS_MSK	= 0xf<<12, /* Bit 15..12: LOS LED Ctrl. Mask */
1606 	PHY_M_LEDC_INIT_MSK	= 0xf<<8, /* Bit 11.. 8: INIT LED Ctrl. Mask */
1607 	PHY_M_LEDC_STA1_MSK	= 0xf<<4, /* Bit  7.. 4: STAT1 LED Ctrl. Mask */
1608 	PHY_M_LEDC_STA0_MSK	= 0xf, /* Bit  3.. 0: STAT0 LED Ctrl. Mask */
1609 };
1610 
1611 #define PHY_M_LEDC_LOS_CTRL(x)	(((x)<<12) & PHY_M_LEDC_LOS_MSK)
1612 #define PHY_M_LEDC_INIT_CTRL(x)	(((x)<<8) & PHY_M_LEDC_INIT_MSK)
1613 #define PHY_M_LEDC_STA1_CTRL(x)	(((x)<<4) & PHY_M_LEDC_STA1_MSK)
1614 #define PHY_M_LEDC_STA0_CTRL(x)	(((x)<<0) & PHY_M_LEDC_STA0_MSK)
1615 
1616 /* GMAC registers  */
1617 /* Port Registers */
1618 enum {
1619 	GM_GP_STAT	= 0x0000,	/* 16 bit r/o	General Purpose Status */
1620 	GM_GP_CTRL	= 0x0004,	/* 16 bit r/w	General Purpose Control */
1621 	GM_TX_CTRL	= 0x0008,	/* 16 bit r/w	Transmit Control Reg. */
1622 	GM_RX_CTRL	= 0x000c,	/* 16 bit r/w	Receive Control Reg. */
1623 	GM_TX_FLOW_CTRL	= 0x0010,	/* 16 bit r/w	Transmit Flow-Control */
1624 	GM_TX_PARAM	= 0x0014,	/* 16 bit r/w	Transmit Parameter Reg. */
1625 	GM_SERIAL_MODE	= 0x0018,	/* 16 bit r/w	Serial Mode Register */
1626 /* Source Address Registers */
1627 	GM_SRC_ADDR_1L	= 0x001c,	/* 16 bit r/w	Source Address 1 (low) */
1628 	GM_SRC_ADDR_1M	= 0x0020,	/* 16 bit r/w	Source Address 1 (middle) */
1629 	GM_SRC_ADDR_1H	= 0x0024,	/* 16 bit r/w	Source Address 1 (high) */
1630 	GM_SRC_ADDR_2L	= 0x0028,	/* 16 bit r/w	Source Address 2 (low) */
1631 	GM_SRC_ADDR_2M	= 0x002c,	/* 16 bit r/w	Source Address 2 (middle) */
1632 	GM_SRC_ADDR_2H	= 0x0030,	/* 16 bit r/w	Source Address 2 (high) */
1633 
1634 /* Multicast Address Hash Registers */
1635 	GM_MC_ADDR_H1	= 0x0034,	/* 16 bit r/w	Multicast Address Hash 1 */
1636 	GM_MC_ADDR_H2	= 0x0038,	/* 16 bit r/w	Multicast Address Hash 2 */
1637 	GM_MC_ADDR_H3	= 0x003c,	/* 16 bit r/w	Multicast Address Hash 3 */
1638 	GM_MC_ADDR_H4	= 0x0040,	/* 16 bit r/w	Multicast Address Hash 4 */
1639 
1640 /* Interrupt Source Registers */
1641 	GM_TX_IRQ_SRC	= 0x0044,	/* 16 bit r/o	Tx Overflow IRQ Source */
1642 	GM_RX_IRQ_SRC	= 0x0048,	/* 16 bit r/o	Rx Overflow IRQ Source */
1643 	GM_TR_IRQ_SRC	= 0x004c,	/* 16 bit r/o	Tx/Rx Over. IRQ Source */
1644 
1645 /* Interrupt Mask Registers */
1646 	GM_TX_IRQ_MSK	= 0x0050,	/* 16 bit r/w	Tx Overflow IRQ Mask */
1647 	GM_RX_IRQ_MSK	= 0x0054,	/* 16 bit r/w	Rx Overflow IRQ Mask */
1648 	GM_TR_IRQ_MSK	= 0x0058,	/* 16 bit r/w	Tx/Rx Over. IRQ Mask */
1649 
1650 /* Serial Management Interface (SMI) Registers */
1651 	GM_SMI_CTRL	= 0x0080,	/* 16 bit r/w	SMI Control Register */
1652 	GM_SMI_DATA	= 0x0084,	/* 16 bit r/w	SMI Data Register */
1653 	GM_PHY_ADDR	= 0x0088,	/* 16 bit r/w	GPHY Address Register */
1654 };
1655 
1656 /* MIB Counters */
1657 #define GM_MIB_CNT_BASE	0x0100		/* Base Address of MIB Counters */
1658 #define GM_MIB_CNT_SIZE	44		/* Number of MIB Counters */
1659 
1660 /*
1661  * MIB Counters base address definitions (low word) -
1662  * use offset 4 for access to high word	(32 bit r/o)
1663  */
1664 enum {
1665 	GM_RXF_UC_OK  = GM_MIB_CNT_BASE + 0,	/* Unicast Frames Received OK */
1666 	GM_RXF_BC_OK	= GM_MIB_CNT_BASE + 8,	/* Broadcast Frames Received OK */
1667 	GM_RXF_MPAUSE	= GM_MIB_CNT_BASE + 16,	/* Pause MAC Ctrl Frames Received */
1668 	GM_RXF_MC_OK	= GM_MIB_CNT_BASE + 24,	/* Multicast Frames Received OK */
1669 	GM_RXF_FCS_ERR	= GM_MIB_CNT_BASE + 32,	/* Rx Frame Check Seq. Error */
1670 	/* GM_MIB_CNT_BASE + 40:	reserved */
1671 	GM_RXO_OK_LO	= GM_MIB_CNT_BASE + 48,	/* Octets Received OK Low */
1672 	GM_RXO_OK_HI	= GM_MIB_CNT_BASE + 56,	/* Octets Received OK High */
1673 	GM_RXO_ERR_LO	= GM_MIB_CNT_BASE + 64,	/* Octets Received Invalid Low */
1674 	GM_RXO_ERR_HI	= GM_MIB_CNT_BASE + 72,	/* Octets Received Invalid High */
1675 	GM_RXF_SHT	= GM_MIB_CNT_BASE + 80,	/* Frames <64 Byte Received OK */
1676 	GM_RXE_FRAG	= GM_MIB_CNT_BASE + 88,	/* Frames <64 Byte Received with FCS Err */
1677 	GM_RXF_64B	= GM_MIB_CNT_BASE + 96,	/* 64 Byte Rx Frame */
1678 	GM_RXF_127B	= GM_MIB_CNT_BASE + 104,	/* 65-127 Byte Rx Frame */
1679 	GM_RXF_255B	= GM_MIB_CNT_BASE + 112,	/* 128-255 Byte Rx Frame */
1680 	GM_RXF_511B	= GM_MIB_CNT_BASE + 120,	/* 256-511 Byte Rx Frame */
1681 	GM_RXF_1023B	= GM_MIB_CNT_BASE + 128,	/* 512-1023 Byte Rx Frame */
1682 	GM_RXF_1518B	= GM_MIB_CNT_BASE + 136,	/* 1024-1518 Byte Rx Frame */
1683 	GM_RXF_MAX_SZ	= GM_MIB_CNT_BASE + 144,	/* 1519-MaxSize Byte Rx Frame */
1684 	GM_RXF_LNG_ERR	= GM_MIB_CNT_BASE + 152,	/* Rx Frame too Long Error */
1685 	GM_RXF_JAB_PKT	= GM_MIB_CNT_BASE + 160,	/* Rx Jabber Packet Frame */
1686 	/* GM_MIB_CNT_BASE + 168:	reserved */
1687 	GM_RXE_FIFO_OV	= GM_MIB_CNT_BASE + 176,	/* Rx FIFO overflow Event */
1688 	/* GM_MIB_CNT_BASE + 184:	reserved */
1689 	GM_TXF_UC_OK	= GM_MIB_CNT_BASE + 192,	/* Unicast Frames Xmitted OK */
1690 	GM_TXF_BC_OK	= GM_MIB_CNT_BASE + 200,	/* Broadcast Frames Xmitted OK */
1691 	GM_TXF_MPAUSE	= GM_MIB_CNT_BASE + 208,	/* Pause MAC Ctrl Frames Xmitted */
1692 	GM_TXF_MC_OK	= GM_MIB_CNT_BASE + 216,	/* Multicast Frames Xmitted OK */
1693 	GM_TXO_OK_LO	= GM_MIB_CNT_BASE + 224,	/* Octets Transmitted OK Low */
1694 	GM_TXO_OK_HI	= GM_MIB_CNT_BASE + 232,	/* Octets Transmitted OK High */
1695 	GM_TXF_64B	= GM_MIB_CNT_BASE + 240,	/* 64 Byte Tx Frame */
1696 	GM_TXF_127B	= GM_MIB_CNT_BASE + 248,	/* 65-127 Byte Tx Frame */
1697 	GM_TXF_255B	= GM_MIB_CNT_BASE + 256,	/* 128-255 Byte Tx Frame */
1698 	GM_TXF_511B	= GM_MIB_CNT_BASE + 264,	/* 256-511 Byte Tx Frame */
1699 	GM_TXF_1023B	= GM_MIB_CNT_BASE + 272,	/* 512-1023 Byte Tx Frame */
1700 	GM_TXF_1518B	= GM_MIB_CNT_BASE + 280,	/* 1024-1518 Byte Tx Frame */
1701 	GM_TXF_MAX_SZ	= GM_MIB_CNT_BASE + 288,	/* 1519-MaxSize Byte Tx Frame */
1702 
1703 	GM_TXF_COL	= GM_MIB_CNT_BASE + 304,	/* Tx Collision */
1704 	GM_TXF_LAT_COL	= GM_MIB_CNT_BASE + 312,	/* Tx Late Collision */
1705 	GM_TXF_ABO_COL	= GM_MIB_CNT_BASE + 320,	/* Tx aborted due to Exces. Col. */
1706 	GM_TXF_MUL_COL	= GM_MIB_CNT_BASE + 328,	/* Tx Multiple Collision */
1707 	GM_TXF_SNG_COL	= GM_MIB_CNT_BASE + 336,	/* Tx Single Collision */
1708 	GM_TXE_FIFO_UR	= GM_MIB_CNT_BASE + 344,	/* Tx FIFO Underrun Event */
1709 };
1710 
1711 /* GMAC Bit Definitions */
1712 /*	GM_GP_STAT	16 bit r/o	General Purpose Status Register */
1713 enum {
1714 	GM_GPSR_SPEED		= 1<<15, /* Bit 15:	Port Speed (1 = 100 Mbps) */
1715 	GM_GPSR_DUPLEX		= 1<<14, /* Bit 14:	Duplex Mode (1 = Full) */
1716 	GM_GPSR_FC_TX_DIS	= 1<<13, /* Bit 13:	Tx Flow-Control Mode Disabled */
1717 	GM_GPSR_LINK_UP		= 1<<12, /* Bit 12:	Link Up Status */
1718 	GM_GPSR_PAUSE		= 1<<11, /* Bit 11:	Pause State */
1719 	GM_GPSR_TX_ACTIVE	= 1<<10, /* Bit 10:	Tx in Progress */
1720 	GM_GPSR_EXC_COL		= 1<<9,	/* Bit  9:	Excessive Collisions Occurred */
1721 	GM_GPSR_LAT_COL		= 1<<8,	/* Bit  8:	Late Collisions Occurred */
1722 
1723 	GM_GPSR_PHY_ST_CH	= 1<<5,	/* Bit  5:	PHY Status Change */
1724 	GM_GPSR_GIG_SPEED	= 1<<4,	/* Bit  4:	Gigabit Speed (1 = 1000 Mbps) */
1725 	GM_GPSR_PART_MODE	= 1<<3,	/* Bit  3:	Partition mode */
1726 	GM_GPSR_FC_RX_DIS	= 1<<2,	/* Bit  2:	Rx Flow-Control Mode Disabled */
1727 	GM_GPSR_PROM_EN		= 1<<1,	/* Bit  1:	Promiscuous Mode Enabled */
1728 };
1729 
1730 /*	GM_GP_CTRL	16 bit r/w	General Purpose Control Register */
1731 enum {
1732 	GM_GPCR_PROM_ENA	= 1<<14,	/* Bit 14:	Enable Promiscuous Mode */
1733 	GM_GPCR_FC_TX_DIS	= 1<<13, /* Bit 13:	Disable Tx Flow-Control Mode */
1734 	GM_GPCR_TX_ENA		= 1<<12, /* Bit 12:	Enable Transmit */
1735 	GM_GPCR_RX_ENA		= 1<<11, /* Bit 11:	Enable Receive */
1736 	GM_GPCR_BURST_ENA	= 1<<10, /* Bit 10:	Enable Burst Mode */
1737 	GM_GPCR_LOOP_ENA	= 1<<9,	/* Bit  9:	Enable MAC Loopback Mode */
1738 	GM_GPCR_PART_ENA	= 1<<8,	/* Bit  8:	Enable Partition Mode */
1739 	GM_GPCR_GIGS_ENA	= 1<<7,	/* Bit  7:	Gigabit Speed (1000 Mbps) */
1740 	GM_GPCR_FL_PASS		= 1<<6,	/* Bit  6:	Force Link Pass */
1741 	GM_GPCR_DUP_FULL	= 1<<5,	/* Bit  5:	Full Duplex Mode */
1742 	GM_GPCR_FC_RX_DIS	= 1<<4,	/* Bit  4:	Disable Rx Flow-Control Mode */
1743 	GM_GPCR_SPEED_100	= 1<<3,   /* Bit  3:	Port Speed 100 Mbps */
1744 	GM_GPCR_AU_DUP_DIS	= 1<<2,	/* Bit  2:	Disable Auto-Update Duplex */
1745 	GM_GPCR_AU_FCT_DIS	= 1<<1,	/* Bit  1:	Disable Auto-Update Flow-C. */
1746 	GM_GPCR_AU_SPD_DIS	= 1<<0,	/* Bit  0:	Disable Auto-Update Speed */
1747 };
1748 
1749 #define GM_GPCR_SPEED_1000	(GM_GPCR_GIGS_ENA | GM_GPCR_SPEED_100)
1750 #define GM_GPCR_AU_ALL_DIS	(GM_GPCR_AU_DUP_DIS | GM_GPCR_AU_FCT_DIS|GM_GPCR_AU_SPD_DIS)
1751 
1752 /*	GM_TX_CTRL			16 bit r/w	Transmit Control Register */
1753 enum {
1754 	GM_TXCR_FORCE_JAM	= 1<<15, /* Bit 15:	Force Jam / Flow-Control */
1755 	GM_TXCR_CRC_DIS		= 1<<14, /* Bit 14:	Disable insertion of CRC */
1756 	GM_TXCR_PAD_DIS		= 1<<13, /* Bit 13:	Disable padding of packets */
1757 	GM_TXCR_COL_THR_MSK	= 7<<10, /* Bit 12..10:	Collision Threshold */
1758 };
1759 
1760 #define TX_COL_THR(x)		(((x)<<10) & GM_TXCR_COL_THR_MSK)
1761 #define TX_COL_DEF		0x04	/* late collision after 64 byte */
1762 
1763 /*	GM_RX_CTRL			16 bit r/w	Receive Control Register */
1764 enum {
1765 	GM_RXCR_UCF_ENA	= 1<<15, /* Bit 15:	Enable Unicast filtering */
1766 	GM_RXCR_MCF_ENA	= 1<<14, /* Bit 14:	Enable Multicast filtering */
1767 	GM_RXCR_CRC_DIS	= 1<<13, /* Bit 13:	Remove 4-byte CRC */
1768 	GM_RXCR_PASS_FC	= 1<<12, /* Bit 12:	Pass FC packets to FIFO */
1769 };
1770 
1771 /*	GM_TX_PARAM		16 bit r/w	Transmit Parameter Register */
1772 enum {
1773 	GM_TXPA_JAMLEN_MSK	= 0x03<<14,	/* Bit 15..14:	Jam Length */
1774 	GM_TXPA_JAMIPG_MSK	= 0x1f<<9,	/* Bit 13..9:	Jam IPG */
1775 	GM_TXPA_JAMDAT_MSK	= 0x1f<<4,	/* Bit  8..4:	IPG Jam to Data */
1776 
1777 	TX_JAM_LEN_DEF		= 0x03,
1778 	TX_JAM_IPG_DEF		= 0x0b,
1779 	TX_IPG_JAM_DEF		= 0x1c,
1780 };
1781 
1782 #define TX_JAM_LEN_VAL(x)	(((x)<<14) & GM_TXPA_JAMLEN_MSK)
1783 #define TX_JAM_IPG_VAL(x)	(((x)<<9)  & GM_TXPA_JAMIPG_MSK)
1784 #define TX_IPG_JAM_DATA(x)	(((x)<<4)  & GM_TXPA_JAMDAT_MSK)
1785 
1786 
1787 /*	GM_SERIAL_MODE			16 bit r/w	Serial Mode Register */
1788 enum {
1789 	GM_SMOD_DATABL_MSK	= 0x1f<<11, /* Bit 15..11:	Data Blinder (r/o) */
1790 	GM_SMOD_LIMIT_4		= 1<<10, /* Bit 10:	4 consecutive Tx trials */
1791 	GM_SMOD_VLAN_ENA	= 1<<9,	/* Bit  9:	Enable VLAN  (Max. Frame Len) */
1792 	GM_SMOD_JUMBO_ENA	= 1<<8,	/* Bit  8:	Enable Jumbo (Max. Frame Len) */
1793 	 GM_SMOD_IPG_MSK	= 0x1f	/* Bit 4..0:	Inter-Packet Gap (IPG) */
1794 };
1795 
1796 #define DATA_BLIND_VAL(x)	(((x)<<11) & GM_SMOD_DATABL_MSK)
1797 #define DATA_BLIND_DEF		0x04
1798 
1799 #define IPG_DATA_VAL(x)		(x & GM_SMOD_IPG_MSK)
1800 #define IPG_DATA_DEF		0x1e
1801 
1802 /*	GM_SMI_CTRL			16 bit r/w	SMI Control Register */
1803 enum {
1804 	GM_SMI_CT_PHY_A_MSK	= 0x1f<<11, /* Bit 15..11:	PHY Device Address */
1805 	GM_SMI_CT_REG_A_MSK	= 0x1f<<6, /* Bit 10.. 6:	PHY Register Address */
1806 	GM_SMI_CT_OP_RD		= 1<<5,	/* Bit  5:	OpCode Read (0=Write)*/
1807 	GM_SMI_CT_RD_VAL	= 1<<4,	/* Bit  4:	Read Valid (Read completed) */
1808 	GM_SMI_CT_BUSY		= 1<<3,	/* Bit  3:	Busy (Operation in progress) */
1809 };
1810 
1811 #define GM_SMI_CT_PHY_AD(x)	(((x)<<11) & GM_SMI_CT_PHY_A_MSK)
1812 #define GM_SMI_CT_REG_AD(x)	(((x)<<6) & GM_SMI_CT_REG_A_MSK)
1813 
1814 /*	GM_PHY_ADDR				16 bit r/w	GPHY Address Register */
1815 enum {
1816 	GM_PAR_MIB_CLR	= 1<<5,	/* Bit  5:	Set MIB Clear Counter Mode */
1817 	GM_PAR_MIB_TST	= 1<<4,	/* Bit  4:	MIB Load Counter (Test Mode) */
1818 };
1819 
1820 /* Receive Frame Status Encoding */
1821 enum {
1822 	GMR_FS_LEN	= 0xffff<<16, /* Bit 31..16:	Rx Frame Length */
1823 	GMR_FS_LEN_SHIFT = 16,
1824 	GMR_FS_VLAN	= 1<<13, /* Bit 13:	VLAN Packet */
1825 	GMR_FS_JABBER	= 1<<12, /* Bit 12:	Jabber Packet */
1826 	GMR_FS_UN_SIZE	= 1<<11, /* Bit 11:	Undersize Packet */
1827 	GMR_FS_MC	= 1<<10, /* Bit 10:	Multicast Packet */
1828 	GMR_FS_BC	= 1<<9, /* Bit  9:	Broadcast Packet */
1829 	GMR_FS_RX_OK	= 1<<8, /* Bit  8:	Receive OK (Good Packet) */
1830 	GMR_FS_GOOD_FC	= 1<<7, /* Bit  7:	Good Flow-Control Packet */
1831 	GMR_FS_BAD_FC	= 1<<6, /* Bit  6:	Bad  Flow-Control Packet */
1832 	GMR_FS_MII_ERR	= 1<<5, /* Bit  5:	MII Error */
1833 	GMR_FS_LONG_ERR	= 1<<4, /* Bit  4:	Too Long Packet */
1834 	GMR_FS_FRAGMENT	= 1<<3, /* Bit  3:	Fragment */
1835 
1836 	GMR_FS_CRC_ERR	= 1<<1, /* Bit  1:	CRC Error */
1837 	GMR_FS_RX_FF_OV	= 1<<0, /* Bit  0:	Rx FIFO Overflow */
1838 
1839 /*
1840  * GMR_FS_ANY_ERR (analogous to XMR_FS_ANY_ERR)
1841  */
1842 	GMR_FS_ANY_ERR	= GMR_FS_CRC_ERR | GMR_FS_LONG_ERR |
1843 		  	  GMR_FS_MII_ERR | GMR_FS_BAD_FC | GMR_FS_GOOD_FC |
1844 			  GMR_FS_JABBER,
1845 /* Rx GMAC FIFO Flush Mask (default) */
1846 	RX_FF_FL_DEF_MSK = GMR_FS_CRC_ERR | GMR_FS_RX_FF_OV |GMR_FS_MII_ERR |
1847 			   GMR_FS_BAD_FC |  GMR_FS_UN_SIZE | GMR_FS_JABBER,
1848 };
1849 
1850 /*	RX_GMF_CTRL_T	32 bit	Rx GMAC FIFO Control/Test */
1851 enum {
1852 	GMF_WP_TST_ON	= 1<<14,	/* Write Pointer Test On */
1853 	GMF_WP_TST_OFF	= 1<<13,	/* Write Pointer Test Off */
1854 	GMF_WP_STEP	= 1<<12,	/* Write Pointer Step/Increment */
1855 
1856 	GMF_RP_TST_ON	= 1<<10,	/* Read Pointer Test On */
1857 	GMF_RP_TST_OFF	= 1<<9,		/* Read Pointer Test Off */
1858 	GMF_RP_STEP	= 1<<8,		/* Read Pointer Step/Increment */
1859 	GMF_RX_F_FL_ON	= 1<<7,		/* Rx FIFO Flush Mode On */
1860 	GMF_RX_F_FL_OFF	= 1<<6,		/* Rx FIFO Flush Mode Off */
1861 	GMF_CLI_RX_FO	= 1<<5,		/* Clear IRQ Rx FIFO Overrun */
1862 	GMF_CLI_RX_FC	= 1<<4,		/* Clear IRQ Rx Frame Complete */
1863 	GMF_OPER_ON	= 1<<3,		/* Operational Mode On */
1864 	GMF_OPER_OFF	= 1<<2,		/* Operational Mode Off */
1865 	GMF_RST_CLR	= 1<<1,		/* Clear GMAC FIFO Reset */
1866 	GMF_RST_SET	= 1<<0,		/* Set   GMAC FIFO Reset */
1867 
1868 	RX_GMF_FL_THR_DEF = 0xa,	/* flush threshold (default) */
1869 };
1870 
1871 
1872 /*	TX_GMF_CTRL_T	32 bit	Tx GMAC FIFO Control/Test */
1873 enum {
1874 	GMF_WSP_TST_ON	= 1<<18, /* Write Shadow Pointer Test On */
1875 	GMF_WSP_TST_OFF	= 1<<17, /* Write Shadow Pointer Test Off */
1876 	GMF_WSP_STEP	= 1<<16, /* Write Shadow Pointer Step/Increment */
1877 
1878 	GMF_CLI_TX_FU	= 1<<6,	/* Clear IRQ Tx FIFO Underrun */
1879 	GMF_CLI_TX_FC	= 1<<5,	/* Clear IRQ Tx Frame Complete */
1880 	GMF_CLI_TX_PE	= 1<<4,	/* Clear IRQ Tx Parity Error */
1881 };
1882 
1883 /*	GMAC_TI_ST_CTRL	 8 bit	Time Stamp Timer Ctrl Reg (YUKON only) */
1884 enum {
1885 	GMT_ST_START	= 1<<2,	/* Start Time Stamp Timer */
1886 	GMT_ST_STOP	= 1<<1,	/* Stop  Time Stamp Timer */
1887 	GMT_ST_CLR_IRQ	= 1<<0,	/* Clear Time Stamp Timer IRQ */
1888 };
1889 
1890 /*	GMAC_CTRL		32 bit	GMAC Control Reg (YUKON only) */
1891 enum {
1892 	GMC_H_BURST_ON	= 1<<7,	/* Half Duplex Burst Mode On */
1893 	GMC_H_BURST_OFF	= 1<<6,	/* Half Duplex Burst Mode Off */
1894 	GMC_F_LOOPB_ON	= 1<<5,	/* FIFO Loopback On */
1895 	GMC_F_LOOPB_OFF	= 1<<4,	/* FIFO Loopback Off */
1896 	GMC_PAUSE_ON	= 1<<3,	/* Pause On */
1897 	GMC_PAUSE_OFF	= 1<<2,	/* Pause Off */
1898 	GMC_RST_CLR	= 1<<1,	/* Clear GMAC Reset */
1899 	GMC_RST_SET	= 1<<0,	/* Set   GMAC Reset */
1900 };
1901 
1902 /*	GPHY_CTRL		32 bit	GPHY Control Reg (YUKON only) */
1903 enum {
1904 	GPC_SEL_BDT	= 1<<28, /* Select Bi-Dir. Transfer for MDC/MDIO */
1905 	GPC_INT_POL_HI	= 1<<27, /* IRQ Polarity is Active HIGH */
1906 	GPC_75_OHM	= 1<<26, /* Use 75 Ohm Termination instead of 50 */
1907 	GPC_DIS_FC	= 1<<25, /* Disable Automatic Fiber/Copper Detection */
1908 	GPC_DIS_SLEEP	= 1<<24, /* Disable Energy Detect */
1909 	GPC_HWCFG_M_3	= 1<<23, /* HWCFG_MODE[3] */
1910 	GPC_HWCFG_M_2	= 1<<22, /* HWCFG_MODE[2] */
1911 	GPC_HWCFG_M_1	= 1<<21, /* HWCFG_MODE[1] */
1912 	GPC_HWCFG_M_0	= 1<<20, /* HWCFG_MODE[0] */
1913 	GPC_ANEG_0	= 1<<19, /* ANEG[0] */
1914 	GPC_ENA_XC	= 1<<18, /* Enable MDI crossover */
1915 	GPC_DIS_125	= 1<<17, /* Disable 125 MHz clock */
1916 	GPC_ANEG_3	= 1<<16, /* ANEG[3] */
1917 	GPC_ANEG_2	= 1<<15, /* ANEG[2] */
1918 	GPC_ANEG_1	= 1<<14, /* ANEG[1] */
1919 	GPC_ENA_PAUSE	= 1<<13, /* Enable Pause (SYM_OR_REM) */
1920 	GPC_PHYADDR_4	= 1<<12, /* Bit 4 of Phy Addr */
1921 	GPC_PHYADDR_3	= 1<<11, /* Bit 3 of Phy Addr */
1922 	GPC_PHYADDR_2	= 1<<10, /* Bit 2 of Phy Addr */
1923 	GPC_PHYADDR_1	= 1<<9,	 /* Bit 1 of Phy Addr */
1924 	GPC_PHYADDR_0	= 1<<8,	 /* Bit 0 of Phy Addr */
1925 						/* Bits  7..2:	reserved */
1926 	GPC_RST_CLR	= 1<<1,	/* Clear GPHY Reset */
1927 	GPC_RST_SET	= 1<<0,	/* Set   GPHY Reset */
1928 };
1929 
1930 #define GPC_HWCFG_GMII_COP (GPC_HWCFG_M_3|GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1931 #define GPC_HWCFG_GMII_FIB (GPC_HWCFG_M_2 | GPC_HWCFG_M_1 | GPC_HWCFG_M_0)
1932 #define GPC_ANEG_ADV_ALL_M  (GPC_ANEG_3 | GPC_ANEG_2 | GPC_ANEG_1 | GPC_ANEG_0)
1933 
1934 /* forced speed and duplex mode (don't mix with other ANEG bits) */
1935 #define GPC_FRC10MBIT_HALF	0
1936 #define GPC_FRC10MBIT_FULL	GPC_ANEG_0
1937 #define GPC_FRC100MBIT_HALF	GPC_ANEG_1
1938 #define GPC_FRC100MBIT_FULL	(GPC_ANEG_0 | GPC_ANEG_1)
1939 
1940 /* auto-negotiation with limited advertised speeds */
1941 /* mix only with master/slave settings (for copper) */
1942 #define GPC_ADV_1000_HALF	GPC_ANEG_2
1943 #define GPC_ADV_1000_FULL	GPC_ANEG_3
1944 #define GPC_ADV_ALL		(GPC_ANEG_2 | GPC_ANEG_3)
1945 
1946 /* master/slave settings */
1947 /* only for copper with 1000 Mbps */
1948 #define GPC_FORCE_MASTER	0
1949 #define GPC_FORCE_SLAVE		GPC_ANEG_0
1950 #define GPC_PREF_MASTER		GPC_ANEG_1
1951 #define GPC_PREF_SLAVE		(GPC_ANEG_1 | GPC_ANEG_0)
1952 
1953 /*	GMAC_IRQ_SRC	 8 bit	GMAC Interrupt Source Reg (YUKON only) */
1954 /*	GMAC_IRQ_MSK	 8 bit	GMAC Interrupt Mask   Reg (YUKON only) */
1955 enum {
1956 	GM_IS_TX_CO_OV	= 1<<5,	/* Transmit Counter Overflow IRQ */
1957 	GM_IS_RX_CO_OV	= 1<<4,	/* Receive Counter Overflow IRQ */
1958 	GM_IS_TX_FF_UR	= 1<<3,	/* Transmit FIFO Underrun */
1959 	GM_IS_TX_COMPL	= 1<<2,	/* Frame Transmission Complete */
1960 	GM_IS_RX_FF_OR	= 1<<1,	/* Receive FIFO Overrun */
1961 	GM_IS_RX_COMPL	= 1<<0,	/* Frame Reception Complete */
1962 
1963 #define GMAC_DEF_MSK	(GM_IS_RX_FF_OR | GM_IS_TX_FF_UR)
1964 
1965 /*	GMAC_LINK_CTRL	16 bit	GMAC Link Control Reg (YUKON only) */
1966 						/* Bits 15.. 2:	reserved */
1967 	GMLC_RST_CLR	= 1<<1,	/* Clear GMAC Link Reset */
1968 	GMLC_RST_SET	= 1<<0,	/* Set   GMAC Link Reset */
1969 
1970 
1971 /*	WOL_CTRL_STAT	16 bit	WOL Control/Status Reg */
1972 	WOL_CTL_LINK_CHG_OCC		= 1<<15,
1973 	WOL_CTL_MAGIC_PKT_OCC		= 1<<14,
1974 	WOL_CTL_PATTERN_OCC		= 1<<13,
1975 	WOL_CTL_CLEAR_RESULT		= 1<<12,
1976 	WOL_CTL_ENA_PME_ON_LINK_CHG	= 1<<11,
1977 	WOL_CTL_DIS_PME_ON_LINK_CHG	= 1<<10,
1978 	WOL_CTL_ENA_PME_ON_MAGIC_PKT	= 1<<9,
1979 	WOL_CTL_DIS_PME_ON_MAGIC_PKT	= 1<<8,
1980 	WOL_CTL_ENA_PME_ON_PATTERN	= 1<<7,
1981 	WOL_CTL_DIS_PME_ON_PATTERN	= 1<<6,
1982 	WOL_CTL_ENA_LINK_CHG_UNIT	= 1<<5,
1983 	WOL_CTL_DIS_LINK_CHG_UNIT	= 1<<4,
1984 	WOL_CTL_ENA_MAGIC_PKT_UNIT	= 1<<3,
1985 	WOL_CTL_DIS_MAGIC_PKT_UNIT	= 1<<2,
1986 	WOL_CTL_ENA_PATTERN_UNIT	= 1<<1,
1987 	WOL_CTL_DIS_PATTERN_UNIT	= 1<<0,
1988 };
1989 
1990 #define WOL_CTL_DEFAULT				\
1991 	(WOL_CTL_DIS_PME_ON_LINK_CHG |	\
1992 	WOL_CTL_DIS_PME_ON_PATTERN |	\
1993 	WOL_CTL_DIS_PME_ON_MAGIC_PKT |	\
1994 	WOL_CTL_DIS_LINK_CHG_UNIT |		\
1995 	WOL_CTL_DIS_PATTERN_UNIT |		\
1996 	WOL_CTL_DIS_MAGIC_PKT_UNIT)
1997 
1998 /*	WOL_MATCH_CTL	 8 bit	WOL Match Control Reg */
1999 #define WOL_CTL_PATT_ENA(x)	(1 << (x))
2000 
2001 
2002 /* XMAC II registers				      */
2003 enum {
2004 	XM_MMU_CMD	= 0x0000, /* 16 bit r/w	MMU Command Register */
2005 	XM_POFF		= 0x0008, /* 32 bit r/w	Packet Offset Register */
2006 	XM_BURST	= 0x000c, /* 32 bit r/w	Burst Register for half duplex*/
2007 	XM_1L_VLAN_TAG	= 0x0010, /* 16 bit r/w	One Level VLAN Tag ID */
2008 	XM_2L_VLAN_TAG	= 0x0014, /* 16 bit r/w	Two Level VLAN Tag ID */
2009 	XM_TX_CMD	= 0x0020, /* 16 bit r/w	Transmit Command Register */
2010 	XM_TX_RT_LIM	= 0x0024, /* 16 bit r/w	Transmit Retry Limit Register */
2011 	XM_TX_STIME	= 0x0028, /* 16 bit r/w	Transmit Slottime Register */
2012 	XM_TX_IPG	= 0x002c, /* 16 bit r/w	Transmit Inter Packet Gap */
2013 	XM_RX_CMD	= 0x0030, /* 16 bit r/w	Receive Command Register */
2014 	XM_PHY_ADDR	= 0x0034, /* 16 bit r/w	PHY Address Register */
2015 	XM_PHY_DATA	= 0x0038, /* 16 bit r/w	PHY Data Register */
2016 	XM_GP_PORT	= 0x0040, /* 32 bit r/w	General Purpose Port Register */
2017 	XM_IMSK		= 0x0044, /* 16 bit r/w	Interrupt Mask Register */
2018 	XM_ISRC		= 0x0048, /* 16 bit r/o	Interrupt Status Register */
2019 	XM_HW_CFG	= 0x004c, /* 16 bit r/w	Hardware Config Register */
2020 	XM_TX_LO_WM	= 0x0060, /* 16 bit r/w	Tx FIFO Low Water Mark */
2021 	XM_TX_HI_WM	= 0x0062, /* 16 bit r/w	Tx FIFO High Water Mark */
2022 	XM_TX_THR	= 0x0064, /* 16 bit r/w	Tx Request Threshold */
2023 	XM_HT_THR	= 0x0066, /* 16 bit r/w	Host Request Threshold */
2024 	XM_PAUSE_DA	= 0x0068, /* NA reg r/w	Pause Destination Address */
2025 	XM_CTL_PARA	= 0x0070, /* 32 bit r/w	Control Parameter Register */
2026 	XM_MAC_OPCODE	= 0x0074, /* 16 bit r/w	Opcode for MAC control frames */
2027 	XM_MAC_PTIME	= 0x0076, /* 16 bit r/w	Pause time for MAC ctrl frames*/
2028 	XM_TX_STAT	= 0x0078, /* 32 bit r/o	Tx Status LIFO Register */
2029 
2030 	XM_EXM_START	= 0x0080, /* r/w	Start Address of the EXM Regs */
2031 #define XM_EXM(reg)	(XM_EXM_START + ((reg) << 3))
2032 };
2033 
2034 enum {
2035 	XM_SRC_CHK	= 0x0100, /* NA reg r/w	Source Check Address Register */
2036 	XM_SA		= 0x0108, /* NA reg r/w	Station Address Register */
2037 	XM_HSM		= 0x0110, /* 64 bit r/w	Hash Match Address Registers */
2038 	XM_RX_LO_WM	= 0x0118, /* 16 bit r/w	Receive Low Water Mark */
2039 	XM_RX_HI_WM	= 0x011a, /* 16 bit r/w	Receive High Water Mark */
2040 	XM_RX_THR	= 0x011c, /* 32 bit r/w	Receive Request Threshold */
2041 	XM_DEV_ID	= 0x0120, /* 32 bit r/o	Device ID Register */
2042 	XM_MODE		= 0x0124, /* 32 bit r/w	Mode Register */
2043 	XM_LSA		= 0x0128, /* NA reg r/o	Last Source Register */
2044 	XM_TS_READ	= 0x0130, /* 32 bit r/o	Time Stamp Read Register */
2045 	XM_TS_LOAD	= 0x0134, /* 32 bit r/o	Time Stamp Load Value */
2046 	XM_STAT_CMD	= 0x0200, /* 16 bit r/w	Statistics Command Register */
2047 	XM_RX_CNT_EV	= 0x0204, /* 32 bit r/o	Rx Counter Event Register */
2048 	XM_TX_CNT_EV	= 0x0208, /* 32 bit r/o	Tx Counter Event Register */
2049 	XM_RX_EV_MSK	= 0x020c, /* 32 bit r/w	Rx Counter Event Mask */
2050 	XM_TX_EV_MSK	= 0x0210, /* 32 bit r/w	Tx Counter Event Mask */
2051 	XM_TXF_OK	= 0x0280, /* 32 bit r/o	Frames Transmitted OK Conuter */
2052 	XM_TXO_OK_HI	= 0x0284, /* 32 bit r/o	Octets Transmitted OK High Cnt*/
2053 	XM_TXO_OK_LO	= 0x0288, /* 32 bit r/o	Octets Transmitted OK Low Cnt */
2054 	XM_TXF_BC_OK	= 0x028c, /* 32 bit r/o	Broadcast Frames Xmitted OK */
2055 	XM_TXF_MC_OK	= 0x0290, /* 32 bit r/o	Multicast Frames Xmitted OK */
2056 	XM_TXF_UC_OK	= 0x0294, /* 32 bit r/o	Unicast Frames Xmitted OK */
2057 	XM_TXF_LONG	= 0x0298, /* 32 bit r/o	Tx Long Frame Counter */
2058 	XM_TXE_BURST	= 0x029c, /* 32 bit r/o	Tx Burst Event Counter */
2059 	XM_TXF_MPAUSE	= 0x02a0, /* 32 bit r/o	Tx Pause MAC Ctrl Frame Cnt */
2060 	XM_TXF_MCTRL	= 0x02a4, /* 32 bit r/o	Tx MAC Ctrl Frame Counter */
2061 	XM_TXF_SNG_COL	= 0x02a8, /* 32 bit r/o	Tx Single Collision Counter */
2062 	XM_TXF_MUL_COL	= 0x02ac, /* 32 bit r/o	Tx Multiple Collision Counter */
2063 	XM_TXF_ABO_COL	= 0x02b0, /* 32 bit r/o	Tx aborted due to Exces. Col. */
2064 	XM_TXF_LAT_COL	= 0x02b4, /* 32 bit r/o	Tx Late Collision Counter */
2065 	XM_TXF_DEF	= 0x02b8, /* 32 bit r/o	Tx Deferred Frame Counter */
2066 	XM_TXF_EX_DEF	= 0x02bc, /* 32 bit r/o	Tx Excessive Deferall Counter */
2067 	XM_TXE_FIFO_UR	= 0x02c0, /* 32 bit r/o	Tx FIFO Underrun Event Cnt */
2068 	XM_TXE_CS_ERR	= 0x02c4, /* 32 bit r/o	Tx Carrier Sense Error Cnt */
2069 	XM_TXP_UTIL	= 0x02c8, /* 32 bit r/o	Tx Utilization in % */
2070 	XM_TXF_64B	= 0x02d0, /* 32 bit r/o	64 Byte Tx Frame Counter */
2071 	XM_TXF_127B	= 0x02d4, /* 32 bit r/o	65-127 Byte Tx Frame Counter */
2072 	XM_TXF_255B	= 0x02d8, /* 32 bit r/o	128-255 Byte Tx Frame Counter */
2073 	XM_TXF_511B	= 0x02dc, /* 32 bit r/o	256-511 Byte Tx Frame Counter */
2074 	XM_TXF_1023B	= 0x02e0, /* 32 bit r/o	512-1023 Byte Tx Frame Counter*/
2075 	XM_TXF_MAX_SZ	= 0x02e4, /* 32 bit r/o	1024-MaxSize Byte Tx Frame Cnt*/
2076 	XM_RXF_OK	= 0x0300, /* 32 bit r/o	Frames Received OK */
2077 	XM_RXO_OK_HI	= 0x0304, /* 32 bit r/o	Octets Received OK High Cnt */
2078 	XM_RXO_OK_LO	= 0x0308, /* 32 bit r/o	Octets Received OK Low Counter*/
2079 	XM_RXF_BC_OK	= 0x030c, /* 32 bit r/o	Broadcast Frames Received OK */
2080 	XM_RXF_MC_OK	= 0x0310, /* 32 bit r/o	Multicast Frames Received OK */
2081 	XM_RXF_UC_OK	= 0x0314, /* 32 bit r/o	Unicast Frames Received OK */
2082 	XM_RXF_MPAUSE	= 0x0318, /* 32 bit r/o	Rx Pause MAC Ctrl Frame Cnt */
2083 	XM_RXF_MCTRL	= 0x031c, /* 32 bit r/o	Rx MAC Ctrl Frame Counter */
2084 	XM_RXF_INV_MP	= 0x0320, /* 32 bit r/o	Rx invalid Pause Frame Cnt */
2085 	XM_RXF_INV_MOC	= 0x0324, /* 32 bit r/o	Rx Frames with inv. MAC Opcode*/
2086 	XM_RXE_BURST	= 0x0328, /* 32 bit r/o	Rx Burst Event Counter */
2087 	XM_RXE_FMISS	= 0x032c, /* 32 bit r/o	Rx Missed Frames Event Cnt */
2088 	XM_RXF_FRA_ERR	= 0x0330, /* 32 bit r/o	Rx Framing Error Counter */
2089 	XM_RXE_FIFO_OV	= 0x0334, /* 32 bit r/o	Rx FIFO overflow Event Cnt */
2090 	XM_RXF_JAB_PKT	= 0x0338, /* 32 bit r/o	Rx Jabber Packet Frame Cnt */
2091 	XM_RXE_CAR_ERR	= 0x033c, /* 32 bit r/o	Rx Carrier Event Error Cnt */
2092 	XM_RXF_LEN_ERR	= 0x0340, /* 32 bit r/o	Rx in Range Length Error */
2093 	XM_RXE_SYM_ERR	= 0x0344, /* 32 bit r/o	Rx Symbol Error Counter */
2094 	XM_RXE_SHT_ERR	= 0x0348, /* 32 bit r/o	Rx Short Event Error Cnt */
2095 	XM_RXE_RUNT	= 0x034c, /* 32 bit r/o	Rx Runt Event Counter */
2096 	XM_RXF_LNG_ERR	= 0x0350, /* 32 bit r/o	Rx Frame too Long Error Cnt */
2097 	XM_RXF_FCS_ERR	= 0x0354, /* 32 bit r/o	Rx Frame Check Seq. Error Cnt */
2098 	XM_RXF_CEX_ERR	= 0x035c, /* 32 bit r/o	Rx Carrier Ext Error Frame Cnt*/
2099 	XM_RXP_UTIL	= 0x0360, /* 32 bit r/o	Rx Utilization in % */
2100 	XM_RXF_64B	= 0x0368, /* 32 bit r/o	64 Byte Rx Frame Counter */
2101 	XM_RXF_127B	= 0x036c, /* 32 bit r/o	65-127 Byte Rx Frame Counter */
2102 	XM_RXF_255B	= 0x0370, /* 32 bit r/o	128-255 Byte Rx Frame Counter */
2103 	XM_RXF_511B	= 0x0374, /* 32 bit r/o	256-511 Byte Rx Frame Counter */
2104 	XM_RXF_1023B	= 0x0378, /* 32 bit r/o	512-1023 Byte Rx Frame Counter*/
2105 	XM_RXF_MAX_SZ	= 0x037c, /* 32 bit r/o	1024-MaxSize Byte Rx Frame Cnt*/
2106 };
2107 
2108 /*	XM_MMU_CMD	16 bit r/w	MMU Command Register */
2109 enum {
2110 	XM_MMU_PHY_RDY	= 1<<12, /* Bit 12:	PHY Read Ready */
2111 	XM_MMU_PHY_BUSY	= 1<<11, /* Bit 11:	PHY Busy */
2112 	XM_MMU_IGN_PF	= 1<<10, /* Bit 10:	Ignore Pause Frame */
2113 	XM_MMU_MAC_LB	= 1<<9,	 /* Bit  9:	Enable MAC Loopback */
2114 	XM_MMU_FRC_COL	= 1<<7,	 /* Bit  7:	Force Collision */
2115 	XM_MMU_SIM_COL	= 1<<6,	 /* Bit  6:	Simulate Collision */
2116 	XM_MMU_NO_PRE	= 1<<5,	 /* Bit  5:	No MDIO Preamble */
2117 	XM_MMU_GMII_FD	= 1<<4,	 /* Bit  4:	GMII uses Full Duplex */
2118 	XM_MMU_RAT_CTRL	= 1<<3,	 /* Bit  3:	Enable Rate Control */
2119 	XM_MMU_GMII_LOOP= 1<<2,	 /* Bit  2:	PHY is in Loopback Mode */
2120 	XM_MMU_ENA_RX	= 1<<1,	 /* Bit  1:	Enable Receiver */
2121 	XM_MMU_ENA_TX	= 1<<0,	 /* Bit  0:	Enable Transmitter */
2122 };
2123 
2124 
2125 /*	XM_TX_CMD	16 bit r/w	Transmit Command Register */
2126 enum {
2127 	XM_TX_BK2BK	= 1<<6,	/* Bit  6:	Ignor Carrier Sense (Tx Bk2Bk)*/
2128 	XM_TX_ENC_BYP	= 1<<5,	/* Bit  5:	Set Encoder in Bypass Mode */
2129 	XM_TX_SAM_LINE	= 1<<4,	/* Bit  4: (sc)	Start utilization calculation */
2130 	XM_TX_NO_GIG_MD	= 1<<3,	/* Bit  3:	Disable Carrier Extension */
2131 	XM_TX_NO_PRE	= 1<<2,	/* Bit  2:	Disable Preamble Generation */
2132 	XM_TX_NO_CRC	= 1<<1,	/* Bit  1:	Disable CRC Generation */
2133 	XM_TX_AUTO_PAD	= 1<<0,	/* Bit  0:	Enable Automatic Padding */
2134 };
2135 
2136 /*	XM_TX_RT_LIM	16 bit r/w	Transmit Retry Limit Register */
2137 #define XM_RT_LIM_MSK	0x1f	/* Bit  4..0:	Tx Retry Limit */
2138 
2139 
2140 /*	XM_TX_STIME	16 bit r/w	Transmit Slottime Register */
2141 #define XM_STIME_MSK	0x7f	/* Bit  6..0:	Tx Slottime bits */
2142 
2143 
2144 /*	XM_TX_IPG	16 bit r/w	Transmit Inter Packet Gap */
2145 #define XM_IPG_MSK		0xff	/* Bit  7..0:	IPG value bits */
2146 
2147 
2148 /*	XM_RX_CMD	16 bit r/w	Receive Command Register */
2149 enum {
2150 	XM_RX_LENERR_OK	= 1<<8,	/* Bit  8	don't set Rx Err bit for */
2151 				/*		inrange error packets */
2152 	XM_RX_BIG_PK_OK	= 1<<7,	/* Bit  7	don't set Rx Err bit for */
2153 				/*		jumbo packets */
2154 	XM_RX_IPG_CAP	= 1<<6,	/* Bit  6	repl. type field with IPG */
2155 	XM_RX_TP_MD	= 1<<5,	/* Bit  5:	Enable transparent Mode */
2156 	XM_RX_STRIP_FCS	= 1<<4,	/* Bit  4:	Enable FCS Stripping */
2157 	XM_RX_SELF_RX	= 1<<3,	/* Bit  3: 	Enable Rx of own packets */
2158 	XM_RX_SAM_LINE	= 1<<2,	/* Bit  2: (sc)	Start utilization calculation */
2159 	XM_RX_STRIP_PAD	= 1<<1,	/* Bit  1:	Strip pad bytes of Rx frames */
2160 	XM_RX_DIS_CEXT	= 1<<0,	/* Bit  0:	Disable carrier ext. check */
2161 };
2162 
2163 
2164 /*	XM_GP_PORT	32 bit r/w	General Purpose Port Register */
2165 enum {
2166 	XM_GP_ANIP	= 1<<6,	/* Bit  6: (ro)	Auto-Neg. in progress */
2167 	XM_GP_FRC_INT	= 1<<5,	/* Bit  5: (sc)	Force Interrupt */
2168 	XM_GP_RES_MAC	= 1<<3,	/* Bit  3: (sc)	Reset MAC and FIFOs */
2169 	XM_GP_RES_STAT	= 1<<2,	/* Bit  2: (sc)	Reset the statistics module */
2170 	XM_GP_INP_ASS	= 1<<0,	/* Bit  0: (ro) GP Input Pin asserted */
2171 };
2172 
2173 
2174 /*	XM_IMSK		16 bit r/w	Interrupt Mask Register */
2175 /*	XM_ISRC		16 bit r/o	Interrupt Status Register */
2176 enum {
2177 	XM_IS_LNK_AE	= 1<<14, /* Bit 14:	Link Asynchronous Event */
2178 	XM_IS_TX_ABORT	= 1<<13, /* Bit 13:	Transmit Abort, late Col. etc */
2179 	XM_IS_FRC_INT	= 1<<12, /* Bit 12:	Force INT bit set in GP */
2180 	XM_IS_INP_ASS	= 1<<11, /* Bit 11:	Input Asserted, GP bit 0 set */
2181 	XM_IS_LIPA_RC	= 1<<10, /* Bit 10:	Link Partner requests config */
2182 	XM_IS_RX_PAGE	= 1<<9,	/* Bit  9:	Page Received */
2183 	XM_IS_TX_PAGE	= 1<<8,	/* Bit  8:	Next Page Loaded for Transmit */
2184 	XM_IS_AND	= 1<<7,	/* Bit  7:	Auto-Negotiation Done */
2185 	XM_IS_TSC_OV	= 1<<6,	/* Bit  6:	Time Stamp Counter Overflow */
2186 	XM_IS_RXC_OV	= 1<<5,	/* Bit  5:	Rx Counter Event Overflow */
2187 	XM_IS_TXC_OV	= 1<<4,	/* Bit  4:	Tx Counter Event Overflow */
2188 	XM_IS_RXF_OV	= 1<<3,	/* Bit  3:	Receive FIFO Overflow */
2189 	XM_IS_TXF_UR	= 1<<2,	/* Bit  2:	Transmit FIFO Underrun */
2190 	XM_IS_TX_COMP	= 1<<1,	/* Bit  1:	Frame Tx Complete */
2191 	XM_IS_RX_COMP	= 1<<0,	/* Bit  0:	Frame Rx Complete */
2192 
2193 	XM_IMSK_DISABLE	= 0xffff,
2194 };
2195 
2196 /*	XM_HW_CFG	16 bit r/w	Hardware Config Register */
2197 enum {
2198 	XM_HW_GEN_EOP	= 1<<3,	/* Bit  3:	generate End of Packet pulse */
2199 	XM_HW_COM4SIG	= 1<<2,	/* Bit  2:	use Comma Detect for Sig. Det.*/
2200 	XM_HW_GMII_MD	= 1<<0,	/* Bit  0:	GMII Interface selected */
2201 };
2202 
2203 
2204 /*	XM_TX_LO_WM	16 bit r/w	Tx FIFO Low Water Mark */
2205 /*	XM_TX_HI_WM	16 bit r/w	Tx FIFO High Water Mark */
2206 #define XM_TX_WM_MSK	0x01ff	/* Bit  9.. 0	Tx FIFO Watermark bits */
2207 
2208 /*	XM_TX_THR	16 bit r/w	Tx Request Threshold */
2209 /*	XM_HT_THR	16 bit r/w	Host Request Threshold */
2210 /*	XM_RX_THR	16 bit r/w	Rx Request Threshold */
2211 #define XM_THR_MSK		0x03ff	/* Bit 10.. 0	Rx/Tx Request Threshold bits */
2212 
2213 
2214 /*	XM_TX_STAT	32 bit r/o	Tx Status LIFO Register */
2215 enum {
2216 	XM_ST_VALID	= (1UL<<31),	/* Bit 31:	Status Valid */
2217 	XM_ST_BYTE_CNT	= (0x3fffL<<17),	/* Bit 30..17:	Tx frame Length */
2218 	XM_ST_RETRY_CNT	= (0x1fL<<12),	/* Bit 16..12:	Retry Count */
2219 	XM_ST_EX_COL	= 1<<11,	/* Bit 11:	Excessive Collisions */
2220 	XM_ST_EX_DEF	= 1<<10,	/* Bit 10:	Excessive Deferral */
2221 	XM_ST_BURST	= 1<<9,		/* Bit  9:	p. xmitted in burst md*/
2222 	XM_ST_DEFER	= 1<<8,		/* Bit  8:	packet was defered */
2223 	XM_ST_BC	= 1<<7,		/* Bit  7:	Broadcast packet */
2224 	XM_ST_MC	= 1<<6,		/* Bit  6:	Multicast packet */
2225 	XM_ST_UC	= 1<<5,		/* Bit  5:	Unicast packet */
2226 	XM_ST_TX_UR	= 1<<4,		/* Bit  4:	FIFO Underrun occurred */
2227 	XM_ST_CS_ERR	= 1<<3,		/* Bit  3:	Carrier Sense Error */
2228 	XM_ST_LAT_COL	= 1<<2,		/* Bit  2:	Late Collision Error */
2229 	XM_ST_MUL_COL	= 1<<1,		/* Bit  1:	Multiple Collisions */
2230 	XM_ST_SGN_COL	= 1<<0,		/* Bit  0:	Single Collision */
2231 };
2232 
2233 /*	XM_RX_LO_WM	16 bit r/w	Receive Low Water Mark */
2234 /*	XM_RX_HI_WM	16 bit r/w	Receive High Water Mark */
2235 #define XM_RX_WM_MSK	0x03ff		/* Bit 11.. 0:	Rx FIFO Watermark bits */
2236 
2237 
2238 /*	XM_DEV_ID	32 bit r/o	Device ID Register */
2239 #define XM_DEV_OUI	(0x00ffffffUL<<8)	/* Bit 31..8:	Device OUI */
2240 #define XM_DEV_REV	(0x07L << 5)		/* Bit  7..5:	Chip Rev Num */
2241 
2242 
2243 /*	XM_MODE		32 bit r/w	Mode Register */
2244 enum {
2245 	XM_MD_ENA_REJ	= 1<<26, /* Bit 26:	Enable Frame Reject */
2246 	XM_MD_SPOE_E	= 1<<25, /* Bit 25:	Send Pause on Edge */
2247 									/* 		extern generated */
2248 	XM_MD_TX_REP	= 1<<24, /* Bit 24:	Transmit Repeater Mode */
2249 	XM_MD_SPOFF_I	= 1<<23, /* Bit 23:	Send Pause on FIFO full */
2250 									/*		intern generated */
2251 	XM_MD_LE_STW	= 1<<22, /* Bit 22:	Rx Stat Word in Little Endian */
2252 	XM_MD_TX_CONT	= 1<<21, /* Bit 21:	Send Continuous */
2253 	XM_MD_TX_PAUSE	= 1<<20, /* Bit 20: (sc)	Send Pause Frame */
2254 	XM_MD_ATS	= 1<<19, /* Bit 19:	Append Time Stamp */
2255 	XM_MD_SPOL_I	= 1<<18, /* Bit 18:	Send Pause on Low */
2256 									/*		intern generated */
2257 	XM_MD_SPOH_I	= 1<<17, /* Bit 17:	Send Pause on High */
2258 									/*		intern generated */
2259 	XM_MD_CAP	= 1<<16, /* Bit 16:	Check Address Pair */
2260 	XM_MD_ENA_HASH	= 1<<15, /* Bit 15:	Enable Hashing */
2261 	XM_MD_CSA	= 1<<14, /* Bit 14:	Check Station Address */
2262 	XM_MD_CAA	= 1<<13, /* Bit 13:	Check Address Array */
2263 	XM_MD_RX_MCTRL	= 1<<12, /* Bit 12:	Rx MAC Control Frame */
2264 	XM_MD_RX_RUNT	= 1<<11, /* Bit 11:	Rx Runt Frames */
2265 	XM_MD_RX_IRLE	= 1<<10, /* Bit 10:	Rx in Range Len Err Frame */
2266 	XM_MD_RX_LONG	= 1<<9,  /* Bit  9:	Rx Long Frame */
2267 	XM_MD_RX_CRCE	= 1<<8,  /* Bit  8:	Rx CRC Error Frame */
2268 	XM_MD_RX_ERR	= 1<<7,  /* Bit  7:	Rx Error Frame */
2269 	XM_MD_DIS_UC	= 1<<6,  /* Bit  6:	Disable Rx Unicast */
2270 	XM_MD_DIS_MC	= 1<<5,  /* Bit  5:	Disable Rx Multicast */
2271 	XM_MD_DIS_BC	= 1<<4,  /* Bit  4:	Disable Rx Broadcast */
2272 	XM_MD_ENA_PROM	= 1<<3,  /* Bit  3:	Enable Promiscuous */
2273 	XM_MD_ENA_BE	= 1<<2,  /* Bit  2:	Enable Big Endian */
2274 	XM_MD_FTF	= 1<<1,  /* Bit  1: (sc)	Flush Tx FIFO */
2275 	XM_MD_FRF	= 1<<0,  /* Bit  0: (sc)	Flush Rx FIFO */
2276 };
2277 
2278 #define XM_PAUSE_MODE	(XM_MD_SPOE_E | XM_MD_SPOL_I | XM_MD_SPOH_I)
2279 #define XM_DEF_MODE	(XM_MD_RX_RUNT | XM_MD_RX_IRLE | XM_MD_RX_LONG |\
2280 			 XM_MD_RX_CRCE | XM_MD_RX_ERR | XM_MD_CSA)
2281 
2282 /*	XM_STAT_CMD	16 bit r/w	Statistics Command Register */
2283 enum {
2284 	XM_SC_SNP_RXC	= 1<<5,	/* Bit  5: (sc)	Snap Rx Counters */
2285 	XM_SC_SNP_TXC	= 1<<4,	/* Bit  4: (sc)	Snap Tx Counters */
2286 	XM_SC_CP_RXC	= 1<<3,	/* Bit  3: 	Copy Rx Counters Continuously */
2287 	XM_SC_CP_TXC	= 1<<2,	/* Bit  2:	Copy Tx Counters Continuously */
2288 	XM_SC_CLR_RXC	= 1<<1,	/* Bit  1: (sc)	Clear Rx Counters */
2289 	XM_SC_CLR_TXC	= 1<<0,	/* Bit  0: (sc) Clear Tx Counters */
2290 };
2291 
2292 
2293 /*	XM_RX_CNT_EV	32 bit r/o	Rx Counter Event Register */
2294 /*	XM_RX_EV_MSK	32 bit r/w	Rx Counter Event Mask */
2295 enum {
2296 	XMR_MAX_SZ_OV	= 1<<31, /* Bit 31:	1024-MaxSize Rx Cnt Ov*/
2297 	XMR_1023B_OV	= 1<<30, /* Bit 30:	512-1023Byte Rx Cnt Ov*/
2298 	XMR_511B_OV	= 1<<29, /* Bit 29:	256-511 Byte Rx Cnt Ov*/
2299 	XMR_255B_OV	= 1<<28, /* Bit 28:	128-255 Byte Rx Cnt Ov*/
2300 	XMR_127B_OV	= 1<<27, /* Bit 27:	65-127 Byte Rx Cnt Ov */
2301 	XMR_64B_OV	= 1<<26, /* Bit 26:	64 Byte Rx Cnt Ov */
2302 	XMR_UTIL_OV	= 1<<25, /* Bit 25:	Rx Util Cnt Overflow */
2303 	XMR_UTIL_UR	= 1<<24, /* Bit 24:	Rx Util Cnt Underrun */
2304 	XMR_CEX_ERR_OV	= 1<<23, /* Bit 23:	CEXT Err Cnt Ov */
2305 	XMR_FCS_ERR_OV	= 1<<21, /* Bit 21:	Rx FCS Error Cnt Ov */
2306 	XMR_LNG_ERR_OV	= 1<<20, /* Bit 20:	Rx too Long Err Cnt Ov*/
2307 	XMR_RUNT_OV	= 1<<19, /* Bit 19:	Runt Event Cnt Ov */
2308 	XMR_SHT_ERR_OV	= 1<<18, /* Bit 18:	Rx Short Ev Err Cnt Ov*/
2309 	XMR_SYM_ERR_OV	= 1<<17, /* Bit 17:	Rx Sym Err Cnt Ov */
2310 	XMR_CAR_ERR_OV	= 1<<15, /* Bit 15:	Rx Carr Ev Err Cnt Ov */
2311 	XMR_JAB_PKT_OV	= 1<<14, /* Bit 14:	Rx Jabb Packet Cnt Ov */
2312 	XMR_FIFO_OV	= 1<<13, /* Bit 13:	Rx FIFO Ov Ev Cnt Ov */
2313 	XMR_FRA_ERR_OV	= 1<<12, /* Bit 12:	Rx Framing Err Cnt Ov */
2314 	XMR_FMISS_OV	= 1<<11, /* Bit 11:	Rx Missed Ev Cnt Ov */
2315 	XMR_BURST	= 1<<10, /* Bit 10:	Rx Burst Event Cnt Ov */
2316 	XMR_INV_MOC	= 1<<9,  /* Bit  9:	Rx with inv. MAC OC Ov*/
2317 	XMR_INV_MP	= 1<<8,  /* Bit  8:	Rx inv Pause Frame Ov */
2318 	XMR_MCTRL_OV	= 1<<7,  /* Bit  7:	Rx MAC Ctrl-F Cnt Ov */
2319 	XMR_MPAUSE_OV	= 1<<6,  /* Bit  6:	Rx Pause MAC Ctrl-F Ov*/
2320 	XMR_UC_OK_OV	= 1<<5,  /* Bit  5:	Rx Unicast Frame CntOv*/
2321 	XMR_MC_OK_OV	= 1<<4,  /* Bit  4:	Rx Multicast Cnt Ov */
2322 	XMR_BC_OK_OV	= 1<<3,  /* Bit  3:	Rx Broadcast Cnt Ov */
2323 	XMR_OK_LO_OV	= 1<<2,  /* Bit  2:	Octets Rx OK Low CntOv*/
2324 	XMR_OK_HI_OV	= 1<<1,  /* Bit  1:	Octets Rx OK Hi Cnt Ov*/
2325 	XMR_OK_OV	= 1<<0,  /* Bit  0:	Frames Received Ok Ov */
2326 };
2327 
2328 #define XMR_DEF_MSK		(XMR_OK_LO_OV | XMR_OK_HI_OV)
2329 
2330 /*	XM_TX_CNT_EV	32 bit r/o	Tx Counter Event Register */
2331 /*	XM_TX_EV_MSK	32 bit r/w	Tx Counter Event Mask */
2332 enum {
2333 	XMT_MAX_SZ_OV	= 1<<25,	/* Bit 25:	1024-MaxSize Tx Cnt Ov*/
2334 	XMT_1023B_OV	= 1<<24,	/* Bit 24:	512-1023Byte Tx Cnt Ov*/
2335 	XMT_511B_OV	= 1<<23,	/* Bit 23:	256-511 Byte Tx Cnt Ov*/
2336 	XMT_255B_OV	= 1<<22,	/* Bit 22:	128-255 Byte Tx Cnt Ov*/
2337 	XMT_127B_OV	= 1<<21,	/* Bit 21:	65-127 Byte Tx Cnt Ov */
2338 	XMT_64B_OV	= 1<<20,	/* Bit 20:	64 Byte Tx Cnt Ov */
2339 	XMT_UTIL_OV	= 1<<19,	/* Bit 19:	Tx Util Cnt Overflow */
2340 	XMT_UTIL_UR	= 1<<18,	/* Bit 18:	Tx Util Cnt Underrun */
2341 	XMT_CS_ERR_OV	= 1<<17,	/* Bit 17:	Tx Carr Sen Err Cnt Ov*/
2342 	XMT_FIFO_UR_OV	= 1<<16,	/* Bit 16:	Tx FIFO Ur Ev Cnt Ov */
2343 	XMT_EX_DEF_OV	= 1<<15,	/* Bit 15:	Tx Ex Deferall Cnt Ov */
2344 	XMT_DEF	= 1<<14,	/* Bit 14:	Tx Deferred Cnt Ov */
2345 	XMT_LAT_COL_OV	= 1<<13,	/* Bit 13:	Tx Late Col Cnt Ov */
2346 	XMT_ABO_COL_OV	= 1<<12,	/* Bit 12:	Tx abo dueto Ex Col Ov*/
2347 	XMT_MUL_COL_OV	= 1<<11,	/* Bit 11:	Tx Mult Col Cnt Ov */
2348 	XMT_SNG_COL	= 1<<10,	/* Bit 10:	Tx Single Col Cnt Ov */
2349 	XMT_MCTRL_OV	= 1<<9,		/* Bit  9:	Tx MAC Ctrl Counter Ov*/
2350 	XMT_MPAUSE	= 1<<8,		/* Bit  8:	Tx Pause MAC Ctrl-F Ov*/
2351 	XMT_BURST	= 1<<7,		/* Bit  7:	Tx Burst Event Cnt Ov */
2352 	XMT_LONG	= 1<<6,		/* Bit  6:	Tx Long Frame Cnt Ov */
2353 	XMT_UC_OK_OV	= 1<<5,		/* Bit  5:	Tx Unicast Cnt Ov */
2354 	XMT_MC_OK_OV	= 1<<4,		/* Bit  4:	Tx Multicast Cnt Ov */
2355 	XMT_BC_OK_OV	= 1<<3,		/* Bit  3:	Tx Broadcast Cnt Ov */
2356 	XMT_OK_LO_OV	= 1<<2,		/* Bit  2:	Octets Tx OK Low CntOv*/
2357 	XMT_OK_HI_OV	= 1<<1,		/* Bit  1:	Octets Tx OK Hi Cnt Ov*/
2358 	XMT_OK_OV	= 1<<0,		/* Bit  0:	Frames Tx Ok Ov */
2359 };
2360 
2361 #define XMT_DEF_MSK		(XMT_OK_LO_OV | XMT_OK_HI_OV)
2362 
2363 struct skge_rx_desc {
2364 	u32		control;
2365 	u32		next_offset;
2366 	u32		dma_lo;
2367 	u32		dma_hi;
2368 	u32		status;
2369 	u32		timestamp;
2370 	u16		csum2;
2371 	u16		csum1;
2372 	u16		csum2_start;
2373 	u16		csum1_start;
2374 };
2375 
2376 struct skge_tx_desc {
2377 	u32		control;
2378 	u32		next_offset;
2379 	u32		dma_lo;
2380 	u32		dma_hi;
2381 	u32		status;
2382 	u32		csum_offs;
2383 	u16		csum_write;
2384 	u16		csum_start;
2385 	u32		rsvd;
2386 };
2387 
2388 struct skge_element {
2389 	struct skge_element	*next;
2390 	void			*desc;
2391 	struct sk_buff  	*skb;
2392 	DEFINE_DMA_UNMAP_ADDR(mapaddr);
2393 	DEFINE_DMA_UNMAP_LEN(maplen);
2394 };
2395 
2396 struct skge_ring {
2397 	struct skge_element *to_clean;
2398 	struct skge_element *to_use;
2399 	struct skge_element *start;
2400 	unsigned long	    count;
2401 };
2402 
2403 
2404 struct skge_hw {
2405 	void __iomem  	     *regs;
2406 	struct pci_dev	     *pdev;
2407 	spinlock_t	     hw_lock;
2408 	u32		     intr_mask;
2409 	struct net_device    *dev[2];
2410 
2411 	u8	     	     chip_id;
2412 	u8		     chip_rev;
2413 	u8		     copper;
2414 	u8		     ports;
2415 	u8		     phy_type;
2416 
2417 	u32	     	     ram_size;
2418 	u32	     	     ram_offset;
2419 	u16		     phy_addr;
2420 	spinlock_t	     phy_lock;
2421 	struct tasklet_struct phy_task;
2422 
2423 	char		     irq_name[]; /* skge@pci:000:04:00.0 */
2424 };
2425 
2426 enum pause_control {
2427 	FLOW_MODE_NONE 		= 1, /* No Flow-Control */
2428 	FLOW_MODE_LOC_SEND	= 2, /* Local station sends PAUSE */
2429 	FLOW_MODE_SYMMETRIC	= 3, /* Both stations may send PAUSE */
2430 	FLOW_MODE_SYM_OR_REM	= 4, /* Both stations may send PAUSE or
2431 				      * just the remote station may send PAUSE
2432 				      */
2433 };
2434 
2435 enum pause_status {
2436 	FLOW_STAT_INDETERMINATED=0,	/* indeterminated */
2437 	FLOW_STAT_NONE,			/* No Flow Control */
2438 	FLOW_STAT_REM_SEND,		/* Remote Station sends PAUSE */
2439 	FLOW_STAT_LOC_SEND,		/* Local station sends PAUSE */
2440 	FLOW_STAT_SYMMETRIC,		/* Both station may send PAUSE */
2441 };
2442 
2443 
2444 struct skge_port {
2445 	struct skge_hw	     *hw;
2446 	struct net_device    *netdev;
2447 	struct napi_struct   napi;
2448 	int		     port;
2449 	u32		     msg_enable;
2450 
2451 	struct skge_ring     tx_ring;
2452 
2453 	struct skge_ring     rx_ring ____cacheline_aligned_in_smp;
2454 	unsigned int	     rx_buf_size;
2455 
2456 	struct timer_list    link_timer;
2457 	enum pause_control   flow_control;
2458 	enum pause_status    flow_status;
2459 	u8		     blink_on;
2460 	u8		     wol;
2461 	u8		     autoneg;	/* AUTONEG_ENABLE, AUTONEG_DISABLE */
2462 	u8		     duplex;	/* DUPLEX_HALF, DUPLEX_FULL */
2463 	u16		     speed;	/* SPEED_1000, SPEED_100, ... */
2464 	u32		     advertising;
2465 
2466 	void		     *mem;	/* PCI memory for rings */
2467 	dma_addr_t	     dma;
2468 	unsigned long	     mem_size;
2469 #ifdef CONFIG_SKGE_DEBUG
2470 	struct dentry	     *debugfs;
2471 #endif
2472 };
2473 
2474 
2475 /* Register accessor for memory mapped device */
skge_read32(const struct skge_hw * hw,int reg)2476 static inline u32 skge_read32(const struct skge_hw *hw, int reg)
2477 {
2478 	return readl(hw->regs + reg);
2479 }
2480 
skge_read16(const struct skge_hw * hw,int reg)2481 static inline u16 skge_read16(const struct skge_hw *hw, int reg)
2482 {
2483 	return readw(hw->regs + reg);
2484 }
2485 
skge_read8(const struct skge_hw * hw,int reg)2486 static inline u8 skge_read8(const struct skge_hw *hw, int reg)
2487 {
2488 	return readb(hw->regs + reg);
2489 }
2490 
skge_write32(const struct skge_hw * hw,int reg,u32 val)2491 static inline void skge_write32(const struct skge_hw *hw, int reg, u32 val)
2492 {
2493 	writel(val, hw->regs + reg);
2494 }
2495 
skge_write16(const struct skge_hw * hw,int reg,u16 val)2496 static inline void skge_write16(const struct skge_hw *hw, int reg, u16 val)
2497 {
2498 	writew(val, hw->regs + reg);
2499 }
2500 
skge_write8(const struct skge_hw * hw,int reg,u8 val)2501 static inline void skge_write8(const struct skge_hw *hw, int reg, u8 val)
2502 {
2503 	writeb(val, hw->regs + reg);
2504 }
2505 
2506 /* MAC Related Registers inside the device. */
2507 #define SK_REG(port,reg)	(((port)<<7)+(u16)(reg))
2508 #define SK_XMAC_REG(port, reg) \
2509 	((BASE_XMAC_1 + (port) * (BASE_XMAC_2 - BASE_XMAC_1)) | (reg) << 1)
2510 
xm_read32(const struct skge_hw * hw,int port,int reg)2511 static inline u32 xm_read32(const struct skge_hw *hw, int port, int reg)
2512 {
2513 	u32 v;
2514 	v = skge_read16(hw, SK_XMAC_REG(port, reg));
2515 	v |= (u32)skge_read16(hw, SK_XMAC_REG(port, reg+2)) << 16;
2516 	return v;
2517 }
2518 
xm_read16(const struct skge_hw * hw,int port,int reg)2519 static inline u16 xm_read16(const struct skge_hw *hw, int port, int reg)
2520 {
2521 	return skge_read16(hw, SK_XMAC_REG(port,reg));
2522 }
2523 
xm_write32(const struct skge_hw * hw,int port,int r,u32 v)2524 static inline void xm_write32(const struct skge_hw *hw, int port, int r, u32 v)
2525 {
2526 	skge_write16(hw, SK_XMAC_REG(port,r), v & 0xffff);
2527 	skge_write16(hw, SK_XMAC_REG(port,r+2), v >> 16);
2528 }
2529 
xm_write16(const struct skge_hw * hw,int port,int r,u16 v)2530 static inline void xm_write16(const struct skge_hw *hw, int port, int r, u16 v)
2531 {
2532 	skge_write16(hw, SK_XMAC_REG(port,r), v);
2533 }
2534 
xm_outhash(const struct skge_hw * hw,int port,int reg,const u8 * hash)2535 static inline void xm_outhash(const struct skge_hw *hw, int port, int reg,
2536 				   const u8 *hash)
2537 {
2538 	xm_write16(hw, port, reg,   (u16)hash[0] | ((u16)hash[1] << 8));
2539 	xm_write16(hw, port, reg+2, (u16)hash[2] | ((u16)hash[3] << 8));
2540 	xm_write16(hw, port, reg+4, (u16)hash[4] | ((u16)hash[5] << 8));
2541 	xm_write16(hw, port, reg+6, (u16)hash[6] | ((u16)hash[7] << 8));
2542 }
2543 
xm_outaddr(const struct skge_hw * hw,int port,int reg,const u8 * addr)2544 static inline void xm_outaddr(const struct skge_hw *hw, int port, int reg,
2545 				   const u8 *addr)
2546 {
2547 	xm_write16(hw, port, reg,   (u16)addr[0] | ((u16)addr[1] << 8));
2548 	xm_write16(hw, port, reg+2, (u16)addr[2] | ((u16)addr[3] << 8));
2549 	xm_write16(hw, port, reg+4, (u16)addr[4] | ((u16)addr[5] << 8));
2550 }
2551 
2552 #define SK_GMAC_REG(port,reg) \
2553 	(BASE_GMAC_1 + (port) * (BASE_GMAC_2-BASE_GMAC_1) + (reg))
2554 
gma_read16(const struct skge_hw * hw,int port,int reg)2555 static inline u16 gma_read16(const struct skge_hw *hw, int port, int reg)
2556 {
2557 	return skge_read16(hw, SK_GMAC_REG(port,reg));
2558 }
2559 
gma_read32(const struct skge_hw * hw,int port,int reg)2560 static inline u32 gma_read32(const struct skge_hw *hw, int port, int reg)
2561 {
2562 	return (u32) skge_read16(hw, SK_GMAC_REG(port,reg))
2563 		| ((u32)skge_read16(hw, SK_GMAC_REG(port,reg+4)) << 16);
2564 }
2565 
gma_write16(const struct skge_hw * hw,int port,int r,u16 v)2566 static inline void gma_write16(const struct skge_hw *hw, int port, int r, u16 v)
2567 {
2568 	skge_write16(hw, SK_GMAC_REG(port,r), v);
2569 }
2570 
gma_set_addr(struct skge_hw * hw,int port,int reg,const u8 * addr)2571 static inline void gma_set_addr(struct skge_hw *hw, int port, int reg,
2572 				    const u8 *addr)
2573 {
2574 	gma_write16(hw, port, reg,  (u16) addr[0] | ((u16) addr[1] << 8));
2575 	gma_write16(hw, port, reg+4,(u16) addr[2] | ((u16) addr[3] << 8));
2576 	gma_write16(hw, port, reg+8,(u16) addr[4] | ((u16) addr[5] << 8));
2577 }
2578 
2579 #endif
2580