1 /* SPDX-License-Identifier: GPL-2.0 */
2 /* Copyright (C) 2021, Intel Corporation. */
3
4 #ifndef _ICE_PTP_HW_H_
5 #define _ICE_PTP_HW_H_
6
7 enum ice_ptp_tmr_cmd {
8 INIT_TIME,
9 INIT_INCVAL,
10 ADJ_TIME,
11 ADJ_TIME_AT_TIME,
12 READ_TIME,
13 ICE_PTP_NOP,
14 };
15
16 enum ice_ptp_serdes {
17 ICE_PTP_SERDES_1G,
18 ICE_PTP_SERDES_10G,
19 ICE_PTP_SERDES_25G,
20 ICE_PTP_SERDES_40G,
21 ICE_PTP_SERDES_50G,
22 ICE_PTP_SERDES_100G
23 };
24
25 enum ice_ptp_link_spd {
26 ICE_PTP_LNK_SPD_1G,
27 ICE_PTP_LNK_SPD_10G,
28 ICE_PTP_LNK_SPD_25G,
29 ICE_PTP_LNK_SPD_25G_RS,
30 ICE_PTP_LNK_SPD_40G,
31 ICE_PTP_LNK_SPD_50G,
32 ICE_PTP_LNK_SPD_50G_RS,
33 ICE_PTP_LNK_SPD_100G_RS,
34 NUM_ICE_PTP_LNK_SPD /* Must be last */
35 };
36
37 enum ice_ptp_fec_mode {
38 ICE_PTP_FEC_MODE_NONE,
39 ICE_PTP_FEC_MODE_CLAUSE74,
40 ICE_PTP_FEC_MODE_RS_FEC
41 };
42
43 /**
44 * struct ice_time_ref_info_e822
45 * @pll_freq: Frequency of PLL that drives timer ticks in Hz
46 * @nominal_incval: increment to generate nanoseconds in GLTSYN_TIME_L
47 * @pps_delay: propagation delay of the PPS output signal
48 *
49 * Characteristic information for the various TIME_REF sources possible in the
50 * E822 devices
51 */
52 struct ice_time_ref_info_e822 {
53 u64 pll_freq;
54 u64 nominal_incval;
55 u8 pps_delay;
56 };
57
58 /**
59 * struct ice_vernier_info_e822
60 * @tx_par_clk: Frequency used to calculate P_REG_PAR_TX_TUS
61 * @rx_par_clk: Frequency used to calculate P_REG_PAR_RX_TUS
62 * @tx_pcs_clk: Frequency used to calculate P_REG_PCS_TX_TUS
63 * @rx_pcs_clk: Frequency used to calculate P_REG_PCS_RX_TUS
64 * @tx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_TX_TUS
65 * @rx_desk_rsgb_par: Frequency used to calculate P_REG_DESK_PAR_RX_TUS
66 * @tx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_TX_TUS
67 * @rx_desk_rsgb_pcs: Frequency used to calculate P_REG_DESK_PCS_RX_TUS
68 * @tx_fixed_delay: Fixed Tx latency measured in 1/100th nanoseconds
69 * @pmd_adj_divisor: Divisor used to calculate PDM alignment adjustment
70 * @rx_fixed_delay: Fixed Rx latency measured in 1/100th nanoseconds
71 *
72 * Table of constants used during as part of the Vernier calibration of the Tx
73 * and Rx timestamps. This includes frequency values used to compute TUs per
74 * PAR/PCS clock cycle, and static delay values measured during hardware
75 * design.
76 *
77 * Note that some values are not used for all link speeds, and the
78 * P_REG_DESK_PAR* registers may represent different clock markers at
79 * different link speeds, either the deskew marker for multi-lane link speeds
80 * or the Reed Solomon gearbox marker for RS-FEC.
81 */
82 struct ice_vernier_info_e822 {
83 u32 tx_par_clk;
84 u32 rx_par_clk;
85 u32 tx_pcs_clk;
86 u32 rx_pcs_clk;
87 u32 tx_desk_rsgb_par;
88 u32 rx_desk_rsgb_par;
89 u32 tx_desk_rsgb_pcs;
90 u32 rx_desk_rsgb_pcs;
91 u32 tx_fixed_delay;
92 u32 pmd_adj_divisor;
93 u32 rx_fixed_delay;
94 };
95
96 /**
97 * struct ice_cgu_pll_params_e822
98 * @refclk_pre_div: Reference clock pre-divisor
99 * @feedback_div: Feedback divisor
100 * @frac_n_div: Fractional divisor
101 * @post_pll_div: Post PLL divisor
102 *
103 * Clock Generation Unit parameters used to program the PLL based on the
104 * selected TIME_REF frequency.
105 */
106 struct ice_cgu_pll_params_e822 {
107 u32 refclk_pre_div;
108 u32 feedback_div;
109 u32 frac_n_div;
110 u32 post_pll_div;
111 };
112
113 extern const struct
114 ice_cgu_pll_params_e822 e822_cgu_params[NUM_ICE_TIME_REF_FREQ];
115
116 #define E810C_QSFP_C827_0_HANDLE 2
117 #define E810C_QSFP_C827_1_HANDLE 3
118
119 /* Table of constants related to possible TIME_REF sources */
120 extern const struct ice_time_ref_info_e822 e822_time_ref[NUM_ICE_TIME_REF_FREQ];
121
122 /* Table of constants for Vernier calibration on E822 */
123 extern const struct ice_vernier_info_e822 e822_vernier[NUM_ICE_PTP_LNK_SPD];
124
125 /* Increment value to generate nanoseconds in the GLTSYN_TIME_L register for
126 * the E810 devices. Based off of a PLL with an 812.5 MHz frequency.
127 */
128 #define ICE_PTP_NOMINAL_INCVAL_E810 0x13b13b13bULL
129
130 /* Device agnostic functions */
131 u8 ice_get_ptp_src_clock_index(struct ice_hw *hw);
132 bool ice_ptp_lock(struct ice_hw *hw);
133 void ice_ptp_unlock(struct ice_hw *hw);
134 int ice_ptp_init_time(struct ice_hw *hw, u64 time);
135 int ice_ptp_write_incval(struct ice_hw *hw, u64 incval);
136 int ice_ptp_write_incval_locked(struct ice_hw *hw, u64 incval);
137 int ice_ptp_adj_clock(struct ice_hw *hw, s32 adj);
138 int ice_read_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx, u64 *tstamp);
139 int ice_clear_phy_tstamp(struct ice_hw *hw, u8 block, u8 idx);
140 void ice_ptp_reset_ts_memory(struct ice_hw *hw);
141 int ice_ptp_init_phc(struct ice_hw *hw);
142 int ice_get_phy_tx_tstamp_ready(struct ice_hw *hw, u8 block, u64 *tstamp_ready);
143
144 /* E822 family functions */
145 int ice_read_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 *val);
146 int ice_write_quad_reg_e822(struct ice_hw *hw, u8 quad, u16 offset, u32 val);
147 void ice_ptp_reset_ts_memory_quad_e822(struct ice_hw *hw, u8 quad);
148
149 /**
150 * ice_e822_time_ref - Get the current TIME_REF from capabilities
151 * @hw: pointer to the HW structure
152 *
153 * Returns the current TIME_REF from the capabilities structure.
154 */
ice_e822_time_ref(struct ice_hw * hw)155 static inline enum ice_time_ref_freq ice_e822_time_ref(struct ice_hw *hw)
156 {
157 return hw->func_caps.ts_func_info.time_ref;
158 }
159
160 /**
161 * ice_set_e822_time_ref - Set new TIME_REF
162 * @hw: pointer to the HW structure
163 * @time_ref: new TIME_REF to set
164 *
165 * Update the TIME_REF in the capabilities structure in response to some
166 * change, such as an update to the CGU registers.
167 */
168 static inline void
ice_set_e822_time_ref(struct ice_hw * hw,enum ice_time_ref_freq time_ref)169 ice_set_e822_time_ref(struct ice_hw *hw, enum ice_time_ref_freq time_ref)
170 {
171 hw->func_caps.ts_func_info.time_ref = time_ref;
172 }
173
ice_e822_pll_freq(enum ice_time_ref_freq time_ref)174 static inline u64 ice_e822_pll_freq(enum ice_time_ref_freq time_ref)
175 {
176 return e822_time_ref[time_ref].pll_freq;
177 }
178
ice_e822_nominal_incval(enum ice_time_ref_freq time_ref)179 static inline u64 ice_e822_nominal_incval(enum ice_time_ref_freq time_ref)
180 {
181 return e822_time_ref[time_ref].nominal_incval;
182 }
183
ice_e822_pps_delay(enum ice_time_ref_freq time_ref)184 static inline u64 ice_e822_pps_delay(enum ice_time_ref_freq time_ref)
185 {
186 return e822_time_ref[time_ref].pps_delay;
187 }
188
189 /* E822 Vernier calibration functions */
190 int ice_stop_phy_timer_e822(struct ice_hw *hw, u8 port, bool soft_reset);
191 int ice_start_phy_timer_e822(struct ice_hw *hw, u8 port);
192 int ice_phy_cfg_tx_offset_e822(struct ice_hw *hw, u8 port);
193 int ice_phy_cfg_rx_offset_e822(struct ice_hw *hw, u8 port);
194
195 /* E810 family functions */
196 int ice_ptp_init_phy_e810(struct ice_hw *hw);
197 int ice_read_sma_ctrl_e810t(struct ice_hw *hw, u8 *data);
198 int ice_write_sma_ctrl_e810t(struct ice_hw *hw, u8 data);
199 int ice_read_pca9575_reg_e810t(struct ice_hw *hw, u8 offset, u8 *data);
200
201 #define PFTSYN_SEM_BYTES 4
202
203 #define ICE_PTP_CLOCK_INDEX_0 0x00
204 #define ICE_PTP_CLOCK_INDEX_1 0x01
205
206 /* PHY timer commands */
207 #define SEL_CPK_SRC 8
208 #define SEL_PHY_SRC 3
209
210 /* Time Sync command Definitions */
211 #define GLTSYN_CMD_INIT_TIME BIT(0)
212 #define GLTSYN_CMD_INIT_INCVAL BIT(1)
213 #define GLTSYN_CMD_INIT_TIME_INCVAL (BIT(0) | BIT(1))
214 #define GLTSYN_CMD_ADJ_TIME BIT(2)
215 #define GLTSYN_CMD_ADJ_INIT_TIME (BIT(2) | BIT(3))
216 #define GLTSYN_CMD_READ_TIME BIT(7)
217
218 /* PHY port Time Sync command definitions */
219 #define PHY_CMD_INIT_TIME BIT(0)
220 #define PHY_CMD_INIT_INCVAL BIT(1)
221 #define PHY_CMD_ADJ_TIME (BIT(0) | BIT(1))
222 #define PHY_CMD_ADJ_TIME_AT_TIME (BIT(0) | BIT(2))
223 #define PHY_CMD_READ_TIME (BIT(0) | BIT(1) | BIT(2))
224
225 #define TS_CMD_MASK_E810 0xFF
226 #define TS_CMD_MASK 0xF
227 #define SYNC_EXEC_CMD 0x3
228
229 /* Macros to derive port low and high addresses on both quads */
230 #define P_Q0_L(a, p) ((((a) + (0x2000 * (p)))) & 0xFFFF)
231 #define P_Q0_H(a, p) ((((a) + (0x2000 * (p)))) >> 16)
232 #define P_Q1_L(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) & 0xFFFF)
233 #define P_Q1_H(a, p) ((((a) - (0x2000 * ((p) - ICE_PORTS_PER_QUAD)))) >> 16)
234
235 /* PHY QUAD register base addresses */
236 #define Q_0_BASE 0x94000
237 #define Q_1_BASE 0x114000
238
239 /* Timestamp memory reset registers */
240 #define Q_REG_TS_CTRL 0x618
241 #define Q_REG_TS_CTRL_S 0
242 #define Q_REG_TS_CTRL_M BIT(0)
243
244 /* Timestamp availability status registers */
245 #define Q_REG_TX_MEMORY_STATUS_L 0xCF0
246 #define Q_REG_TX_MEMORY_STATUS_U 0xCF4
247
248 /* Tx FIFO status registers */
249 #define Q_REG_FIFO23_STATUS 0xCF8
250 #define Q_REG_FIFO01_STATUS 0xCFC
251 #define Q_REG_FIFO02_S 0
252 #define Q_REG_FIFO02_M ICE_M(0x3FF, 0)
253 #define Q_REG_FIFO13_S 10
254 #define Q_REG_FIFO13_M ICE_M(0x3FF, 10)
255
256 /* Interrupt control Config registers */
257 #define Q_REG_TX_MEM_GBL_CFG 0xC08
258 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_S 0
259 #define Q_REG_TX_MEM_GBL_CFG_LANE_TYPE_M BIT(0)
260 #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_S 1
261 #define Q_REG_TX_MEM_GBL_CFG_TX_TYPE_M ICE_M(0xFF, 1)
262 #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_S 9
263 #define Q_REG_TX_MEM_GBL_CFG_INTR_THR_M ICE_M(0x3F, 9)
264 #define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_S 15
265 #define Q_REG_TX_MEM_GBL_CFG_INTR_ENA_M BIT(15)
266
267 /* Tx Timestamp data registers */
268 #define Q_REG_TX_MEMORY_BANK_START 0xA00
269
270 /* PHY port register base addresses */
271 #define P_0_BASE 0x80000
272 #define P_4_BASE 0x106000
273
274 /* Timestamp init registers */
275 #define P_REG_RX_TIMER_INC_PRE_L 0x46C
276 #define P_REG_RX_TIMER_INC_PRE_U 0x470
277 #define P_REG_TX_TIMER_INC_PRE_L 0x44C
278 #define P_REG_TX_TIMER_INC_PRE_U 0x450
279
280 /* Timestamp match and adjust target registers */
281 #define P_REG_RX_TIMER_CNT_ADJ_L 0x474
282 #define P_REG_RX_TIMER_CNT_ADJ_U 0x478
283 #define P_REG_TX_TIMER_CNT_ADJ_L 0x454
284 #define P_REG_TX_TIMER_CNT_ADJ_U 0x458
285
286 /* Timestamp capture registers */
287 #define P_REG_RX_CAPTURE_L 0x4D8
288 #define P_REG_RX_CAPTURE_U 0x4DC
289 #define P_REG_TX_CAPTURE_L 0x4B4
290 #define P_REG_TX_CAPTURE_U 0x4B8
291
292 /* Timestamp PHY incval registers */
293 #define P_REG_TIMETUS_L 0x410
294 #define P_REG_TIMETUS_U 0x414
295
296 #define P_REG_40B_LOW_M 0xFF
297 #define P_REG_40B_HIGH_S 8
298
299 /* PHY window length registers */
300 #define P_REG_WL 0x40C
301
302 #define PTP_VERNIER_WL 0x111ed
303
304 /* PHY start registers */
305 #define P_REG_PS 0x408
306 #define P_REG_PS_START_S 0
307 #define P_REG_PS_START_M BIT(0)
308 #define P_REG_PS_BYPASS_MODE_S 1
309 #define P_REG_PS_BYPASS_MODE_M BIT(1)
310 #define P_REG_PS_ENA_CLK_S 2
311 #define P_REG_PS_ENA_CLK_M BIT(2)
312 #define P_REG_PS_LOAD_OFFSET_S 3
313 #define P_REG_PS_LOAD_OFFSET_M BIT(3)
314 #define P_REG_PS_SFT_RESET_S 11
315 #define P_REG_PS_SFT_RESET_M BIT(11)
316
317 /* PHY offset valid registers */
318 #define P_REG_TX_OV_STATUS 0x4D4
319 #define P_REG_TX_OV_STATUS_OV_S 0
320 #define P_REG_TX_OV_STATUS_OV_M BIT(0)
321 #define P_REG_RX_OV_STATUS 0x4F8
322 #define P_REG_RX_OV_STATUS_OV_S 0
323 #define P_REG_RX_OV_STATUS_OV_M BIT(0)
324
325 /* PHY offset ready registers */
326 #define P_REG_TX_OR 0x45C
327 #define P_REG_RX_OR 0x47C
328
329 /* PHY total offset registers */
330 #define P_REG_TOTAL_RX_OFFSET_L 0x460
331 #define P_REG_TOTAL_RX_OFFSET_U 0x464
332 #define P_REG_TOTAL_TX_OFFSET_L 0x440
333 #define P_REG_TOTAL_TX_OFFSET_U 0x444
334
335 /* Timestamp PAR/PCS registers */
336 #define P_REG_UIX66_10G_40G_L 0x480
337 #define P_REG_UIX66_10G_40G_U 0x484
338 #define P_REG_UIX66_25G_100G_L 0x488
339 #define P_REG_UIX66_25G_100G_U 0x48C
340 #define P_REG_DESK_PAR_RX_TUS_L 0x490
341 #define P_REG_DESK_PAR_RX_TUS_U 0x494
342 #define P_REG_DESK_PAR_TX_TUS_L 0x498
343 #define P_REG_DESK_PAR_TX_TUS_U 0x49C
344 #define P_REG_DESK_PCS_RX_TUS_L 0x4A0
345 #define P_REG_DESK_PCS_RX_TUS_U 0x4A4
346 #define P_REG_DESK_PCS_TX_TUS_L 0x4A8
347 #define P_REG_DESK_PCS_TX_TUS_U 0x4AC
348 #define P_REG_PAR_RX_TUS_L 0x420
349 #define P_REG_PAR_RX_TUS_U 0x424
350 #define P_REG_PAR_TX_TUS_L 0x428
351 #define P_REG_PAR_TX_TUS_U 0x42C
352 #define P_REG_PCS_RX_TUS_L 0x430
353 #define P_REG_PCS_RX_TUS_U 0x434
354 #define P_REG_PCS_TX_TUS_L 0x438
355 #define P_REG_PCS_TX_TUS_U 0x43C
356 #define P_REG_PAR_RX_TIME_L 0x4F0
357 #define P_REG_PAR_RX_TIME_U 0x4F4
358 #define P_REG_PAR_TX_TIME_L 0x4CC
359 #define P_REG_PAR_TX_TIME_U 0x4D0
360 #define P_REG_PAR_PCS_RX_OFFSET_L 0x4E8
361 #define P_REG_PAR_PCS_RX_OFFSET_U 0x4EC
362 #define P_REG_PAR_PCS_TX_OFFSET_L 0x4C4
363 #define P_REG_PAR_PCS_TX_OFFSET_U 0x4C8
364 #define P_REG_LINK_SPEED 0x4FC
365 #define P_REG_LINK_SPEED_SERDES_S 0
366 #define P_REG_LINK_SPEED_SERDES_M ICE_M(0x7, 0)
367 #define P_REG_LINK_SPEED_FEC_MODE_S 3
368 #define P_REG_LINK_SPEED_FEC_MODE_M ICE_M(0x3, 3)
369 #define P_REG_LINK_SPEED_FEC_MODE(reg) \
370 (((reg) & P_REG_LINK_SPEED_FEC_MODE_M) >> \
371 P_REG_LINK_SPEED_FEC_MODE_S)
372
373 /* PHY timestamp related registers */
374 #define P_REG_PMD_ALIGNMENT 0x0FC
375 #define P_REG_RX_80_TO_160_CNT 0x6FC
376 #define P_REG_RX_80_TO_160_CNT_RXCYC_S 0
377 #define P_REG_RX_80_TO_160_CNT_RXCYC_M BIT(0)
378 #define P_REG_RX_40_TO_160_CNT 0x8FC
379 #define P_REG_RX_40_TO_160_CNT_RXCYC_S 0
380 #define P_REG_RX_40_TO_160_CNT_RXCYC_M ICE_M(0x3, 0)
381
382 /* Rx FIFO status registers */
383 #define P_REG_RX_OV_FS 0x4F8
384 #define P_REG_RX_OV_FS_FIFO_STATUS_S 2
385 #define P_REG_RX_OV_FS_FIFO_STATUS_M ICE_M(0x3FF, 2)
386
387 /* Timestamp command registers */
388 #define P_REG_TX_TMR_CMD 0x448
389 #define P_REG_RX_TMR_CMD 0x468
390
391 /* E810 timesync enable register */
392 #define ETH_GLTSYN_ENA(_i) (0x03000348 + ((_i) * 4))
393
394 /* E810 shadow init time registers */
395 #define ETH_GLTSYN_SHTIME_0(i) (0x03000368 + ((i) * 32))
396 #define ETH_GLTSYN_SHTIME_L(i) (0x0300036C + ((i) * 32))
397
398 /* E810 shadow time adjust registers */
399 #define ETH_GLTSYN_SHADJ_L(_i) (0x03000378 + ((_i) * 32))
400 #define ETH_GLTSYN_SHADJ_H(_i) (0x0300037C + ((_i) * 32))
401
402 /* E810 timer command register */
403 #define ETH_GLTSYN_CMD 0x03000344
404
405 /* Source timer incval macros */
406 #define INCVAL_HIGH_M 0xFF
407
408 /* Timestamp block macros */
409 #define TS_VALID BIT(0)
410 #define TS_LOW_M 0xFFFFFFFF
411 #define TS_HIGH_M 0xFF
412 #define TS_HIGH_S 32
413
414 #define TS_PHY_LOW_M 0xFF
415 #define TS_PHY_HIGH_M 0xFFFFFFFF
416 #define TS_PHY_HIGH_S 8
417
418 #define BYTES_PER_IDX_ADDR_L_U 8
419 #define BYTES_PER_IDX_ADDR_L 4
420
421 /* Tx timestamp low latency read definitions */
422 #define TS_LL_READ_RETRIES 200
423 #define TS_LL_READ_TS_HIGH GENMASK(23, 16)
424 #define TS_LL_READ_TS_IDX GENMASK(29, 24)
425 #define TS_LL_READ_TS BIT(31)
426
427 /* Internal PHY timestamp address */
428 #define TS_L(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U))
429 #define TS_H(a, idx) ((a) + ((idx) * BYTES_PER_IDX_ADDR_L_U + \
430 BYTES_PER_IDX_ADDR_L))
431
432 /* External PHY timestamp address */
433 #define TS_EXT(a, port, idx) ((a) + (0x1000 * (port)) + \
434 ((idx) * BYTES_PER_IDX_ADDR_L_U))
435
436 #define LOW_TX_MEMORY_BANK_START 0x03090000
437 #define HIGH_TX_MEMORY_BANK_START 0x03090004
438
439 /* E810T SMA controller pin control */
440 #define ICE_SMA1_DIR_EN_E810T BIT(4)
441 #define ICE_SMA1_TX_EN_E810T BIT(5)
442 #define ICE_SMA2_UFL2_RX_DIS_E810T BIT(3)
443 #define ICE_SMA2_DIR_EN_E810T BIT(6)
444 #define ICE_SMA2_TX_EN_E810T BIT(7)
445
446 #define ICE_SMA1_MASK_E810T (ICE_SMA1_DIR_EN_E810T | \
447 ICE_SMA1_TX_EN_E810T)
448 #define ICE_SMA2_MASK_E810T (ICE_SMA2_UFL2_RX_DIS_E810T | \
449 ICE_SMA2_DIR_EN_E810T | \
450 ICE_SMA2_TX_EN_E810T)
451 #define ICE_ALL_SMA_MASK_E810T (ICE_SMA1_MASK_E810T | \
452 ICE_SMA2_MASK_E810T)
453
454 #define ICE_SMA_MIN_BIT_E810T 3
455 #define ICE_SMA_MAX_BIT_E810T 7
456 #define ICE_PCA9575_P1_OFFSET 8
457
458 /* E810T PCA9575 IO controller registers */
459 #define ICE_PCA9575_P0_IN 0x0
460
461 /* E810T PCA9575 IO controller pin control */
462 #define ICE_E810T_P0_GNSS_PRSNT_N BIT(4)
463
464 #endif /* _ICE_PTP_HW_H_ */
465