xref: /openbmc/linux/drivers/clk/qcom/mmcc-msm8998.c (revision 6973cb78)
1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2019, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/kernel.h>
7 #include <linux/bitops.h>
8 #include <linux/err.h>
9 #include <linux/platform_device.h>
10 #include <linux/module.h>
11 #include <linux/of.h>
12 #include <linux/clk-provider.h>
13 #include <linux/regmap.h>
14 #include <linux/reset-controller.h>
15 
16 #include <dt-bindings/clock/qcom,mmcc-msm8998.h>
17 
18 #include "common.h"
19 #include "clk-regmap.h"
20 #include "clk-regmap-divider.h"
21 #include "clk-alpha-pll.h"
22 #include "clk-rcg.h"
23 #include "clk-branch.h"
24 #include "reset.h"
25 #include "gdsc.h"
26 
27 enum {
28 	P_XO,
29 	P_GPLL0,
30 	P_GPLL0_DIV,
31 	P_MMPLL0_OUT_EVEN,
32 	P_MMPLL1_OUT_EVEN,
33 	P_MMPLL3_OUT_EVEN,
34 	P_MMPLL4_OUT_EVEN,
35 	P_MMPLL5_OUT_EVEN,
36 	P_MMPLL6_OUT_EVEN,
37 	P_MMPLL7_OUT_EVEN,
38 	P_MMPLL10_OUT_EVEN,
39 	P_DSI0PLL,
40 	P_DSI1PLL,
41 	P_DSI0PLL_BYTE,
42 	P_DSI1PLL_BYTE,
43 	P_HDMIPLL,
44 	P_DPVCO,
45 	P_DPLINK,
46 };
47 
48 static const struct clk_div_table post_div_table_fabia_even[] = {
49 	{ 0x0, 1 },
50 	{ 0x1, 2 },
51 	{ 0x3, 4 },
52 	{ 0x7, 8 },
53 	{ }
54 };
55 
56 static struct clk_alpha_pll mmpll0 = {
57 	.offset = 0xc000,
58 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
59 	.clkr = {
60 		.enable_reg = 0x1e0,
61 		.enable_mask = BIT(0),
62 		.hw.init = &(struct clk_init_data){
63 			.name = "mmpll0",
64 			.parent_data = &(const struct clk_parent_data){
65 				.fw_name = "xo"
66 			},
67 			.num_parents = 1,
68 			.ops = &clk_alpha_pll_fixed_fabia_ops,
69 		},
70 	},
71 };
72 
73 static struct clk_alpha_pll_postdiv mmpll0_out_even = {
74 	.offset = 0xc000,
75 	.post_div_shift = 8,
76 	.post_div_table = post_div_table_fabia_even,
77 	.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
78 	.width = 4,
79 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
80 	.clkr.hw.init = &(struct clk_init_data){
81 		.name = "mmpll0_out_even",
82 		.parent_hws = (const struct clk_hw *[]){ &mmpll0.clkr.hw },
83 		.num_parents = 1,
84 		.ops = &clk_alpha_pll_postdiv_fabia_ops,
85 	},
86 };
87 
88 static struct clk_alpha_pll mmpll1 = {
89 	.offset = 0xc050,
90 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
91 	.clkr = {
92 		.enable_reg = 0x1e0,
93 		.enable_mask = BIT(1),
94 		.hw.init = &(struct clk_init_data){
95 			.name = "mmpll1",
96 			.parent_data = &(const struct clk_parent_data){
97 				.fw_name = "xo"
98 			},
99 			.num_parents = 1,
100 			.ops = &clk_alpha_pll_fixed_fabia_ops,
101 		},
102 	},
103 };
104 
105 static struct clk_alpha_pll_postdiv mmpll1_out_even = {
106 	.offset = 0xc050,
107 	.post_div_shift = 8,
108 	.post_div_table = post_div_table_fabia_even,
109 	.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
110 	.width = 4,
111 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
112 	.clkr.hw.init = &(struct clk_init_data){
113 		.name = "mmpll1_out_even",
114 		.parent_hws = (const struct clk_hw *[]){ &mmpll1.clkr.hw },
115 		.num_parents = 1,
116 		.ops = &clk_alpha_pll_postdiv_fabia_ops,
117 	},
118 };
119 
120 static struct clk_alpha_pll mmpll3 = {
121 	.offset = 0x0,
122 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
123 	.clkr.hw.init = &(struct clk_init_data){
124 		.name = "mmpll3",
125 		.parent_data = &(const struct clk_parent_data){
126 			.fw_name = "xo"
127 		},
128 		.num_parents = 1,
129 		.ops = &clk_alpha_pll_fixed_fabia_ops,
130 	},
131 };
132 
133 static struct clk_alpha_pll_postdiv mmpll3_out_even = {
134 	.offset = 0x0,
135 	.post_div_shift = 8,
136 	.post_div_table = post_div_table_fabia_even,
137 	.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
138 	.width = 4,
139 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
140 	.clkr.hw.init = &(struct clk_init_data){
141 		.name = "mmpll3_out_even",
142 		.parent_hws = (const struct clk_hw *[]){ &mmpll3.clkr.hw },
143 		.num_parents = 1,
144 		.ops = &clk_alpha_pll_postdiv_fabia_ops,
145 	},
146 };
147 
148 static struct clk_alpha_pll mmpll4 = {
149 	.offset = 0x50,
150 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
151 	.clkr.hw.init = &(struct clk_init_data){
152 		.name = "mmpll4",
153 		.parent_data = &(const struct clk_parent_data){
154 			.fw_name = "xo"
155 		},
156 		.num_parents = 1,
157 		.ops = &clk_alpha_pll_fixed_fabia_ops,
158 	},
159 };
160 
161 static struct clk_alpha_pll_postdiv mmpll4_out_even = {
162 	.offset = 0x50,
163 	.post_div_shift = 8,
164 	.post_div_table = post_div_table_fabia_even,
165 	.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
166 	.width = 4,
167 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
168 	.clkr.hw.init = &(struct clk_init_data){
169 		.name = "mmpll4_out_even",
170 		.parent_hws = (const struct clk_hw *[]){ &mmpll4.clkr.hw },
171 		.num_parents = 1,
172 		.ops = &clk_alpha_pll_postdiv_fabia_ops,
173 	},
174 };
175 
176 static struct clk_alpha_pll mmpll5 = {
177 	.offset = 0xa0,
178 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
179 	.clkr.hw.init = &(struct clk_init_data){
180 		.name = "mmpll5",
181 		.parent_data = &(const struct clk_parent_data){
182 			.fw_name = "xo"
183 		},
184 		.num_parents = 1,
185 		.ops = &clk_alpha_pll_fixed_fabia_ops,
186 	},
187 };
188 
189 static struct clk_alpha_pll_postdiv mmpll5_out_even = {
190 	.offset = 0xa0,
191 	.post_div_shift = 8,
192 	.post_div_table = post_div_table_fabia_even,
193 	.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
194 	.width = 4,
195 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
196 	.clkr.hw.init = &(struct clk_init_data){
197 		.name = "mmpll5_out_even",
198 		.parent_hws = (const struct clk_hw *[]){ &mmpll5.clkr.hw },
199 		.num_parents = 1,
200 		.ops = &clk_alpha_pll_postdiv_fabia_ops,
201 	},
202 };
203 
204 static struct clk_alpha_pll mmpll6 = {
205 	.offset = 0xf0,
206 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
207 	.clkr.hw.init = &(struct clk_init_data){
208 		.name = "mmpll6",
209 		.parent_data = &(const struct clk_parent_data){
210 			.fw_name = "xo"
211 		},
212 		.num_parents = 1,
213 		.ops = &clk_alpha_pll_fixed_fabia_ops,
214 	},
215 };
216 
217 static struct clk_alpha_pll_postdiv mmpll6_out_even = {
218 	.offset = 0xf0,
219 	.post_div_shift = 8,
220 	.post_div_table = post_div_table_fabia_even,
221 	.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
222 	.width = 4,
223 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
224 	.clkr.hw.init = &(struct clk_init_data){
225 		.name = "mmpll6_out_even",
226 		.parent_hws = (const struct clk_hw *[]){ &mmpll6.clkr.hw },
227 		.num_parents = 1,
228 		.ops = &clk_alpha_pll_postdiv_fabia_ops,
229 	},
230 };
231 
232 static struct clk_alpha_pll mmpll7 = {
233 	.offset = 0x140,
234 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
235 	.clkr.hw.init = &(struct clk_init_data){
236 		.name = "mmpll7",
237 		.parent_data = &(const struct clk_parent_data){
238 			.fw_name = "xo"
239 		},
240 		.num_parents = 1,
241 		.ops = &clk_alpha_pll_fixed_fabia_ops,
242 	},
243 };
244 
245 static struct clk_alpha_pll_postdiv mmpll7_out_even = {
246 	.offset = 0x140,
247 	.post_div_shift = 8,
248 	.post_div_table = post_div_table_fabia_even,
249 	.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
250 	.width = 4,
251 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
252 	.clkr.hw.init = &(struct clk_init_data){
253 		.name = "mmpll7_out_even",
254 		.parent_hws = (const struct clk_hw *[]){ &mmpll7.clkr.hw },
255 		.num_parents = 1,
256 		.ops = &clk_alpha_pll_postdiv_fabia_ops,
257 	},
258 };
259 
260 static struct clk_alpha_pll mmpll10 = {
261 	.offset = 0x190,
262 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
263 	.clkr.hw.init = &(struct clk_init_data){
264 		.name = "mmpll10",
265 		.parent_data = &(const struct clk_parent_data){
266 			.fw_name = "xo"
267 		},
268 		.num_parents = 1,
269 		.ops = &clk_alpha_pll_fixed_fabia_ops,
270 	},
271 };
272 
273 static struct clk_alpha_pll_postdiv mmpll10_out_even = {
274 	.offset = 0x190,
275 	.post_div_shift = 8,
276 	.post_div_table = post_div_table_fabia_even,
277 	.num_post_div = ARRAY_SIZE(post_div_table_fabia_even),
278 	.width = 4,
279 	.regs = clk_alpha_pll_regs[CLK_ALPHA_PLL_TYPE_FABIA],
280 	.clkr.hw.init = &(struct clk_init_data){
281 		.name = "mmpll10_out_even",
282 		.parent_hws = (const struct clk_hw *[]){ &mmpll10.clkr.hw },
283 		.num_parents = 1,
284 		.ops = &clk_alpha_pll_postdiv_fabia_ops,
285 	},
286 };
287 
288 static const struct parent_map mmss_xo_hdmi_map[] = {
289 	{ P_XO, 0 },
290 	{ P_HDMIPLL, 1 },
291 };
292 
293 static const struct clk_parent_data mmss_xo_hdmi[] = {
294 	{ .fw_name = "xo" },
295 	{ .fw_name = "hdmipll" },
296 };
297 
298 static const struct parent_map mmss_xo_dsi0pll_dsi1pll_map[] = {
299 	{ P_XO, 0 },
300 	{ P_DSI0PLL, 1 },
301 	{ P_DSI1PLL, 2 },
302 };
303 
304 static const struct clk_parent_data mmss_xo_dsi0pll_dsi1pll[] = {
305 	{ .fw_name = "xo" },
306 	{ .fw_name = "dsi0dsi" },
307 	{ .fw_name = "dsi1dsi" },
308 };
309 
310 static const struct parent_map mmss_xo_dsibyte_map[] = {
311 	{ P_XO, 0 },
312 	{ P_DSI0PLL_BYTE, 1 },
313 	{ P_DSI1PLL_BYTE, 2 },
314 };
315 
316 static const struct clk_parent_data mmss_xo_dsibyte[] = {
317 	{ .fw_name = "xo" },
318 	{ .fw_name = "dsi0byte" },
319 	{ .fw_name = "dsi1byte" },
320 };
321 
322 static const struct parent_map mmss_xo_dp_map[] = {
323 	{ P_XO, 0 },
324 	{ P_DPLINK, 1 },
325 	{ P_DPVCO, 2 },
326 };
327 
328 static const struct clk_parent_data mmss_xo_dp[] = {
329 	{ .fw_name = "xo" },
330 	{ .fw_name = "dplink" },
331 	{ .fw_name = "dpvco" },
332 };
333 
334 static const struct parent_map mmss_xo_gpll0_gpll0_div_map[] = {
335 	{ P_XO, 0 },
336 	{ P_GPLL0, 5 },
337 	{ P_GPLL0_DIV, 6 },
338 };
339 
340 static const struct clk_parent_data mmss_xo_gpll0_gpll0_div[] = {
341 	{ .fw_name = "xo" },
342 	{ .fw_name = "gpll0" },
343 	{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
344 };
345 
346 static const struct parent_map mmss_xo_mmpll0_gpll0_gpll0_div_map[] = {
347 	{ P_XO, 0 },
348 	{ P_MMPLL0_OUT_EVEN, 1 },
349 	{ P_GPLL0, 5 },
350 	{ P_GPLL0_DIV, 6 },
351 };
352 
353 static const struct clk_parent_data mmss_xo_mmpll0_gpll0_gpll0_div[] = {
354 	{ .fw_name = "xo" },
355 	{ .hw = &mmpll0_out_even.clkr.hw },
356 	{ .fw_name = "gpll0" },
357 	{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
358 };
359 
360 static const struct parent_map mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map[] = {
361 	{ P_XO, 0 },
362 	{ P_MMPLL0_OUT_EVEN, 1 },
363 	{ P_MMPLL1_OUT_EVEN, 2 },
364 	{ P_GPLL0, 5 },
365 	{ P_GPLL0_DIV, 6 },
366 };
367 
368 static const struct clk_parent_data mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div[] = {
369 	{ .fw_name = "xo" },
370 	{ .hw = &mmpll0_out_even.clkr.hw },
371 	{ .hw = &mmpll1_out_even.clkr.hw },
372 	{ .fw_name = "gpll0" },
373 	{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
374 };
375 
376 static const struct parent_map mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map[] = {
377 	{ P_XO, 0 },
378 	{ P_MMPLL0_OUT_EVEN, 1 },
379 	{ P_MMPLL5_OUT_EVEN, 2 },
380 	{ P_GPLL0, 5 },
381 	{ P_GPLL0_DIV, 6 },
382 };
383 
384 static const struct clk_parent_data mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div[] = {
385 	{ .fw_name = "xo" },
386 	{ .hw = &mmpll0_out_even.clkr.hw },
387 	{ .hw = &mmpll5_out_even.clkr.hw },
388 	{ .fw_name = "gpll0" },
389 	{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
390 };
391 
392 static const struct parent_map mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map[] = {
393 	{ P_XO, 0 },
394 	{ P_MMPLL0_OUT_EVEN, 1 },
395 	{ P_MMPLL3_OUT_EVEN, 3 },
396 	{ P_MMPLL6_OUT_EVEN, 4 },
397 	{ P_GPLL0, 5 },
398 	{ P_GPLL0_DIV, 6 },
399 };
400 
401 static const struct clk_parent_data mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div[] = {
402 	{ .fw_name = "xo" },
403 	{ .hw = &mmpll0_out_even.clkr.hw },
404 	{ .hw = &mmpll3_out_even.clkr.hw },
405 	{ .hw = &mmpll6_out_even.clkr.hw },
406 	{ .fw_name = "gpll0" },
407 	{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
408 };
409 
410 static const struct parent_map mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
411 	{ P_XO, 0 },
412 	{ P_MMPLL4_OUT_EVEN, 1 },
413 	{ P_MMPLL7_OUT_EVEN, 2 },
414 	{ P_MMPLL10_OUT_EVEN, 3 },
415 	{ P_GPLL0, 5 },
416 	{ P_GPLL0_DIV, 6 },
417 };
418 
419 static const struct clk_parent_data mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
420 	{ .fw_name = "xo" },
421 	{ .hw = &mmpll4_out_even.clkr.hw },
422 	{ .hw = &mmpll7_out_even.clkr.hw },
423 	{ .hw = &mmpll10_out_even.clkr.hw },
424 	{ .fw_name = "gpll0" },
425 	{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
426 };
427 
428 static const struct parent_map mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
429 	{ P_XO, 0 },
430 	{ P_MMPLL0_OUT_EVEN, 1 },
431 	{ P_MMPLL7_OUT_EVEN, 2 },
432 	{ P_MMPLL10_OUT_EVEN, 3 },
433 	{ P_GPLL0, 5 },
434 	{ P_GPLL0_DIV, 6 },
435 };
436 
437 static const struct clk_parent_data mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div[] = {
438 	{ .fw_name = "xo" },
439 	{ .hw = &mmpll0_out_even.clkr.hw },
440 	{ .hw = &mmpll7_out_even.clkr.hw },
441 	{ .hw = &mmpll10_out_even.clkr.hw },
442 	{ .fw_name = "gpll0" },
443 	{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
444 };
445 
446 static const struct parent_map mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map[] = {
447 	{ P_XO, 0 },
448 	{ P_MMPLL0_OUT_EVEN, 1 },
449 	{ P_MMPLL4_OUT_EVEN, 2 },
450 	{ P_MMPLL7_OUT_EVEN, 3 },
451 	{ P_MMPLL10_OUT_EVEN, 4 },
452 	{ P_GPLL0, 5 },
453 	{ P_GPLL0_DIV, 6 },
454 };
455 
456 static const struct clk_parent_data mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div[] = {
457 	{ .fw_name = "xo" },
458 	{ .hw = &mmpll0_out_even.clkr.hw },
459 	{ .hw = &mmpll4_out_even.clkr.hw },
460 	{ .hw = &mmpll7_out_even.clkr.hw },
461 	{ .hw = &mmpll10_out_even.clkr.hw },
462 	{ .fw_name = "gpll0" },
463 	{ .fw_name = "gpll0_div", .name = "gcc_mmss_gpll0_div_clk" },
464 };
465 
466 static struct clk_rcg2 byte0_clk_src = {
467 	.cmd_rcgr = 0x2120,
468 	.hid_width = 5,
469 	.parent_map = mmss_xo_dsibyte_map,
470 	.clkr.hw.init = &(struct clk_init_data){
471 		.name = "byte0_clk_src",
472 		.parent_data = mmss_xo_dsibyte,
473 		.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
474 		.ops = &clk_byte2_ops,
475 		.flags = CLK_SET_RATE_PARENT,
476 	},
477 };
478 
479 static struct clk_rcg2 byte1_clk_src = {
480 	.cmd_rcgr = 0x2140,
481 	.hid_width = 5,
482 	.parent_map = mmss_xo_dsibyte_map,
483 	.clkr.hw.init = &(struct clk_init_data){
484 		.name = "byte1_clk_src",
485 		.parent_data = mmss_xo_dsibyte,
486 		.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
487 		.ops = &clk_byte2_ops,
488 		.flags = CLK_SET_RATE_PARENT,
489 	},
490 };
491 
492 static const struct freq_tbl ftbl_cci_clk_src[] = {
493 	F(37500000, P_GPLL0, 16, 0, 0),
494 	F(50000000, P_GPLL0, 12, 0, 0),
495 	F(100000000, P_GPLL0, 6, 0, 0),
496 	{ }
497 };
498 
499 static struct clk_rcg2 cci_clk_src = {
500 	.cmd_rcgr = 0x3300,
501 	.hid_width = 5,
502 	.parent_map = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div_map,
503 	.freq_tbl = ftbl_cci_clk_src,
504 	.clkr.hw.init = &(struct clk_init_data){
505 		.name = "cci_clk_src",
506 		.parent_data = mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div,
507 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll7_mmpll10_gpll0_gpll0_div),
508 		.ops = &clk_rcg2_ops,
509 	},
510 };
511 
512 static const struct freq_tbl ftbl_cpp_clk_src[] = {
513 	F(100000000, P_GPLL0, 6, 0, 0),
514 	F(200000000, P_GPLL0, 3, 0, 0),
515 	F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
516 	F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
517 	F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
518 	F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
519 	F(600000000, P_GPLL0, 1, 0, 0),
520 	{ }
521 };
522 
523 static struct clk_rcg2 cpp_clk_src = {
524 	.cmd_rcgr = 0x3640,
525 	.hid_width = 5,
526 	.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
527 	.freq_tbl = ftbl_cpp_clk_src,
528 	.clkr.hw.init = &(struct clk_init_data){
529 		.name = "cpp_clk_src",
530 		.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
531 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
532 		.ops = &clk_rcg2_ops,
533 	},
534 };
535 
536 static const struct freq_tbl ftbl_csi_clk_src[] = {
537 	F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
538 	F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
539 	F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
540 	F(300000000, P_GPLL0, 2, 0, 0),
541 	F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
542 	F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
543 	{ }
544 };
545 
546 static struct clk_rcg2 csi0_clk_src = {
547 	.cmd_rcgr = 0x3090,
548 	.hid_width = 5,
549 	.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
550 	.freq_tbl = ftbl_csi_clk_src,
551 	.clkr.hw.init = &(struct clk_init_data){
552 		.name = "csi0_clk_src",
553 		.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
554 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
555 		.ops = &clk_rcg2_ops,
556 	},
557 };
558 
559 static struct clk_rcg2 csi1_clk_src = {
560 	.cmd_rcgr = 0x3100,
561 	.hid_width = 5,
562 	.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
563 	.freq_tbl = ftbl_csi_clk_src,
564 	.clkr.hw.init = &(struct clk_init_data){
565 		.name = "csi1_clk_src",
566 		.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
567 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
568 		.ops = &clk_rcg2_ops,
569 	},
570 };
571 
572 static struct clk_rcg2 csi2_clk_src = {
573 	.cmd_rcgr = 0x3160,
574 	.hid_width = 5,
575 	.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
576 	.freq_tbl = ftbl_csi_clk_src,
577 	.clkr.hw.init = &(struct clk_init_data){
578 		.name = "csi2_clk_src",
579 		.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
580 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
581 		.ops = &clk_rcg2_ops,
582 	},
583 };
584 
585 static struct clk_rcg2 csi3_clk_src = {
586 	.cmd_rcgr = 0x31c0,
587 	.hid_width = 5,
588 	.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
589 	.freq_tbl = ftbl_csi_clk_src,
590 	.clkr.hw.init = &(struct clk_init_data){
591 		.name = "csi3_clk_src",
592 		.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
593 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
594 		.ops = &clk_rcg2_ops,
595 	},
596 };
597 
598 static const struct freq_tbl ftbl_csiphy_clk_src[] = {
599 	F(164571429, P_MMPLL10_OUT_EVEN, 3.5, 0, 0),
600 	F(256000000, P_MMPLL4_OUT_EVEN, 3, 0, 0),
601 	F(274290000, P_MMPLL7_OUT_EVEN, 3.5, 0, 0),
602 	F(300000000, P_GPLL0, 2, 0, 0),
603 	F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
604 	{ }
605 };
606 
607 static struct clk_rcg2 csiphy_clk_src = {
608 	.cmd_rcgr = 0x3800,
609 	.hid_width = 5,
610 	.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
611 	.freq_tbl = ftbl_csiphy_clk_src,
612 	.clkr.hw.init = &(struct clk_init_data){
613 		.name = "csiphy_clk_src",
614 		.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
615 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
616 		.ops = &clk_rcg2_ops,
617 	},
618 };
619 
620 static const struct freq_tbl ftbl_csiphytimer_clk_src[] = {
621 	F(200000000, P_GPLL0, 3, 0, 0),
622 	F(269333333, P_MMPLL0_OUT_EVEN, 3, 0, 0),
623 	{ }
624 };
625 
626 static struct clk_rcg2 csi0phytimer_clk_src = {
627 	.cmd_rcgr = 0x3000,
628 	.hid_width = 5,
629 	.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
630 	.freq_tbl = ftbl_csiphytimer_clk_src,
631 	.clkr.hw.init = &(struct clk_init_data){
632 		.name = "csi0phytimer_clk_src",
633 		.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
634 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
635 		.ops = &clk_rcg2_ops,
636 	},
637 };
638 
639 static struct clk_rcg2 csi1phytimer_clk_src = {
640 	.cmd_rcgr = 0x3030,
641 	.hid_width = 5,
642 	.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
643 	.freq_tbl = ftbl_csiphytimer_clk_src,
644 	.clkr.hw.init = &(struct clk_init_data){
645 		.name = "csi1phytimer_clk_src",
646 		.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
647 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
648 		.ops = &clk_rcg2_ops,
649 	},
650 };
651 
652 static struct clk_rcg2 csi2phytimer_clk_src = {
653 	.cmd_rcgr = 0x3060,
654 	.hid_width = 5,
655 	.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
656 	.freq_tbl = ftbl_csiphytimer_clk_src,
657 	.clkr.hw.init = &(struct clk_init_data){
658 		.name = "csi2phytimer_clk_src",
659 		.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
660 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
661 		.ops = &clk_rcg2_ops,
662 	},
663 };
664 
665 static const struct freq_tbl ftbl_dp_aux_clk_src[] = {
666 	F(19200000, P_XO, 1, 0, 0),
667 	{ }
668 };
669 
670 static struct clk_rcg2 dp_aux_clk_src = {
671 	.cmd_rcgr = 0x2260,
672 	.hid_width = 5,
673 	.parent_map = mmss_xo_gpll0_gpll0_div_map,
674 	.freq_tbl = ftbl_dp_aux_clk_src,
675 	.clkr.hw.init = &(struct clk_init_data){
676 		.name = "dp_aux_clk_src",
677 		.parent_data = mmss_xo_gpll0_gpll0_div,
678 		.num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
679 		.ops = &clk_rcg2_ops,
680 	},
681 };
682 
683 static const struct freq_tbl ftbl_dp_crypto_clk_src[] = {
684 	F(101250, P_DPLINK, 1, 5, 16),
685 	F(168750, P_DPLINK, 1, 5, 16),
686 	F(337500, P_DPLINK, 1, 5, 16),
687 	{ }
688 };
689 
690 static struct clk_rcg2 dp_crypto_clk_src = {
691 	.cmd_rcgr = 0x2220,
692 	.hid_width = 5,
693 	.parent_map = mmss_xo_dp_map,
694 	.freq_tbl = ftbl_dp_crypto_clk_src,
695 	.clkr.hw.init = &(struct clk_init_data){
696 		.name = "dp_crypto_clk_src",
697 		.parent_data = mmss_xo_dp,
698 		.num_parents = ARRAY_SIZE(mmss_xo_dp),
699 		.ops = &clk_rcg2_ops,
700 	},
701 };
702 
703 static const struct freq_tbl ftbl_dp_link_clk_src[] = {
704 	F(162000, P_DPLINK, 2, 0, 0),
705 	F(270000, P_DPLINK, 2, 0, 0),
706 	F(540000, P_DPLINK, 2, 0, 0),
707 	{ }
708 };
709 
710 static struct clk_rcg2 dp_link_clk_src = {
711 	.cmd_rcgr = 0x2200,
712 	.hid_width = 5,
713 	.parent_map = mmss_xo_dp_map,
714 	.freq_tbl = ftbl_dp_link_clk_src,
715 	.clkr.hw.init = &(struct clk_init_data){
716 		.name = "dp_link_clk_src",
717 		.parent_data = mmss_xo_dp,
718 		.num_parents = ARRAY_SIZE(mmss_xo_dp),
719 		.ops = &clk_rcg2_ops,
720 	},
721 };
722 
723 static const struct freq_tbl ftbl_dp_pixel_clk_src[] = {
724 	F(154000000, P_DPVCO, 1, 0, 0),
725 	F(337500000, P_DPVCO, 2, 0, 0),
726 	F(675000000, P_DPVCO, 2, 0, 0),
727 	{ }
728 };
729 
730 static struct clk_rcg2 dp_pixel_clk_src = {
731 	.cmd_rcgr = 0x2240,
732 	.hid_width = 5,
733 	.parent_map = mmss_xo_dp_map,
734 	.freq_tbl = ftbl_dp_pixel_clk_src,
735 	.clkr.hw.init = &(struct clk_init_data){
736 		.name = "dp_pixel_clk_src",
737 		.parent_data = mmss_xo_dp,
738 		.num_parents = ARRAY_SIZE(mmss_xo_dp),
739 		.ops = &clk_rcg2_ops,
740 	},
741 };
742 
743 static const struct freq_tbl ftbl_esc_clk_src[] = {
744 	F(19200000, P_XO, 1, 0, 0),
745 	{ }
746 };
747 
748 static struct clk_rcg2 esc0_clk_src = {
749 	.cmd_rcgr = 0x2160,
750 	.hid_width = 5,
751 	.parent_map = mmss_xo_dsibyte_map,
752 	.freq_tbl = ftbl_esc_clk_src,
753 	.clkr.hw.init = &(struct clk_init_data){
754 		.name = "esc0_clk_src",
755 		.parent_data = mmss_xo_dsibyte,
756 		.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
757 		.ops = &clk_rcg2_ops,
758 	},
759 };
760 
761 static struct clk_rcg2 esc1_clk_src = {
762 	.cmd_rcgr = 0x2180,
763 	.hid_width = 5,
764 	.parent_map = mmss_xo_dsibyte_map,
765 	.freq_tbl = ftbl_esc_clk_src,
766 	.clkr.hw.init = &(struct clk_init_data){
767 		.name = "esc1_clk_src",
768 		.parent_data = mmss_xo_dsibyte,
769 		.num_parents = ARRAY_SIZE(mmss_xo_dsibyte),
770 		.ops = &clk_rcg2_ops,
771 	},
772 };
773 
774 static const struct freq_tbl ftbl_extpclk_clk_src[] = {
775 	{ .src = P_HDMIPLL },
776 	{ }
777 };
778 
779 static struct clk_rcg2 extpclk_clk_src = {
780 	.cmd_rcgr = 0x2060,
781 	.hid_width = 5,
782 	.parent_map = mmss_xo_hdmi_map,
783 	.freq_tbl = ftbl_extpclk_clk_src,
784 	.clkr.hw.init = &(struct clk_init_data){
785 		.name = "extpclk_clk_src",
786 		.parent_data = mmss_xo_hdmi,
787 		.num_parents = ARRAY_SIZE(mmss_xo_hdmi),
788 		.ops = &clk_byte_ops,
789 		.flags = CLK_SET_RATE_PARENT,
790 	},
791 };
792 
793 static const struct freq_tbl ftbl_fd_core_clk_src[] = {
794 	F(100000000, P_GPLL0, 6, 0, 0),
795 	F(200000000, P_GPLL0, 3, 0, 0),
796 	F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
797 	F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
798 	F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
799 	{ }
800 };
801 
802 static struct clk_rcg2 fd_core_clk_src = {
803 	.cmd_rcgr = 0x3b00,
804 	.hid_width = 5,
805 	.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
806 	.freq_tbl = ftbl_fd_core_clk_src,
807 	.clkr.hw.init = &(struct clk_init_data){
808 		.name = "fd_core_clk_src",
809 		.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
810 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
811 		.ops = &clk_rcg2_ops,
812 	},
813 };
814 
815 static const struct freq_tbl ftbl_hdmi_clk_src[] = {
816 	F(19200000, P_XO, 1, 0, 0),
817 	{ }
818 };
819 
820 static struct clk_rcg2 hdmi_clk_src = {
821 	.cmd_rcgr = 0x2100,
822 	.hid_width = 5,
823 	.parent_map = mmss_xo_gpll0_gpll0_div_map,
824 	.freq_tbl = ftbl_hdmi_clk_src,
825 	.clkr.hw.init = &(struct clk_init_data){
826 		.name = "hdmi_clk_src",
827 		.parent_data = mmss_xo_gpll0_gpll0_div,
828 		.num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
829 		.ops = &clk_rcg2_ops,
830 	},
831 };
832 
833 static const struct freq_tbl ftbl_jpeg0_clk_src[] = {
834 	F(75000000, P_GPLL0, 8, 0, 0),
835 	F(150000000, P_GPLL0, 4, 0, 0),
836 	F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
837 	F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
838 	{ }
839 };
840 
841 static struct clk_rcg2 jpeg0_clk_src = {
842 	.cmd_rcgr = 0x3500,
843 	.hid_width = 5,
844 	.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
845 	.freq_tbl = ftbl_jpeg0_clk_src,
846 	.clkr.hw.init = &(struct clk_init_data){
847 		.name = "jpeg0_clk_src",
848 		.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
849 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
850 		.ops = &clk_rcg2_ops,
851 	},
852 };
853 
854 static const struct freq_tbl ftbl_maxi_clk_src[] = {
855 	F(19200000, P_XO, 1, 0, 0),
856 	F(75000000, P_GPLL0_DIV, 4, 0, 0),
857 	F(171428571, P_GPLL0, 3.5, 0, 0),
858 	F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
859 	F(406000000, P_MMPLL1_OUT_EVEN, 2, 0, 0),
860 	{ }
861 };
862 
863 static struct clk_rcg2 maxi_clk_src = {
864 	.cmd_rcgr = 0xf020,
865 	.hid_width = 5,
866 	.parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
867 	.freq_tbl = ftbl_maxi_clk_src,
868 	.clkr.hw.init = &(struct clk_init_data){
869 		.name = "maxi_clk_src",
870 		.parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
871 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
872 		.ops = &clk_rcg2_ops,
873 	},
874 };
875 
876 static const struct freq_tbl ftbl_mclk_clk_src[] = {
877 	F(4800000, P_XO, 4, 0, 0),
878 	F(6000000, P_GPLL0_DIV, 10, 1, 5),
879 	F(8000000, P_GPLL0_DIV, 1, 2, 75),
880 	F(9600000, P_XO, 2, 0, 0),
881 	F(16666667, P_GPLL0_DIV, 2, 1, 9),
882 	F(19200000, P_XO, 1, 0, 0),
883 	F(24000000, P_GPLL0_DIV, 1, 2, 25),
884 	F(33333333, P_GPLL0_DIV, 1, 2, 9),
885 	F(48000000, P_GPLL0, 1, 2, 25),
886 	F(66666667, P_GPLL0, 1, 2, 9),
887 	{ }
888 };
889 
890 static struct clk_rcg2 mclk0_clk_src = {
891 	.cmd_rcgr = 0x3360,
892 	.hid_width = 5,
893 	.parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
894 	.freq_tbl = ftbl_mclk_clk_src,
895 	.clkr.hw.init = &(struct clk_init_data){
896 		.name = "mclk0_clk_src",
897 		.parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
898 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
899 		.ops = &clk_rcg2_ops,
900 	},
901 };
902 
903 static struct clk_rcg2 mclk1_clk_src = {
904 	.cmd_rcgr = 0x3390,
905 	.hid_width = 5,
906 	.parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
907 	.freq_tbl = ftbl_mclk_clk_src,
908 	.clkr.hw.init = &(struct clk_init_data){
909 		.name = "mclk1_clk_src",
910 		.parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
911 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
912 		.ops = &clk_rcg2_ops,
913 	},
914 };
915 
916 static struct clk_rcg2 mclk2_clk_src = {
917 	.cmd_rcgr = 0x33c0,
918 	.hid_width = 5,
919 	.parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
920 	.freq_tbl = ftbl_mclk_clk_src,
921 	.clkr.hw.init = &(struct clk_init_data){
922 		.name = "mclk2_clk_src",
923 		.parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
924 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
925 		.ops = &clk_rcg2_ops,
926 	},
927 };
928 
929 static struct clk_rcg2 mclk3_clk_src = {
930 	.cmd_rcgr = 0x33f0,
931 	.hid_width = 5,
932 	.parent_map = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
933 	.freq_tbl = ftbl_mclk_clk_src,
934 	.clkr.hw.init = &(struct clk_init_data){
935 		.name = "mclk3_clk_src",
936 		.parent_data = mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
937 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
938 		.ops = &clk_rcg2_ops,
939 	},
940 };
941 
942 static const struct freq_tbl ftbl_mdp_clk_src[] = {
943 	F(85714286, P_GPLL0, 7, 0, 0),
944 	F(100000000, P_GPLL0, 6, 0, 0),
945 	F(150000000, P_GPLL0, 4, 0, 0),
946 	F(171428571, P_GPLL0, 3.5, 0, 0),
947 	F(200000000, P_GPLL0, 3, 0, 0),
948 	F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
949 	F(300000000, P_GPLL0, 2, 0, 0),
950 	F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
951 	F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
952 	{ }
953 };
954 
955 static struct clk_rcg2 mdp_clk_src = {
956 	.cmd_rcgr = 0x2040,
957 	.hid_width = 5,
958 	.parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
959 	.freq_tbl = ftbl_mdp_clk_src,
960 	.clkr.hw.init = &(struct clk_init_data){
961 		.name = "mdp_clk_src",
962 		.parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
963 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div),
964 		.ops = &clk_rcg2_ops,
965 	},
966 };
967 
968 static const struct freq_tbl ftbl_vsync_clk_src[] = {
969 	F(19200000, P_XO, 1, 0, 0),
970 	{ }
971 };
972 
973 static struct clk_rcg2 vsync_clk_src = {
974 	.cmd_rcgr = 0x2080,
975 	.hid_width = 5,
976 	.parent_map = mmss_xo_gpll0_gpll0_div_map,
977 	.freq_tbl = ftbl_vsync_clk_src,
978 	.clkr.hw.init = &(struct clk_init_data){
979 		.name = "vsync_clk_src",
980 		.parent_data = mmss_xo_gpll0_gpll0_div,
981 		.num_parents = ARRAY_SIZE(mmss_xo_gpll0_gpll0_div),
982 		.ops = &clk_rcg2_ops,
983 	},
984 };
985 
986 static const struct freq_tbl ftbl_ahb_clk_src[] = {
987 	F(19200000, P_XO, 1, 0, 0),
988 	F(40000000, P_GPLL0, 15, 0, 0),
989 	F(80800000, P_MMPLL0_OUT_EVEN, 10, 0, 0),
990 	{ }
991 };
992 
993 static struct clk_rcg2 ahb_clk_src = {
994 	.cmd_rcgr = 0x5000,
995 	.hid_width = 5,
996 	.parent_map = mmss_xo_mmpll0_gpll0_gpll0_div_map,
997 	.freq_tbl = ftbl_ahb_clk_src,
998 	.clkr.hw.init = &(struct clk_init_data){
999 		.name = "ahb_clk_src",
1000 		.parent_data = mmss_xo_mmpll0_gpll0_gpll0_div,
1001 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_gpll0_gpll0_div),
1002 		.ops = &clk_rcg2_ops,
1003 	},
1004 };
1005 
1006 static const struct freq_tbl ftbl_axi_clk_src[] = {
1007 	F(75000000, P_GPLL0, 8, 0, 0),
1008 	F(171428571, P_GPLL0, 3.5, 0, 0),
1009 	F(240000000, P_GPLL0, 2.5, 0, 0),
1010 	F(323200000, P_MMPLL0_OUT_EVEN, 2.5, 0, 0),
1011 	F(406000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1012 	{ }
1013 };
1014 
1015 /* RO to linux */
1016 static struct clk_rcg2 axi_clk_src = {
1017 	.cmd_rcgr = 0xd000,
1018 	.hid_width = 5,
1019 	.parent_map = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div_map,
1020 	.freq_tbl = ftbl_axi_clk_src,
1021 	.clkr.hw.init = &(struct clk_init_data){
1022 		.name = "axi_clk_src",
1023 		.parent_data = mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div,
1024 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll1_gpll0_gpll0_div),
1025 		.ops = &clk_rcg2_ops,
1026 	},
1027 };
1028 
1029 static struct clk_rcg2 pclk0_clk_src = {
1030 	.cmd_rcgr = 0x2000,
1031 	.mnd_width = 8,
1032 	.hid_width = 5,
1033 	.parent_map = mmss_xo_dsi0pll_dsi1pll_map,
1034 	.clkr.hw.init = &(struct clk_init_data){
1035 		.name = "pclk0_clk_src",
1036 		.parent_data = mmss_xo_dsi0pll_dsi1pll,
1037 		.num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
1038 		.ops = &clk_pixel_ops,
1039 		.flags = CLK_SET_RATE_PARENT,
1040 	},
1041 };
1042 
1043 static struct clk_rcg2 pclk1_clk_src = {
1044 	.cmd_rcgr = 0x2020,
1045 	.mnd_width = 8,
1046 	.hid_width = 5,
1047 	.parent_map = mmss_xo_dsi0pll_dsi1pll_map,
1048 	.clkr.hw.init = &(struct clk_init_data){
1049 		.name = "pclk1_clk_src",
1050 		.parent_data = mmss_xo_dsi0pll_dsi1pll,
1051 		.num_parents = ARRAY_SIZE(mmss_xo_dsi0pll_dsi1pll),
1052 		.ops = &clk_pixel_ops,
1053 		.flags = CLK_SET_RATE_PARENT,
1054 	},
1055 };
1056 
1057 static const struct freq_tbl ftbl_rot_clk_src[] = {
1058 	F(171428571, P_GPLL0, 3.5, 0, 0),
1059 	F(275000000, P_MMPLL5_OUT_EVEN, 3, 0, 0),
1060 	F(330000000, P_MMPLL5_OUT_EVEN, 2.5, 0, 0),
1061 	F(412500000, P_MMPLL5_OUT_EVEN, 2, 0, 0),
1062 	{ }
1063 };
1064 
1065 static struct clk_rcg2 rot_clk_src = {
1066 	.cmd_rcgr = 0x21a0,
1067 	.hid_width = 5,
1068 	.parent_map = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div_map,
1069 	.freq_tbl = ftbl_rot_clk_src,
1070 	.clkr.hw.init = &(struct clk_init_data){
1071 		.name = "rot_clk_src",
1072 		.parent_data = mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div,
1073 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll5_gpll0_gpll0_div),
1074 		.ops = &clk_rcg2_ops,
1075 	},
1076 };
1077 
1078 static const struct freq_tbl ftbl_video_core_clk_src[] = {
1079 	F(200000000, P_GPLL0, 3, 0, 0),
1080 	F(269330000, P_MMPLL0_OUT_EVEN, 3, 0, 0),
1081 	F(355200000, P_MMPLL6_OUT_EVEN, 2.5, 0, 0),
1082 	F(444000000, P_MMPLL6_OUT_EVEN, 2, 0, 0),
1083 	F(533000000, P_MMPLL3_OUT_EVEN, 2, 0, 0),
1084 	{ }
1085 };
1086 
1087 static struct clk_rcg2 video_core_clk_src = {
1088 	.cmd_rcgr = 0x1000,
1089 	.hid_width = 5,
1090 	.parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1091 	.freq_tbl = ftbl_video_core_clk_src,
1092 	.clkr.hw.init = &(struct clk_init_data){
1093 		.name = "video_core_clk_src",
1094 		.parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1095 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div),
1096 		.ops = &clk_rcg2_ops,
1097 	},
1098 };
1099 
1100 static struct clk_rcg2 video_subcore0_clk_src = {
1101 	.cmd_rcgr = 0x1060,
1102 	.hid_width = 5,
1103 	.parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1104 	.freq_tbl = ftbl_video_core_clk_src,
1105 	.clkr.hw.init = &(struct clk_init_data){
1106 		.name = "video_subcore0_clk_src",
1107 		.parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1108 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div),
1109 		.ops = &clk_rcg2_ops,
1110 	},
1111 };
1112 
1113 static struct clk_rcg2 video_subcore1_clk_src = {
1114 	.cmd_rcgr = 0x1080,
1115 	.hid_width = 5,
1116 	.parent_map = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div_map,
1117 	.freq_tbl = ftbl_video_core_clk_src,
1118 	.clkr.hw.init = &(struct clk_init_data){
1119 		.name = "video_subcore1_clk_src",
1120 		.parent_data = mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div,
1121 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll3_mmpll6_gpll0_gpll0_div),
1122 		.ops = &clk_rcg2_ops,
1123 	},
1124 };
1125 
1126 static const struct freq_tbl ftbl_vfe_clk_src[] = {
1127 	F(200000000, P_GPLL0, 3, 0, 0),
1128 	F(300000000, P_GPLL0, 2, 0, 0),
1129 	F(320000000, P_MMPLL7_OUT_EVEN, 3, 0, 0),
1130 	F(384000000, P_MMPLL4_OUT_EVEN, 2, 0, 0),
1131 	F(404000000, P_MMPLL0_OUT_EVEN, 2, 0, 0),
1132 	F(480000000, P_MMPLL7_OUT_EVEN, 2, 0, 0),
1133 	F(576000000, P_MMPLL10_OUT_EVEN, 1, 0, 0),
1134 	F(600000000, P_GPLL0, 1, 0, 0),
1135 	{ }
1136 };
1137 
1138 static struct clk_rcg2 vfe0_clk_src = {
1139 	.cmd_rcgr = 0x3600,
1140 	.hid_width = 5,
1141 	.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
1142 	.freq_tbl = ftbl_vfe_clk_src,
1143 	.clkr.hw.init = &(struct clk_init_data){
1144 		.name = "vfe0_clk_src",
1145 		.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
1146 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
1147 		.ops = &clk_rcg2_ops,
1148 	},
1149 };
1150 
1151 static struct clk_rcg2 vfe1_clk_src = {
1152 	.cmd_rcgr = 0x3620,
1153 	.hid_width = 5,
1154 	.parent_map = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div_map,
1155 	.freq_tbl = ftbl_vfe_clk_src,
1156 	.clkr.hw.init = &(struct clk_init_data){
1157 		.name = "vfe1_clk_src",
1158 		.parent_data = mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div,
1159 		.num_parents = ARRAY_SIZE(mmss_xo_mmpll0_mmpll4_mmpll7_mmpll10_gpll0_gpll0_div),
1160 		.ops = &clk_rcg2_ops,
1161 	},
1162 };
1163 
1164 static struct clk_branch misc_ahb_clk = {
1165 	.halt_reg = 0x328,
1166 	.hwcg_reg = 0x328,
1167 	.hwcg_bit = 1,
1168 	.clkr = {
1169 		.enable_reg = 0x328,
1170 		.enable_mask = BIT(0),
1171 		.hw.init = &(struct clk_init_data){
1172 			.name = "misc_ahb_clk",
1173 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1174 			.num_parents = 1,
1175 			.ops = &clk_branch2_ops,
1176 			.flags = CLK_SET_RATE_PARENT,
1177 		},
1178 	},
1179 };
1180 
1181 static struct clk_branch video_core_clk = {
1182 	.halt_reg = 0x1028,
1183 	.clkr = {
1184 		.enable_reg = 0x1028,
1185 		.enable_mask = BIT(0),
1186 		.hw.init = &(struct clk_init_data){
1187 			.name = "video_core_clk",
1188 			.parent_hws = (const struct clk_hw *[]){ &video_core_clk_src.clkr.hw },
1189 			.num_parents = 1,
1190 			.ops = &clk_branch2_ops,
1191 			.flags = CLK_SET_RATE_PARENT,
1192 		},
1193 	},
1194 };
1195 
1196 static struct clk_branch video_ahb_clk = {
1197 	.halt_reg = 0x1030,
1198 	.hwcg_reg = 0x1030,
1199 	.hwcg_bit = 1,
1200 	.clkr = {
1201 		.enable_reg = 0x1030,
1202 		.enable_mask = BIT(0),
1203 		.hw.init = &(struct clk_init_data){
1204 			.name = "video_ahb_clk",
1205 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1206 			.num_parents = 1,
1207 			.ops = &clk_branch2_ops,
1208 			.flags = CLK_SET_RATE_PARENT,
1209 		},
1210 	},
1211 };
1212 
1213 static struct clk_branch video_axi_clk = {
1214 	.halt_reg = 0x1034,
1215 	.clkr = {
1216 		.enable_reg = 0x1034,
1217 		.enable_mask = BIT(0),
1218 		.hw.init = &(struct clk_init_data){
1219 			.name = "video_axi_clk",
1220 			.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1221 			.num_parents = 1,
1222 			.ops = &clk_branch2_ops,
1223 		},
1224 	},
1225 };
1226 
1227 static struct clk_branch video_maxi_clk = {
1228 	.halt_reg = 0x1038,
1229 	.clkr = {
1230 		.enable_reg = 0x1038,
1231 		.enable_mask = BIT(0),
1232 		.hw.init = &(struct clk_init_data){
1233 			.name = "video_maxi_clk",
1234 			.parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
1235 			.num_parents = 1,
1236 			.ops = &clk_branch2_ops,
1237 			.flags = CLK_SET_RATE_PARENT,
1238 		},
1239 	},
1240 };
1241 
1242 static struct clk_branch video_subcore0_clk = {
1243 	.halt_reg = 0x1048,
1244 	.clkr = {
1245 		.enable_reg = 0x1048,
1246 		.enable_mask = BIT(0),
1247 		.hw.init = &(struct clk_init_data){
1248 			.name = "video_subcore0_clk",
1249 			.parent_hws = (const struct clk_hw *[]){ &video_subcore0_clk_src.clkr.hw },
1250 			.num_parents = 1,
1251 			.ops = &clk_branch2_ops,
1252 			.flags = CLK_SET_RATE_PARENT,
1253 		},
1254 	},
1255 };
1256 
1257 static struct clk_branch video_subcore1_clk = {
1258 	.halt_reg = 0x104c,
1259 	.clkr = {
1260 		.enable_reg = 0x104c,
1261 		.enable_mask = BIT(0),
1262 		.hw.init = &(struct clk_init_data){
1263 			.name = "video_subcore1_clk",
1264 			.parent_hws = (const struct clk_hw *[]){ &video_subcore1_clk_src.clkr.hw },
1265 			.num_parents = 1,
1266 			.ops = &clk_branch2_ops,
1267 			.flags = CLK_SET_RATE_PARENT,
1268 		},
1269 	},
1270 };
1271 
1272 static struct clk_branch mdss_ahb_clk = {
1273 	.halt_reg = 0x2308,
1274 	.hwcg_reg = 0x2308,
1275 	.hwcg_bit = 1,
1276 	.clkr = {
1277 		.enable_reg = 0x2308,
1278 		.enable_mask = BIT(0),
1279 		.hw.init = &(struct clk_init_data){
1280 			.name = "mdss_ahb_clk",
1281 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1282 			.num_parents = 1,
1283 			.ops = &clk_branch2_ops,
1284 			.flags = CLK_SET_RATE_PARENT,
1285 		},
1286 	},
1287 };
1288 
1289 static struct clk_branch mdss_hdmi_dp_ahb_clk = {
1290 	.halt_reg = 0x230c,
1291 	.clkr = {
1292 		.enable_reg = 0x230c,
1293 		.enable_mask = BIT(0),
1294 		.hw.init = &(struct clk_init_data){
1295 			.name = "mdss_hdmi_dp_ahb_clk",
1296 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1297 			.num_parents = 1,
1298 			.ops = &clk_branch2_ops,
1299 			.flags = CLK_SET_RATE_PARENT,
1300 		},
1301 	},
1302 };
1303 
1304 static struct clk_branch mdss_axi_clk = {
1305 	.halt_reg = 0x2310,
1306 	.clkr = {
1307 		.enable_reg = 0x2310,
1308 		.enable_mask = BIT(0),
1309 		.hw.init = &(struct clk_init_data){
1310 			.name = "mdss_axi_clk",
1311 			.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
1312 			.num_parents = 1,
1313 			.ops = &clk_branch2_ops,
1314 		},
1315 	},
1316 };
1317 
1318 static struct clk_branch mdss_pclk0_clk = {
1319 	.halt_reg = 0x2314,
1320 	.clkr = {
1321 		.enable_reg = 0x2314,
1322 		.enable_mask = BIT(0),
1323 		.hw.init = &(struct clk_init_data){
1324 			.name = "mdss_pclk0_clk",
1325 			.parent_hws = (const struct clk_hw *[]){ &pclk0_clk_src.clkr.hw },
1326 			.num_parents = 1,
1327 			.ops = &clk_branch2_ops,
1328 			.flags = CLK_SET_RATE_PARENT,
1329 		},
1330 	},
1331 };
1332 
1333 static struct clk_branch mdss_pclk1_clk = {
1334 	.halt_reg = 0x2318,
1335 	.clkr = {
1336 		.enable_reg = 0x2318,
1337 		.enable_mask = BIT(0),
1338 		.hw.init = &(struct clk_init_data){
1339 			.name = "mdss_pclk1_clk",
1340 			.parent_hws = (const struct clk_hw *[]){ &pclk1_clk_src.clkr.hw },
1341 			.num_parents = 1,
1342 			.ops = &clk_branch2_ops,
1343 			.flags = CLK_SET_RATE_PARENT,
1344 		},
1345 	},
1346 };
1347 
1348 static struct clk_branch mdss_mdp_clk = {
1349 	.halt_reg = 0x231c,
1350 	.clkr = {
1351 		.enable_reg = 0x231c,
1352 		.enable_mask = BIT(0),
1353 		.hw.init = &(struct clk_init_data){
1354 			.name = "mdss_mdp_clk",
1355 			.parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1356 			.num_parents = 1,
1357 			.ops = &clk_branch2_ops,
1358 			.flags = CLK_SET_RATE_PARENT,
1359 		},
1360 	},
1361 };
1362 
1363 static struct clk_branch mdss_mdp_lut_clk = {
1364 	.halt_reg = 0x2320,
1365 	.clkr = {
1366 		.enable_reg = 0x2320,
1367 		.enable_mask = BIT(0),
1368 		.hw.init = &(struct clk_init_data){
1369 			.name = "mdss_mdp_lut_clk",
1370 			.parent_hws = (const struct clk_hw *[]){ &mdp_clk_src.clkr.hw },
1371 			.num_parents = 1,
1372 			.ops = &clk_branch2_ops,
1373 			.flags = CLK_SET_RATE_PARENT,
1374 		},
1375 	},
1376 };
1377 
1378 static struct clk_branch mdss_extpclk_clk = {
1379 	.halt_reg = 0x2324,
1380 	.clkr = {
1381 		.enable_reg = 0x2324,
1382 		.enable_mask = BIT(0),
1383 		.hw.init = &(struct clk_init_data){
1384 			.name = "mdss_extpclk_clk",
1385 			.parent_hws = (const struct clk_hw *[]){ &extpclk_clk_src.clkr.hw },
1386 			.num_parents = 1,
1387 			.ops = &clk_branch2_ops,
1388 			.flags = CLK_SET_RATE_PARENT,
1389 		},
1390 	},
1391 };
1392 
1393 static struct clk_branch mdss_vsync_clk = {
1394 	.halt_reg = 0x2328,
1395 	.clkr = {
1396 		.enable_reg = 0x2328,
1397 		.enable_mask = BIT(0),
1398 		.hw.init = &(struct clk_init_data){
1399 			.name = "mdss_vsync_clk",
1400 			.parent_hws = (const struct clk_hw *[]){ &vsync_clk_src.clkr.hw },
1401 			.num_parents = 1,
1402 			.ops = &clk_branch2_ops,
1403 			.flags = CLK_SET_RATE_PARENT,
1404 		},
1405 	},
1406 };
1407 
1408 static struct clk_branch mdss_hdmi_clk = {
1409 	.halt_reg = 0x2338,
1410 	.clkr = {
1411 		.enable_reg = 0x2338,
1412 		.enable_mask = BIT(0),
1413 		.hw.init = &(struct clk_init_data){
1414 			.name = "mdss_hdmi_clk",
1415 			.parent_hws = (const struct clk_hw *[]){ &hdmi_clk_src.clkr.hw },
1416 			.num_parents = 1,
1417 			.ops = &clk_branch2_ops,
1418 			.flags = CLK_SET_RATE_PARENT,
1419 		},
1420 	},
1421 };
1422 
1423 static struct clk_branch mdss_byte0_clk = {
1424 	.halt_reg = 0x233c,
1425 	.clkr = {
1426 		.enable_reg = 0x233c,
1427 		.enable_mask = BIT(0),
1428 		.hw.init = &(struct clk_init_data){
1429 			.name = "mdss_byte0_clk",
1430 			.parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1431 			.num_parents = 1,
1432 			.ops = &clk_branch2_ops,
1433 			.flags = CLK_SET_RATE_PARENT,
1434 		},
1435 	},
1436 };
1437 
1438 static struct clk_branch mdss_byte1_clk = {
1439 	.halt_reg = 0x2340,
1440 	.clkr = {
1441 		.enable_reg = 0x2340,
1442 		.enable_mask = BIT(0),
1443 		.hw.init = &(struct clk_init_data){
1444 			.name = "mdss_byte1_clk",
1445 			.parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1446 			.num_parents = 1,
1447 			.ops = &clk_branch2_ops,
1448 			.flags = CLK_SET_RATE_PARENT,
1449 		},
1450 	},
1451 };
1452 
1453 static struct clk_branch mdss_esc0_clk = {
1454 	.halt_reg = 0x2344,
1455 	.clkr = {
1456 		.enable_reg = 0x2344,
1457 		.enable_mask = BIT(0),
1458 		.hw.init = &(struct clk_init_data){
1459 			.name = "mdss_esc0_clk",
1460 			.parent_hws = (const struct clk_hw *[]){ &esc0_clk_src.clkr.hw },
1461 			.num_parents = 1,
1462 			.ops = &clk_branch2_ops,
1463 			.flags = CLK_SET_RATE_PARENT,
1464 		},
1465 	},
1466 };
1467 
1468 static struct clk_branch mdss_esc1_clk = {
1469 	.halt_reg = 0x2348,
1470 	.clkr = {
1471 		.enable_reg = 0x2348,
1472 		.enable_mask = BIT(0),
1473 		.hw.init = &(struct clk_init_data){
1474 			.name = "mdss_esc1_clk",
1475 			.parent_hws = (const struct clk_hw *[]){ &esc1_clk_src.clkr.hw },
1476 			.num_parents = 1,
1477 			.ops = &clk_branch2_ops,
1478 			.flags = CLK_SET_RATE_PARENT,
1479 		},
1480 	},
1481 };
1482 
1483 static struct clk_branch mdss_rot_clk = {
1484 	.halt_reg = 0x2350,
1485 	.clkr = {
1486 		.enable_reg = 0x2350,
1487 		.enable_mask = BIT(0),
1488 		.hw.init = &(struct clk_init_data){
1489 			.name = "mdss_rot_clk",
1490 			.parent_hws = (const struct clk_hw *[]){ &rot_clk_src.clkr.hw },
1491 			.num_parents = 1,
1492 			.ops = &clk_branch2_ops,
1493 			.flags = CLK_SET_RATE_PARENT,
1494 		},
1495 	},
1496 };
1497 
1498 static struct clk_branch mdss_dp_link_clk = {
1499 	.halt_reg = 0x2354,
1500 	.clkr = {
1501 		.enable_reg = 0x2354,
1502 		.enable_mask = BIT(0),
1503 		.hw.init = &(struct clk_init_data){
1504 			.name = "mdss_dp_link_clk",
1505 			.parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
1506 			.num_parents = 1,
1507 			.ops = &clk_branch2_ops,
1508 			.flags = CLK_SET_RATE_PARENT,
1509 		},
1510 	},
1511 };
1512 
1513 static struct clk_branch mdss_dp_link_intf_clk = {
1514 	.halt_reg = 0x2358,
1515 	.clkr = {
1516 		.enable_reg = 0x2358,
1517 		.enable_mask = BIT(0),
1518 		.hw.init = &(struct clk_init_data){
1519 			.name = "mdss_dp_link_intf_clk",
1520 			.parent_hws = (const struct clk_hw *[]){ &dp_link_clk_src.clkr.hw },
1521 			.num_parents = 1,
1522 			.ops = &clk_branch2_ops,
1523 			.flags = CLK_SET_RATE_PARENT,
1524 		},
1525 	},
1526 };
1527 
1528 static struct clk_branch mdss_dp_crypto_clk = {
1529 	.halt_reg = 0x235c,
1530 	.clkr = {
1531 		.enable_reg = 0x235c,
1532 		.enable_mask = BIT(0),
1533 		.hw.init = &(struct clk_init_data){
1534 			.name = "mdss_dp_crypto_clk",
1535 			.parent_hws = (const struct clk_hw *[]){ &dp_crypto_clk_src.clkr.hw },
1536 			.num_parents = 1,
1537 			.ops = &clk_branch2_ops,
1538 			.flags = CLK_SET_RATE_PARENT,
1539 		},
1540 	},
1541 };
1542 
1543 static struct clk_branch mdss_dp_pixel_clk = {
1544 	.halt_reg = 0x2360,
1545 	.clkr = {
1546 		.enable_reg = 0x2360,
1547 		.enable_mask = BIT(0),
1548 		.hw.init = &(struct clk_init_data){
1549 			.name = "mdss_dp_pixel_clk",
1550 			.parent_hws = (const struct clk_hw *[]){ &dp_pixel_clk_src.clkr.hw },
1551 			.num_parents = 1,
1552 			.ops = &clk_branch2_ops,
1553 			.flags = CLK_SET_RATE_PARENT,
1554 		},
1555 	},
1556 };
1557 
1558 static struct clk_branch mdss_dp_aux_clk = {
1559 	.halt_reg = 0x2364,
1560 	.clkr = {
1561 		.enable_reg = 0x2364,
1562 		.enable_mask = BIT(0),
1563 		.hw.init = &(struct clk_init_data){
1564 			.name = "mdss_dp_aux_clk",
1565 			.parent_hws = (const struct clk_hw *[]){ &dp_aux_clk_src.clkr.hw },
1566 			.num_parents = 1,
1567 			.ops = &clk_branch2_ops,
1568 			.flags = CLK_SET_RATE_PARENT,
1569 		},
1570 	},
1571 };
1572 
1573 static struct clk_branch mdss_byte0_intf_clk = {
1574 	.halt_reg = 0x2374,
1575 	.clkr = {
1576 		.enable_reg = 0x2374,
1577 		.enable_mask = BIT(0),
1578 		.hw.init = &(struct clk_init_data){
1579 			.name = "mdss_byte0_intf_clk",
1580 			.parent_hws = (const struct clk_hw *[]){ &byte0_clk_src.clkr.hw },
1581 			.num_parents = 1,
1582 			.ops = &clk_branch2_ops,
1583 			.flags = CLK_SET_RATE_PARENT,
1584 		},
1585 	},
1586 };
1587 
1588 static struct clk_branch mdss_byte1_intf_clk = {
1589 	.halt_reg = 0x2378,
1590 	.clkr = {
1591 		.enable_reg = 0x2378,
1592 		.enable_mask = BIT(0),
1593 		.hw.init = &(struct clk_init_data){
1594 			.name = "mdss_byte1_intf_clk",
1595 			.parent_hws = (const struct clk_hw *[]){ &byte1_clk_src.clkr.hw },
1596 			.num_parents = 1,
1597 			.ops = &clk_branch2_ops,
1598 			.flags = CLK_SET_RATE_PARENT,
1599 		},
1600 	},
1601 };
1602 
1603 static struct clk_branch camss_csi0phytimer_clk = {
1604 	.halt_reg = 0x3024,
1605 	.clkr = {
1606 		.enable_reg = 0x3024,
1607 		.enable_mask = BIT(0),
1608 		.hw.init = &(struct clk_init_data){
1609 			.name = "camss_csi0phytimer_clk",
1610 			.parent_hws = (const struct clk_hw *[]){ &csi0phytimer_clk_src.clkr.hw },
1611 			.num_parents = 1,
1612 			.ops = &clk_branch2_ops,
1613 			.flags = CLK_SET_RATE_PARENT,
1614 		},
1615 	},
1616 };
1617 
1618 static struct clk_branch camss_csi1phytimer_clk = {
1619 	.halt_reg = 0x3054,
1620 	.clkr = {
1621 		.enable_reg = 0x3054,
1622 		.enable_mask = BIT(0),
1623 		.hw.init = &(struct clk_init_data){
1624 			.name = "camss_csi1phytimer_clk",
1625 			.parent_hws = (const struct clk_hw *[]){ &csi1phytimer_clk_src.clkr.hw },
1626 			.num_parents = 1,
1627 			.ops = &clk_branch2_ops,
1628 			.flags = CLK_SET_RATE_PARENT,
1629 		},
1630 	},
1631 };
1632 
1633 static struct clk_branch camss_csi2phytimer_clk = {
1634 	.halt_reg = 0x3084,
1635 	.clkr = {
1636 		.enable_reg = 0x3084,
1637 		.enable_mask = BIT(0),
1638 		.hw.init = &(struct clk_init_data){
1639 			.name = "camss_csi2phytimer_clk",
1640 			.parent_hws = (const struct clk_hw *[]){ &csi2phytimer_clk_src.clkr.hw },
1641 			.num_parents = 1,
1642 			.ops = &clk_branch2_ops,
1643 			.flags = CLK_SET_RATE_PARENT,
1644 		},
1645 	},
1646 };
1647 
1648 static struct clk_branch camss_csi0_clk = {
1649 	.halt_reg = 0x30b4,
1650 	.clkr = {
1651 		.enable_reg = 0x30b4,
1652 		.enable_mask = BIT(0),
1653 		.hw.init = &(struct clk_init_data){
1654 			.name = "camss_csi0_clk",
1655 			.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1656 			.num_parents = 1,
1657 			.ops = &clk_branch2_ops,
1658 			.flags = CLK_SET_RATE_PARENT,
1659 		},
1660 	},
1661 };
1662 
1663 static struct clk_branch camss_csi0_ahb_clk = {
1664 	.halt_reg = 0x30bc,
1665 	.clkr = {
1666 		.enable_reg = 0x30bc,
1667 		.enable_mask = BIT(0),
1668 		.hw.init = &(struct clk_init_data){
1669 			.name = "camss_csi0_ahb_clk",
1670 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1671 			.num_parents = 1,
1672 			.ops = &clk_branch2_ops,
1673 			.flags = CLK_SET_RATE_PARENT,
1674 		},
1675 	},
1676 };
1677 
1678 static struct clk_branch camss_csi0rdi_clk = {
1679 	.halt_reg = 0x30d4,
1680 	.clkr = {
1681 		.enable_reg = 0x30d4,
1682 		.enable_mask = BIT(0),
1683 		.hw.init = &(struct clk_init_data){
1684 			.name = "camss_csi0rdi_clk",
1685 			.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1686 			.num_parents = 1,
1687 			.ops = &clk_branch2_ops,
1688 			.flags = CLK_SET_RATE_PARENT,
1689 		},
1690 	},
1691 };
1692 
1693 static struct clk_branch camss_csi0pix_clk = {
1694 	.halt_reg = 0x30e4,
1695 	.clkr = {
1696 		.enable_reg = 0x30e4,
1697 		.enable_mask = BIT(0),
1698 		.hw.init = &(struct clk_init_data){
1699 			.name = "camss_csi0pix_clk",
1700 			.parent_hws = (const struct clk_hw *[]){ &csi0_clk_src.clkr.hw },
1701 			.num_parents = 1,
1702 			.ops = &clk_branch2_ops,
1703 			.flags = CLK_SET_RATE_PARENT,
1704 		},
1705 	},
1706 };
1707 
1708 static struct clk_branch camss_csi1_clk = {
1709 	.halt_reg = 0x3124,
1710 	.clkr = {
1711 		.enable_reg = 0x3124,
1712 		.enable_mask = BIT(0),
1713 		.hw.init = &(struct clk_init_data){
1714 			.name = "camss_csi1_clk",
1715 			.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1716 			.num_parents = 1,
1717 			.ops = &clk_branch2_ops,
1718 			.flags = CLK_SET_RATE_PARENT,
1719 		},
1720 	},
1721 };
1722 
1723 static struct clk_branch camss_csi1_ahb_clk = {
1724 	.halt_reg = 0x3128,
1725 	.clkr = {
1726 		.enable_reg = 0x3128,
1727 		.enable_mask = BIT(0),
1728 		.hw.init = &(struct clk_init_data){
1729 			.name = "camss_csi1_ahb_clk",
1730 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1731 			.num_parents = 1,
1732 			.ops = &clk_branch2_ops,
1733 			.flags = CLK_SET_RATE_PARENT,
1734 		},
1735 	},
1736 };
1737 
1738 static struct clk_branch camss_csi1rdi_clk = {
1739 	.halt_reg = 0x3144,
1740 	.clkr = {
1741 		.enable_reg = 0x3144,
1742 		.enable_mask = BIT(0),
1743 		.hw.init = &(struct clk_init_data){
1744 			.name = "camss_csi1rdi_clk",
1745 			.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1746 			.num_parents = 1,
1747 			.ops = &clk_branch2_ops,
1748 			.flags = CLK_SET_RATE_PARENT,
1749 		},
1750 	},
1751 };
1752 
1753 static struct clk_branch camss_csi1pix_clk = {
1754 	.halt_reg = 0x3154,
1755 	.clkr = {
1756 		.enable_reg = 0x3154,
1757 		.enable_mask = BIT(0),
1758 		.hw.init = &(struct clk_init_data){
1759 			.name = "camss_csi1pix_clk",
1760 			.parent_hws = (const struct clk_hw *[]){ &csi1_clk_src.clkr.hw },
1761 			.num_parents = 1,
1762 			.ops = &clk_branch2_ops,
1763 			.flags = CLK_SET_RATE_PARENT,
1764 		},
1765 	},
1766 };
1767 
1768 static struct clk_branch camss_csi2_clk = {
1769 	.halt_reg = 0x3184,
1770 	.clkr = {
1771 		.enable_reg = 0x3184,
1772 		.enable_mask = BIT(0),
1773 		.hw.init = &(struct clk_init_data){
1774 			.name = "camss_csi2_clk",
1775 			.parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1776 			.num_parents = 1,
1777 			.ops = &clk_branch2_ops,
1778 			.flags = CLK_SET_RATE_PARENT,
1779 		},
1780 	},
1781 };
1782 
1783 static struct clk_branch camss_csi2_ahb_clk = {
1784 	.halt_reg = 0x3188,
1785 	.clkr = {
1786 		.enable_reg = 0x3188,
1787 		.enable_mask = BIT(0),
1788 		.hw.init = &(struct clk_init_data){
1789 			.name = "camss_csi2_ahb_clk",
1790 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1791 			.num_parents = 1,
1792 			.ops = &clk_branch2_ops,
1793 			.flags = CLK_SET_RATE_PARENT,
1794 		},
1795 	},
1796 };
1797 
1798 static struct clk_branch camss_csi2rdi_clk = {
1799 	.halt_reg = 0x31a4,
1800 	.clkr = {
1801 		.enable_reg = 0x31a4,
1802 		.enable_mask = BIT(0),
1803 		.hw.init = &(struct clk_init_data){
1804 			.name = "camss_csi2rdi_clk",
1805 			.parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1806 			.num_parents = 1,
1807 			.ops = &clk_branch2_ops,
1808 			.flags = CLK_SET_RATE_PARENT,
1809 		},
1810 	},
1811 };
1812 
1813 static struct clk_branch camss_csi2pix_clk = {
1814 	.halt_reg = 0x31b4,
1815 	.clkr = {
1816 		.enable_reg = 0x31b4,
1817 		.enable_mask = BIT(0),
1818 		.hw.init = &(struct clk_init_data){
1819 			.name = "camss_csi2pix_clk",
1820 			.parent_hws = (const struct clk_hw *[]){ &csi2_clk_src.clkr.hw },
1821 			.num_parents = 1,
1822 			.ops = &clk_branch2_ops,
1823 			.flags = CLK_SET_RATE_PARENT,
1824 		},
1825 	},
1826 };
1827 
1828 static struct clk_branch camss_csi3_clk = {
1829 	.halt_reg = 0x31e4,
1830 	.clkr = {
1831 		.enable_reg = 0x31e4,
1832 		.enable_mask = BIT(0),
1833 		.hw.init = &(struct clk_init_data){
1834 			.name = "camss_csi3_clk",
1835 			.parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1836 			.num_parents = 1,
1837 			.ops = &clk_branch2_ops,
1838 			.flags = CLK_SET_RATE_PARENT,
1839 		},
1840 	},
1841 };
1842 
1843 static struct clk_branch camss_csi3_ahb_clk = {
1844 	.halt_reg = 0x31e8,
1845 	.clkr = {
1846 		.enable_reg = 0x31e8,
1847 		.enable_mask = BIT(0),
1848 		.hw.init = &(struct clk_init_data){
1849 			.name = "camss_csi3_ahb_clk",
1850 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1851 			.num_parents = 1,
1852 			.ops = &clk_branch2_ops,
1853 			.flags = CLK_SET_RATE_PARENT,
1854 		},
1855 	},
1856 };
1857 
1858 static struct clk_branch camss_csi3rdi_clk = {
1859 	.halt_reg = 0x3204,
1860 	.clkr = {
1861 		.enable_reg = 0x3204,
1862 		.enable_mask = BIT(0),
1863 		.hw.init = &(struct clk_init_data){
1864 			.name = "camss_csi3rdi_clk",
1865 			.parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1866 			.num_parents = 1,
1867 			.ops = &clk_branch2_ops,
1868 			.flags = CLK_SET_RATE_PARENT,
1869 		},
1870 	},
1871 };
1872 
1873 static struct clk_branch camss_csi3pix_clk = {
1874 	.halt_reg = 0x3214,
1875 	.clkr = {
1876 		.enable_reg = 0x3214,
1877 		.enable_mask = BIT(0),
1878 		.hw.init = &(struct clk_init_data){
1879 			.name = "camss_csi3pix_clk",
1880 			.parent_hws = (const struct clk_hw *[]){ &csi3_clk_src.clkr.hw },
1881 			.num_parents = 1,
1882 			.ops = &clk_branch2_ops,
1883 			.flags = CLK_SET_RATE_PARENT,
1884 		},
1885 	},
1886 };
1887 
1888 static struct clk_branch camss_ispif_ahb_clk = {
1889 	.halt_reg = 0x3224,
1890 	.clkr = {
1891 		.enable_reg = 0x3224,
1892 		.enable_mask = BIT(0),
1893 		.hw.init = &(struct clk_init_data){
1894 			.name = "camss_ispif_ahb_clk",
1895 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1896 			.num_parents = 1,
1897 			.ops = &clk_branch2_ops,
1898 			.flags = CLK_SET_RATE_PARENT,
1899 		},
1900 	},
1901 };
1902 
1903 static struct clk_branch camss_cci_clk = {
1904 	.halt_reg = 0x3344,
1905 	.clkr = {
1906 		.enable_reg = 0x3344,
1907 		.enable_mask = BIT(0),
1908 		.hw.init = &(struct clk_init_data){
1909 			.name = "camss_cci_clk",
1910 			.parent_hws = (const struct clk_hw *[]){ &cci_clk_src.clkr.hw },
1911 			.num_parents = 1,
1912 			.ops = &clk_branch2_ops,
1913 			.flags = CLK_SET_RATE_PARENT,
1914 		},
1915 	},
1916 };
1917 
1918 static struct clk_branch camss_cci_ahb_clk = {
1919 	.halt_reg = 0x3348,
1920 	.clkr = {
1921 		.enable_reg = 0x3348,
1922 		.enable_mask = BIT(0),
1923 		.hw.init = &(struct clk_init_data){
1924 			.name = "camss_cci_ahb_clk",
1925 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
1926 			.num_parents = 1,
1927 			.ops = &clk_branch2_ops,
1928 			.flags = CLK_SET_RATE_PARENT,
1929 		},
1930 	},
1931 };
1932 
1933 static struct clk_branch camss_mclk0_clk = {
1934 	.halt_reg = 0x3384,
1935 	.clkr = {
1936 		.enable_reg = 0x3384,
1937 		.enable_mask = BIT(0),
1938 		.hw.init = &(struct clk_init_data){
1939 			.name = "camss_mclk0_clk",
1940 			.parent_hws = (const struct clk_hw *[]){ &mclk0_clk_src.clkr.hw },
1941 			.num_parents = 1,
1942 			.ops = &clk_branch2_ops,
1943 			.flags = CLK_SET_RATE_PARENT,
1944 		},
1945 	},
1946 };
1947 
1948 static struct clk_branch camss_mclk1_clk = {
1949 	.halt_reg = 0x33b4,
1950 	.clkr = {
1951 		.enable_reg = 0x33b4,
1952 		.enable_mask = BIT(0),
1953 		.hw.init = &(struct clk_init_data){
1954 			.name = "camss_mclk1_clk",
1955 			.parent_hws = (const struct clk_hw *[]){ &mclk1_clk_src.clkr.hw },
1956 			.num_parents = 1,
1957 			.ops = &clk_branch2_ops,
1958 			.flags = CLK_SET_RATE_PARENT,
1959 		},
1960 	},
1961 };
1962 
1963 static struct clk_branch camss_mclk2_clk = {
1964 	.halt_reg = 0x33e4,
1965 	.clkr = {
1966 		.enable_reg = 0x33e4,
1967 		.enable_mask = BIT(0),
1968 		.hw.init = &(struct clk_init_data){
1969 			.name = "camss_mclk2_clk",
1970 			.parent_hws = (const struct clk_hw *[]){ &mclk2_clk_src.clkr.hw },
1971 			.num_parents = 1,
1972 			.ops = &clk_branch2_ops,
1973 			.flags = CLK_SET_RATE_PARENT,
1974 		},
1975 	},
1976 };
1977 
1978 static struct clk_branch camss_mclk3_clk = {
1979 	.halt_reg = 0x3414,
1980 	.clkr = {
1981 		.enable_reg = 0x3414,
1982 		.enable_mask = BIT(0),
1983 		.hw.init = &(struct clk_init_data){
1984 			.name = "camss_mclk3_clk",
1985 			.parent_hws = (const struct clk_hw *[]){ &mclk3_clk_src.clkr.hw },
1986 			.num_parents = 1,
1987 			.ops = &clk_branch2_ops,
1988 			.flags = CLK_SET_RATE_PARENT,
1989 		},
1990 	},
1991 };
1992 
1993 static struct clk_branch camss_top_ahb_clk = {
1994 	.halt_reg = 0x3484,
1995 	.clkr = {
1996 		.enable_reg = 0x3484,
1997 		.enable_mask = BIT(0),
1998 		.hw.init = &(struct clk_init_data){
1999 			.name = "camss_top_ahb_clk",
2000 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2001 			.num_parents = 1,
2002 			.ops = &clk_branch2_ops,
2003 			.flags = CLK_SET_RATE_PARENT,
2004 		},
2005 	},
2006 };
2007 
2008 static struct clk_branch camss_ahb_clk = {
2009 	.halt_reg = 0x348c,
2010 	.clkr = {
2011 		.enable_reg = 0x348c,
2012 		.enable_mask = BIT(0),
2013 		.hw.init = &(struct clk_init_data){
2014 			.name = "camss_ahb_clk",
2015 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2016 			.num_parents = 1,
2017 			.ops = &clk_branch2_ops,
2018 			.flags = CLK_SET_RATE_PARENT,
2019 		},
2020 	},
2021 };
2022 
2023 static struct clk_branch camss_micro_ahb_clk = {
2024 	.halt_reg = 0x3494,
2025 	.clkr = {
2026 		.enable_reg = 0x3494,
2027 		.enable_mask = BIT(0),
2028 		.hw.init = &(struct clk_init_data){
2029 			.name = "camss_micro_ahb_clk",
2030 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2031 			.num_parents = 1,
2032 			.ops = &clk_branch2_ops,
2033 			.flags = CLK_SET_RATE_PARENT,
2034 		},
2035 	},
2036 };
2037 
2038 static struct clk_branch camss_jpeg0_clk = {
2039 	.halt_reg = 0x35a8,
2040 	.clkr = {
2041 		.enable_reg = 0x35a8,
2042 		.enable_mask = BIT(0),
2043 		.hw.init = &(struct clk_init_data){
2044 			.name = "camss_jpeg0_clk",
2045 			.parent_hws = (const struct clk_hw *[]){ &jpeg0_clk_src.clkr.hw },
2046 			.num_parents = 1,
2047 			.ops = &clk_branch2_ops,
2048 			.flags = CLK_SET_RATE_PARENT,
2049 		},
2050 	},
2051 };
2052 
2053 static struct clk_branch camss_jpeg_ahb_clk = {
2054 	.halt_reg = 0x35b4,
2055 	.clkr = {
2056 		.enable_reg = 0x35b4,
2057 		.enable_mask = BIT(0),
2058 		.hw.init = &(struct clk_init_data){
2059 			.name = "camss_jpeg_ahb_clk",
2060 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2061 			.num_parents = 1,
2062 			.ops = &clk_branch2_ops,
2063 			.flags = CLK_SET_RATE_PARENT,
2064 		},
2065 	},
2066 };
2067 
2068 static struct clk_branch camss_jpeg_axi_clk = {
2069 	.halt_reg = 0x35b8,
2070 	.clkr = {
2071 		.enable_reg = 0x35b8,
2072 		.enable_mask = BIT(0),
2073 		.hw.init = &(struct clk_init_data){
2074 			.name = "camss_jpeg_axi_clk",
2075 			.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2076 			.num_parents = 1,
2077 			.ops = &clk_branch2_ops,
2078 		},
2079 	},
2080 };
2081 
2082 static struct clk_branch camss_vfe0_ahb_clk = {
2083 	.halt_reg = 0x3668,
2084 	.clkr = {
2085 		.enable_reg = 0x3668,
2086 		.enable_mask = BIT(0),
2087 		.hw.init = &(struct clk_init_data){
2088 			.name = "camss_vfe0_ahb_clk",
2089 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2090 			.num_parents = 1,
2091 			.ops = &clk_branch2_ops,
2092 			.flags = CLK_SET_RATE_PARENT,
2093 		},
2094 	},
2095 };
2096 
2097 static struct clk_branch camss_vfe1_ahb_clk = {
2098 	.halt_reg = 0x3678,
2099 	.clkr = {
2100 		.enable_reg = 0x3678,
2101 		.enable_mask = BIT(0),
2102 		.hw.init = &(struct clk_init_data){
2103 			.name = "camss_vfe1_ahb_clk",
2104 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2105 			.num_parents = 1,
2106 			.ops = &clk_branch2_ops,
2107 			.flags = CLK_SET_RATE_PARENT,
2108 		},
2109 	},
2110 };
2111 
2112 static struct clk_branch camss_vfe0_clk = {
2113 	.halt_reg = 0x36a8,
2114 	.clkr = {
2115 		.enable_reg = 0x36a8,
2116 		.enable_mask = BIT(0),
2117 		.hw.init = &(struct clk_init_data){
2118 			.name = "camss_vfe0_clk",
2119 			.parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2120 			.num_parents = 1,
2121 			.ops = &clk_branch2_ops,
2122 			.flags = CLK_SET_RATE_PARENT,
2123 		},
2124 	},
2125 };
2126 
2127 static struct clk_branch camss_vfe1_clk = {
2128 	.halt_reg = 0x36ac,
2129 	.clkr = {
2130 		.enable_reg = 0x36ac,
2131 		.enable_mask = BIT(0),
2132 		.hw.init = &(struct clk_init_data){
2133 			.name = "camss_vfe1_clk",
2134 			.parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2135 			.num_parents = 1,
2136 			.ops = &clk_branch2_ops,
2137 			.flags = CLK_SET_RATE_PARENT,
2138 		},
2139 	},
2140 };
2141 
2142 static struct clk_branch camss_cpp_clk = {
2143 	.halt_reg = 0x36b0,
2144 	.clkr = {
2145 		.enable_reg = 0x36b0,
2146 		.enable_mask = BIT(0),
2147 		.hw.init = &(struct clk_init_data){
2148 			.name = "camss_cpp_clk",
2149 			.parent_hws = (const struct clk_hw *[]){ &cpp_clk_src.clkr.hw },
2150 			.num_parents = 1,
2151 			.ops = &clk_branch2_ops,
2152 			.flags = CLK_SET_RATE_PARENT,
2153 		},
2154 	},
2155 };
2156 
2157 static struct clk_branch camss_cpp_ahb_clk = {
2158 	.halt_reg = 0x36b4,
2159 	.clkr = {
2160 		.enable_reg = 0x36b4,
2161 		.enable_mask = BIT(0),
2162 		.hw.init = &(struct clk_init_data){
2163 			.name = "camss_cpp_ahb_clk",
2164 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2165 			.num_parents = 1,
2166 			.ops = &clk_branch2_ops,
2167 			.flags = CLK_SET_RATE_PARENT,
2168 		},
2169 	},
2170 };
2171 
2172 static struct clk_branch camss_vfe_vbif_ahb_clk = {
2173 	.halt_reg = 0x36b8,
2174 	.clkr = {
2175 		.enable_reg = 0x36b8,
2176 		.enable_mask = BIT(0),
2177 		.hw.init = &(struct clk_init_data){
2178 			.name = "camss_vfe_vbif_ahb_clk",
2179 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2180 			.num_parents = 1,
2181 			.ops = &clk_branch2_ops,
2182 			.flags = CLK_SET_RATE_PARENT,
2183 		},
2184 	},
2185 };
2186 
2187 static struct clk_branch camss_vfe_vbif_axi_clk = {
2188 	.halt_reg = 0x36bc,
2189 	.clkr = {
2190 		.enable_reg = 0x36bc,
2191 		.enable_mask = BIT(0),
2192 		.hw.init = &(struct clk_init_data){
2193 			.name = "camss_vfe_vbif_axi_clk",
2194 			.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2195 			.num_parents = 1,
2196 			.ops = &clk_branch2_ops,
2197 		},
2198 	},
2199 };
2200 
2201 static struct clk_branch camss_cpp_axi_clk = {
2202 	.halt_reg = 0x36c4,
2203 	.clkr = {
2204 		.enable_reg = 0x36c4,
2205 		.enable_mask = BIT(0),
2206 		.hw.init = &(struct clk_init_data){
2207 			.name = "camss_cpp_axi_clk",
2208 			.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2209 			.num_parents = 1,
2210 			.ops = &clk_branch2_ops,
2211 		},
2212 	},
2213 };
2214 
2215 static struct clk_branch camss_cpp_vbif_ahb_clk = {
2216 	.halt_reg = 0x36c8,
2217 	.clkr = {
2218 		.enable_reg = 0x36c8,
2219 		.enable_mask = BIT(0),
2220 		.hw.init = &(struct clk_init_data){
2221 			.name = "camss_cpp_vbif_ahb_clk",
2222 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2223 			.num_parents = 1,
2224 			.ops = &clk_branch2_ops,
2225 			.flags = CLK_SET_RATE_PARENT,
2226 		},
2227 	},
2228 };
2229 
2230 static struct clk_branch camss_csi_vfe0_clk = {
2231 	.halt_reg = 0x3704,
2232 	.clkr = {
2233 		.enable_reg = 0x3704,
2234 		.enable_mask = BIT(0),
2235 		.hw.init = &(struct clk_init_data){
2236 			.name = "camss_csi_vfe0_clk",
2237 			.parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2238 			.num_parents = 1,
2239 			.ops = &clk_branch2_ops,
2240 			.flags = CLK_SET_RATE_PARENT,
2241 		},
2242 	},
2243 };
2244 
2245 static struct clk_branch camss_csi_vfe1_clk = {
2246 	.halt_reg = 0x3714,
2247 	.clkr = {
2248 		.enable_reg = 0x3714,
2249 		.enable_mask = BIT(0),
2250 		.hw.init = &(struct clk_init_data){
2251 			.name = "camss_csi_vfe1_clk",
2252 			.parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2253 			.num_parents = 1,
2254 			.ops = &clk_branch2_ops,
2255 			.flags = CLK_SET_RATE_PARENT,
2256 		},
2257 	},
2258 };
2259 
2260 static struct clk_branch camss_vfe0_stream_clk = {
2261 	.halt_reg = 0x3720,
2262 	.clkr = {
2263 		.enable_reg = 0x3720,
2264 		.enable_mask = BIT(0),
2265 		.hw.init = &(struct clk_init_data){
2266 			.name = "camss_vfe0_stream_clk",
2267 			.parent_hws = (const struct clk_hw *[]){ &vfe0_clk_src.clkr.hw },
2268 			.num_parents = 1,
2269 			.ops = &clk_branch2_ops,
2270 			.flags = CLK_SET_RATE_PARENT,
2271 		},
2272 	},
2273 };
2274 
2275 static struct clk_branch camss_vfe1_stream_clk = {
2276 	.halt_reg = 0x3724,
2277 	.clkr = {
2278 		.enable_reg = 0x3724,
2279 		.enable_mask = BIT(0),
2280 		.hw.init = &(struct clk_init_data){
2281 			.name = "camss_vfe1_stream_clk",
2282 			.parent_hws = (const struct clk_hw *[]){ &vfe1_clk_src.clkr.hw },
2283 			.num_parents = 1,
2284 			.ops = &clk_branch2_ops,
2285 			.flags = CLK_SET_RATE_PARENT,
2286 		},
2287 	},
2288 };
2289 
2290 static struct clk_branch camss_cphy_csid0_clk = {
2291 	.halt_reg = 0x3730,
2292 	.clkr = {
2293 		.enable_reg = 0x3730,
2294 		.enable_mask = BIT(0),
2295 		.hw.init = &(struct clk_init_data){
2296 			.name = "camss_cphy_csid0_clk",
2297 			.parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2298 			.num_parents = 1,
2299 			.ops = &clk_branch2_ops,
2300 			.flags = CLK_SET_RATE_PARENT,
2301 		},
2302 	},
2303 };
2304 
2305 static struct clk_branch camss_cphy_csid1_clk = {
2306 	.halt_reg = 0x3734,
2307 	.clkr = {
2308 		.enable_reg = 0x3734,
2309 		.enable_mask = BIT(0),
2310 		.hw.init = &(struct clk_init_data){
2311 			.name = "camss_cphy_csid1_clk",
2312 			.parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2313 			.num_parents = 1,
2314 			.ops = &clk_branch2_ops,
2315 			.flags = CLK_SET_RATE_PARENT,
2316 		},
2317 	},
2318 };
2319 
2320 static struct clk_branch camss_cphy_csid2_clk = {
2321 	.halt_reg = 0x3738,
2322 	.clkr = {
2323 		.enable_reg = 0x3738,
2324 		.enable_mask = BIT(0),
2325 		.hw.init = &(struct clk_init_data){
2326 			.name = "camss_cphy_csid2_clk",
2327 			.parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2328 			.num_parents = 1,
2329 			.ops = &clk_branch2_ops,
2330 			.flags = CLK_SET_RATE_PARENT,
2331 		},
2332 	},
2333 };
2334 
2335 static struct clk_branch camss_cphy_csid3_clk = {
2336 	.halt_reg = 0x373c,
2337 	.clkr = {
2338 		.enable_reg = 0x373c,
2339 		.enable_mask = BIT(0),
2340 		.hw.init = &(struct clk_init_data){
2341 			.name = "camss_cphy_csid3_clk",
2342 			.parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2343 			.num_parents = 1,
2344 			.ops = &clk_branch2_ops,
2345 			.flags = CLK_SET_RATE_PARENT,
2346 		},
2347 	},
2348 };
2349 
2350 static struct clk_branch camss_csiphy0_clk = {
2351 	.halt_reg = 0x3740,
2352 	.clkr = {
2353 		.enable_reg = 0x3740,
2354 		.enable_mask = BIT(0),
2355 		.hw.init = &(struct clk_init_data){
2356 			.name = "camss_csiphy0_clk",
2357 			.parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2358 			.num_parents = 1,
2359 			.ops = &clk_branch2_ops,
2360 			.flags = CLK_SET_RATE_PARENT,
2361 		},
2362 	},
2363 };
2364 
2365 static struct clk_branch camss_csiphy1_clk = {
2366 	.halt_reg = 0x3744,
2367 	.clkr = {
2368 		.enable_reg = 0x3744,
2369 		.enable_mask = BIT(0),
2370 		.hw.init = &(struct clk_init_data){
2371 			.name = "camss_csiphy1_clk",
2372 			.parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2373 			.num_parents = 1,
2374 			.ops = &clk_branch2_ops,
2375 			.flags = CLK_SET_RATE_PARENT,
2376 		},
2377 	},
2378 };
2379 
2380 static struct clk_branch camss_csiphy2_clk = {
2381 	.halt_reg = 0x3748,
2382 	.clkr = {
2383 		.enable_reg = 0x3748,
2384 		.enable_mask = BIT(0),
2385 		.hw.init = &(struct clk_init_data){
2386 			.name = "camss_csiphy2_clk",
2387 			.parent_hws = (const struct clk_hw *[]){ &csiphy_clk_src.clkr.hw },
2388 			.num_parents = 1,
2389 			.ops = &clk_branch2_ops,
2390 			.flags = CLK_SET_RATE_PARENT,
2391 		},
2392 	},
2393 };
2394 
2395 static struct clk_branch fd_core_clk = {
2396 	.halt_reg = 0x3b68,
2397 	.clkr = {
2398 		.enable_reg = 0x3b68,
2399 		.enable_mask = BIT(0),
2400 		.hw.init = &(struct clk_init_data){
2401 			.name = "fd_core_clk",
2402 			.parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
2403 			.num_parents = 1,
2404 			.ops = &clk_branch2_ops,
2405 			.flags = CLK_SET_RATE_PARENT,
2406 		},
2407 	},
2408 };
2409 
2410 static struct clk_branch fd_core_uar_clk = {
2411 	.halt_reg = 0x3b6c,
2412 	.clkr = {
2413 		.enable_reg = 0x3b6c,
2414 		.enable_mask = BIT(0),
2415 		.hw.init = &(struct clk_init_data){
2416 			.name = "fd_core_uar_clk",
2417 			.parent_hws = (const struct clk_hw *[]){ &fd_core_clk_src.clkr.hw },
2418 			.num_parents = 1,
2419 			.ops = &clk_branch2_ops,
2420 			.flags = CLK_SET_RATE_PARENT,
2421 		},
2422 	},
2423 };
2424 
2425 static struct clk_branch fd_ahb_clk = {
2426 	.halt_reg = 0x3b74,
2427 	.clkr = {
2428 		.enable_reg = 0x3b74,
2429 		.enable_mask = BIT(0),
2430 		.hw.init = &(struct clk_init_data){
2431 			.name = "fd_ahb_clk",
2432 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2433 			.num_parents = 1,
2434 			.ops = &clk_branch2_ops,
2435 			.flags = CLK_SET_RATE_PARENT,
2436 		},
2437 	},
2438 };
2439 
2440 static struct clk_branch mnoc_ahb_clk = {
2441 	.halt_reg = 0x5024,
2442 	.halt_check = BRANCH_HALT_SKIP,
2443 	.clkr = {
2444 		.enable_reg = 0x5024,
2445 		.enable_mask = BIT(0),
2446 		.hw.init = &(struct clk_init_data){
2447 			.name = "mnoc_ahb_clk",
2448 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2449 			.num_parents = 1,
2450 			.ops = &clk_branch2_ops,
2451 			.flags = CLK_SET_RATE_PARENT,
2452 		},
2453 	},
2454 };
2455 
2456 static struct clk_branch bimc_smmu_ahb_clk = {
2457 	.halt_reg = 0xe004,
2458 	.halt_check = BRANCH_HALT_SKIP,
2459 	.hwcg_reg = 0xe004,
2460 	.hwcg_bit = 1,
2461 	.clkr = {
2462 		.enable_reg = 0xe004,
2463 		.enable_mask = BIT(0),
2464 		.hw.init = &(struct clk_init_data){
2465 			.name = "bimc_smmu_ahb_clk",
2466 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2467 			.num_parents = 1,
2468 			.ops = &clk_branch2_ops,
2469 			.flags = CLK_SET_RATE_PARENT,
2470 		},
2471 	},
2472 };
2473 
2474 static struct clk_branch bimc_smmu_axi_clk = {
2475 	.halt_reg = 0xe008,
2476 	.halt_check = BRANCH_HALT_SKIP,
2477 	.hwcg_reg = 0xe008,
2478 	.hwcg_bit = 1,
2479 	.clkr = {
2480 		.enable_reg = 0xe008,
2481 		.enable_mask = BIT(0),
2482 		.hw.init = &(struct clk_init_data){
2483 			.name = "bimc_smmu_axi_clk",
2484 			.parent_hws = (const struct clk_hw *[]){ &axi_clk_src.clkr.hw },
2485 			.num_parents = 1,
2486 			.ops = &clk_branch2_ops,
2487 		},
2488 	},
2489 };
2490 
2491 static struct clk_branch mnoc_maxi_clk = {
2492 	.halt_reg = 0xf004,
2493 	.clkr = {
2494 		.enable_reg = 0xf004,
2495 		.enable_mask = BIT(0),
2496 		.hw.init = &(struct clk_init_data){
2497 			.name = "mnoc_maxi_clk",
2498 			.parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
2499 			.num_parents = 1,
2500 			.ops = &clk_branch2_ops,
2501 			.flags = CLK_SET_RATE_PARENT,
2502 		},
2503 	},
2504 };
2505 
2506 static struct clk_branch vmem_maxi_clk = {
2507 	.halt_reg = 0xf064,
2508 	.clkr = {
2509 		.enable_reg = 0xf064,
2510 		.enable_mask = BIT(0),
2511 		.hw.init = &(struct clk_init_data){
2512 			.name = "vmem_maxi_clk",
2513 			.parent_hws = (const struct clk_hw *[]){ &maxi_clk_src.clkr.hw },
2514 			.num_parents = 1,
2515 			.ops = &clk_branch2_ops,
2516 			.flags = CLK_SET_RATE_PARENT,
2517 		},
2518 	},
2519 };
2520 
2521 static struct clk_branch vmem_ahb_clk = {
2522 	.halt_reg = 0xf068,
2523 	.clkr = {
2524 		.enable_reg = 0xf068,
2525 		.enable_mask = BIT(0),
2526 		.hw.init = &(struct clk_init_data){
2527 			.name = "vmem_ahb_clk",
2528 			.parent_hws = (const struct clk_hw *[]){ &ahb_clk_src.clkr.hw },
2529 			.num_parents = 1,
2530 			.ops = &clk_branch2_ops,
2531 			.flags = CLK_SET_RATE_PARENT,
2532 		},
2533 	},
2534 };
2535 
2536 static struct gdsc video_top_gdsc = {
2537 	.gdscr = 0x1024,
2538 	.cxcs = (unsigned int []){ 0x1028, 0x1034, 0x1038 },
2539 	.cxc_count = 3,
2540 	.pd = {
2541 		.name = "video_top",
2542 	},
2543 	.pwrsts = PWRSTS_OFF_ON,
2544 };
2545 
2546 static struct gdsc video_subcore0_gdsc = {
2547 	.gdscr = 0x1040,
2548 	.cxcs = (unsigned int []){ 0x1048 },
2549 	.cxc_count = 1,
2550 	.pd = {
2551 		.name = "video_subcore0",
2552 	},
2553 	.parent = &video_top_gdsc.pd,
2554 	.pwrsts = PWRSTS_OFF_ON,
2555 	.flags = HW_CTRL,
2556 };
2557 
2558 static struct gdsc video_subcore1_gdsc = {
2559 	.gdscr = 0x1044,
2560 	.cxcs = (unsigned int []){ 0x104c },
2561 	.cxc_count = 1,
2562 	.pd = {
2563 		.name = "video_subcore1",
2564 	},
2565 	.parent = &video_top_gdsc.pd,
2566 	.pwrsts = PWRSTS_OFF_ON,
2567 	.flags = HW_CTRL,
2568 };
2569 
2570 static struct gdsc mdss_gdsc = {
2571 	.gdscr = 0x2304,
2572 	.cxcs = (unsigned int []){ 0x2310, 0x2350, 0x231c, 0x2320 },
2573 	.cxc_count = 4,
2574 	.pd = {
2575 		.name = "mdss",
2576 	},
2577 	.pwrsts = PWRSTS_OFF_ON,
2578 };
2579 
2580 static struct gdsc camss_top_gdsc = {
2581 	.gdscr = 0x34a0,
2582 	.cxcs = (unsigned int []){ 0x35b8, 0x36c4, 0x3704, 0x3714, 0x3494,
2583 				   0x35a8, 0x3868 },
2584 	.cxc_count = 7,
2585 	.pd = {
2586 		.name = "camss_top",
2587 	},
2588 	.pwrsts = PWRSTS_OFF_ON,
2589 };
2590 
2591 static struct gdsc camss_vfe0_gdsc = {
2592 	.gdscr = 0x3664,
2593 	.pd = {
2594 		.name = "camss_vfe0",
2595 	},
2596 	.parent = &camss_top_gdsc.pd,
2597 	.pwrsts = PWRSTS_OFF_ON,
2598 };
2599 
2600 static struct gdsc camss_vfe1_gdsc = {
2601 	.gdscr = 0x3674,
2602 	.pd = {
2603 		.name = "camss_vfe1_gdsc",
2604 	},
2605 	.parent = &camss_top_gdsc.pd,
2606 	.pwrsts = PWRSTS_OFF_ON,
2607 };
2608 
2609 static struct gdsc camss_cpp_gdsc = {
2610 	.gdscr = 0x36d4,
2611 	.pd = {
2612 		.name = "camss_cpp",
2613 	},
2614 	.parent = &camss_top_gdsc.pd,
2615 	.pwrsts = PWRSTS_OFF_ON,
2616 };
2617 
2618 static struct gdsc bimc_smmu_gdsc = {
2619 	.gdscr = 0xe020,
2620 	.gds_hw_ctrl = 0xe024,
2621 	.cxcs = (unsigned int []){ 0xe008 },
2622 	.cxc_count = 1,
2623 	.pd = {
2624 		.name = "bimc_smmu",
2625 	},
2626 	.pwrsts = PWRSTS_OFF_ON,
2627 	.flags = VOTABLE,
2628 };
2629 
2630 static struct clk_regmap *mmcc_msm8998_clocks[] = {
2631 	[MMPLL0] = &mmpll0.clkr,
2632 	[MMPLL0_OUT_EVEN] = &mmpll0_out_even.clkr,
2633 	[MMPLL1] = &mmpll1.clkr,
2634 	[MMPLL1_OUT_EVEN] = &mmpll1_out_even.clkr,
2635 	[MMPLL3] = &mmpll3.clkr,
2636 	[MMPLL3_OUT_EVEN] = &mmpll3_out_even.clkr,
2637 	[MMPLL4] = &mmpll4.clkr,
2638 	[MMPLL4_OUT_EVEN] = &mmpll4_out_even.clkr,
2639 	[MMPLL5] = &mmpll5.clkr,
2640 	[MMPLL5_OUT_EVEN] = &mmpll5_out_even.clkr,
2641 	[MMPLL6] = &mmpll6.clkr,
2642 	[MMPLL6_OUT_EVEN] = &mmpll6_out_even.clkr,
2643 	[MMPLL7] = &mmpll7.clkr,
2644 	[MMPLL7_OUT_EVEN] = &mmpll7_out_even.clkr,
2645 	[MMPLL10] = &mmpll10.clkr,
2646 	[MMPLL10_OUT_EVEN] = &mmpll10_out_even.clkr,
2647 	[BYTE0_CLK_SRC] = &byte0_clk_src.clkr,
2648 	[BYTE1_CLK_SRC] = &byte1_clk_src.clkr,
2649 	[CCI_CLK_SRC] = &cci_clk_src.clkr,
2650 	[CPP_CLK_SRC] = &cpp_clk_src.clkr,
2651 	[CSI0_CLK_SRC] = &csi0_clk_src.clkr,
2652 	[CSI1_CLK_SRC] = &csi1_clk_src.clkr,
2653 	[CSI2_CLK_SRC] = &csi2_clk_src.clkr,
2654 	[CSI3_CLK_SRC] = &csi3_clk_src.clkr,
2655 	[CSIPHY_CLK_SRC] = &csiphy_clk_src.clkr,
2656 	[CSI0PHYTIMER_CLK_SRC] = &csi0phytimer_clk_src.clkr,
2657 	[CSI1PHYTIMER_CLK_SRC] = &csi1phytimer_clk_src.clkr,
2658 	[CSI2PHYTIMER_CLK_SRC] = &csi2phytimer_clk_src.clkr,
2659 	[DP_AUX_CLK_SRC] = &dp_aux_clk_src.clkr,
2660 	[DP_CRYPTO_CLK_SRC] = &dp_crypto_clk_src.clkr,
2661 	[DP_LINK_CLK_SRC] = &dp_link_clk_src.clkr,
2662 	[DP_PIXEL_CLK_SRC] = &dp_pixel_clk_src.clkr,
2663 	[ESC0_CLK_SRC] = &esc0_clk_src.clkr,
2664 	[ESC1_CLK_SRC] = &esc1_clk_src.clkr,
2665 	[EXTPCLK_CLK_SRC] = &extpclk_clk_src.clkr,
2666 	[FD_CORE_CLK_SRC] = &fd_core_clk_src.clkr,
2667 	[HDMI_CLK_SRC] = &hdmi_clk_src.clkr,
2668 	[JPEG0_CLK_SRC] = &jpeg0_clk_src.clkr,
2669 	[MAXI_CLK_SRC] = &maxi_clk_src.clkr,
2670 	[MCLK0_CLK_SRC] = &mclk0_clk_src.clkr,
2671 	[MCLK1_CLK_SRC] = &mclk1_clk_src.clkr,
2672 	[MCLK2_CLK_SRC] = &mclk2_clk_src.clkr,
2673 	[MCLK3_CLK_SRC] = &mclk3_clk_src.clkr,
2674 	[MDP_CLK_SRC] = &mdp_clk_src.clkr,
2675 	[VSYNC_CLK_SRC] = &vsync_clk_src.clkr,
2676 	[AHB_CLK_SRC] = &ahb_clk_src.clkr,
2677 	[AXI_CLK_SRC] = &axi_clk_src.clkr,
2678 	[PCLK0_CLK_SRC] = &pclk0_clk_src.clkr,
2679 	[PCLK1_CLK_SRC] = &pclk1_clk_src.clkr,
2680 	[ROT_CLK_SRC] = &rot_clk_src.clkr,
2681 	[VIDEO_CORE_CLK_SRC] = &video_core_clk_src.clkr,
2682 	[VIDEO_SUBCORE0_CLK_SRC] = &video_subcore0_clk_src.clkr,
2683 	[VIDEO_SUBCORE1_CLK_SRC] = &video_subcore1_clk_src.clkr,
2684 	[VFE0_CLK_SRC] = &vfe0_clk_src.clkr,
2685 	[VFE1_CLK_SRC] = &vfe1_clk_src.clkr,
2686 	[MISC_AHB_CLK] = &misc_ahb_clk.clkr,
2687 	[VIDEO_CORE_CLK] = &video_core_clk.clkr,
2688 	[VIDEO_AHB_CLK] = &video_ahb_clk.clkr,
2689 	[VIDEO_AXI_CLK] = &video_axi_clk.clkr,
2690 	[VIDEO_MAXI_CLK] = &video_maxi_clk.clkr,
2691 	[VIDEO_SUBCORE0_CLK] = &video_subcore0_clk.clkr,
2692 	[VIDEO_SUBCORE1_CLK] = &video_subcore1_clk.clkr,
2693 	[MDSS_AHB_CLK] = &mdss_ahb_clk.clkr,
2694 	[MDSS_HDMI_DP_AHB_CLK] = &mdss_hdmi_dp_ahb_clk.clkr,
2695 	[MDSS_AXI_CLK] = &mdss_axi_clk.clkr,
2696 	[MDSS_PCLK0_CLK] = &mdss_pclk0_clk.clkr,
2697 	[MDSS_PCLK1_CLK] = &mdss_pclk1_clk.clkr,
2698 	[MDSS_MDP_CLK] = &mdss_mdp_clk.clkr,
2699 	[MDSS_MDP_LUT_CLK] = &mdss_mdp_lut_clk.clkr,
2700 	[MDSS_EXTPCLK_CLK] = &mdss_extpclk_clk.clkr,
2701 	[MDSS_VSYNC_CLK] = &mdss_vsync_clk.clkr,
2702 	[MDSS_HDMI_CLK] = &mdss_hdmi_clk.clkr,
2703 	[MDSS_BYTE0_CLK] = &mdss_byte0_clk.clkr,
2704 	[MDSS_BYTE1_CLK] = &mdss_byte1_clk.clkr,
2705 	[MDSS_ESC0_CLK] = &mdss_esc0_clk.clkr,
2706 	[MDSS_ESC1_CLK] = &mdss_esc1_clk.clkr,
2707 	[MDSS_ROT_CLK] = &mdss_rot_clk.clkr,
2708 	[MDSS_DP_LINK_CLK] = &mdss_dp_link_clk.clkr,
2709 	[MDSS_DP_LINK_INTF_CLK] = &mdss_dp_link_intf_clk.clkr,
2710 	[MDSS_DP_CRYPTO_CLK] = &mdss_dp_crypto_clk.clkr,
2711 	[MDSS_DP_PIXEL_CLK] = &mdss_dp_pixel_clk.clkr,
2712 	[MDSS_DP_AUX_CLK] = &mdss_dp_aux_clk.clkr,
2713 	[MDSS_BYTE0_INTF_CLK] = &mdss_byte0_intf_clk.clkr,
2714 	[MDSS_BYTE1_INTF_CLK] = &mdss_byte1_intf_clk.clkr,
2715 	[CAMSS_CSI0PHYTIMER_CLK] = &camss_csi0phytimer_clk.clkr,
2716 	[CAMSS_CSI1PHYTIMER_CLK] = &camss_csi1phytimer_clk.clkr,
2717 	[CAMSS_CSI2PHYTIMER_CLK] = &camss_csi2phytimer_clk.clkr,
2718 	[CAMSS_CSI0_CLK] = &camss_csi0_clk.clkr,
2719 	[CAMSS_CSI0_AHB_CLK] = &camss_csi0_ahb_clk.clkr,
2720 	[CAMSS_CSI0RDI_CLK] = &camss_csi0rdi_clk.clkr,
2721 	[CAMSS_CSI0PIX_CLK] = &camss_csi0pix_clk.clkr,
2722 	[CAMSS_CSI1_CLK] = &camss_csi1_clk.clkr,
2723 	[CAMSS_CSI1_AHB_CLK] = &camss_csi1_ahb_clk.clkr,
2724 	[CAMSS_CSI1RDI_CLK] = &camss_csi1rdi_clk.clkr,
2725 	[CAMSS_CSI1PIX_CLK] = &camss_csi1pix_clk.clkr,
2726 	[CAMSS_CSI2_CLK] = &camss_csi2_clk.clkr,
2727 	[CAMSS_CSI2_AHB_CLK] = &camss_csi2_ahb_clk.clkr,
2728 	[CAMSS_CSI2RDI_CLK] = &camss_csi2rdi_clk.clkr,
2729 	[CAMSS_CSI2PIX_CLK] = &camss_csi2pix_clk.clkr,
2730 	[CAMSS_CSI3_CLK] = &camss_csi3_clk.clkr,
2731 	[CAMSS_CSI3_AHB_CLK] = &camss_csi3_ahb_clk.clkr,
2732 	[CAMSS_CSI3RDI_CLK] = &camss_csi3rdi_clk.clkr,
2733 	[CAMSS_CSI3PIX_CLK] = &camss_csi3pix_clk.clkr,
2734 	[CAMSS_ISPIF_AHB_CLK] = &camss_ispif_ahb_clk.clkr,
2735 	[CAMSS_CCI_CLK] = &camss_cci_clk.clkr,
2736 	[CAMSS_CCI_AHB_CLK] = &camss_cci_ahb_clk.clkr,
2737 	[CAMSS_MCLK0_CLK] = &camss_mclk0_clk.clkr,
2738 	[CAMSS_MCLK1_CLK] = &camss_mclk1_clk.clkr,
2739 	[CAMSS_MCLK2_CLK] = &camss_mclk2_clk.clkr,
2740 	[CAMSS_MCLK3_CLK] = &camss_mclk3_clk.clkr,
2741 	[CAMSS_TOP_AHB_CLK] = &camss_top_ahb_clk.clkr,
2742 	[CAMSS_AHB_CLK] = &camss_ahb_clk.clkr,
2743 	[CAMSS_MICRO_AHB_CLK] = &camss_micro_ahb_clk.clkr,
2744 	[CAMSS_JPEG0_CLK] = &camss_jpeg0_clk.clkr,
2745 	[CAMSS_JPEG_AHB_CLK] = &camss_jpeg_ahb_clk.clkr,
2746 	[CAMSS_JPEG_AXI_CLK] = &camss_jpeg_axi_clk.clkr,
2747 	[CAMSS_VFE0_AHB_CLK] = &camss_vfe0_ahb_clk.clkr,
2748 	[CAMSS_VFE1_AHB_CLK] = &camss_vfe1_ahb_clk.clkr,
2749 	[CAMSS_VFE0_CLK] = &camss_vfe0_clk.clkr,
2750 	[CAMSS_VFE1_CLK] = &camss_vfe1_clk.clkr,
2751 	[CAMSS_CPP_CLK] = &camss_cpp_clk.clkr,
2752 	[CAMSS_CPP_AHB_CLK] = &camss_cpp_ahb_clk.clkr,
2753 	[CAMSS_VFE_VBIF_AHB_CLK] = &camss_vfe_vbif_ahb_clk.clkr,
2754 	[CAMSS_VFE_VBIF_AXI_CLK] = &camss_vfe_vbif_axi_clk.clkr,
2755 	[CAMSS_CPP_AXI_CLK] = &camss_cpp_axi_clk.clkr,
2756 	[CAMSS_CPP_VBIF_AHB_CLK] = &camss_cpp_vbif_ahb_clk.clkr,
2757 	[CAMSS_CSI_VFE0_CLK] = &camss_csi_vfe0_clk.clkr,
2758 	[CAMSS_CSI_VFE1_CLK] = &camss_csi_vfe1_clk.clkr,
2759 	[CAMSS_VFE0_STREAM_CLK] = &camss_vfe0_stream_clk.clkr,
2760 	[CAMSS_VFE1_STREAM_CLK] = &camss_vfe1_stream_clk.clkr,
2761 	[CAMSS_CPHY_CSID0_CLK] = &camss_cphy_csid0_clk.clkr,
2762 	[CAMSS_CPHY_CSID1_CLK] = &camss_cphy_csid1_clk.clkr,
2763 	[CAMSS_CPHY_CSID2_CLK] = &camss_cphy_csid2_clk.clkr,
2764 	[CAMSS_CPHY_CSID3_CLK] = &camss_cphy_csid3_clk.clkr,
2765 	[CAMSS_CSIPHY0_CLK] = &camss_csiphy0_clk.clkr,
2766 	[CAMSS_CSIPHY1_CLK] = &camss_csiphy1_clk.clkr,
2767 	[CAMSS_CSIPHY2_CLK] = &camss_csiphy2_clk.clkr,
2768 	[FD_CORE_CLK] = &fd_core_clk.clkr,
2769 	[FD_CORE_UAR_CLK] = &fd_core_uar_clk.clkr,
2770 	[FD_AHB_CLK] = &fd_ahb_clk.clkr,
2771 	[MNOC_AHB_CLK] = &mnoc_ahb_clk.clkr,
2772 	[BIMC_SMMU_AHB_CLK] = &bimc_smmu_ahb_clk.clkr,
2773 	[BIMC_SMMU_AXI_CLK] = &bimc_smmu_axi_clk.clkr,
2774 	[MNOC_MAXI_CLK] = &mnoc_maxi_clk.clkr,
2775 	[VMEM_MAXI_CLK] = &vmem_maxi_clk.clkr,
2776 	[VMEM_AHB_CLK] = &vmem_ahb_clk.clkr,
2777 };
2778 
2779 static struct gdsc *mmcc_msm8998_gdscs[] = {
2780 	[VIDEO_TOP_GDSC] = &video_top_gdsc,
2781 	[VIDEO_SUBCORE0_GDSC] = &video_subcore0_gdsc,
2782 	[VIDEO_SUBCORE1_GDSC] = &video_subcore1_gdsc,
2783 	[MDSS_GDSC] = &mdss_gdsc,
2784 	[CAMSS_TOP_GDSC] = &camss_top_gdsc,
2785 	[CAMSS_VFE0_GDSC] = &camss_vfe0_gdsc,
2786 	[CAMSS_VFE1_GDSC] = &camss_vfe1_gdsc,
2787 	[CAMSS_CPP_GDSC] = &camss_cpp_gdsc,
2788 	[BIMC_SMMU_GDSC] = &bimc_smmu_gdsc,
2789 };
2790 
2791 static const struct qcom_reset_map mmcc_msm8998_resets[] = {
2792 	[SPDM_BCR] = { 0x200 },
2793 	[SPDM_RM_BCR] = { 0x300 },
2794 	[MISC_BCR] = { 0x320 },
2795 	[VIDEO_TOP_BCR] = { 0x1020 },
2796 	[THROTTLE_VIDEO_BCR] = { 0x1180 },
2797 	[MDSS_BCR] = { 0x2300 },
2798 	[THROTTLE_MDSS_BCR] = { 0x2460 },
2799 	[CAMSS_PHY0_BCR] = { 0x3020 },
2800 	[CAMSS_PHY1_BCR] = { 0x3050 },
2801 	[CAMSS_PHY2_BCR] = { 0x3080 },
2802 	[CAMSS_CSI0_BCR] = { 0x30b0 },
2803 	[CAMSS_CSI0RDI_BCR] = { 0x30d0 },
2804 	[CAMSS_CSI0PIX_BCR] = { 0x30e0 },
2805 	[CAMSS_CSI1_BCR] = { 0x3120 },
2806 	[CAMSS_CSI1RDI_BCR] = { 0x3140 },
2807 	[CAMSS_CSI1PIX_BCR] = { 0x3150 },
2808 	[CAMSS_CSI2_BCR] = { 0x3180 },
2809 	[CAMSS_CSI2RDI_BCR] = { 0x31a0 },
2810 	[CAMSS_CSI2PIX_BCR] = { 0x31b0 },
2811 	[CAMSS_CSI3_BCR] = { 0x31e0 },
2812 	[CAMSS_CSI3RDI_BCR] = { 0x3200 },
2813 	[CAMSS_CSI3PIX_BCR] = { 0x3210 },
2814 	[CAMSS_ISPIF_BCR] = { 0x3220 },
2815 	[CAMSS_CCI_BCR] = { 0x3340 },
2816 	[CAMSS_TOP_BCR] = { 0x3480 },
2817 	[CAMSS_AHB_BCR] = { 0x3488 },
2818 	[CAMSS_MICRO_BCR] = { 0x3490 },
2819 	[CAMSS_JPEG_BCR] = { 0x35a0 },
2820 	[CAMSS_VFE0_BCR] = { 0x3660 },
2821 	[CAMSS_VFE1_BCR] = { 0x3670 },
2822 	[CAMSS_VFE_VBIF_BCR] = { 0x36a0 },
2823 	[CAMSS_CPP_TOP_BCR] = { 0x36c0 },
2824 	[CAMSS_CPP_BCR] = { 0x36d0 },
2825 	[CAMSS_CSI_VFE0_BCR] = { 0x3700 },
2826 	[CAMSS_CSI_VFE1_BCR] = { 0x3710 },
2827 	[CAMSS_FD_BCR] = { 0x3b60 },
2828 	[THROTTLE_CAMSS_BCR] = { 0x3c30 },
2829 	[MNOCAHB_BCR] = { 0x5020 },
2830 	[MNOCAXI_BCR] = { 0xd020 },
2831 	[BMIC_SMMU_BCR] = { 0xe000 },
2832 	[MNOC_MAXI_BCR] = { 0xf000 },
2833 	[VMEM_BCR] = { 0xf060 },
2834 	[BTO_BCR] = { 0x10004 },
2835 };
2836 
2837 static const struct regmap_config mmcc_msm8998_regmap_config = {
2838 	.reg_bits	= 32,
2839 	.reg_stride	= 4,
2840 	.val_bits	= 32,
2841 	.max_register	= 0x10004,
2842 	.fast_io	= true,
2843 };
2844 
2845 static const struct qcom_cc_desc mmcc_msm8998_desc = {
2846 	.config = &mmcc_msm8998_regmap_config,
2847 	.clks = mmcc_msm8998_clocks,
2848 	.num_clks = ARRAY_SIZE(mmcc_msm8998_clocks),
2849 	.resets = mmcc_msm8998_resets,
2850 	.num_resets = ARRAY_SIZE(mmcc_msm8998_resets),
2851 	.gdscs = mmcc_msm8998_gdscs,
2852 	.num_gdscs = ARRAY_SIZE(mmcc_msm8998_gdscs),
2853 };
2854 
2855 static const struct of_device_id mmcc_msm8998_match_table[] = {
2856 	{ .compatible = "qcom,mmcc-msm8998" },
2857 	{ }
2858 };
2859 MODULE_DEVICE_TABLE(of, mmcc_msm8998_match_table);
2860 
mmcc_msm8998_probe(struct platform_device * pdev)2861 static int mmcc_msm8998_probe(struct platform_device *pdev)
2862 {
2863 	struct regmap *regmap;
2864 
2865 	regmap = qcom_cc_map(pdev, &mmcc_msm8998_desc);
2866 	if (IS_ERR(regmap))
2867 		return PTR_ERR(regmap);
2868 
2869 	return qcom_cc_really_probe(pdev, &mmcc_msm8998_desc, regmap);
2870 }
2871 
2872 static struct platform_driver mmcc_msm8998_driver = {
2873 	.probe		= mmcc_msm8998_probe,
2874 	.driver		= {
2875 		.name	= "mmcc-msm8998",
2876 		.of_match_table = mmcc_msm8998_match_table,
2877 	},
2878 };
2879 module_platform_driver(mmcc_msm8998_driver);
2880 
2881 MODULE_DESCRIPTION("QCOM MMCC MSM8998 Driver");
2882 MODULE_LICENSE("GPL v2");
2883