1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * intel_pstate.c: Native P state management for Intel processors
4 *
5 * (C) Copyright 2012 Intel Corporation
6 * Author: Dirk Brandewie <dirk.j.brandewie@intel.com>
7 */
8
9 #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
10
11 #include <linux/kernel.h>
12 #include <linux/kernel_stat.h>
13 #include <linux/module.h>
14 #include <linux/ktime.h>
15 #include <linux/hrtimer.h>
16 #include <linux/tick.h>
17 #include <linux/slab.h>
18 #include <linux/sched/cpufreq.h>
19 #include <linux/list.h>
20 #include <linux/cpu.h>
21 #include <linux/cpufreq.h>
22 #include <linux/sysfs.h>
23 #include <linux/types.h>
24 #include <linux/fs.h>
25 #include <linux/acpi.h>
26 #include <linux/vmalloc.h>
27 #include <linux/pm_qos.h>
28 #include <trace/events/power.h>
29
30 #include <asm/cpu.h>
31 #include <asm/div64.h>
32 #include <asm/msr.h>
33 #include <asm/cpu_device_id.h>
34 #include <asm/cpufeature.h>
35 #include <asm/intel-family.h>
36 #include "../drivers/thermal/intel/thermal_interrupt.h"
37
38 #define INTEL_PSTATE_SAMPLING_INTERVAL (10 * NSEC_PER_MSEC)
39
40 #define INTEL_CPUFREQ_TRANSITION_LATENCY 20000
41 #define INTEL_CPUFREQ_TRANSITION_DELAY_HWP 5000
42 #define INTEL_CPUFREQ_TRANSITION_DELAY 500
43
44 #ifdef CONFIG_ACPI
45 #include <acpi/processor.h>
46 #include <acpi/cppc_acpi.h>
47 #endif
48
49 #define FRAC_BITS 8
50 #define int_tofp(X) ((int64_t)(X) << FRAC_BITS)
51 #define fp_toint(X) ((X) >> FRAC_BITS)
52
53 #define ONE_EIGHTH_FP ((int64_t)1 << (FRAC_BITS - 3))
54
55 #define EXT_BITS 6
56 #define EXT_FRAC_BITS (EXT_BITS + FRAC_BITS)
57 #define fp_ext_toint(X) ((X) >> EXT_FRAC_BITS)
58 #define int_ext_tofp(X) ((int64_t)(X) << EXT_FRAC_BITS)
59
mul_fp(int32_t x,int32_t y)60 static inline int32_t mul_fp(int32_t x, int32_t y)
61 {
62 return ((int64_t)x * (int64_t)y) >> FRAC_BITS;
63 }
64
div_fp(s64 x,s64 y)65 static inline int32_t div_fp(s64 x, s64 y)
66 {
67 return div64_s64((int64_t)x << FRAC_BITS, y);
68 }
69
ceiling_fp(int32_t x)70 static inline int ceiling_fp(int32_t x)
71 {
72 int mask, ret;
73
74 ret = fp_toint(x);
75 mask = (1 << FRAC_BITS) - 1;
76 if (x & mask)
77 ret += 1;
78 return ret;
79 }
80
mul_ext_fp(u64 x,u64 y)81 static inline u64 mul_ext_fp(u64 x, u64 y)
82 {
83 return (x * y) >> EXT_FRAC_BITS;
84 }
85
div_ext_fp(u64 x,u64 y)86 static inline u64 div_ext_fp(u64 x, u64 y)
87 {
88 return div64_u64(x << EXT_FRAC_BITS, y);
89 }
90
91 /**
92 * struct sample - Store performance sample
93 * @core_avg_perf: Ratio of APERF/MPERF which is the actual average
94 * performance during last sample period
95 * @busy_scaled: Scaled busy value which is used to calculate next
96 * P state. This can be different than core_avg_perf
97 * to account for cpu idle period
98 * @aperf: Difference of actual performance frequency clock count
99 * read from APERF MSR between last and current sample
100 * @mperf: Difference of maximum performance frequency clock count
101 * read from MPERF MSR between last and current sample
102 * @tsc: Difference of time stamp counter between last and
103 * current sample
104 * @time: Current time from scheduler
105 *
106 * This structure is used in the cpudata structure to store performance sample
107 * data for choosing next P State.
108 */
109 struct sample {
110 int32_t core_avg_perf;
111 int32_t busy_scaled;
112 u64 aperf;
113 u64 mperf;
114 u64 tsc;
115 u64 time;
116 };
117
118 /**
119 * struct pstate_data - Store P state data
120 * @current_pstate: Current requested P state
121 * @min_pstate: Min P state possible for this platform
122 * @max_pstate: Max P state possible for this platform
123 * @max_pstate_physical:This is physical Max P state for a processor
124 * This can be higher than the max_pstate which can
125 * be limited by platform thermal design power limits
126 * @perf_ctl_scaling: PERF_CTL P-state to frequency scaling factor
127 * @scaling: Scaling factor between performance and frequency
128 * @turbo_pstate: Max Turbo P state possible for this platform
129 * @min_freq: @min_pstate frequency in cpufreq units
130 * @max_freq: @max_pstate frequency in cpufreq units
131 * @turbo_freq: @turbo_pstate frequency in cpufreq units
132 *
133 * Stores the per cpu model P state limits and current P state.
134 */
135 struct pstate_data {
136 int current_pstate;
137 int min_pstate;
138 int max_pstate;
139 int max_pstate_physical;
140 int perf_ctl_scaling;
141 int scaling;
142 int turbo_pstate;
143 unsigned int min_freq;
144 unsigned int max_freq;
145 unsigned int turbo_freq;
146 };
147
148 /**
149 * struct vid_data - Stores voltage information data
150 * @min: VID data for this platform corresponding to
151 * the lowest P state
152 * @max: VID data corresponding to the highest P State.
153 * @turbo: VID data for turbo P state
154 * @ratio: Ratio of (vid max - vid min) /
155 * (max P state - Min P State)
156 *
157 * Stores the voltage data for DVFS (Dynamic Voltage and Frequency Scaling)
158 * This data is used in Atom platforms, where in addition to target P state,
159 * the voltage data needs to be specified to select next P State.
160 */
161 struct vid_data {
162 int min;
163 int max;
164 int turbo;
165 int32_t ratio;
166 };
167
168 /**
169 * struct global_params - Global parameters, mostly tunable via sysfs.
170 * @no_turbo: Whether or not to use turbo P-states.
171 * @turbo_disabled: Whether or not turbo P-states are available at all,
172 * based on the MSR_IA32_MISC_ENABLE value and whether or
173 * not the maximum reported turbo P-state is different from
174 * the maximum reported non-turbo one.
175 * @turbo_disabled_mf: The @turbo_disabled value reflected by cpuinfo.max_freq.
176 * @min_perf_pct: Minimum capacity limit in percent of the maximum turbo
177 * P-state capacity.
178 * @max_perf_pct: Maximum capacity limit in percent of the maximum turbo
179 * P-state capacity.
180 */
181 struct global_params {
182 bool no_turbo;
183 bool turbo_disabled;
184 bool turbo_disabled_mf;
185 int max_perf_pct;
186 int min_perf_pct;
187 };
188
189 /**
190 * struct cpudata - Per CPU instance data storage
191 * @cpu: CPU number for this instance data
192 * @policy: CPUFreq policy value
193 * @update_util: CPUFreq utility callback information
194 * @update_util_set: CPUFreq utility callback is set
195 * @iowait_boost: iowait-related boost fraction
196 * @last_update: Time of the last update.
197 * @pstate: Stores P state limits for this CPU
198 * @vid: Stores VID limits for this CPU
199 * @last_sample_time: Last Sample time
200 * @aperf_mperf_shift: APERF vs MPERF counting frequency difference
201 * @prev_aperf: Last APERF value read from APERF MSR
202 * @prev_mperf: Last MPERF value read from MPERF MSR
203 * @prev_tsc: Last timestamp counter (TSC) value
204 * @prev_cummulative_iowait: IO Wait time difference from last and
205 * current sample
206 * @sample: Storage for storing last Sample data
207 * @min_perf_ratio: Minimum capacity in terms of PERF or HWP ratios
208 * @max_perf_ratio: Maximum capacity in terms of PERF or HWP ratios
209 * @acpi_perf_data: Stores ACPI perf information read from _PSS
210 * @valid_pss_table: Set to true for valid ACPI _PSS entries found
211 * @epp_powersave: Last saved HWP energy performance preference
212 * (EPP) or energy performance bias (EPB),
213 * when policy switched to performance
214 * @epp_policy: Last saved policy used to set EPP/EPB
215 * @epp_default: Power on default HWP energy performance
216 * preference/bias
217 * @epp_cached Cached HWP energy-performance preference value
218 * @hwp_req_cached: Cached value of the last HWP Request MSR
219 * @hwp_cap_cached: Cached value of the last HWP Capabilities MSR
220 * @last_io_update: Last time when IO wake flag was set
221 * @sched_flags: Store scheduler flags for possible cross CPU update
222 * @hwp_boost_min: Last HWP boosted min performance
223 * @suspended: Whether or not the driver has been suspended.
224 * @hwp_notify_work: workqueue for HWP notifications.
225 *
226 * This structure stores per CPU instance data for all CPUs.
227 */
228 struct cpudata {
229 int cpu;
230
231 unsigned int policy;
232 struct update_util_data update_util;
233 bool update_util_set;
234
235 struct pstate_data pstate;
236 struct vid_data vid;
237
238 u64 last_update;
239 u64 last_sample_time;
240 u64 aperf_mperf_shift;
241 u64 prev_aperf;
242 u64 prev_mperf;
243 u64 prev_tsc;
244 u64 prev_cummulative_iowait;
245 struct sample sample;
246 int32_t min_perf_ratio;
247 int32_t max_perf_ratio;
248 #ifdef CONFIG_ACPI
249 struct acpi_processor_performance acpi_perf_data;
250 bool valid_pss_table;
251 #endif
252 unsigned int iowait_boost;
253 s16 epp_powersave;
254 s16 epp_policy;
255 s16 epp_default;
256 s16 epp_cached;
257 u64 hwp_req_cached;
258 u64 hwp_cap_cached;
259 u64 last_io_update;
260 unsigned int sched_flags;
261 u32 hwp_boost_min;
262 bool suspended;
263 struct delayed_work hwp_notify_work;
264 };
265
266 static struct cpudata **all_cpu_data;
267
268 /**
269 * struct pstate_funcs - Per CPU model specific callbacks
270 * @get_max: Callback to get maximum non turbo effective P state
271 * @get_max_physical: Callback to get maximum non turbo physical P state
272 * @get_min: Callback to get minimum P state
273 * @get_turbo: Callback to get turbo P state
274 * @get_scaling: Callback to get frequency scaling factor
275 * @get_cpu_scaling: Get frequency scaling factor for a given cpu
276 * @get_aperf_mperf_shift: Callback to get the APERF vs MPERF frequency difference
277 * @get_val: Callback to convert P state to actual MSR write value
278 * @get_vid: Callback to get VID data for Atom platforms
279 *
280 * Core and Atom CPU models have different way to get P State limits. This
281 * structure is used to store those callbacks.
282 */
283 struct pstate_funcs {
284 int (*get_max)(int cpu);
285 int (*get_max_physical)(int cpu);
286 int (*get_min)(int cpu);
287 int (*get_turbo)(int cpu);
288 int (*get_scaling)(void);
289 int (*get_cpu_scaling)(int cpu);
290 int (*get_aperf_mperf_shift)(void);
291 u64 (*get_val)(struct cpudata*, int pstate);
292 void (*get_vid)(struct cpudata *);
293 };
294
295 static struct pstate_funcs pstate_funcs __read_mostly;
296
297 static int hwp_active __read_mostly;
298 static int hwp_mode_bdw __read_mostly;
299 static bool per_cpu_limits __read_mostly;
300 static bool hwp_boost __read_mostly;
301 static bool hwp_forced __read_mostly;
302
303 static struct cpufreq_driver *intel_pstate_driver __read_mostly;
304
305 #define HYBRID_SCALING_FACTOR 78741
306
core_get_scaling(void)307 static inline int core_get_scaling(void)
308 {
309 return 100000;
310 }
311
312 #ifdef CONFIG_ACPI
313 static bool acpi_ppc;
314 #endif
315
316 static struct global_params global;
317
318 static DEFINE_MUTEX(intel_pstate_driver_lock);
319 static DEFINE_MUTEX(intel_pstate_limits_lock);
320
321 #ifdef CONFIG_ACPI
322
intel_pstate_acpi_pm_profile_server(void)323 static bool intel_pstate_acpi_pm_profile_server(void)
324 {
325 if (acpi_gbl_FADT.preferred_profile == PM_ENTERPRISE_SERVER ||
326 acpi_gbl_FADT.preferred_profile == PM_PERFORMANCE_SERVER)
327 return true;
328
329 return false;
330 }
331
intel_pstate_get_ppc_enable_status(void)332 static bool intel_pstate_get_ppc_enable_status(void)
333 {
334 if (intel_pstate_acpi_pm_profile_server())
335 return true;
336
337 return acpi_ppc;
338 }
339
340 #ifdef CONFIG_ACPI_CPPC_LIB
341
342 /* The work item is needed to avoid CPU hotplug locking issues */
intel_pstste_sched_itmt_work_fn(struct work_struct * work)343 static void intel_pstste_sched_itmt_work_fn(struct work_struct *work)
344 {
345 sched_set_itmt_support();
346 }
347
348 static DECLARE_WORK(sched_itmt_work, intel_pstste_sched_itmt_work_fn);
349
350 #define CPPC_MAX_PERF U8_MAX
351
intel_pstate_set_itmt_prio(int cpu)352 static void intel_pstate_set_itmt_prio(int cpu)
353 {
354 struct cppc_perf_caps cppc_perf;
355 static u32 max_highest_perf = 0, min_highest_perf = U32_MAX;
356 int ret;
357
358 ret = cppc_get_perf_caps(cpu, &cppc_perf);
359 /*
360 * If CPPC is not available, fall back to MSR_HWP_CAPABILITIES bits [8:0].
361 *
362 * Also, on some systems with overclocking enabled, CPPC.highest_perf is
363 * hardcoded to 0xff, so CPPC.highest_perf cannot be used to enable ITMT.
364 * Fall back to MSR_HWP_CAPABILITIES then too.
365 */
366 if (ret || cppc_perf.highest_perf == CPPC_MAX_PERF)
367 cppc_perf.highest_perf = HWP_HIGHEST_PERF(READ_ONCE(all_cpu_data[cpu]->hwp_cap_cached));
368
369 /*
370 * The priorities can be set regardless of whether or not
371 * sched_set_itmt_support(true) has been called and it is valid to
372 * update them at any time after it has been called.
373 */
374 sched_set_itmt_core_prio(cppc_perf.highest_perf, cpu);
375
376 if (max_highest_perf <= min_highest_perf) {
377 if (cppc_perf.highest_perf > max_highest_perf)
378 max_highest_perf = cppc_perf.highest_perf;
379
380 if (cppc_perf.highest_perf < min_highest_perf)
381 min_highest_perf = cppc_perf.highest_perf;
382
383 if (max_highest_perf > min_highest_perf) {
384 /*
385 * This code can be run during CPU online under the
386 * CPU hotplug locks, so sched_set_itmt_support()
387 * cannot be called from here. Queue up a work item
388 * to invoke it.
389 */
390 schedule_work(&sched_itmt_work);
391 }
392 }
393 }
394
intel_pstate_get_cppc_guaranteed(int cpu)395 static int intel_pstate_get_cppc_guaranteed(int cpu)
396 {
397 struct cppc_perf_caps cppc_perf;
398 int ret;
399
400 ret = cppc_get_perf_caps(cpu, &cppc_perf);
401 if (ret)
402 return ret;
403
404 if (cppc_perf.guaranteed_perf)
405 return cppc_perf.guaranteed_perf;
406
407 return cppc_perf.nominal_perf;
408 }
409
intel_pstate_cppc_get_scaling(int cpu)410 static int intel_pstate_cppc_get_scaling(int cpu)
411 {
412 struct cppc_perf_caps cppc_perf;
413 int ret;
414
415 ret = cppc_get_perf_caps(cpu, &cppc_perf);
416
417 /*
418 * If the nominal frequency and the nominal performance are not
419 * zero and the ratio between them is not 100, return the hybrid
420 * scaling factor.
421 */
422 if (!ret && cppc_perf.nominal_perf && cppc_perf.nominal_freq &&
423 cppc_perf.nominal_perf * 100 != cppc_perf.nominal_freq)
424 return HYBRID_SCALING_FACTOR;
425
426 return core_get_scaling();
427 }
428
429 #else /* CONFIG_ACPI_CPPC_LIB */
intel_pstate_set_itmt_prio(int cpu)430 static inline void intel_pstate_set_itmt_prio(int cpu)
431 {
432 }
433 #endif /* CONFIG_ACPI_CPPC_LIB */
434
intel_pstate_init_acpi_perf_limits(struct cpufreq_policy * policy)435 static void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
436 {
437 struct cpudata *cpu;
438 int ret;
439 int i;
440
441 if (hwp_active) {
442 intel_pstate_set_itmt_prio(policy->cpu);
443 return;
444 }
445
446 if (!intel_pstate_get_ppc_enable_status())
447 return;
448
449 cpu = all_cpu_data[policy->cpu];
450
451 ret = acpi_processor_register_performance(&cpu->acpi_perf_data,
452 policy->cpu);
453 if (ret)
454 return;
455
456 /*
457 * Check if the control value in _PSS is for PERF_CTL MSR, which should
458 * guarantee that the states returned by it map to the states in our
459 * list directly.
460 */
461 if (cpu->acpi_perf_data.control_register.space_id !=
462 ACPI_ADR_SPACE_FIXED_HARDWARE)
463 goto err;
464
465 /*
466 * If there is only one entry _PSS, simply ignore _PSS and continue as
467 * usual without taking _PSS into account
468 */
469 if (cpu->acpi_perf_data.state_count < 2)
470 goto err;
471
472 pr_debug("CPU%u - ACPI _PSS perf data\n", policy->cpu);
473 for (i = 0; i < cpu->acpi_perf_data.state_count; i++) {
474 pr_debug(" %cP%d: %u MHz, %u mW, 0x%x\n",
475 (i == cpu->acpi_perf_data.state ? '*' : ' '), i,
476 (u32) cpu->acpi_perf_data.states[i].core_frequency,
477 (u32) cpu->acpi_perf_data.states[i].power,
478 (u32) cpu->acpi_perf_data.states[i].control);
479 }
480
481 cpu->valid_pss_table = true;
482 pr_debug("_PPC limits will be enforced\n");
483
484 return;
485
486 err:
487 cpu->valid_pss_table = false;
488 acpi_processor_unregister_performance(policy->cpu);
489 }
490
intel_pstate_exit_perf_limits(struct cpufreq_policy * policy)491 static void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
492 {
493 struct cpudata *cpu;
494
495 cpu = all_cpu_data[policy->cpu];
496 if (!cpu->valid_pss_table)
497 return;
498
499 acpi_processor_unregister_performance(policy->cpu);
500 }
501 #else /* CONFIG_ACPI */
intel_pstate_init_acpi_perf_limits(struct cpufreq_policy * policy)502 static inline void intel_pstate_init_acpi_perf_limits(struct cpufreq_policy *policy)
503 {
504 }
505
intel_pstate_exit_perf_limits(struct cpufreq_policy * policy)506 static inline void intel_pstate_exit_perf_limits(struct cpufreq_policy *policy)
507 {
508 }
509
intel_pstate_acpi_pm_profile_server(void)510 static inline bool intel_pstate_acpi_pm_profile_server(void)
511 {
512 return false;
513 }
514 #endif /* CONFIG_ACPI */
515
516 #ifndef CONFIG_ACPI_CPPC_LIB
intel_pstate_get_cppc_guaranteed(int cpu)517 static inline int intel_pstate_get_cppc_guaranteed(int cpu)
518 {
519 return -ENOTSUPP;
520 }
521
intel_pstate_cppc_get_scaling(int cpu)522 static int intel_pstate_cppc_get_scaling(int cpu)
523 {
524 return core_get_scaling();
525 }
526 #endif /* CONFIG_ACPI_CPPC_LIB */
527
intel_pstate_freq_to_hwp_rel(struct cpudata * cpu,int freq,unsigned int relation)528 static int intel_pstate_freq_to_hwp_rel(struct cpudata *cpu, int freq,
529 unsigned int relation)
530 {
531 if (freq == cpu->pstate.turbo_freq)
532 return cpu->pstate.turbo_pstate;
533
534 if (freq == cpu->pstate.max_freq)
535 return cpu->pstate.max_pstate;
536
537 switch (relation) {
538 case CPUFREQ_RELATION_H:
539 return freq / cpu->pstate.scaling;
540 case CPUFREQ_RELATION_C:
541 return DIV_ROUND_CLOSEST(freq, cpu->pstate.scaling);
542 }
543
544 return DIV_ROUND_UP(freq, cpu->pstate.scaling);
545 }
546
intel_pstate_freq_to_hwp(struct cpudata * cpu,int freq)547 static int intel_pstate_freq_to_hwp(struct cpudata *cpu, int freq)
548 {
549 return intel_pstate_freq_to_hwp_rel(cpu, freq, CPUFREQ_RELATION_L);
550 }
551
552 /**
553 * intel_pstate_hybrid_hwp_adjust - Calibrate HWP performance levels.
554 * @cpu: Target CPU.
555 *
556 * On hybrid processors, HWP may expose more performance levels than there are
557 * P-states accessible through the PERF_CTL interface. If that happens, the
558 * scaling factor between HWP performance levels and CPU frequency will be less
559 * than the scaling factor between P-state values and CPU frequency.
560 *
561 * In that case, adjust the CPU parameters used in computations accordingly.
562 */
intel_pstate_hybrid_hwp_adjust(struct cpudata * cpu)563 static void intel_pstate_hybrid_hwp_adjust(struct cpudata *cpu)
564 {
565 int perf_ctl_max_phys = cpu->pstate.max_pstate_physical;
566 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
567 int perf_ctl_turbo = pstate_funcs.get_turbo(cpu->cpu);
568 int scaling = cpu->pstate.scaling;
569 int freq;
570
571 pr_debug("CPU%d: perf_ctl_max_phys = %d\n", cpu->cpu, perf_ctl_max_phys);
572 pr_debug("CPU%d: perf_ctl_turbo = %d\n", cpu->cpu, perf_ctl_turbo);
573 pr_debug("CPU%d: perf_ctl_scaling = %d\n", cpu->cpu, perf_ctl_scaling);
574 pr_debug("CPU%d: HWP_CAP guaranteed = %d\n", cpu->cpu, cpu->pstate.max_pstate);
575 pr_debug("CPU%d: HWP_CAP highest = %d\n", cpu->cpu, cpu->pstate.turbo_pstate);
576 pr_debug("CPU%d: HWP-to-frequency scaling factor: %d\n", cpu->cpu, scaling);
577
578 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_pstate * scaling,
579 perf_ctl_scaling);
580 cpu->pstate.max_freq = rounddown(cpu->pstate.max_pstate * scaling,
581 perf_ctl_scaling);
582
583 freq = perf_ctl_max_phys * perf_ctl_scaling;
584 cpu->pstate.max_pstate_physical = intel_pstate_freq_to_hwp(cpu, freq);
585
586 freq = cpu->pstate.min_pstate * perf_ctl_scaling;
587 cpu->pstate.min_freq = freq;
588 /*
589 * Cast the min P-state value retrieved via pstate_funcs.get_min() to
590 * the effective range of HWP performance levels.
591 */
592 cpu->pstate.min_pstate = intel_pstate_freq_to_hwp(cpu, freq);
593 }
594
update_turbo_state(void)595 static inline void update_turbo_state(void)
596 {
597 u64 misc_en;
598 struct cpudata *cpu;
599
600 cpu = all_cpu_data[0];
601 rdmsrl(MSR_IA32_MISC_ENABLE, misc_en);
602 global.turbo_disabled =
603 (misc_en & MSR_IA32_MISC_ENABLE_TURBO_DISABLE ||
604 cpu->pstate.max_pstate == cpu->pstate.turbo_pstate);
605 }
606
min_perf_pct_min(void)607 static int min_perf_pct_min(void)
608 {
609 struct cpudata *cpu = all_cpu_data[0];
610 int turbo_pstate = cpu->pstate.turbo_pstate;
611
612 return turbo_pstate ?
613 (cpu->pstate.min_pstate * 100 / turbo_pstate) : 0;
614 }
615
intel_pstate_get_epb(struct cpudata * cpu_data)616 static s16 intel_pstate_get_epb(struct cpudata *cpu_data)
617 {
618 u64 epb;
619 int ret;
620
621 if (!boot_cpu_has(X86_FEATURE_EPB))
622 return -ENXIO;
623
624 ret = rdmsrl_on_cpu(cpu_data->cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
625 if (ret)
626 return (s16)ret;
627
628 return (s16)(epb & 0x0f);
629 }
630
intel_pstate_get_epp(struct cpudata * cpu_data,u64 hwp_req_data)631 static s16 intel_pstate_get_epp(struct cpudata *cpu_data, u64 hwp_req_data)
632 {
633 s16 epp;
634
635 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
636 /*
637 * When hwp_req_data is 0, means that caller didn't read
638 * MSR_HWP_REQUEST, so need to read and get EPP.
639 */
640 if (!hwp_req_data) {
641 epp = rdmsrl_on_cpu(cpu_data->cpu, MSR_HWP_REQUEST,
642 &hwp_req_data);
643 if (epp)
644 return epp;
645 }
646 epp = (hwp_req_data >> 24) & 0xff;
647 } else {
648 /* When there is no EPP present, HWP uses EPB settings */
649 epp = intel_pstate_get_epb(cpu_data);
650 }
651
652 return epp;
653 }
654
intel_pstate_set_epb(int cpu,s16 pref)655 static int intel_pstate_set_epb(int cpu, s16 pref)
656 {
657 u64 epb;
658 int ret;
659
660 if (!boot_cpu_has(X86_FEATURE_EPB))
661 return -ENXIO;
662
663 ret = rdmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, &epb);
664 if (ret)
665 return ret;
666
667 epb = (epb & ~0x0f) | pref;
668 wrmsrl_on_cpu(cpu, MSR_IA32_ENERGY_PERF_BIAS, epb);
669
670 return 0;
671 }
672
673 /*
674 * EPP/EPB display strings corresponding to EPP index in the
675 * energy_perf_strings[]
676 * index String
677 *-------------------------------------
678 * 0 default
679 * 1 performance
680 * 2 balance_performance
681 * 3 balance_power
682 * 4 power
683 */
684
685 enum energy_perf_value_index {
686 EPP_INDEX_DEFAULT = 0,
687 EPP_INDEX_PERFORMANCE,
688 EPP_INDEX_BALANCE_PERFORMANCE,
689 EPP_INDEX_BALANCE_POWERSAVE,
690 EPP_INDEX_POWERSAVE,
691 };
692
693 static const char * const energy_perf_strings[] = {
694 [EPP_INDEX_DEFAULT] = "default",
695 [EPP_INDEX_PERFORMANCE] = "performance",
696 [EPP_INDEX_BALANCE_PERFORMANCE] = "balance_performance",
697 [EPP_INDEX_BALANCE_POWERSAVE] = "balance_power",
698 [EPP_INDEX_POWERSAVE] = "power",
699 NULL
700 };
701 static unsigned int epp_values[] = {
702 [EPP_INDEX_DEFAULT] = 0, /* Unused index */
703 [EPP_INDEX_PERFORMANCE] = HWP_EPP_PERFORMANCE,
704 [EPP_INDEX_BALANCE_PERFORMANCE] = HWP_EPP_BALANCE_PERFORMANCE,
705 [EPP_INDEX_BALANCE_POWERSAVE] = HWP_EPP_BALANCE_POWERSAVE,
706 [EPP_INDEX_POWERSAVE] = HWP_EPP_POWERSAVE,
707 };
708
intel_pstate_get_energy_pref_index(struct cpudata * cpu_data,int * raw_epp)709 static int intel_pstate_get_energy_pref_index(struct cpudata *cpu_data, int *raw_epp)
710 {
711 s16 epp;
712 int index = -EINVAL;
713
714 *raw_epp = 0;
715 epp = intel_pstate_get_epp(cpu_data, 0);
716 if (epp < 0)
717 return epp;
718
719 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
720 if (epp == epp_values[EPP_INDEX_PERFORMANCE])
721 return EPP_INDEX_PERFORMANCE;
722 if (epp == epp_values[EPP_INDEX_BALANCE_PERFORMANCE])
723 return EPP_INDEX_BALANCE_PERFORMANCE;
724 if (epp == epp_values[EPP_INDEX_BALANCE_POWERSAVE])
725 return EPP_INDEX_BALANCE_POWERSAVE;
726 if (epp == epp_values[EPP_INDEX_POWERSAVE])
727 return EPP_INDEX_POWERSAVE;
728 *raw_epp = epp;
729 return 0;
730 } else if (boot_cpu_has(X86_FEATURE_EPB)) {
731 /*
732 * Range:
733 * 0x00-0x03 : Performance
734 * 0x04-0x07 : Balance performance
735 * 0x08-0x0B : Balance power
736 * 0x0C-0x0F : Power
737 * The EPB is a 4 bit value, but our ranges restrict the
738 * value which can be set. Here only using top two bits
739 * effectively.
740 */
741 index = (epp >> 2) + 1;
742 }
743
744 return index;
745 }
746
intel_pstate_set_epp(struct cpudata * cpu,u32 epp)747 static int intel_pstate_set_epp(struct cpudata *cpu, u32 epp)
748 {
749 int ret;
750
751 /*
752 * Use the cached HWP Request MSR value, because in the active mode the
753 * register itself may be updated by intel_pstate_hwp_boost_up() or
754 * intel_pstate_hwp_boost_down() at any time.
755 */
756 u64 value = READ_ONCE(cpu->hwp_req_cached);
757
758 value &= ~GENMASK_ULL(31, 24);
759 value |= (u64)epp << 24;
760 /*
761 * The only other updater of hwp_req_cached in the active mode,
762 * intel_pstate_hwp_set(), is called under the same lock as this
763 * function, so it cannot run in parallel with the update below.
764 */
765 WRITE_ONCE(cpu->hwp_req_cached, value);
766 ret = wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
767 if (!ret)
768 cpu->epp_cached = epp;
769
770 return ret;
771 }
772
intel_pstate_set_energy_pref_index(struct cpudata * cpu_data,int pref_index,bool use_raw,u32 raw_epp)773 static int intel_pstate_set_energy_pref_index(struct cpudata *cpu_data,
774 int pref_index, bool use_raw,
775 u32 raw_epp)
776 {
777 int epp = -EINVAL;
778 int ret;
779
780 if (!pref_index)
781 epp = cpu_data->epp_default;
782
783 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
784 if (use_raw)
785 epp = raw_epp;
786 else if (epp == -EINVAL)
787 epp = epp_values[pref_index];
788
789 /*
790 * To avoid confusion, refuse to set EPP to any values different
791 * from 0 (performance) if the current policy is "performance",
792 * because those values would be overridden.
793 */
794 if (epp > 0 && cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
795 return -EBUSY;
796
797 ret = intel_pstate_set_epp(cpu_data, epp);
798 } else {
799 if (epp == -EINVAL)
800 epp = (pref_index - 1) << 2;
801 ret = intel_pstate_set_epb(cpu_data->cpu, epp);
802 }
803
804 return ret;
805 }
806
show_energy_performance_available_preferences(struct cpufreq_policy * policy,char * buf)807 static ssize_t show_energy_performance_available_preferences(
808 struct cpufreq_policy *policy, char *buf)
809 {
810 int i = 0;
811 int ret = 0;
812
813 while (energy_perf_strings[i] != NULL)
814 ret += sprintf(&buf[ret], "%s ", energy_perf_strings[i++]);
815
816 ret += sprintf(&buf[ret], "\n");
817
818 return ret;
819 }
820
821 cpufreq_freq_attr_ro(energy_performance_available_preferences);
822
823 static struct cpufreq_driver intel_pstate;
824
store_energy_performance_preference(struct cpufreq_policy * policy,const char * buf,size_t count)825 static ssize_t store_energy_performance_preference(
826 struct cpufreq_policy *policy, const char *buf, size_t count)
827 {
828 struct cpudata *cpu = all_cpu_data[policy->cpu];
829 char str_preference[21];
830 bool raw = false;
831 ssize_t ret;
832 u32 epp = 0;
833
834 ret = sscanf(buf, "%20s", str_preference);
835 if (ret != 1)
836 return -EINVAL;
837
838 ret = match_string(energy_perf_strings, -1, str_preference);
839 if (ret < 0) {
840 if (!boot_cpu_has(X86_FEATURE_HWP_EPP))
841 return ret;
842
843 ret = kstrtouint(buf, 10, &epp);
844 if (ret)
845 return ret;
846
847 if (epp > 255)
848 return -EINVAL;
849
850 raw = true;
851 }
852
853 /*
854 * This function runs with the policy R/W semaphore held, which
855 * guarantees that the driver pointer will not change while it is
856 * running.
857 */
858 if (!intel_pstate_driver)
859 return -EAGAIN;
860
861 mutex_lock(&intel_pstate_limits_lock);
862
863 if (intel_pstate_driver == &intel_pstate) {
864 ret = intel_pstate_set_energy_pref_index(cpu, ret, raw, epp);
865 } else {
866 /*
867 * In the passive mode the governor needs to be stopped on the
868 * target CPU before the EPP update and restarted after it,
869 * which is super-heavy-weight, so make sure it is worth doing
870 * upfront.
871 */
872 if (!raw)
873 epp = ret ? epp_values[ret] : cpu->epp_default;
874
875 if (cpu->epp_cached != epp) {
876 int err;
877
878 cpufreq_stop_governor(policy);
879 ret = intel_pstate_set_epp(cpu, epp);
880 err = cpufreq_start_governor(policy);
881 if (!ret)
882 ret = err;
883 } else {
884 ret = 0;
885 }
886 }
887
888 mutex_unlock(&intel_pstate_limits_lock);
889
890 return ret ?: count;
891 }
892
show_energy_performance_preference(struct cpufreq_policy * policy,char * buf)893 static ssize_t show_energy_performance_preference(
894 struct cpufreq_policy *policy, char *buf)
895 {
896 struct cpudata *cpu_data = all_cpu_data[policy->cpu];
897 int preference, raw_epp;
898
899 preference = intel_pstate_get_energy_pref_index(cpu_data, &raw_epp);
900 if (preference < 0)
901 return preference;
902
903 if (raw_epp)
904 return sprintf(buf, "%d\n", raw_epp);
905 else
906 return sprintf(buf, "%s\n", energy_perf_strings[preference]);
907 }
908
909 cpufreq_freq_attr_rw(energy_performance_preference);
910
show_base_frequency(struct cpufreq_policy * policy,char * buf)911 static ssize_t show_base_frequency(struct cpufreq_policy *policy, char *buf)
912 {
913 struct cpudata *cpu = all_cpu_data[policy->cpu];
914 int ratio, freq;
915
916 ratio = intel_pstate_get_cppc_guaranteed(policy->cpu);
917 if (ratio <= 0) {
918 u64 cap;
919
920 rdmsrl_on_cpu(policy->cpu, MSR_HWP_CAPABILITIES, &cap);
921 ratio = HWP_GUARANTEED_PERF(cap);
922 }
923
924 freq = ratio * cpu->pstate.scaling;
925 if (cpu->pstate.scaling != cpu->pstate.perf_ctl_scaling)
926 freq = rounddown(freq, cpu->pstate.perf_ctl_scaling);
927
928 return sprintf(buf, "%d\n", freq);
929 }
930
931 cpufreq_freq_attr_ro(base_frequency);
932
933 static struct freq_attr *hwp_cpufreq_attrs[] = {
934 &energy_performance_preference,
935 &energy_performance_available_preferences,
936 &base_frequency,
937 NULL,
938 };
939
__intel_pstate_get_hwp_cap(struct cpudata * cpu)940 static void __intel_pstate_get_hwp_cap(struct cpudata *cpu)
941 {
942 u64 cap;
943
944 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_CAPABILITIES, &cap);
945 WRITE_ONCE(cpu->hwp_cap_cached, cap);
946 cpu->pstate.max_pstate = HWP_GUARANTEED_PERF(cap);
947 cpu->pstate.turbo_pstate = HWP_HIGHEST_PERF(cap);
948 }
949
intel_pstate_get_hwp_cap(struct cpudata * cpu)950 static void intel_pstate_get_hwp_cap(struct cpudata *cpu)
951 {
952 int scaling = cpu->pstate.scaling;
953
954 __intel_pstate_get_hwp_cap(cpu);
955
956 cpu->pstate.max_freq = cpu->pstate.max_pstate * scaling;
957 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * scaling;
958 if (scaling != cpu->pstate.perf_ctl_scaling) {
959 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
960
961 cpu->pstate.max_freq = rounddown(cpu->pstate.max_freq,
962 perf_ctl_scaling);
963 cpu->pstate.turbo_freq = rounddown(cpu->pstate.turbo_freq,
964 perf_ctl_scaling);
965 }
966 }
967
intel_pstate_hwp_set(unsigned int cpu)968 static void intel_pstate_hwp_set(unsigned int cpu)
969 {
970 struct cpudata *cpu_data = all_cpu_data[cpu];
971 int max, min;
972 u64 value;
973 s16 epp;
974
975 max = cpu_data->max_perf_ratio;
976 min = cpu_data->min_perf_ratio;
977
978 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE)
979 min = max;
980
981 rdmsrl_on_cpu(cpu, MSR_HWP_REQUEST, &value);
982
983 value &= ~HWP_MIN_PERF(~0L);
984 value |= HWP_MIN_PERF(min);
985
986 value &= ~HWP_MAX_PERF(~0L);
987 value |= HWP_MAX_PERF(max);
988
989 if (cpu_data->epp_policy == cpu_data->policy)
990 goto skip_epp;
991
992 cpu_data->epp_policy = cpu_data->policy;
993
994 if (cpu_data->policy == CPUFREQ_POLICY_PERFORMANCE) {
995 epp = intel_pstate_get_epp(cpu_data, value);
996 cpu_data->epp_powersave = epp;
997 /* If EPP read was failed, then don't try to write */
998 if (epp < 0)
999 goto skip_epp;
1000
1001 epp = 0;
1002 } else {
1003 /* skip setting EPP, when saved value is invalid */
1004 if (cpu_data->epp_powersave < 0)
1005 goto skip_epp;
1006
1007 /*
1008 * No need to restore EPP when it is not zero. This
1009 * means:
1010 * - Policy is not changed
1011 * - user has manually changed
1012 * - Error reading EPB
1013 */
1014 epp = intel_pstate_get_epp(cpu_data, value);
1015 if (epp)
1016 goto skip_epp;
1017
1018 epp = cpu_data->epp_powersave;
1019 }
1020 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1021 value &= ~GENMASK_ULL(31, 24);
1022 value |= (u64)epp << 24;
1023 } else {
1024 intel_pstate_set_epb(cpu, epp);
1025 }
1026 skip_epp:
1027 WRITE_ONCE(cpu_data->hwp_req_cached, value);
1028 wrmsrl_on_cpu(cpu, MSR_HWP_REQUEST, value);
1029 }
1030
1031 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata);
1032
intel_pstate_hwp_offline(struct cpudata * cpu)1033 static void intel_pstate_hwp_offline(struct cpudata *cpu)
1034 {
1035 u64 value = READ_ONCE(cpu->hwp_req_cached);
1036 int min_perf;
1037
1038 intel_pstate_disable_hwp_interrupt(cpu);
1039
1040 if (boot_cpu_has(X86_FEATURE_HWP_EPP)) {
1041 /*
1042 * In case the EPP has been set to "performance" by the
1043 * active mode "performance" scaling algorithm, replace that
1044 * temporary value with the cached EPP one.
1045 */
1046 value &= ~GENMASK_ULL(31, 24);
1047 value |= HWP_ENERGY_PERF_PREFERENCE(cpu->epp_cached);
1048 /*
1049 * However, make sure that EPP will be set to "performance" when
1050 * the CPU is brought back online again and the "performance"
1051 * scaling algorithm is still in effect.
1052 */
1053 cpu->epp_policy = CPUFREQ_POLICY_UNKNOWN;
1054 }
1055
1056 /*
1057 * Clear the desired perf field in the cached HWP request value to
1058 * prevent nonzero desired values from being leaked into the active
1059 * mode.
1060 */
1061 value &= ~HWP_DESIRED_PERF(~0L);
1062 WRITE_ONCE(cpu->hwp_req_cached, value);
1063
1064 value &= ~GENMASK_ULL(31, 0);
1065 min_perf = HWP_LOWEST_PERF(READ_ONCE(cpu->hwp_cap_cached));
1066
1067 /* Set hwp_max = hwp_min */
1068 value |= HWP_MAX_PERF(min_perf);
1069 value |= HWP_MIN_PERF(min_perf);
1070
1071 /* Set EPP to min */
1072 if (boot_cpu_has(X86_FEATURE_HWP_EPP))
1073 value |= HWP_ENERGY_PERF_PREFERENCE(HWP_EPP_POWERSAVE);
1074
1075 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
1076 }
1077
1078 #define POWER_CTL_EE_ENABLE 1
1079 #define POWER_CTL_EE_DISABLE 2
1080
1081 static int power_ctl_ee_state;
1082
set_power_ctl_ee_state(bool input)1083 static void set_power_ctl_ee_state(bool input)
1084 {
1085 u64 power_ctl;
1086
1087 mutex_lock(&intel_pstate_driver_lock);
1088 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1089 if (input) {
1090 power_ctl &= ~BIT(MSR_IA32_POWER_CTL_BIT_EE);
1091 power_ctl_ee_state = POWER_CTL_EE_ENABLE;
1092 } else {
1093 power_ctl |= BIT(MSR_IA32_POWER_CTL_BIT_EE);
1094 power_ctl_ee_state = POWER_CTL_EE_DISABLE;
1095 }
1096 wrmsrl(MSR_IA32_POWER_CTL, power_ctl);
1097 mutex_unlock(&intel_pstate_driver_lock);
1098 }
1099
1100 static void intel_pstate_hwp_enable(struct cpudata *cpudata);
1101
intel_pstate_hwp_reenable(struct cpudata * cpu)1102 static void intel_pstate_hwp_reenable(struct cpudata *cpu)
1103 {
1104 intel_pstate_hwp_enable(cpu);
1105 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, READ_ONCE(cpu->hwp_req_cached));
1106 }
1107
intel_pstate_suspend(struct cpufreq_policy * policy)1108 static int intel_pstate_suspend(struct cpufreq_policy *policy)
1109 {
1110 struct cpudata *cpu = all_cpu_data[policy->cpu];
1111
1112 pr_debug("CPU %d suspending\n", cpu->cpu);
1113
1114 cpu->suspended = true;
1115
1116 /* disable HWP interrupt and cancel any pending work */
1117 intel_pstate_disable_hwp_interrupt(cpu);
1118
1119 return 0;
1120 }
1121
intel_pstate_resume(struct cpufreq_policy * policy)1122 static int intel_pstate_resume(struct cpufreq_policy *policy)
1123 {
1124 struct cpudata *cpu = all_cpu_data[policy->cpu];
1125
1126 pr_debug("CPU %d resuming\n", cpu->cpu);
1127
1128 /* Only restore if the system default is changed */
1129 if (power_ctl_ee_state == POWER_CTL_EE_ENABLE)
1130 set_power_ctl_ee_state(true);
1131 else if (power_ctl_ee_state == POWER_CTL_EE_DISABLE)
1132 set_power_ctl_ee_state(false);
1133
1134 if (cpu->suspended && hwp_active) {
1135 mutex_lock(&intel_pstate_limits_lock);
1136
1137 /* Re-enable HWP, because "online" has not done that. */
1138 intel_pstate_hwp_reenable(cpu);
1139
1140 mutex_unlock(&intel_pstate_limits_lock);
1141 }
1142
1143 cpu->suspended = false;
1144
1145 return 0;
1146 }
1147
intel_pstate_update_policies(void)1148 static void intel_pstate_update_policies(void)
1149 {
1150 int cpu;
1151
1152 for_each_possible_cpu(cpu)
1153 cpufreq_update_policy(cpu);
1154 }
1155
__intel_pstate_update_max_freq(struct cpudata * cpudata,struct cpufreq_policy * policy)1156 static void __intel_pstate_update_max_freq(struct cpudata *cpudata,
1157 struct cpufreq_policy *policy)
1158 {
1159 policy->cpuinfo.max_freq = global.turbo_disabled_mf ?
1160 cpudata->pstate.max_freq : cpudata->pstate.turbo_freq;
1161 refresh_frequency_limits(policy);
1162 }
1163
intel_pstate_update_max_freq(unsigned int cpu)1164 static void intel_pstate_update_max_freq(unsigned int cpu)
1165 {
1166 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpu);
1167
1168 if (!policy)
1169 return;
1170
1171 __intel_pstate_update_max_freq(all_cpu_data[cpu], policy);
1172
1173 cpufreq_cpu_release(policy);
1174 }
1175
intel_pstate_update_limits(unsigned int cpu)1176 static void intel_pstate_update_limits(unsigned int cpu)
1177 {
1178 mutex_lock(&intel_pstate_driver_lock);
1179
1180 update_turbo_state();
1181 /*
1182 * If turbo has been turned on or off globally, policy limits for
1183 * all CPUs need to be updated to reflect that.
1184 */
1185 if (global.turbo_disabled_mf != global.turbo_disabled) {
1186 global.turbo_disabled_mf = global.turbo_disabled;
1187 arch_set_max_freq_ratio(global.turbo_disabled);
1188 for_each_possible_cpu(cpu)
1189 intel_pstate_update_max_freq(cpu);
1190 } else {
1191 cpufreq_update_policy(cpu);
1192 }
1193
1194 mutex_unlock(&intel_pstate_driver_lock);
1195 }
1196
1197 /************************** sysfs begin ************************/
1198 #define show_one(file_name, object) \
1199 static ssize_t show_##file_name \
1200 (struct kobject *kobj, struct kobj_attribute *attr, char *buf) \
1201 { \
1202 return sprintf(buf, "%u\n", global.object); \
1203 }
1204
1205 static ssize_t intel_pstate_show_status(char *buf);
1206 static int intel_pstate_update_status(const char *buf, size_t size);
1207
show_status(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1208 static ssize_t show_status(struct kobject *kobj,
1209 struct kobj_attribute *attr, char *buf)
1210 {
1211 ssize_t ret;
1212
1213 mutex_lock(&intel_pstate_driver_lock);
1214 ret = intel_pstate_show_status(buf);
1215 mutex_unlock(&intel_pstate_driver_lock);
1216
1217 return ret;
1218 }
1219
store_status(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1220 static ssize_t store_status(struct kobject *a, struct kobj_attribute *b,
1221 const char *buf, size_t count)
1222 {
1223 char *p = memchr(buf, '\n', count);
1224 int ret;
1225
1226 mutex_lock(&intel_pstate_driver_lock);
1227 ret = intel_pstate_update_status(buf, p ? p - buf : count);
1228 mutex_unlock(&intel_pstate_driver_lock);
1229
1230 return ret < 0 ? ret : count;
1231 }
1232
show_turbo_pct(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1233 static ssize_t show_turbo_pct(struct kobject *kobj,
1234 struct kobj_attribute *attr, char *buf)
1235 {
1236 struct cpudata *cpu;
1237 int total, no_turbo, turbo_pct;
1238 uint32_t turbo_fp;
1239
1240 mutex_lock(&intel_pstate_driver_lock);
1241
1242 if (!intel_pstate_driver) {
1243 mutex_unlock(&intel_pstate_driver_lock);
1244 return -EAGAIN;
1245 }
1246
1247 cpu = all_cpu_data[0];
1248
1249 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1250 no_turbo = cpu->pstate.max_pstate - cpu->pstate.min_pstate + 1;
1251 turbo_fp = div_fp(no_turbo, total);
1252 turbo_pct = 100 - fp_toint(mul_fp(turbo_fp, int_tofp(100)));
1253
1254 mutex_unlock(&intel_pstate_driver_lock);
1255
1256 return sprintf(buf, "%u\n", turbo_pct);
1257 }
1258
show_num_pstates(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1259 static ssize_t show_num_pstates(struct kobject *kobj,
1260 struct kobj_attribute *attr, char *buf)
1261 {
1262 struct cpudata *cpu;
1263 int total;
1264
1265 mutex_lock(&intel_pstate_driver_lock);
1266
1267 if (!intel_pstate_driver) {
1268 mutex_unlock(&intel_pstate_driver_lock);
1269 return -EAGAIN;
1270 }
1271
1272 cpu = all_cpu_data[0];
1273 total = cpu->pstate.turbo_pstate - cpu->pstate.min_pstate + 1;
1274
1275 mutex_unlock(&intel_pstate_driver_lock);
1276
1277 return sprintf(buf, "%u\n", total);
1278 }
1279
show_no_turbo(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1280 static ssize_t show_no_turbo(struct kobject *kobj,
1281 struct kobj_attribute *attr, char *buf)
1282 {
1283 ssize_t ret;
1284
1285 mutex_lock(&intel_pstate_driver_lock);
1286
1287 if (!intel_pstate_driver) {
1288 mutex_unlock(&intel_pstate_driver_lock);
1289 return -EAGAIN;
1290 }
1291
1292 update_turbo_state();
1293 if (global.turbo_disabled)
1294 ret = sprintf(buf, "%u\n", global.turbo_disabled);
1295 else
1296 ret = sprintf(buf, "%u\n", global.no_turbo);
1297
1298 mutex_unlock(&intel_pstate_driver_lock);
1299
1300 return ret;
1301 }
1302
store_no_turbo(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1303 static ssize_t store_no_turbo(struct kobject *a, struct kobj_attribute *b,
1304 const char *buf, size_t count)
1305 {
1306 unsigned int input;
1307 int ret;
1308
1309 ret = sscanf(buf, "%u", &input);
1310 if (ret != 1)
1311 return -EINVAL;
1312
1313 mutex_lock(&intel_pstate_driver_lock);
1314
1315 if (!intel_pstate_driver) {
1316 mutex_unlock(&intel_pstate_driver_lock);
1317 return -EAGAIN;
1318 }
1319
1320 mutex_lock(&intel_pstate_limits_lock);
1321
1322 update_turbo_state();
1323 if (global.turbo_disabled) {
1324 pr_notice_once("Turbo disabled by BIOS or unavailable on processor\n");
1325 mutex_unlock(&intel_pstate_limits_lock);
1326 mutex_unlock(&intel_pstate_driver_lock);
1327 return -EPERM;
1328 }
1329
1330 global.no_turbo = clamp_t(int, input, 0, 1);
1331
1332 if (global.no_turbo) {
1333 struct cpudata *cpu = all_cpu_data[0];
1334 int pct = cpu->pstate.max_pstate * 100 / cpu->pstate.turbo_pstate;
1335
1336 /* Squash the global minimum into the permitted range. */
1337 if (global.min_perf_pct > pct)
1338 global.min_perf_pct = pct;
1339 }
1340
1341 mutex_unlock(&intel_pstate_limits_lock);
1342
1343 intel_pstate_update_policies();
1344 arch_set_max_freq_ratio(global.no_turbo);
1345
1346 mutex_unlock(&intel_pstate_driver_lock);
1347
1348 return count;
1349 }
1350
update_qos_request(enum freq_qos_req_type type)1351 static void update_qos_request(enum freq_qos_req_type type)
1352 {
1353 struct freq_qos_request *req;
1354 struct cpufreq_policy *policy;
1355 int i;
1356
1357 for_each_possible_cpu(i) {
1358 struct cpudata *cpu = all_cpu_data[i];
1359 unsigned int freq, perf_pct;
1360
1361 policy = cpufreq_cpu_get(i);
1362 if (!policy)
1363 continue;
1364
1365 req = policy->driver_data;
1366 cpufreq_cpu_put(policy);
1367
1368 if (!req)
1369 continue;
1370
1371 if (hwp_active)
1372 intel_pstate_get_hwp_cap(cpu);
1373
1374 if (type == FREQ_QOS_MIN) {
1375 perf_pct = global.min_perf_pct;
1376 } else {
1377 req++;
1378 perf_pct = global.max_perf_pct;
1379 }
1380
1381 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * perf_pct, 100);
1382
1383 if (freq_qos_update_request(req, freq) < 0)
1384 pr_warn("Failed to update freq constraint: CPU%d\n", i);
1385 }
1386 }
1387
store_max_perf_pct(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1388 static ssize_t store_max_perf_pct(struct kobject *a, struct kobj_attribute *b,
1389 const char *buf, size_t count)
1390 {
1391 unsigned int input;
1392 int ret;
1393
1394 ret = sscanf(buf, "%u", &input);
1395 if (ret != 1)
1396 return -EINVAL;
1397
1398 mutex_lock(&intel_pstate_driver_lock);
1399
1400 if (!intel_pstate_driver) {
1401 mutex_unlock(&intel_pstate_driver_lock);
1402 return -EAGAIN;
1403 }
1404
1405 mutex_lock(&intel_pstate_limits_lock);
1406
1407 global.max_perf_pct = clamp_t(int, input, global.min_perf_pct, 100);
1408
1409 mutex_unlock(&intel_pstate_limits_lock);
1410
1411 if (intel_pstate_driver == &intel_pstate)
1412 intel_pstate_update_policies();
1413 else
1414 update_qos_request(FREQ_QOS_MAX);
1415
1416 mutex_unlock(&intel_pstate_driver_lock);
1417
1418 return count;
1419 }
1420
store_min_perf_pct(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1421 static ssize_t store_min_perf_pct(struct kobject *a, struct kobj_attribute *b,
1422 const char *buf, size_t count)
1423 {
1424 unsigned int input;
1425 int ret;
1426
1427 ret = sscanf(buf, "%u", &input);
1428 if (ret != 1)
1429 return -EINVAL;
1430
1431 mutex_lock(&intel_pstate_driver_lock);
1432
1433 if (!intel_pstate_driver) {
1434 mutex_unlock(&intel_pstate_driver_lock);
1435 return -EAGAIN;
1436 }
1437
1438 mutex_lock(&intel_pstate_limits_lock);
1439
1440 global.min_perf_pct = clamp_t(int, input,
1441 min_perf_pct_min(), global.max_perf_pct);
1442
1443 mutex_unlock(&intel_pstate_limits_lock);
1444
1445 if (intel_pstate_driver == &intel_pstate)
1446 intel_pstate_update_policies();
1447 else
1448 update_qos_request(FREQ_QOS_MIN);
1449
1450 mutex_unlock(&intel_pstate_driver_lock);
1451
1452 return count;
1453 }
1454
show_hwp_dynamic_boost(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1455 static ssize_t show_hwp_dynamic_boost(struct kobject *kobj,
1456 struct kobj_attribute *attr, char *buf)
1457 {
1458 return sprintf(buf, "%u\n", hwp_boost);
1459 }
1460
store_hwp_dynamic_boost(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1461 static ssize_t store_hwp_dynamic_boost(struct kobject *a,
1462 struct kobj_attribute *b,
1463 const char *buf, size_t count)
1464 {
1465 unsigned int input;
1466 int ret;
1467
1468 ret = kstrtouint(buf, 10, &input);
1469 if (ret)
1470 return ret;
1471
1472 mutex_lock(&intel_pstate_driver_lock);
1473 hwp_boost = !!input;
1474 intel_pstate_update_policies();
1475 mutex_unlock(&intel_pstate_driver_lock);
1476
1477 return count;
1478 }
1479
show_energy_efficiency(struct kobject * kobj,struct kobj_attribute * attr,char * buf)1480 static ssize_t show_energy_efficiency(struct kobject *kobj, struct kobj_attribute *attr,
1481 char *buf)
1482 {
1483 u64 power_ctl;
1484 int enable;
1485
1486 rdmsrl(MSR_IA32_POWER_CTL, power_ctl);
1487 enable = !!(power_ctl & BIT(MSR_IA32_POWER_CTL_BIT_EE));
1488 return sprintf(buf, "%d\n", !enable);
1489 }
1490
store_energy_efficiency(struct kobject * a,struct kobj_attribute * b,const char * buf,size_t count)1491 static ssize_t store_energy_efficiency(struct kobject *a, struct kobj_attribute *b,
1492 const char *buf, size_t count)
1493 {
1494 bool input;
1495 int ret;
1496
1497 ret = kstrtobool(buf, &input);
1498 if (ret)
1499 return ret;
1500
1501 set_power_ctl_ee_state(input);
1502
1503 return count;
1504 }
1505
1506 show_one(max_perf_pct, max_perf_pct);
1507 show_one(min_perf_pct, min_perf_pct);
1508
1509 define_one_global_rw(status);
1510 define_one_global_rw(no_turbo);
1511 define_one_global_rw(max_perf_pct);
1512 define_one_global_rw(min_perf_pct);
1513 define_one_global_ro(turbo_pct);
1514 define_one_global_ro(num_pstates);
1515 define_one_global_rw(hwp_dynamic_boost);
1516 define_one_global_rw(energy_efficiency);
1517
1518 static struct attribute *intel_pstate_attributes[] = {
1519 &status.attr,
1520 &no_turbo.attr,
1521 NULL
1522 };
1523
1524 static const struct attribute_group intel_pstate_attr_group = {
1525 .attrs = intel_pstate_attributes,
1526 };
1527
1528 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[];
1529
1530 static struct kobject *intel_pstate_kobject;
1531
intel_pstate_sysfs_expose_params(void)1532 static void __init intel_pstate_sysfs_expose_params(void)
1533 {
1534 struct device *dev_root = bus_get_dev_root(&cpu_subsys);
1535 int rc;
1536
1537 if (dev_root) {
1538 intel_pstate_kobject = kobject_create_and_add("intel_pstate", &dev_root->kobj);
1539 put_device(dev_root);
1540 }
1541 if (WARN_ON(!intel_pstate_kobject))
1542 return;
1543
1544 rc = sysfs_create_group(intel_pstate_kobject, &intel_pstate_attr_group);
1545 if (WARN_ON(rc))
1546 return;
1547
1548 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1549 rc = sysfs_create_file(intel_pstate_kobject, &turbo_pct.attr);
1550 WARN_ON(rc);
1551
1552 rc = sysfs_create_file(intel_pstate_kobject, &num_pstates.attr);
1553 WARN_ON(rc);
1554 }
1555
1556 /*
1557 * If per cpu limits are enforced there are no global limits, so
1558 * return without creating max/min_perf_pct attributes
1559 */
1560 if (per_cpu_limits)
1561 return;
1562
1563 rc = sysfs_create_file(intel_pstate_kobject, &max_perf_pct.attr);
1564 WARN_ON(rc);
1565
1566 rc = sysfs_create_file(intel_pstate_kobject, &min_perf_pct.attr);
1567 WARN_ON(rc);
1568
1569 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids)) {
1570 rc = sysfs_create_file(intel_pstate_kobject, &energy_efficiency.attr);
1571 WARN_ON(rc);
1572 }
1573 }
1574
intel_pstate_sysfs_remove(void)1575 static void __init intel_pstate_sysfs_remove(void)
1576 {
1577 if (!intel_pstate_kobject)
1578 return;
1579
1580 sysfs_remove_group(intel_pstate_kobject, &intel_pstate_attr_group);
1581
1582 if (!boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
1583 sysfs_remove_file(intel_pstate_kobject, &num_pstates.attr);
1584 sysfs_remove_file(intel_pstate_kobject, &turbo_pct.attr);
1585 }
1586
1587 if (!per_cpu_limits) {
1588 sysfs_remove_file(intel_pstate_kobject, &max_perf_pct.attr);
1589 sysfs_remove_file(intel_pstate_kobject, &min_perf_pct.attr);
1590
1591 if (x86_match_cpu(intel_pstate_cpu_ee_disable_ids))
1592 sysfs_remove_file(intel_pstate_kobject, &energy_efficiency.attr);
1593 }
1594
1595 kobject_put(intel_pstate_kobject);
1596 }
1597
intel_pstate_sysfs_expose_hwp_dynamic_boost(void)1598 static void intel_pstate_sysfs_expose_hwp_dynamic_boost(void)
1599 {
1600 int rc;
1601
1602 if (!hwp_active)
1603 return;
1604
1605 rc = sysfs_create_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1606 WARN_ON_ONCE(rc);
1607 }
1608
intel_pstate_sysfs_hide_hwp_dynamic_boost(void)1609 static void intel_pstate_sysfs_hide_hwp_dynamic_boost(void)
1610 {
1611 if (!hwp_active)
1612 return;
1613
1614 sysfs_remove_file(intel_pstate_kobject, &hwp_dynamic_boost.attr);
1615 }
1616
1617 /************************** sysfs end ************************/
1618
intel_pstate_notify_work(struct work_struct * work)1619 static void intel_pstate_notify_work(struct work_struct *work)
1620 {
1621 struct cpudata *cpudata =
1622 container_of(to_delayed_work(work), struct cpudata, hwp_notify_work);
1623 struct cpufreq_policy *policy = cpufreq_cpu_acquire(cpudata->cpu);
1624
1625 if (policy) {
1626 intel_pstate_get_hwp_cap(cpudata);
1627 __intel_pstate_update_max_freq(cpudata, policy);
1628
1629 cpufreq_cpu_release(policy);
1630 }
1631
1632 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1633 }
1634
1635 static DEFINE_RAW_SPINLOCK(hwp_notify_lock);
1636 static cpumask_t hwp_intr_enable_mask;
1637
notify_hwp_interrupt(void)1638 void notify_hwp_interrupt(void)
1639 {
1640 unsigned int this_cpu = smp_processor_id();
1641 struct cpudata *cpudata;
1642 unsigned long flags;
1643 u64 value;
1644
1645 if (!READ_ONCE(hwp_active) || !boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1646 return;
1647
1648 rdmsrl_safe(MSR_HWP_STATUS, &value);
1649 if (!(value & 0x01))
1650 return;
1651
1652 raw_spin_lock_irqsave(&hwp_notify_lock, flags);
1653
1654 if (!cpumask_test_cpu(this_cpu, &hwp_intr_enable_mask))
1655 goto ack_intr;
1656
1657 /*
1658 * Currently we never free all_cpu_data. And we can't reach here
1659 * without this allocated. But for safety for future changes, added
1660 * check.
1661 */
1662 if (unlikely(!READ_ONCE(all_cpu_data)))
1663 goto ack_intr;
1664
1665 /*
1666 * The free is done during cleanup, when cpufreq registry is failed.
1667 * We wouldn't be here if it fails on init or switch status. But for
1668 * future changes, added check.
1669 */
1670 cpudata = READ_ONCE(all_cpu_data[this_cpu]);
1671 if (unlikely(!cpudata))
1672 goto ack_intr;
1673
1674 schedule_delayed_work(&cpudata->hwp_notify_work, msecs_to_jiffies(10));
1675
1676 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags);
1677
1678 return;
1679
1680 ack_intr:
1681 wrmsrl_safe(MSR_HWP_STATUS, 0);
1682 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags);
1683 }
1684
intel_pstate_disable_hwp_interrupt(struct cpudata * cpudata)1685 static void intel_pstate_disable_hwp_interrupt(struct cpudata *cpudata)
1686 {
1687 unsigned long flags;
1688
1689 if (!boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1690 return;
1691
1692 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1693 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1694
1695 raw_spin_lock_irqsave(&hwp_notify_lock, flags);
1696 if (cpumask_test_and_clear_cpu(cpudata->cpu, &hwp_intr_enable_mask))
1697 cancel_delayed_work(&cpudata->hwp_notify_work);
1698 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags);
1699 }
1700
intel_pstate_enable_hwp_interrupt(struct cpudata * cpudata)1701 static void intel_pstate_enable_hwp_interrupt(struct cpudata *cpudata)
1702 {
1703 /* Enable HWP notification interrupt for guaranteed performance change */
1704 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY)) {
1705 unsigned long flags;
1706
1707 raw_spin_lock_irqsave(&hwp_notify_lock, flags);
1708 INIT_DELAYED_WORK(&cpudata->hwp_notify_work, intel_pstate_notify_work);
1709 cpumask_set_cpu(cpudata->cpu, &hwp_intr_enable_mask);
1710 raw_spin_unlock_irqrestore(&hwp_notify_lock, flags);
1711
1712 /* wrmsrl_on_cpu has to be outside spinlock as this can result in IPC */
1713 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x01);
1714 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_STATUS, 0);
1715 }
1716 }
1717
intel_pstate_update_epp_defaults(struct cpudata * cpudata)1718 static void intel_pstate_update_epp_defaults(struct cpudata *cpudata)
1719 {
1720 cpudata->epp_default = intel_pstate_get_epp(cpudata, 0);
1721
1722 /*
1723 * If this CPU gen doesn't call for change in balance_perf
1724 * EPP return.
1725 */
1726 if (epp_values[EPP_INDEX_BALANCE_PERFORMANCE] == HWP_EPP_BALANCE_PERFORMANCE)
1727 return;
1728
1729 /*
1730 * If the EPP is set by firmware, which means that firmware enabled HWP
1731 * - Is equal or less than 0x80 (default balance_perf EPP)
1732 * - But less performance oriented than performance EPP
1733 * then use this as new balance_perf EPP.
1734 */
1735 if (hwp_forced && cpudata->epp_default <= HWP_EPP_BALANCE_PERFORMANCE &&
1736 cpudata->epp_default > HWP_EPP_PERFORMANCE) {
1737 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = cpudata->epp_default;
1738 return;
1739 }
1740
1741 /*
1742 * Use hard coded value per gen to update the balance_perf
1743 * and default EPP.
1744 */
1745 cpudata->epp_default = epp_values[EPP_INDEX_BALANCE_PERFORMANCE];
1746 intel_pstate_set_epp(cpudata, cpudata->epp_default);
1747 }
1748
intel_pstate_hwp_enable(struct cpudata * cpudata)1749 static void intel_pstate_hwp_enable(struct cpudata *cpudata)
1750 {
1751 /* First disable HWP notification interrupt till we activate again */
1752 if (boot_cpu_has(X86_FEATURE_HWP_NOTIFY))
1753 wrmsrl_on_cpu(cpudata->cpu, MSR_HWP_INTERRUPT, 0x00);
1754
1755 wrmsrl_on_cpu(cpudata->cpu, MSR_PM_ENABLE, 0x1);
1756
1757 intel_pstate_enable_hwp_interrupt(cpudata);
1758
1759 if (cpudata->epp_default >= 0)
1760 return;
1761
1762 intel_pstate_update_epp_defaults(cpudata);
1763 }
1764
atom_get_min_pstate(int not_used)1765 static int atom_get_min_pstate(int not_used)
1766 {
1767 u64 value;
1768
1769 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1770 return (value >> 8) & 0x7F;
1771 }
1772
atom_get_max_pstate(int not_used)1773 static int atom_get_max_pstate(int not_used)
1774 {
1775 u64 value;
1776
1777 rdmsrl(MSR_ATOM_CORE_RATIOS, value);
1778 return (value >> 16) & 0x7F;
1779 }
1780
atom_get_turbo_pstate(int not_used)1781 static int atom_get_turbo_pstate(int not_used)
1782 {
1783 u64 value;
1784
1785 rdmsrl(MSR_ATOM_CORE_TURBO_RATIOS, value);
1786 return value & 0x7F;
1787 }
1788
atom_get_val(struct cpudata * cpudata,int pstate)1789 static u64 atom_get_val(struct cpudata *cpudata, int pstate)
1790 {
1791 u64 val;
1792 int32_t vid_fp;
1793 u32 vid;
1794
1795 val = (u64)pstate << 8;
1796 if (global.no_turbo && !global.turbo_disabled)
1797 val |= (u64)1 << 32;
1798
1799 vid_fp = cpudata->vid.min + mul_fp(
1800 int_tofp(pstate - cpudata->pstate.min_pstate),
1801 cpudata->vid.ratio);
1802
1803 vid_fp = clamp_t(int32_t, vid_fp, cpudata->vid.min, cpudata->vid.max);
1804 vid = ceiling_fp(vid_fp);
1805
1806 if (pstate > cpudata->pstate.max_pstate)
1807 vid = cpudata->vid.turbo;
1808
1809 return val | vid;
1810 }
1811
silvermont_get_scaling(void)1812 static int silvermont_get_scaling(void)
1813 {
1814 u64 value;
1815 int i;
1816 /* Defined in Table 35-6 from SDM (Sept 2015) */
1817 static int silvermont_freq_table[] = {
1818 83300, 100000, 133300, 116700, 80000};
1819
1820 rdmsrl(MSR_FSB_FREQ, value);
1821 i = value & 0x7;
1822 WARN_ON(i > 4);
1823
1824 return silvermont_freq_table[i];
1825 }
1826
airmont_get_scaling(void)1827 static int airmont_get_scaling(void)
1828 {
1829 u64 value;
1830 int i;
1831 /* Defined in Table 35-10 from SDM (Sept 2015) */
1832 static int airmont_freq_table[] = {
1833 83300, 100000, 133300, 116700, 80000,
1834 93300, 90000, 88900, 87500};
1835
1836 rdmsrl(MSR_FSB_FREQ, value);
1837 i = value & 0xF;
1838 WARN_ON(i > 8);
1839
1840 return airmont_freq_table[i];
1841 }
1842
atom_get_vid(struct cpudata * cpudata)1843 static void atom_get_vid(struct cpudata *cpudata)
1844 {
1845 u64 value;
1846
1847 rdmsrl(MSR_ATOM_CORE_VIDS, value);
1848 cpudata->vid.min = int_tofp((value >> 8) & 0x7f);
1849 cpudata->vid.max = int_tofp((value >> 16) & 0x7f);
1850 cpudata->vid.ratio = div_fp(
1851 cpudata->vid.max - cpudata->vid.min,
1852 int_tofp(cpudata->pstate.max_pstate -
1853 cpudata->pstate.min_pstate));
1854
1855 rdmsrl(MSR_ATOM_CORE_TURBO_VIDS, value);
1856 cpudata->vid.turbo = value & 0x7f;
1857 }
1858
core_get_min_pstate(int cpu)1859 static int core_get_min_pstate(int cpu)
1860 {
1861 u64 value;
1862
1863 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1864 return (value >> 40) & 0xFF;
1865 }
1866
core_get_max_pstate_physical(int cpu)1867 static int core_get_max_pstate_physical(int cpu)
1868 {
1869 u64 value;
1870
1871 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &value);
1872 return (value >> 8) & 0xFF;
1873 }
1874
core_get_tdp_ratio(int cpu,u64 plat_info)1875 static int core_get_tdp_ratio(int cpu, u64 plat_info)
1876 {
1877 /* Check how many TDP levels present */
1878 if (plat_info & 0x600000000) {
1879 u64 tdp_ctrl;
1880 u64 tdp_ratio;
1881 int tdp_msr;
1882 int err;
1883
1884 /* Get the TDP level (0, 1, 2) to get ratios */
1885 err = rdmsrl_safe_on_cpu(cpu, MSR_CONFIG_TDP_CONTROL, &tdp_ctrl);
1886 if (err)
1887 return err;
1888
1889 /* TDP MSR are continuous starting at 0x648 */
1890 tdp_msr = MSR_CONFIG_TDP_NOMINAL + (tdp_ctrl & 0x03);
1891 err = rdmsrl_safe_on_cpu(cpu, tdp_msr, &tdp_ratio);
1892 if (err)
1893 return err;
1894
1895 /* For level 1 and 2, bits[23:16] contain the ratio */
1896 if (tdp_ctrl & 0x03)
1897 tdp_ratio >>= 16;
1898
1899 tdp_ratio &= 0xff; /* ratios are only 8 bits long */
1900 pr_debug("tdp_ratio %x\n", (int)tdp_ratio);
1901
1902 return (int)tdp_ratio;
1903 }
1904
1905 return -ENXIO;
1906 }
1907
core_get_max_pstate(int cpu)1908 static int core_get_max_pstate(int cpu)
1909 {
1910 u64 tar;
1911 u64 plat_info;
1912 int max_pstate;
1913 int tdp_ratio;
1914 int err;
1915
1916 rdmsrl_on_cpu(cpu, MSR_PLATFORM_INFO, &plat_info);
1917 max_pstate = (plat_info >> 8) & 0xFF;
1918
1919 tdp_ratio = core_get_tdp_ratio(cpu, plat_info);
1920 if (tdp_ratio <= 0)
1921 return max_pstate;
1922
1923 if (hwp_active) {
1924 /* Turbo activation ratio is not used on HWP platforms */
1925 return tdp_ratio;
1926 }
1927
1928 err = rdmsrl_safe_on_cpu(cpu, MSR_TURBO_ACTIVATION_RATIO, &tar);
1929 if (!err) {
1930 int tar_levels;
1931
1932 /* Do some sanity checking for safety */
1933 tar_levels = tar & 0xff;
1934 if (tdp_ratio - 1 == tar_levels) {
1935 max_pstate = tar_levels;
1936 pr_debug("max_pstate=TAC %x\n", max_pstate);
1937 }
1938 }
1939
1940 return max_pstate;
1941 }
1942
core_get_turbo_pstate(int cpu)1943 static int core_get_turbo_pstate(int cpu)
1944 {
1945 u64 value;
1946 int nont, ret;
1947
1948 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1949 nont = core_get_max_pstate(cpu);
1950 ret = (value) & 255;
1951 if (ret <= nont)
1952 ret = nont;
1953 return ret;
1954 }
1955
core_get_val(struct cpudata * cpudata,int pstate)1956 static u64 core_get_val(struct cpudata *cpudata, int pstate)
1957 {
1958 u64 val;
1959
1960 val = (u64)pstate << 8;
1961 if (global.no_turbo && !global.turbo_disabled)
1962 val |= (u64)1 << 32;
1963
1964 return val;
1965 }
1966
knl_get_aperf_mperf_shift(void)1967 static int knl_get_aperf_mperf_shift(void)
1968 {
1969 return 10;
1970 }
1971
knl_get_turbo_pstate(int cpu)1972 static int knl_get_turbo_pstate(int cpu)
1973 {
1974 u64 value;
1975 int nont, ret;
1976
1977 rdmsrl_on_cpu(cpu, MSR_TURBO_RATIO_LIMIT, &value);
1978 nont = core_get_max_pstate(cpu);
1979 ret = (((value) >> 8) & 0xFF);
1980 if (ret <= nont)
1981 ret = nont;
1982 return ret;
1983 }
1984
hybrid_get_type(void * data)1985 static void hybrid_get_type(void *data)
1986 {
1987 u8 *cpu_type = data;
1988
1989 *cpu_type = get_this_hybrid_cpu_type();
1990 }
1991
hwp_get_cpu_scaling(int cpu)1992 static int hwp_get_cpu_scaling(int cpu)
1993 {
1994 u8 cpu_type = 0;
1995
1996 smp_call_function_single(cpu, hybrid_get_type, &cpu_type, 1);
1997 /* P-cores have a smaller perf level-to-freqency scaling factor. */
1998 if (cpu_type == 0x40)
1999 return HYBRID_SCALING_FACTOR;
2000
2001 /* Use default core scaling for E-cores */
2002 if (cpu_type == 0x20)
2003 return core_get_scaling();
2004
2005 /*
2006 * If reached here, this system is either non-hybrid (like Tiger
2007 * Lake) or hybrid-capable (like Alder Lake or Raptor Lake) with
2008 * no E cores (in which case CPUID for hybrid support is 0).
2009 *
2010 * The CPPC nominal_frequency field is 0 for non-hybrid systems,
2011 * so the default core scaling will be used for them.
2012 */
2013 return intel_pstate_cppc_get_scaling(cpu);
2014 }
2015
intel_pstate_set_pstate(struct cpudata * cpu,int pstate)2016 static void intel_pstate_set_pstate(struct cpudata *cpu, int pstate)
2017 {
2018 trace_cpu_frequency(pstate * cpu->pstate.scaling, cpu->cpu);
2019 cpu->pstate.current_pstate = pstate;
2020 /*
2021 * Generally, there is no guarantee that this code will always run on
2022 * the CPU being updated, so force the register update to run on the
2023 * right CPU.
2024 */
2025 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2026 pstate_funcs.get_val(cpu, pstate));
2027 }
2028
intel_pstate_set_min_pstate(struct cpudata * cpu)2029 static void intel_pstate_set_min_pstate(struct cpudata *cpu)
2030 {
2031 intel_pstate_set_pstate(cpu, cpu->pstate.min_pstate);
2032 }
2033
intel_pstate_max_within_limits(struct cpudata * cpu)2034 static void intel_pstate_max_within_limits(struct cpudata *cpu)
2035 {
2036 int pstate = max(cpu->pstate.min_pstate, cpu->max_perf_ratio);
2037
2038 update_turbo_state();
2039 intel_pstate_set_pstate(cpu, pstate);
2040 }
2041
intel_pstate_get_cpu_pstates(struct cpudata * cpu)2042 static void intel_pstate_get_cpu_pstates(struct cpudata *cpu)
2043 {
2044 int perf_ctl_max_phys = pstate_funcs.get_max_physical(cpu->cpu);
2045 int perf_ctl_scaling = pstate_funcs.get_scaling();
2046
2047 cpu->pstate.min_pstate = pstate_funcs.get_min(cpu->cpu);
2048 cpu->pstate.max_pstate_physical = perf_ctl_max_phys;
2049 cpu->pstate.perf_ctl_scaling = perf_ctl_scaling;
2050
2051 if (hwp_active && !hwp_mode_bdw) {
2052 __intel_pstate_get_hwp_cap(cpu);
2053
2054 if (pstate_funcs.get_cpu_scaling) {
2055 cpu->pstate.scaling = pstate_funcs.get_cpu_scaling(cpu->cpu);
2056 if (cpu->pstate.scaling != perf_ctl_scaling)
2057 intel_pstate_hybrid_hwp_adjust(cpu);
2058 } else {
2059 cpu->pstate.scaling = perf_ctl_scaling;
2060 }
2061 } else {
2062 cpu->pstate.scaling = perf_ctl_scaling;
2063 cpu->pstate.max_pstate = pstate_funcs.get_max(cpu->cpu);
2064 cpu->pstate.turbo_pstate = pstate_funcs.get_turbo(cpu->cpu);
2065 }
2066
2067 if (cpu->pstate.scaling == perf_ctl_scaling) {
2068 cpu->pstate.min_freq = cpu->pstate.min_pstate * perf_ctl_scaling;
2069 cpu->pstate.max_freq = cpu->pstate.max_pstate * perf_ctl_scaling;
2070 cpu->pstate.turbo_freq = cpu->pstate.turbo_pstate * perf_ctl_scaling;
2071 }
2072
2073 if (pstate_funcs.get_aperf_mperf_shift)
2074 cpu->aperf_mperf_shift = pstate_funcs.get_aperf_mperf_shift();
2075
2076 if (pstate_funcs.get_vid)
2077 pstate_funcs.get_vid(cpu);
2078
2079 intel_pstate_set_min_pstate(cpu);
2080 }
2081
2082 /*
2083 * Long hold time will keep high perf limits for long time,
2084 * which negatively impacts perf/watt for some workloads,
2085 * like specpower. 3ms is based on experiements on some
2086 * workoads.
2087 */
2088 static int hwp_boost_hold_time_ns = 3 * NSEC_PER_MSEC;
2089
intel_pstate_hwp_boost_up(struct cpudata * cpu)2090 static inline void intel_pstate_hwp_boost_up(struct cpudata *cpu)
2091 {
2092 u64 hwp_req = READ_ONCE(cpu->hwp_req_cached);
2093 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2094 u32 max_limit = (hwp_req & 0xff00) >> 8;
2095 u32 min_limit = (hwp_req & 0xff);
2096 u32 boost_level1;
2097
2098 /*
2099 * Cases to consider (User changes via sysfs or boot time):
2100 * If, P0 (Turbo max) = P1 (Guaranteed max) = min:
2101 * No boost, return.
2102 * If, P0 (Turbo max) > P1 (Guaranteed max) = min:
2103 * Should result in one level boost only for P0.
2104 * If, P0 (Turbo max) = P1 (Guaranteed max) > min:
2105 * Should result in two level boost:
2106 * (min + p1)/2 and P1.
2107 * If, P0 (Turbo max) > P1 (Guaranteed max) > min:
2108 * Should result in three level boost:
2109 * (min + p1)/2, P1 and P0.
2110 */
2111
2112 /* If max and min are equal or already at max, nothing to boost */
2113 if (max_limit == min_limit || cpu->hwp_boost_min >= max_limit)
2114 return;
2115
2116 if (!cpu->hwp_boost_min)
2117 cpu->hwp_boost_min = min_limit;
2118
2119 /* level at half way mark between min and guranteed */
2120 boost_level1 = (HWP_GUARANTEED_PERF(hwp_cap) + min_limit) >> 1;
2121
2122 if (cpu->hwp_boost_min < boost_level1)
2123 cpu->hwp_boost_min = boost_level1;
2124 else if (cpu->hwp_boost_min < HWP_GUARANTEED_PERF(hwp_cap))
2125 cpu->hwp_boost_min = HWP_GUARANTEED_PERF(hwp_cap);
2126 else if (cpu->hwp_boost_min == HWP_GUARANTEED_PERF(hwp_cap) &&
2127 max_limit != HWP_GUARANTEED_PERF(hwp_cap))
2128 cpu->hwp_boost_min = max_limit;
2129 else
2130 return;
2131
2132 hwp_req = (hwp_req & ~GENMASK_ULL(7, 0)) | cpu->hwp_boost_min;
2133 wrmsrl(MSR_HWP_REQUEST, hwp_req);
2134 cpu->last_update = cpu->sample.time;
2135 }
2136
intel_pstate_hwp_boost_down(struct cpudata * cpu)2137 static inline void intel_pstate_hwp_boost_down(struct cpudata *cpu)
2138 {
2139 if (cpu->hwp_boost_min) {
2140 bool expired;
2141
2142 /* Check if we are idle for hold time to boost down */
2143 expired = time_after64(cpu->sample.time, cpu->last_update +
2144 hwp_boost_hold_time_ns);
2145 if (expired) {
2146 wrmsrl(MSR_HWP_REQUEST, cpu->hwp_req_cached);
2147 cpu->hwp_boost_min = 0;
2148 }
2149 }
2150 cpu->last_update = cpu->sample.time;
2151 }
2152
intel_pstate_update_util_hwp_local(struct cpudata * cpu,u64 time)2153 static inline void intel_pstate_update_util_hwp_local(struct cpudata *cpu,
2154 u64 time)
2155 {
2156 cpu->sample.time = time;
2157
2158 if (cpu->sched_flags & SCHED_CPUFREQ_IOWAIT) {
2159 bool do_io = false;
2160
2161 cpu->sched_flags = 0;
2162 /*
2163 * Set iowait_boost flag and update time. Since IO WAIT flag
2164 * is set all the time, we can't just conclude that there is
2165 * some IO bound activity is scheduled on this CPU with just
2166 * one occurrence. If we receive at least two in two
2167 * consecutive ticks, then we treat as boost candidate.
2168 */
2169 if (time_before64(time, cpu->last_io_update + 2 * TICK_NSEC))
2170 do_io = true;
2171
2172 cpu->last_io_update = time;
2173
2174 if (do_io)
2175 intel_pstate_hwp_boost_up(cpu);
2176
2177 } else {
2178 intel_pstate_hwp_boost_down(cpu);
2179 }
2180 }
2181
intel_pstate_update_util_hwp(struct update_util_data * data,u64 time,unsigned int flags)2182 static inline void intel_pstate_update_util_hwp(struct update_util_data *data,
2183 u64 time, unsigned int flags)
2184 {
2185 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2186
2187 cpu->sched_flags |= flags;
2188
2189 if (smp_processor_id() == cpu->cpu)
2190 intel_pstate_update_util_hwp_local(cpu, time);
2191 }
2192
intel_pstate_calc_avg_perf(struct cpudata * cpu)2193 static inline void intel_pstate_calc_avg_perf(struct cpudata *cpu)
2194 {
2195 struct sample *sample = &cpu->sample;
2196
2197 sample->core_avg_perf = div_ext_fp(sample->aperf, sample->mperf);
2198 }
2199
intel_pstate_sample(struct cpudata * cpu,u64 time)2200 static inline bool intel_pstate_sample(struct cpudata *cpu, u64 time)
2201 {
2202 u64 aperf, mperf;
2203 unsigned long flags;
2204 u64 tsc;
2205
2206 local_irq_save(flags);
2207 rdmsrl(MSR_IA32_APERF, aperf);
2208 rdmsrl(MSR_IA32_MPERF, mperf);
2209 tsc = rdtsc();
2210 if (cpu->prev_mperf == mperf || cpu->prev_tsc == tsc) {
2211 local_irq_restore(flags);
2212 return false;
2213 }
2214 local_irq_restore(flags);
2215
2216 cpu->last_sample_time = cpu->sample.time;
2217 cpu->sample.time = time;
2218 cpu->sample.aperf = aperf;
2219 cpu->sample.mperf = mperf;
2220 cpu->sample.tsc = tsc;
2221 cpu->sample.aperf -= cpu->prev_aperf;
2222 cpu->sample.mperf -= cpu->prev_mperf;
2223 cpu->sample.tsc -= cpu->prev_tsc;
2224
2225 cpu->prev_aperf = aperf;
2226 cpu->prev_mperf = mperf;
2227 cpu->prev_tsc = tsc;
2228 /*
2229 * First time this function is invoked in a given cycle, all of the
2230 * previous sample data fields are equal to zero or stale and they must
2231 * be populated with meaningful numbers for things to work, so assume
2232 * that sample.time will always be reset before setting the utilization
2233 * update hook and make the caller skip the sample then.
2234 */
2235 if (cpu->last_sample_time) {
2236 intel_pstate_calc_avg_perf(cpu);
2237 return true;
2238 }
2239 return false;
2240 }
2241
get_avg_frequency(struct cpudata * cpu)2242 static inline int32_t get_avg_frequency(struct cpudata *cpu)
2243 {
2244 return mul_ext_fp(cpu->sample.core_avg_perf, cpu_khz);
2245 }
2246
get_avg_pstate(struct cpudata * cpu)2247 static inline int32_t get_avg_pstate(struct cpudata *cpu)
2248 {
2249 return mul_ext_fp(cpu->pstate.max_pstate_physical,
2250 cpu->sample.core_avg_perf);
2251 }
2252
get_target_pstate(struct cpudata * cpu)2253 static inline int32_t get_target_pstate(struct cpudata *cpu)
2254 {
2255 struct sample *sample = &cpu->sample;
2256 int32_t busy_frac;
2257 int target, avg_pstate;
2258
2259 busy_frac = div_fp(sample->mperf << cpu->aperf_mperf_shift,
2260 sample->tsc);
2261
2262 if (busy_frac < cpu->iowait_boost)
2263 busy_frac = cpu->iowait_boost;
2264
2265 sample->busy_scaled = busy_frac * 100;
2266
2267 target = global.no_turbo || global.turbo_disabled ?
2268 cpu->pstate.max_pstate : cpu->pstate.turbo_pstate;
2269 target += target >> 2;
2270 target = mul_fp(target, busy_frac);
2271 if (target < cpu->pstate.min_pstate)
2272 target = cpu->pstate.min_pstate;
2273
2274 /*
2275 * If the average P-state during the previous cycle was higher than the
2276 * current target, add 50% of the difference to the target to reduce
2277 * possible performance oscillations and offset possible performance
2278 * loss related to moving the workload from one CPU to another within
2279 * a package/module.
2280 */
2281 avg_pstate = get_avg_pstate(cpu);
2282 if (avg_pstate > target)
2283 target += (avg_pstate - target) >> 1;
2284
2285 return target;
2286 }
2287
intel_pstate_prepare_request(struct cpudata * cpu,int pstate)2288 static int intel_pstate_prepare_request(struct cpudata *cpu, int pstate)
2289 {
2290 int min_pstate = max(cpu->pstate.min_pstate, cpu->min_perf_ratio);
2291 int max_pstate = max(min_pstate, cpu->max_perf_ratio);
2292
2293 return clamp_t(int, pstate, min_pstate, max_pstate);
2294 }
2295
intel_pstate_update_pstate(struct cpudata * cpu,int pstate)2296 static void intel_pstate_update_pstate(struct cpudata *cpu, int pstate)
2297 {
2298 if (pstate == cpu->pstate.current_pstate)
2299 return;
2300
2301 cpu->pstate.current_pstate = pstate;
2302 wrmsrl(MSR_IA32_PERF_CTL, pstate_funcs.get_val(cpu, pstate));
2303 }
2304
intel_pstate_adjust_pstate(struct cpudata * cpu)2305 static void intel_pstate_adjust_pstate(struct cpudata *cpu)
2306 {
2307 int from = cpu->pstate.current_pstate;
2308 struct sample *sample;
2309 int target_pstate;
2310
2311 update_turbo_state();
2312
2313 target_pstate = get_target_pstate(cpu);
2314 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2315 trace_cpu_frequency(target_pstate * cpu->pstate.scaling, cpu->cpu);
2316 intel_pstate_update_pstate(cpu, target_pstate);
2317
2318 sample = &cpu->sample;
2319 trace_pstate_sample(mul_ext_fp(100, sample->core_avg_perf),
2320 fp_toint(sample->busy_scaled),
2321 from,
2322 cpu->pstate.current_pstate,
2323 sample->mperf,
2324 sample->aperf,
2325 sample->tsc,
2326 get_avg_frequency(cpu),
2327 fp_toint(cpu->iowait_boost * 100));
2328 }
2329
intel_pstate_update_util(struct update_util_data * data,u64 time,unsigned int flags)2330 static void intel_pstate_update_util(struct update_util_data *data, u64 time,
2331 unsigned int flags)
2332 {
2333 struct cpudata *cpu = container_of(data, struct cpudata, update_util);
2334 u64 delta_ns;
2335
2336 /* Don't allow remote callbacks */
2337 if (smp_processor_id() != cpu->cpu)
2338 return;
2339
2340 delta_ns = time - cpu->last_update;
2341 if (flags & SCHED_CPUFREQ_IOWAIT) {
2342 /* Start over if the CPU may have been idle. */
2343 if (delta_ns > TICK_NSEC) {
2344 cpu->iowait_boost = ONE_EIGHTH_FP;
2345 } else if (cpu->iowait_boost >= ONE_EIGHTH_FP) {
2346 cpu->iowait_boost <<= 1;
2347 if (cpu->iowait_boost > int_tofp(1))
2348 cpu->iowait_boost = int_tofp(1);
2349 } else {
2350 cpu->iowait_boost = ONE_EIGHTH_FP;
2351 }
2352 } else if (cpu->iowait_boost) {
2353 /* Clear iowait_boost if the CPU may have been idle. */
2354 if (delta_ns > TICK_NSEC)
2355 cpu->iowait_boost = 0;
2356 else
2357 cpu->iowait_boost >>= 1;
2358 }
2359 cpu->last_update = time;
2360 delta_ns = time - cpu->sample.time;
2361 if ((s64)delta_ns < INTEL_PSTATE_SAMPLING_INTERVAL)
2362 return;
2363
2364 if (intel_pstate_sample(cpu, time))
2365 intel_pstate_adjust_pstate(cpu);
2366 }
2367
2368 static struct pstate_funcs core_funcs = {
2369 .get_max = core_get_max_pstate,
2370 .get_max_physical = core_get_max_pstate_physical,
2371 .get_min = core_get_min_pstate,
2372 .get_turbo = core_get_turbo_pstate,
2373 .get_scaling = core_get_scaling,
2374 .get_val = core_get_val,
2375 };
2376
2377 static const struct pstate_funcs silvermont_funcs = {
2378 .get_max = atom_get_max_pstate,
2379 .get_max_physical = atom_get_max_pstate,
2380 .get_min = atom_get_min_pstate,
2381 .get_turbo = atom_get_turbo_pstate,
2382 .get_val = atom_get_val,
2383 .get_scaling = silvermont_get_scaling,
2384 .get_vid = atom_get_vid,
2385 };
2386
2387 static const struct pstate_funcs airmont_funcs = {
2388 .get_max = atom_get_max_pstate,
2389 .get_max_physical = atom_get_max_pstate,
2390 .get_min = atom_get_min_pstate,
2391 .get_turbo = atom_get_turbo_pstate,
2392 .get_val = atom_get_val,
2393 .get_scaling = airmont_get_scaling,
2394 .get_vid = atom_get_vid,
2395 };
2396
2397 static const struct pstate_funcs knl_funcs = {
2398 .get_max = core_get_max_pstate,
2399 .get_max_physical = core_get_max_pstate_physical,
2400 .get_min = core_get_min_pstate,
2401 .get_turbo = knl_get_turbo_pstate,
2402 .get_aperf_mperf_shift = knl_get_aperf_mperf_shift,
2403 .get_scaling = core_get_scaling,
2404 .get_val = core_get_val,
2405 };
2406
2407 #define X86_MATCH(model, policy) \
2408 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
2409 X86_FEATURE_APERFMPERF, &policy)
2410
2411 static const struct x86_cpu_id intel_pstate_cpu_ids[] = {
2412 X86_MATCH(SANDYBRIDGE, core_funcs),
2413 X86_MATCH(SANDYBRIDGE_X, core_funcs),
2414 X86_MATCH(ATOM_SILVERMONT, silvermont_funcs),
2415 X86_MATCH(IVYBRIDGE, core_funcs),
2416 X86_MATCH(HASWELL, core_funcs),
2417 X86_MATCH(BROADWELL, core_funcs),
2418 X86_MATCH(IVYBRIDGE_X, core_funcs),
2419 X86_MATCH(HASWELL_X, core_funcs),
2420 X86_MATCH(HASWELL_L, core_funcs),
2421 X86_MATCH(HASWELL_G, core_funcs),
2422 X86_MATCH(BROADWELL_G, core_funcs),
2423 X86_MATCH(ATOM_AIRMONT, airmont_funcs),
2424 X86_MATCH(SKYLAKE_L, core_funcs),
2425 X86_MATCH(BROADWELL_X, core_funcs),
2426 X86_MATCH(SKYLAKE, core_funcs),
2427 X86_MATCH(BROADWELL_D, core_funcs),
2428 X86_MATCH(XEON_PHI_KNL, knl_funcs),
2429 X86_MATCH(XEON_PHI_KNM, knl_funcs),
2430 X86_MATCH(ATOM_GOLDMONT, core_funcs),
2431 X86_MATCH(ATOM_GOLDMONT_PLUS, core_funcs),
2432 X86_MATCH(SKYLAKE_X, core_funcs),
2433 X86_MATCH(COMETLAKE, core_funcs),
2434 X86_MATCH(ICELAKE_X, core_funcs),
2435 X86_MATCH(TIGERLAKE, core_funcs),
2436 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs),
2437 {}
2438 };
2439 MODULE_DEVICE_TABLE(x86cpu, intel_pstate_cpu_ids);
2440
2441 static const struct x86_cpu_id intel_pstate_cpu_oob_ids[] __initconst = {
2442 X86_MATCH(BROADWELL_D, core_funcs),
2443 X86_MATCH(BROADWELL_X, core_funcs),
2444 X86_MATCH(SKYLAKE_X, core_funcs),
2445 X86_MATCH(ICELAKE_X, core_funcs),
2446 X86_MATCH(SAPPHIRERAPIDS_X, core_funcs),
2447 {}
2448 };
2449
2450 static const struct x86_cpu_id intel_pstate_cpu_ee_disable_ids[] = {
2451 X86_MATCH(KABYLAKE, core_funcs),
2452 {}
2453 };
2454
intel_pstate_init_cpu(unsigned int cpunum)2455 static int intel_pstate_init_cpu(unsigned int cpunum)
2456 {
2457 struct cpudata *cpu;
2458
2459 cpu = all_cpu_data[cpunum];
2460
2461 if (!cpu) {
2462 cpu = kzalloc(sizeof(*cpu), GFP_KERNEL);
2463 if (!cpu)
2464 return -ENOMEM;
2465
2466 WRITE_ONCE(all_cpu_data[cpunum], cpu);
2467
2468 cpu->cpu = cpunum;
2469
2470 cpu->epp_default = -EINVAL;
2471
2472 if (hwp_active) {
2473 intel_pstate_hwp_enable(cpu);
2474
2475 if (intel_pstate_acpi_pm_profile_server())
2476 hwp_boost = true;
2477 }
2478 } else if (hwp_active) {
2479 /*
2480 * Re-enable HWP in case this happens after a resume from ACPI
2481 * S3 if the CPU was offline during the whole system/resume
2482 * cycle.
2483 */
2484 intel_pstate_hwp_reenable(cpu);
2485 }
2486
2487 cpu->epp_powersave = -EINVAL;
2488 cpu->epp_policy = 0;
2489
2490 intel_pstate_get_cpu_pstates(cpu);
2491
2492 pr_debug("controlling: cpu %d\n", cpunum);
2493
2494 return 0;
2495 }
2496
intel_pstate_set_update_util_hook(unsigned int cpu_num)2497 static void intel_pstate_set_update_util_hook(unsigned int cpu_num)
2498 {
2499 struct cpudata *cpu = all_cpu_data[cpu_num];
2500
2501 if (hwp_active && !hwp_boost)
2502 return;
2503
2504 if (cpu->update_util_set)
2505 return;
2506
2507 /* Prevent intel_pstate_update_util() from using stale data. */
2508 cpu->sample.time = 0;
2509 cpufreq_add_update_util_hook(cpu_num, &cpu->update_util,
2510 (hwp_active ?
2511 intel_pstate_update_util_hwp :
2512 intel_pstate_update_util));
2513 cpu->update_util_set = true;
2514 }
2515
intel_pstate_clear_update_util_hook(unsigned int cpu)2516 static void intel_pstate_clear_update_util_hook(unsigned int cpu)
2517 {
2518 struct cpudata *cpu_data = all_cpu_data[cpu];
2519
2520 if (!cpu_data->update_util_set)
2521 return;
2522
2523 cpufreq_remove_update_util_hook(cpu);
2524 cpu_data->update_util_set = false;
2525 synchronize_rcu();
2526 }
2527
intel_pstate_get_max_freq(struct cpudata * cpu)2528 static int intel_pstate_get_max_freq(struct cpudata *cpu)
2529 {
2530 return global.turbo_disabled || global.no_turbo ?
2531 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2532 }
2533
intel_pstate_update_perf_limits(struct cpudata * cpu,unsigned int policy_min,unsigned int policy_max)2534 static void intel_pstate_update_perf_limits(struct cpudata *cpu,
2535 unsigned int policy_min,
2536 unsigned int policy_max)
2537 {
2538 int perf_ctl_scaling = cpu->pstate.perf_ctl_scaling;
2539 int32_t max_policy_perf, min_policy_perf;
2540
2541 max_policy_perf = policy_max / perf_ctl_scaling;
2542 if (policy_max == policy_min) {
2543 min_policy_perf = max_policy_perf;
2544 } else {
2545 min_policy_perf = policy_min / perf_ctl_scaling;
2546 min_policy_perf = clamp_t(int32_t, min_policy_perf,
2547 0, max_policy_perf);
2548 }
2549
2550 /*
2551 * HWP needs some special consideration, because HWP_REQUEST uses
2552 * abstract values to represent performance rather than pure ratios.
2553 */
2554 if (hwp_active && cpu->pstate.scaling != perf_ctl_scaling) {
2555 int freq;
2556
2557 freq = max_policy_perf * perf_ctl_scaling;
2558 max_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2559 freq = min_policy_perf * perf_ctl_scaling;
2560 min_policy_perf = intel_pstate_freq_to_hwp(cpu, freq);
2561 }
2562
2563 pr_debug("cpu:%d min_policy_perf:%d max_policy_perf:%d\n",
2564 cpu->cpu, min_policy_perf, max_policy_perf);
2565
2566 /* Normalize user input to [min_perf, max_perf] */
2567 if (per_cpu_limits) {
2568 cpu->min_perf_ratio = min_policy_perf;
2569 cpu->max_perf_ratio = max_policy_perf;
2570 } else {
2571 int turbo_max = cpu->pstate.turbo_pstate;
2572 int32_t global_min, global_max;
2573
2574 /* Global limits are in percent of the maximum turbo P-state. */
2575 global_max = DIV_ROUND_UP(turbo_max * global.max_perf_pct, 100);
2576 global_min = DIV_ROUND_UP(turbo_max * global.min_perf_pct, 100);
2577 global_min = clamp_t(int32_t, global_min, 0, global_max);
2578
2579 pr_debug("cpu:%d global_min:%d global_max:%d\n", cpu->cpu,
2580 global_min, global_max);
2581
2582 cpu->min_perf_ratio = max(min_policy_perf, global_min);
2583 cpu->min_perf_ratio = min(cpu->min_perf_ratio, max_policy_perf);
2584 cpu->max_perf_ratio = min(max_policy_perf, global_max);
2585 cpu->max_perf_ratio = max(min_policy_perf, cpu->max_perf_ratio);
2586
2587 /* Make sure min_perf <= max_perf */
2588 cpu->min_perf_ratio = min(cpu->min_perf_ratio,
2589 cpu->max_perf_ratio);
2590
2591 }
2592 pr_debug("cpu:%d max_perf_ratio:%d min_perf_ratio:%d\n", cpu->cpu,
2593 cpu->max_perf_ratio,
2594 cpu->min_perf_ratio);
2595 }
2596
intel_pstate_set_policy(struct cpufreq_policy * policy)2597 static int intel_pstate_set_policy(struct cpufreq_policy *policy)
2598 {
2599 struct cpudata *cpu;
2600
2601 if (!policy->cpuinfo.max_freq)
2602 return -ENODEV;
2603
2604 pr_debug("set_policy cpuinfo.max %u policy->max %u\n",
2605 policy->cpuinfo.max_freq, policy->max);
2606
2607 cpu = all_cpu_data[policy->cpu];
2608 cpu->policy = policy->policy;
2609
2610 mutex_lock(&intel_pstate_limits_lock);
2611
2612 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2613
2614 if (cpu->policy == CPUFREQ_POLICY_PERFORMANCE) {
2615 /*
2616 * NOHZ_FULL CPUs need this as the governor callback may not
2617 * be invoked on them.
2618 */
2619 intel_pstate_clear_update_util_hook(policy->cpu);
2620 intel_pstate_max_within_limits(cpu);
2621 } else {
2622 intel_pstate_set_update_util_hook(policy->cpu);
2623 }
2624
2625 if (hwp_active) {
2626 /*
2627 * When hwp_boost was active before and dynamically it
2628 * was turned off, in that case we need to clear the
2629 * update util hook.
2630 */
2631 if (!hwp_boost)
2632 intel_pstate_clear_update_util_hook(policy->cpu);
2633 intel_pstate_hwp_set(policy->cpu);
2634 }
2635 /*
2636 * policy->cur is never updated with the intel_pstate driver, but it
2637 * is used as a stale frequency value. So, keep it within limits.
2638 */
2639 policy->cur = policy->min;
2640
2641 mutex_unlock(&intel_pstate_limits_lock);
2642
2643 return 0;
2644 }
2645
intel_pstate_adjust_policy_max(struct cpudata * cpu,struct cpufreq_policy_data * policy)2646 static void intel_pstate_adjust_policy_max(struct cpudata *cpu,
2647 struct cpufreq_policy_data *policy)
2648 {
2649 if (!hwp_active &&
2650 cpu->pstate.max_pstate_physical > cpu->pstate.max_pstate &&
2651 policy->max < policy->cpuinfo.max_freq &&
2652 policy->max > cpu->pstate.max_freq) {
2653 pr_debug("policy->max > max non turbo frequency\n");
2654 policy->max = policy->cpuinfo.max_freq;
2655 }
2656 }
2657
intel_pstate_verify_cpu_policy(struct cpudata * cpu,struct cpufreq_policy_data * policy)2658 static void intel_pstate_verify_cpu_policy(struct cpudata *cpu,
2659 struct cpufreq_policy_data *policy)
2660 {
2661 int max_freq;
2662
2663 update_turbo_state();
2664 if (hwp_active) {
2665 intel_pstate_get_hwp_cap(cpu);
2666 max_freq = global.no_turbo || global.turbo_disabled ?
2667 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2668 } else {
2669 max_freq = intel_pstate_get_max_freq(cpu);
2670 }
2671 cpufreq_verify_within_limits(policy, policy->cpuinfo.min_freq, max_freq);
2672
2673 intel_pstate_adjust_policy_max(cpu, policy);
2674 }
2675
intel_pstate_verify_policy(struct cpufreq_policy_data * policy)2676 static int intel_pstate_verify_policy(struct cpufreq_policy_data *policy)
2677 {
2678 intel_pstate_verify_cpu_policy(all_cpu_data[policy->cpu], policy);
2679
2680 return 0;
2681 }
2682
intel_cpufreq_cpu_offline(struct cpufreq_policy * policy)2683 static int intel_cpufreq_cpu_offline(struct cpufreq_policy *policy)
2684 {
2685 struct cpudata *cpu = all_cpu_data[policy->cpu];
2686
2687 pr_debug("CPU %d going offline\n", cpu->cpu);
2688
2689 if (cpu->suspended)
2690 return 0;
2691
2692 /*
2693 * If the CPU is an SMT thread and it goes offline with the performance
2694 * settings different from the minimum, it will prevent its sibling
2695 * from getting to lower performance levels, so force the minimum
2696 * performance on CPU offline to prevent that from happening.
2697 */
2698 if (hwp_active)
2699 intel_pstate_hwp_offline(cpu);
2700 else
2701 intel_pstate_set_min_pstate(cpu);
2702
2703 intel_pstate_exit_perf_limits(policy);
2704
2705 return 0;
2706 }
2707
intel_pstate_cpu_online(struct cpufreq_policy * policy)2708 static int intel_pstate_cpu_online(struct cpufreq_policy *policy)
2709 {
2710 struct cpudata *cpu = all_cpu_data[policy->cpu];
2711
2712 pr_debug("CPU %d going online\n", cpu->cpu);
2713
2714 intel_pstate_init_acpi_perf_limits(policy);
2715
2716 if (hwp_active) {
2717 /*
2718 * Re-enable HWP and clear the "suspended" flag to let "resume"
2719 * know that it need not do that.
2720 */
2721 intel_pstate_hwp_reenable(cpu);
2722 cpu->suspended = false;
2723 }
2724
2725 return 0;
2726 }
2727
intel_pstate_cpu_offline(struct cpufreq_policy * policy)2728 static int intel_pstate_cpu_offline(struct cpufreq_policy *policy)
2729 {
2730 intel_pstate_clear_update_util_hook(policy->cpu);
2731
2732 return intel_cpufreq_cpu_offline(policy);
2733 }
2734
intel_pstate_cpu_exit(struct cpufreq_policy * policy)2735 static int intel_pstate_cpu_exit(struct cpufreq_policy *policy)
2736 {
2737 pr_debug("CPU %d exiting\n", policy->cpu);
2738
2739 policy->fast_switch_possible = false;
2740
2741 return 0;
2742 }
2743
__intel_pstate_cpu_init(struct cpufreq_policy * policy)2744 static int __intel_pstate_cpu_init(struct cpufreq_policy *policy)
2745 {
2746 struct cpudata *cpu;
2747 int rc;
2748
2749 rc = intel_pstate_init_cpu(policy->cpu);
2750 if (rc)
2751 return rc;
2752
2753 cpu = all_cpu_data[policy->cpu];
2754
2755 cpu->max_perf_ratio = 0xFF;
2756 cpu->min_perf_ratio = 0;
2757
2758 /* cpuinfo and default policy values */
2759 policy->cpuinfo.min_freq = cpu->pstate.min_freq;
2760 update_turbo_state();
2761 global.turbo_disabled_mf = global.turbo_disabled;
2762 policy->cpuinfo.max_freq = global.turbo_disabled ?
2763 cpu->pstate.max_freq : cpu->pstate.turbo_freq;
2764
2765 policy->min = policy->cpuinfo.min_freq;
2766 policy->max = policy->cpuinfo.max_freq;
2767
2768 intel_pstate_init_acpi_perf_limits(policy);
2769
2770 policy->fast_switch_possible = true;
2771
2772 return 0;
2773 }
2774
intel_pstate_cpu_init(struct cpufreq_policy * policy)2775 static int intel_pstate_cpu_init(struct cpufreq_policy *policy)
2776 {
2777 int ret = __intel_pstate_cpu_init(policy);
2778
2779 if (ret)
2780 return ret;
2781
2782 /*
2783 * Set the policy to powersave to provide a valid fallback value in case
2784 * the default cpufreq governor is neither powersave nor performance.
2785 */
2786 policy->policy = CPUFREQ_POLICY_POWERSAVE;
2787
2788 if (hwp_active) {
2789 struct cpudata *cpu = all_cpu_data[policy->cpu];
2790
2791 cpu->epp_cached = intel_pstate_get_epp(cpu, 0);
2792 }
2793
2794 return 0;
2795 }
2796
2797 static struct cpufreq_driver intel_pstate = {
2798 .flags = CPUFREQ_CONST_LOOPS,
2799 .verify = intel_pstate_verify_policy,
2800 .setpolicy = intel_pstate_set_policy,
2801 .suspend = intel_pstate_suspend,
2802 .resume = intel_pstate_resume,
2803 .init = intel_pstate_cpu_init,
2804 .exit = intel_pstate_cpu_exit,
2805 .offline = intel_pstate_cpu_offline,
2806 .online = intel_pstate_cpu_online,
2807 .update_limits = intel_pstate_update_limits,
2808 .name = "intel_pstate",
2809 };
2810
intel_cpufreq_verify_policy(struct cpufreq_policy_data * policy)2811 static int intel_cpufreq_verify_policy(struct cpufreq_policy_data *policy)
2812 {
2813 struct cpudata *cpu = all_cpu_data[policy->cpu];
2814
2815 intel_pstate_verify_cpu_policy(cpu, policy);
2816 intel_pstate_update_perf_limits(cpu, policy->min, policy->max);
2817
2818 return 0;
2819 }
2820
2821 /* Use of trace in passive mode:
2822 *
2823 * In passive mode the trace core_busy field (also known as the
2824 * performance field, and lablelled as such on the graphs; also known as
2825 * core_avg_perf) is not needed and so is re-assigned to indicate if the
2826 * driver call was via the normal or fast switch path. Various graphs
2827 * output from the intel_pstate_tracer.py utility that include core_busy
2828 * (or performance or core_avg_perf) have a fixed y-axis from 0 to 100%,
2829 * so we use 10 to indicate the normal path through the driver, and
2830 * 90 to indicate the fast switch path through the driver.
2831 * The scaled_busy field is not used, and is set to 0.
2832 */
2833
2834 #define INTEL_PSTATE_TRACE_TARGET 10
2835 #define INTEL_PSTATE_TRACE_FAST_SWITCH 90
2836
intel_cpufreq_trace(struct cpudata * cpu,unsigned int trace_type,int old_pstate)2837 static void intel_cpufreq_trace(struct cpudata *cpu, unsigned int trace_type, int old_pstate)
2838 {
2839 struct sample *sample;
2840
2841 if (!trace_pstate_sample_enabled())
2842 return;
2843
2844 if (!intel_pstate_sample(cpu, ktime_get()))
2845 return;
2846
2847 sample = &cpu->sample;
2848 trace_pstate_sample(trace_type,
2849 0,
2850 old_pstate,
2851 cpu->pstate.current_pstate,
2852 sample->mperf,
2853 sample->aperf,
2854 sample->tsc,
2855 get_avg_frequency(cpu),
2856 fp_toint(cpu->iowait_boost * 100));
2857 }
2858
intel_cpufreq_hwp_update(struct cpudata * cpu,u32 min,u32 max,u32 desired,bool fast_switch)2859 static void intel_cpufreq_hwp_update(struct cpudata *cpu, u32 min, u32 max,
2860 u32 desired, bool fast_switch)
2861 {
2862 u64 prev = READ_ONCE(cpu->hwp_req_cached), value = prev;
2863
2864 value &= ~HWP_MIN_PERF(~0L);
2865 value |= HWP_MIN_PERF(min);
2866
2867 value &= ~HWP_MAX_PERF(~0L);
2868 value |= HWP_MAX_PERF(max);
2869
2870 value &= ~HWP_DESIRED_PERF(~0L);
2871 value |= HWP_DESIRED_PERF(desired);
2872
2873 if (value == prev)
2874 return;
2875
2876 WRITE_ONCE(cpu->hwp_req_cached, value);
2877 if (fast_switch)
2878 wrmsrl(MSR_HWP_REQUEST, value);
2879 else
2880 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
2881 }
2882
intel_cpufreq_perf_ctl_update(struct cpudata * cpu,u32 target_pstate,bool fast_switch)2883 static void intel_cpufreq_perf_ctl_update(struct cpudata *cpu,
2884 u32 target_pstate, bool fast_switch)
2885 {
2886 if (fast_switch)
2887 wrmsrl(MSR_IA32_PERF_CTL,
2888 pstate_funcs.get_val(cpu, target_pstate));
2889 else
2890 wrmsrl_on_cpu(cpu->cpu, MSR_IA32_PERF_CTL,
2891 pstate_funcs.get_val(cpu, target_pstate));
2892 }
2893
intel_cpufreq_update_pstate(struct cpufreq_policy * policy,int target_pstate,bool fast_switch)2894 static int intel_cpufreq_update_pstate(struct cpufreq_policy *policy,
2895 int target_pstate, bool fast_switch)
2896 {
2897 struct cpudata *cpu = all_cpu_data[policy->cpu];
2898 int old_pstate = cpu->pstate.current_pstate;
2899
2900 target_pstate = intel_pstate_prepare_request(cpu, target_pstate);
2901 if (hwp_active) {
2902 int max_pstate = policy->strict_target ?
2903 target_pstate : cpu->max_perf_ratio;
2904
2905 intel_cpufreq_hwp_update(cpu, target_pstate, max_pstate, 0,
2906 fast_switch);
2907 } else if (target_pstate != old_pstate) {
2908 intel_cpufreq_perf_ctl_update(cpu, target_pstate, fast_switch);
2909 }
2910
2911 cpu->pstate.current_pstate = target_pstate;
2912
2913 intel_cpufreq_trace(cpu, fast_switch ? INTEL_PSTATE_TRACE_FAST_SWITCH :
2914 INTEL_PSTATE_TRACE_TARGET, old_pstate);
2915
2916 return target_pstate;
2917 }
2918
intel_cpufreq_target(struct cpufreq_policy * policy,unsigned int target_freq,unsigned int relation)2919 static int intel_cpufreq_target(struct cpufreq_policy *policy,
2920 unsigned int target_freq,
2921 unsigned int relation)
2922 {
2923 struct cpudata *cpu = all_cpu_data[policy->cpu];
2924 struct cpufreq_freqs freqs;
2925 int target_pstate;
2926
2927 update_turbo_state();
2928
2929 freqs.old = policy->cur;
2930 freqs.new = target_freq;
2931
2932 cpufreq_freq_transition_begin(policy, &freqs);
2933
2934 target_pstate = intel_pstate_freq_to_hwp_rel(cpu, freqs.new, relation);
2935 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, false);
2936
2937 freqs.new = target_pstate * cpu->pstate.scaling;
2938
2939 cpufreq_freq_transition_end(policy, &freqs, false);
2940
2941 return 0;
2942 }
2943
intel_cpufreq_fast_switch(struct cpufreq_policy * policy,unsigned int target_freq)2944 static unsigned int intel_cpufreq_fast_switch(struct cpufreq_policy *policy,
2945 unsigned int target_freq)
2946 {
2947 struct cpudata *cpu = all_cpu_data[policy->cpu];
2948 int target_pstate;
2949
2950 update_turbo_state();
2951
2952 target_pstate = intel_pstate_freq_to_hwp(cpu, target_freq);
2953
2954 target_pstate = intel_cpufreq_update_pstate(policy, target_pstate, true);
2955
2956 return target_pstate * cpu->pstate.scaling;
2957 }
2958
intel_cpufreq_adjust_perf(unsigned int cpunum,unsigned long min_perf,unsigned long target_perf,unsigned long capacity)2959 static void intel_cpufreq_adjust_perf(unsigned int cpunum,
2960 unsigned long min_perf,
2961 unsigned long target_perf,
2962 unsigned long capacity)
2963 {
2964 struct cpudata *cpu = all_cpu_data[cpunum];
2965 u64 hwp_cap = READ_ONCE(cpu->hwp_cap_cached);
2966 int old_pstate = cpu->pstate.current_pstate;
2967 int cap_pstate, min_pstate, max_pstate, target_pstate;
2968
2969 update_turbo_state();
2970 cap_pstate = global.turbo_disabled ? HWP_GUARANTEED_PERF(hwp_cap) :
2971 HWP_HIGHEST_PERF(hwp_cap);
2972
2973 /* Optimization: Avoid unnecessary divisions. */
2974
2975 target_pstate = cap_pstate;
2976 if (target_perf < capacity)
2977 target_pstate = DIV_ROUND_UP(cap_pstate * target_perf, capacity);
2978
2979 min_pstate = cap_pstate;
2980 if (min_perf < capacity)
2981 min_pstate = DIV_ROUND_UP(cap_pstate * min_perf, capacity);
2982
2983 if (min_pstate < cpu->pstate.min_pstate)
2984 min_pstate = cpu->pstate.min_pstate;
2985
2986 if (min_pstate < cpu->min_perf_ratio)
2987 min_pstate = cpu->min_perf_ratio;
2988
2989 if (min_pstate > cpu->max_perf_ratio)
2990 min_pstate = cpu->max_perf_ratio;
2991
2992 max_pstate = min(cap_pstate, cpu->max_perf_ratio);
2993 if (max_pstate < min_pstate)
2994 max_pstate = min_pstate;
2995
2996 target_pstate = clamp_t(int, target_pstate, min_pstate, max_pstate);
2997
2998 intel_cpufreq_hwp_update(cpu, min_pstate, max_pstate, target_pstate, true);
2999
3000 cpu->pstate.current_pstate = target_pstate;
3001 intel_cpufreq_trace(cpu, INTEL_PSTATE_TRACE_FAST_SWITCH, old_pstate);
3002 }
3003
intel_cpufreq_cpu_init(struct cpufreq_policy * policy)3004 static int intel_cpufreq_cpu_init(struct cpufreq_policy *policy)
3005 {
3006 struct freq_qos_request *req;
3007 struct cpudata *cpu;
3008 struct device *dev;
3009 int ret, freq;
3010
3011 dev = get_cpu_device(policy->cpu);
3012 if (!dev)
3013 return -ENODEV;
3014
3015 ret = __intel_pstate_cpu_init(policy);
3016 if (ret)
3017 return ret;
3018
3019 policy->cpuinfo.transition_latency = INTEL_CPUFREQ_TRANSITION_LATENCY;
3020 /* This reflects the intel_pstate_get_cpu_pstates() setting. */
3021 policy->cur = policy->cpuinfo.min_freq;
3022
3023 req = kcalloc(2, sizeof(*req), GFP_KERNEL);
3024 if (!req) {
3025 ret = -ENOMEM;
3026 goto pstate_exit;
3027 }
3028
3029 cpu = all_cpu_data[policy->cpu];
3030
3031 if (hwp_active) {
3032 u64 value;
3033
3034 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY_HWP;
3035
3036 intel_pstate_get_hwp_cap(cpu);
3037
3038 rdmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, &value);
3039 WRITE_ONCE(cpu->hwp_req_cached, value);
3040
3041 cpu->epp_cached = intel_pstate_get_epp(cpu, value);
3042 } else {
3043 policy->transition_delay_us = INTEL_CPUFREQ_TRANSITION_DELAY;
3044 }
3045
3046 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.min_perf_pct, 100);
3047
3048 ret = freq_qos_add_request(&policy->constraints, req, FREQ_QOS_MIN,
3049 freq);
3050 if (ret < 0) {
3051 dev_err(dev, "Failed to add min-freq constraint (%d)\n", ret);
3052 goto free_req;
3053 }
3054
3055 freq = DIV_ROUND_UP(cpu->pstate.turbo_freq * global.max_perf_pct, 100);
3056
3057 ret = freq_qos_add_request(&policy->constraints, req + 1, FREQ_QOS_MAX,
3058 freq);
3059 if (ret < 0) {
3060 dev_err(dev, "Failed to add max-freq constraint (%d)\n", ret);
3061 goto remove_min_req;
3062 }
3063
3064 policy->driver_data = req;
3065
3066 return 0;
3067
3068 remove_min_req:
3069 freq_qos_remove_request(req);
3070 free_req:
3071 kfree(req);
3072 pstate_exit:
3073 intel_pstate_exit_perf_limits(policy);
3074
3075 return ret;
3076 }
3077
intel_cpufreq_cpu_exit(struct cpufreq_policy * policy)3078 static int intel_cpufreq_cpu_exit(struct cpufreq_policy *policy)
3079 {
3080 struct freq_qos_request *req;
3081
3082 req = policy->driver_data;
3083
3084 freq_qos_remove_request(req + 1);
3085 freq_qos_remove_request(req);
3086 kfree(req);
3087
3088 return intel_pstate_cpu_exit(policy);
3089 }
3090
intel_cpufreq_suspend(struct cpufreq_policy * policy)3091 static int intel_cpufreq_suspend(struct cpufreq_policy *policy)
3092 {
3093 intel_pstate_suspend(policy);
3094
3095 if (hwp_active) {
3096 struct cpudata *cpu = all_cpu_data[policy->cpu];
3097 u64 value = READ_ONCE(cpu->hwp_req_cached);
3098
3099 /*
3100 * Clear the desired perf field in MSR_HWP_REQUEST in case
3101 * intel_cpufreq_adjust_perf() is in use and the last value
3102 * written by it may not be suitable.
3103 */
3104 value &= ~HWP_DESIRED_PERF(~0L);
3105 wrmsrl_on_cpu(cpu->cpu, MSR_HWP_REQUEST, value);
3106 WRITE_ONCE(cpu->hwp_req_cached, value);
3107 }
3108
3109 return 0;
3110 }
3111
3112 static struct cpufreq_driver intel_cpufreq = {
3113 .flags = CPUFREQ_CONST_LOOPS,
3114 .verify = intel_cpufreq_verify_policy,
3115 .target = intel_cpufreq_target,
3116 .fast_switch = intel_cpufreq_fast_switch,
3117 .init = intel_cpufreq_cpu_init,
3118 .exit = intel_cpufreq_cpu_exit,
3119 .offline = intel_cpufreq_cpu_offline,
3120 .online = intel_pstate_cpu_online,
3121 .suspend = intel_cpufreq_suspend,
3122 .resume = intel_pstate_resume,
3123 .update_limits = intel_pstate_update_limits,
3124 .name = "intel_cpufreq",
3125 };
3126
3127 static struct cpufreq_driver *default_driver;
3128
intel_pstate_driver_cleanup(void)3129 static void intel_pstate_driver_cleanup(void)
3130 {
3131 unsigned int cpu;
3132
3133 cpus_read_lock();
3134 for_each_online_cpu(cpu) {
3135 if (all_cpu_data[cpu]) {
3136 if (intel_pstate_driver == &intel_pstate)
3137 intel_pstate_clear_update_util_hook(cpu);
3138
3139 raw_spin_lock(&hwp_notify_lock);
3140 kfree(all_cpu_data[cpu]);
3141 WRITE_ONCE(all_cpu_data[cpu], NULL);
3142 raw_spin_unlock(&hwp_notify_lock);
3143 }
3144 }
3145 cpus_read_unlock();
3146
3147 intel_pstate_driver = NULL;
3148 }
3149
intel_pstate_register_driver(struct cpufreq_driver * driver)3150 static int intel_pstate_register_driver(struct cpufreq_driver *driver)
3151 {
3152 int ret;
3153
3154 if (driver == &intel_pstate)
3155 intel_pstate_sysfs_expose_hwp_dynamic_boost();
3156
3157 memset(&global, 0, sizeof(global));
3158 global.max_perf_pct = 100;
3159
3160 intel_pstate_driver = driver;
3161 ret = cpufreq_register_driver(intel_pstate_driver);
3162 if (ret) {
3163 intel_pstate_driver_cleanup();
3164 return ret;
3165 }
3166
3167 global.min_perf_pct = min_perf_pct_min();
3168
3169 return 0;
3170 }
3171
intel_pstate_show_status(char * buf)3172 static ssize_t intel_pstate_show_status(char *buf)
3173 {
3174 if (!intel_pstate_driver)
3175 return sprintf(buf, "off\n");
3176
3177 return sprintf(buf, "%s\n", intel_pstate_driver == &intel_pstate ?
3178 "active" : "passive");
3179 }
3180
intel_pstate_update_status(const char * buf,size_t size)3181 static int intel_pstate_update_status(const char *buf, size_t size)
3182 {
3183 if (size == 3 && !strncmp(buf, "off", size)) {
3184 if (!intel_pstate_driver)
3185 return -EINVAL;
3186
3187 if (hwp_active)
3188 return -EBUSY;
3189
3190 cpufreq_unregister_driver(intel_pstate_driver);
3191 intel_pstate_driver_cleanup();
3192 return 0;
3193 }
3194
3195 if (size == 6 && !strncmp(buf, "active", size)) {
3196 if (intel_pstate_driver) {
3197 if (intel_pstate_driver == &intel_pstate)
3198 return 0;
3199
3200 cpufreq_unregister_driver(intel_pstate_driver);
3201 }
3202
3203 return intel_pstate_register_driver(&intel_pstate);
3204 }
3205
3206 if (size == 7 && !strncmp(buf, "passive", size)) {
3207 if (intel_pstate_driver) {
3208 if (intel_pstate_driver == &intel_cpufreq)
3209 return 0;
3210
3211 cpufreq_unregister_driver(intel_pstate_driver);
3212 intel_pstate_sysfs_hide_hwp_dynamic_boost();
3213 }
3214
3215 return intel_pstate_register_driver(&intel_cpufreq);
3216 }
3217
3218 return -EINVAL;
3219 }
3220
3221 static int no_load __initdata;
3222 static int no_hwp __initdata;
3223 static int hwp_only __initdata;
3224 static unsigned int force_load __initdata;
3225
intel_pstate_msrs_not_valid(void)3226 static int __init intel_pstate_msrs_not_valid(void)
3227 {
3228 if (!pstate_funcs.get_max(0) ||
3229 !pstate_funcs.get_min(0) ||
3230 !pstate_funcs.get_turbo(0))
3231 return -ENODEV;
3232
3233 return 0;
3234 }
3235
copy_cpu_funcs(struct pstate_funcs * funcs)3236 static void __init copy_cpu_funcs(struct pstate_funcs *funcs)
3237 {
3238 pstate_funcs.get_max = funcs->get_max;
3239 pstate_funcs.get_max_physical = funcs->get_max_physical;
3240 pstate_funcs.get_min = funcs->get_min;
3241 pstate_funcs.get_turbo = funcs->get_turbo;
3242 pstate_funcs.get_scaling = funcs->get_scaling;
3243 pstate_funcs.get_val = funcs->get_val;
3244 pstate_funcs.get_vid = funcs->get_vid;
3245 pstate_funcs.get_aperf_mperf_shift = funcs->get_aperf_mperf_shift;
3246 }
3247
3248 #ifdef CONFIG_ACPI
3249
intel_pstate_no_acpi_pss(void)3250 static bool __init intel_pstate_no_acpi_pss(void)
3251 {
3252 int i;
3253
3254 for_each_possible_cpu(i) {
3255 acpi_status status;
3256 union acpi_object *pss;
3257 struct acpi_buffer buffer = { ACPI_ALLOCATE_BUFFER, NULL };
3258 struct acpi_processor *pr = per_cpu(processors, i);
3259
3260 if (!pr)
3261 continue;
3262
3263 status = acpi_evaluate_object(pr->handle, "_PSS", NULL, &buffer);
3264 if (ACPI_FAILURE(status))
3265 continue;
3266
3267 pss = buffer.pointer;
3268 if (pss && pss->type == ACPI_TYPE_PACKAGE) {
3269 kfree(pss);
3270 return false;
3271 }
3272
3273 kfree(pss);
3274 }
3275
3276 pr_debug("ACPI _PSS not found\n");
3277 return true;
3278 }
3279
intel_pstate_no_acpi_pcch(void)3280 static bool __init intel_pstate_no_acpi_pcch(void)
3281 {
3282 acpi_status status;
3283 acpi_handle handle;
3284
3285 status = acpi_get_handle(NULL, "\\_SB", &handle);
3286 if (ACPI_FAILURE(status))
3287 goto not_found;
3288
3289 if (acpi_has_method(handle, "PCCH"))
3290 return false;
3291
3292 not_found:
3293 pr_debug("ACPI PCCH not found\n");
3294 return true;
3295 }
3296
intel_pstate_has_acpi_ppc(void)3297 static bool __init intel_pstate_has_acpi_ppc(void)
3298 {
3299 int i;
3300
3301 for_each_possible_cpu(i) {
3302 struct acpi_processor *pr = per_cpu(processors, i);
3303
3304 if (!pr)
3305 continue;
3306 if (acpi_has_method(pr->handle, "_PPC"))
3307 return true;
3308 }
3309 pr_debug("ACPI _PPC not found\n");
3310 return false;
3311 }
3312
3313 enum {
3314 PSS,
3315 PPC,
3316 };
3317
3318 /* Hardware vendor-specific info that has its own power management modes */
3319 static struct acpi_platform_list plat_info[] __initdata = {
3320 {"HP ", "ProLiant", 0, ACPI_SIG_FADT, all_versions, NULL, PSS},
3321 {"ORACLE", "X4-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3322 {"ORACLE", "X4-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3323 {"ORACLE", "X4-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3324 {"ORACLE", "X3-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3325 {"ORACLE", "X3-2L ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3326 {"ORACLE", "X3-2B ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3327 {"ORACLE", "X4470M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3328 {"ORACLE", "X4270M3 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3329 {"ORACLE", "X4270M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3330 {"ORACLE", "X4170M2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3331 {"ORACLE", "X4170 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3332 {"ORACLE", "X4275 M3", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3333 {"ORACLE", "X6-2 ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3334 {"ORACLE", "Sudbury ", 0, ACPI_SIG_FADT, all_versions, NULL, PPC},
3335 { } /* End */
3336 };
3337
3338 #define BITMASK_OOB (BIT(8) | BIT(18))
3339
intel_pstate_platform_pwr_mgmt_exists(void)3340 static bool __init intel_pstate_platform_pwr_mgmt_exists(void)
3341 {
3342 const struct x86_cpu_id *id;
3343 u64 misc_pwr;
3344 int idx;
3345
3346 id = x86_match_cpu(intel_pstate_cpu_oob_ids);
3347 if (id) {
3348 rdmsrl(MSR_MISC_PWR_MGMT, misc_pwr);
3349 if (misc_pwr & BITMASK_OOB) {
3350 pr_debug("Bit 8 or 18 in the MISC_PWR_MGMT MSR set\n");
3351 pr_debug("P states are controlled in Out of Band mode by the firmware/hardware\n");
3352 return true;
3353 }
3354 }
3355
3356 idx = acpi_match_platform_list(plat_info);
3357 if (idx < 0)
3358 return false;
3359
3360 switch (plat_info[idx].data) {
3361 case PSS:
3362 if (!intel_pstate_no_acpi_pss())
3363 return false;
3364
3365 return intel_pstate_no_acpi_pcch();
3366 case PPC:
3367 return intel_pstate_has_acpi_ppc() && !force_load;
3368 }
3369
3370 return false;
3371 }
3372
intel_pstate_request_control_from_smm(void)3373 static void intel_pstate_request_control_from_smm(void)
3374 {
3375 /*
3376 * It may be unsafe to request P-states control from SMM if _PPC support
3377 * has not been enabled.
3378 */
3379 if (acpi_ppc)
3380 acpi_processor_pstate_control();
3381 }
3382 #else /* CONFIG_ACPI not enabled */
intel_pstate_platform_pwr_mgmt_exists(void)3383 static inline bool intel_pstate_platform_pwr_mgmt_exists(void) { return false; }
intel_pstate_has_acpi_ppc(void)3384 static inline bool intel_pstate_has_acpi_ppc(void) { return false; }
intel_pstate_request_control_from_smm(void)3385 static inline void intel_pstate_request_control_from_smm(void) {}
3386 #endif /* CONFIG_ACPI */
3387
3388 #define INTEL_PSTATE_HWP_BROADWELL 0x01
3389
3390 #define X86_MATCH_HWP(model, hwp_mode) \
3391 X86_MATCH_VENDOR_FAM_MODEL_FEATURE(INTEL, 6, INTEL_FAM6_##model, \
3392 X86_FEATURE_HWP, hwp_mode)
3393
3394 static const struct x86_cpu_id hwp_support_ids[] __initconst = {
3395 X86_MATCH_HWP(BROADWELL_X, INTEL_PSTATE_HWP_BROADWELL),
3396 X86_MATCH_HWP(BROADWELL_D, INTEL_PSTATE_HWP_BROADWELL),
3397 X86_MATCH_HWP(ANY, 0),
3398 {}
3399 };
3400
intel_pstate_hwp_is_enabled(void)3401 static bool intel_pstate_hwp_is_enabled(void)
3402 {
3403 u64 value;
3404
3405 rdmsrl(MSR_PM_ENABLE, value);
3406 return !!(value & 0x1);
3407 }
3408
3409 static const struct x86_cpu_id intel_epp_balance_perf[] = {
3410 /*
3411 * Set EPP value as 102, this is the max suggested EPP
3412 * which can result in one core turbo frequency for
3413 * AlderLake Mobile CPUs.
3414 */
3415 X86_MATCH_INTEL_FAM6_MODEL(ALDERLAKE_L, 102),
3416 X86_MATCH_INTEL_FAM6_MODEL(SAPPHIRERAPIDS_X, 32),
3417 {}
3418 };
3419
intel_pstate_init(void)3420 static int __init intel_pstate_init(void)
3421 {
3422 static struct cpudata **_all_cpu_data;
3423 const struct x86_cpu_id *id;
3424 int rc;
3425
3426 if (boot_cpu_data.x86_vendor != X86_VENDOR_INTEL)
3427 return -ENODEV;
3428
3429 id = x86_match_cpu(hwp_support_ids);
3430 if (id) {
3431 hwp_forced = intel_pstate_hwp_is_enabled();
3432
3433 if (hwp_forced)
3434 pr_info("HWP enabled by BIOS\n");
3435 else if (no_load)
3436 return -ENODEV;
3437
3438 copy_cpu_funcs(&core_funcs);
3439 /*
3440 * Avoid enabling HWP for processors without EPP support,
3441 * because that means incomplete HWP implementation which is a
3442 * corner case and supporting it is generally problematic.
3443 *
3444 * If HWP is enabled already, though, there is no choice but to
3445 * deal with it.
3446 */
3447 if ((!no_hwp && boot_cpu_has(X86_FEATURE_HWP_EPP)) || hwp_forced) {
3448 WRITE_ONCE(hwp_active, 1);
3449 hwp_mode_bdw = id->driver_data;
3450 intel_pstate.attr = hwp_cpufreq_attrs;
3451 intel_cpufreq.attr = hwp_cpufreq_attrs;
3452 intel_cpufreq.flags |= CPUFREQ_NEED_UPDATE_LIMITS;
3453 intel_cpufreq.adjust_perf = intel_cpufreq_adjust_perf;
3454 if (!default_driver)
3455 default_driver = &intel_pstate;
3456
3457 pstate_funcs.get_cpu_scaling = hwp_get_cpu_scaling;
3458
3459 goto hwp_cpu_matched;
3460 }
3461 pr_info("HWP not enabled\n");
3462 } else {
3463 if (no_load)
3464 return -ENODEV;
3465
3466 id = x86_match_cpu(intel_pstate_cpu_ids);
3467 if (!id) {
3468 pr_info("CPU model not supported\n");
3469 return -ENODEV;
3470 }
3471
3472 copy_cpu_funcs((struct pstate_funcs *)id->driver_data);
3473 }
3474
3475 if (intel_pstate_msrs_not_valid()) {
3476 pr_info("Invalid MSRs\n");
3477 return -ENODEV;
3478 }
3479 /* Without HWP start in the passive mode. */
3480 if (!default_driver)
3481 default_driver = &intel_cpufreq;
3482
3483 hwp_cpu_matched:
3484 /*
3485 * The Intel pstate driver will be ignored if the platform
3486 * firmware has its own power management modes.
3487 */
3488 if (intel_pstate_platform_pwr_mgmt_exists()) {
3489 pr_info("P-states controlled by the platform\n");
3490 return -ENODEV;
3491 }
3492
3493 if (!hwp_active && hwp_only)
3494 return -ENOTSUPP;
3495
3496 pr_info("Intel P-state driver initializing\n");
3497
3498 _all_cpu_data = vzalloc(array_size(sizeof(void *), num_possible_cpus()));
3499 if (!_all_cpu_data)
3500 return -ENOMEM;
3501
3502 WRITE_ONCE(all_cpu_data, _all_cpu_data);
3503
3504 intel_pstate_request_control_from_smm();
3505
3506 intel_pstate_sysfs_expose_params();
3507
3508 if (hwp_active) {
3509 const struct x86_cpu_id *id = x86_match_cpu(intel_epp_balance_perf);
3510
3511 if (id)
3512 epp_values[EPP_INDEX_BALANCE_PERFORMANCE] = id->driver_data;
3513 }
3514
3515 mutex_lock(&intel_pstate_driver_lock);
3516 rc = intel_pstate_register_driver(default_driver);
3517 mutex_unlock(&intel_pstate_driver_lock);
3518 if (rc) {
3519 intel_pstate_sysfs_remove();
3520 return rc;
3521 }
3522
3523 if (hwp_active) {
3524 const struct x86_cpu_id *id;
3525
3526 id = x86_match_cpu(intel_pstate_cpu_ee_disable_ids);
3527 if (id) {
3528 set_power_ctl_ee_state(false);
3529 pr_info("Disabling energy efficiency optimization\n");
3530 }
3531
3532 pr_info("HWP enabled\n");
3533 } else if (boot_cpu_has(X86_FEATURE_HYBRID_CPU)) {
3534 pr_warn("Problematic setup: Hybrid processor with disabled HWP\n");
3535 }
3536
3537 return 0;
3538 }
3539 device_initcall(intel_pstate_init);
3540
intel_pstate_setup(char * str)3541 static int __init intel_pstate_setup(char *str)
3542 {
3543 if (!str)
3544 return -EINVAL;
3545
3546 if (!strcmp(str, "disable"))
3547 no_load = 1;
3548 else if (!strcmp(str, "active"))
3549 default_driver = &intel_pstate;
3550 else if (!strcmp(str, "passive"))
3551 default_driver = &intel_cpufreq;
3552
3553 if (!strcmp(str, "no_hwp"))
3554 no_hwp = 1;
3555
3556 if (!strcmp(str, "force"))
3557 force_load = 1;
3558 if (!strcmp(str, "hwp_only"))
3559 hwp_only = 1;
3560 if (!strcmp(str, "per_cpu_perf_limits"))
3561 per_cpu_limits = true;
3562
3563 #ifdef CONFIG_ACPI
3564 if (!strcmp(str, "support_acpi_ppc"))
3565 acpi_ppc = true;
3566 #endif
3567
3568 return 0;
3569 }
3570 early_param("intel_pstate", intel_pstate_setup);
3571
3572 MODULE_AUTHOR("Dirk Brandewie <dirk.j.brandewie@intel.com>");
3573 MODULE_DESCRIPTION("'intel_pstate' - P state driver Intel Core processors");
3574