xref: /openbmc/linux/arch/arm64/include/asm/ptrace.h (revision c888b7bd)
1 /* SPDX-License-Identifier: GPL-2.0-only */
2 /*
3  * Based on arch/arm/include/asm/ptrace.h
4  *
5  * Copyright (C) 1996-2003 Russell King
6  * Copyright (C) 2012 ARM Ltd.
7  */
8 #ifndef __ASM_PTRACE_H
9 #define __ASM_PTRACE_H
10 
11 #include <asm/cpufeature.h>
12 
13 #include <uapi/asm/ptrace.h>
14 
15 /* Current Exception Level values, as contained in CurrentEL */
16 #define CurrentEL_EL1		(1 << 2)
17 #define CurrentEL_EL2		(2 << 2)
18 
19 #define INIT_PSTATE_EL1 \
20 	(PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL1h)
21 #define INIT_PSTATE_EL2 \
22 	(PSR_D_BIT | PSR_A_BIT | PSR_I_BIT | PSR_F_BIT | PSR_MODE_EL2h)
23 
24 /*
25  * PMR values used to mask/unmask interrupts.
26  *
27  * GIC priority masking works as follows: if an IRQ's priority is a higher value
28  * than the value held in PMR, that IRQ is masked. Lowering the value of PMR
29  * means masking more IRQs (or at least that the same IRQs remain masked).
30  *
31  * To mask interrupts, we clear the most significant bit of PMR.
32  *
33  * Some code sections either automatically switch back to PSR.I or explicitly
34  * require to not use priority masking. If bit GIC_PRIO_PSR_I_SET is included
35  * in the priority mask, it indicates that PSR.I should be set and
36  * interrupt disabling temporarily does not rely on IRQ priorities.
37  */
38 #define GIC_PRIO_IRQON			0xe0
39 #define __GIC_PRIO_IRQOFF		(GIC_PRIO_IRQON & ~0x80)
40 #define __GIC_PRIO_IRQOFF_NS		0xa0
41 #define GIC_PRIO_PSR_I_SET		(1 << 4)
42 
43 #define GIC_PRIO_IRQOFF							\
44 	({								\
45 		extern struct static_key_false gic_nonsecure_priorities;\
46 		u8 __prio = __GIC_PRIO_IRQOFF;				\
47 									\
48 		if (static_branch_unlikely(&gic_nonsecure_priorities))	\
49 			__prio = __GIC_PRIO_IRQOFF_NS;			\
50 									\
51 		__prio;							\
52 	})
53 
54 /* Additional SPSR bits not exposed in the UABI */
55 #define PSR_MODE_THREAD_BIT	(1 << 0)
56 #define PSR_IL_BIT		(1 << 20)
57 
58 /* AArch32-specific ptrace requests */
59 #define COMPAT_PTRACE_GETREGS		12
60 #define COMPAT_PTRACE_SETREGS		13
61 #define COMPAT_PTRACE_GET_THREAD_AREA	22
62 #define COMPAT_PTRACE_SET_SYSCALL	23
63 #define COMPAT_PTRACE_GETVFPREGS	27
64 #define COMPAT_PTRACE_SETVFPREGS	28
65 #define COMPAT_PTRACE_GETHBPREGS	29
66 #define COMPAT_PTRACE_SETHBPREGS	30
67 
68 /* SPSR_ELx bits for exceptions taken from AArch32 */
69 #define PSR_AA32_MODE_MASK	0x0000001f
70 #define PSR_AA32_MODE_USR	0x00000010
71 #define PSR_AA32_MODE_FIQ	0x00000011
72 #define PSR_AA32_MODE_IRQ	0x00000012
73 #define PSR_AA32_MODE_SVC	0x00000013
74 #define PSR_AA32_MODE_ABT	0x00000017
75 #define PSR_AA32_MODE_HYP	0x0000001a
76 #define PSR_AA32_MODE_UND	0x0000001b
77 #define PSR_AA32_MODE_SYS	0x0000001f
78 #define PSR_AA32_T_BIT		0x00000020
79 #define PSR_AA32_F_BIT		0x00000040
80 #define PSR_AA32_I_BIT		0x00000080
81 #define PSR_AA32_A_BIT		0x00000100
82 #define PSR_AA32_E_BIT		0x00000200
83 #define PSR_AA32_PAN_BIT	0x00400000
84 #define PSR_AA32_SSBS_BIT	0x00800000
85 #define PSR_AA32_DIT_BIT	0x01000000
86 #define PSR_AA32_Q_BIT		0x08000000
87 #define PSR_AA32_V_BIT		0x10000000
88 #define PSR_AA32_C_BIT		0x20000000
89 #define PSR_AA32_Z_BIT		0x40000000
90 #define PSR_AA32_N_BIT		0x80000000
91 #define PSR_AA32_IT_MASK	0x0600fc00	/* If-Then execution state mask */
92 #define PSR_AA32_GE_MASK	0x000f0000
93 
94 #ifdef CONFIG_CPU_BIG_ENDIAN
95 #define PSR_AA32_ENDSTATE	PSR_AA32_E_BIT
96 #else
97 #define PSR_AA32_ENDSTATE	0
98 #endif
99 
100 /* AArch32 CPSR bits, as seen in AArch32 */
101 #define COMPAT_PSR_DIT_BIT	0x00200000
102 
103 /*
104  * These are 'magic' values for PTRACE_PEEKUSR that return info about where a
105  * process is located in memory.
106  */
107 #define COMPAT_PT_TEXT_ADDR		0x10000
108 #define COMPAT_PT_DATA_ADDR		0x10004
109 #define COMPAT_PT_TEXT_END_ADDR		0x10008
110 
111 /*
112  * If pt_regs.syscallno == NO_SYSCALL, then the thread is not executing
113  * a syscall -- i.e., its most recent entry into the kernel from
114  * userspace was not via SVC, or otherwise a tracer cancelled the syscall.
115  *
116  * This must have the value -1, for ABI compatibility with ptrace etc.
117  */
118 #define NO_SYSCALL (-1)
119 
120 #ifndef __ASSEMBLY__
121 #include <linux/bug.h>
122 #include <linux/types.h>
123 
124 /* sizeof(struct user) for AArch32 */
125 #define COMPAT_USER_SZ	296
126 
127 /* Architecturally defined mapping between AArch32 and AArch64 registers */
128 #define compat_usr(x)	regs[(x)]
129 #define compat_fp	regs[11]
130 #define compat_sp	regs[13]
131 #define compat_lr	regs[14]
132 #define compat_sp_hyp	regs[15]
133 #define compat_lr_irq	regs[16]
134 #define compat_sp_irq	regs[17]
135 #define compat_lr_svc	regs[18]
136 #define compat_sp_svc	regs[19]
137 #define compat_lr_abt	regs[20]
138 #define compat_sp_abt	regs[21]
139 #define compat_lr_und	regs[22]
140 #define compat_sp_und	regs[23]
141 #define compat_r8_fiq	regs[24]
142 #define compat_r9_fiq	regs[25]
143 #define compat_r10_fiq	regs[26]
144 #define compat_r11_fiq	regs[27]
145 #define compat_r12_fiq	regs[28]
146 #define compat_sp_fiq	regs[29]
147 #define compat_lr_fiq	regs[30]
148 
compat_psr_to_pstate(const unsigned long psr)149 static inline unsigned long compat_psr_to_pstate(const unsigned long psr)
150 {
151 	unsigned long pstate;
152 
153 	pstate = psr & ~COMPAT_PSR_DIT_BIT;
154 
155 	if (psr & COMPAT_PSR_DIT_BIT)
156 		pstate |= PSR_AA32_DIT_BIT;
157 
158 	return pstate;
159 }
160 
pstate_to_compat_psr(const unsigned long pstate)161 static inline unsigned long pstate_to_compat_psr(const unsigned long pstate)
162 {
163 	unsigned long psr;
164 
165 	psr = pstate & ~PSR_AA32_DIT_BIT;
166 
167 	if (pstate & PSR_AA32_DIT_BIT)
168 		psr |= COMPAT_PSR_DIT_BIT;
169 
170 	return psr;
171 }
172 
173 /*
174  * This struct defines the way the registers are stored on the stack during an
175  * exception. Note that sizeof(struct pt_regs) has to be a multiple of 16 (for
176  * stack alignment). struct user_pt_regs must form a prefix of struct pt_regs.
177  */
178 struct pt_regs {
179 	union {
180 		struct user_pt_regs user_regs;
181 		struct {
182 			u64 regs[31];
183 			u64 sp;
184 			u64 pc;
185 			u64 pstate;
186 		};
187 	};
188 	u64 orig_x0;
189 #ifdef __AARCH64EB__
190 	u32 unused2;
191 	s32 syscallno;
192 #else
193 	s32 syscallno;
194 	u32 unused2;
195 #endif
196 	u64 sdei_ttbr1;
197 	/* Only valid when ARM64_HAS_GIC_PRIO_MASKING is enabled. */
198 	u64 pmr_save;
199 	u64 stackframe[2];
200 
201 	/* Only valid for some EL1 exceptions. */
202 	u64 lockdep_hardirqs;
203 	u64 exit_rcu;
204 };
205 
in_syscall(struct pt_regs const * regs)206 static inline bool in_syscall(struct pt_regs const *regs)
207 {
208 	return regs->syscallno != NO_SYSCALL;
209 }
210 
forget_syscall(struct pt_regs * regs)211 static inline void forget_syscall(struct pt_regs *regs)
212 {
213 	regs->syscallno = NO_SYSCALL;
214 }
215 
216 #define MAX_REG_OFFSET offsetof(struct pt_regs, pstate)
217 
218 #define arch_has_single_step()	(1)
219 
220 #ifdef CONFIG_COMPAT
221 #define compat_thumb_mode(regs) \
222 	(((regs)->pstate & PSR_AA32_T_BIT))
223 #else
224 #define compat_thumb_mode(regs) (0)
225 #endif
226 
227 #define user_mode(regs)	\
228 	(((regs)->pstate & PSR_MODE_MASK) == PSR_MODE_EL0t)
229 
230 #define compat_user_mode(regs)	\
231 	(((regs)->pstate & (PSR_MODE32_BIT | PSR_MODE_MASK)) == \
232 	 (PSR_MODE32_BIT | PSR_MODE_EL0t))
233 
234 #define processor_mode(regs) \
235 	((regs)->pstate & PSR_MODE_MASK)
236 
237 #define irqs_priority_unmasked(regs)					\
238 	(system_uses_irq_prio_masking() ?				\
239 		(regs)->pmr_save == GIC_PRIO_IRQON :			\
240 		true)
241 
242 #define interrupts_enabled(regs)			\
243 	(!((regs)->pstate & PSR_I_BIT) && irqs_priority_unmasked(regs))
244 
245 #define fast_interrupts_enabled(regs) \
246 	(!((regs)->pstate & PSR_F_BIT))
247 
user_stack_pointer(struct pt_regs * regs)248 static inline unsigned long user_stack_pointer(struct pt_regs *regs)
249 {
250 	if (compat_user_mode(regs))
251 		return regs->compat_sp;
252 	return regs->sp;
253 }
254 
255 extern int regs_query_register_offset(const char *name);
256 extern unsigned long regs_get_kernel_stack_nth(struct pt_regs *regs,
257 					       unsigned int n);
258 
259 /**
260  * regs_get_register() - get register value from its offset
261  * @regs:	pt_regs from which register value is gotten
262  * @offset:	offset of the register.
263  *
264  * regs_get_register returns the value of a register whose offset from @regs.
265  * The @offset is the offset of the register in struct pt_regs.
266  * If @offset is bigger than MAX_REG_OFFSET, this returns 0.
267  */
regs_get_register(struct pt_regs * regs,unsigned int offset)268 static inline u64 regs_get_register(struct pt_regs *regs, unsigned int offset)
269 {
270 	u64 val = 0;
271 
272 	WARN_ON(offset & 7);
273 
274 	offset >>= 3;
275 	switch (offset) {
276 	case 0 ... 30:
277 		val = regs->regs[offset];
278 		break;
279 	case offsetof(struct pt_regs, sp) >> 3:
280 		val = regs->sp;
281 		break;
282 	case offsetof(struct pt_regs, pc) >> 3:
283 		val = regs->pc;
284 		break;
285 	case offsetof(struct pt_regs, pstate) >> 3:
286 		val = regs->pstate;
287 		break;
288 	default:
289 		val = 0;
290 	}
291 
292 	return val;
293 }
294 
295 /*
296  * Read a register given an architectural register index r.
297  * This handles the common case where 31 means XZR, not SP.
298  */
pt_regs_read_reg(const struct pt_regs * regs,int r)299 static inline unsigned long pt_regs_read_reg(const struct pt_regs *regs, int r)
300 {
301 	return (r == 31) ? 0 : regs->regs[r];
302 }
303 
304 /*
305  * Write a register given an architectural register index r.
306  * This handles the common case where 31 means XZR, not SP.
307  */
pt_regs_write_reg(struct pt_regs * regs,int r,unsigned long val)308 static inline void pt_regs_write_reg(struct pt_regs *regs, int r,
309 				     unsigned long val)
310 {
311 	if (r != 31)
312 		regs->regs[r] = val;
313 }
314 
315 /* Valid only for Kernel mode traps. */
kernel_stack_pointer(struct pt_regs * regs)316 static inline unsigned long kernel_stack_pointer(struct pt_regs *regs)
317 {
318 	return regs->sp;
319 }
320 
regs_return_value(struct pt_regs * regs)321 static inline unsigned long regs_return_value(struct pt_regs *regs)
322 {
323 	unsigned long val = regs->regs[0];
324 
325 	/*
326 	 * Audit currently uses regs_return_value() instead of
327 	 * syscall_get_return_value(). Apply the same sign-extension here until
328 	 * audit is updated to use syscall_get_return_value().
329 	 */
330 	if (compat_user_mode(regs))
331 		val = sign_extend64(val, 31);
332 
333 	return val;
334 }
335 
regs_set_return_value(struct pt_regs * regs,unsigned long rc)336 static inline void regs_set_return_value(struct pt_regs *regs, unsigned long rc)
337 {
338 	regs->regs[0] = rc;
339 }
340 
341 /**
342  * regs_get_kernel_argument() - get Nth function argument in kernel
343  * @regs:	pt_regs of that context
344  * @n:		function argument number (start from 0)
345  *
346  * regs_get_argument() returns @n th argument of the function call.
347  *
348  * Note that this chooses the most likely register mapping. In very rare
349  * cases this may not return correct data, for example, if one of the
350  * function parameters is 16 bytes or bigger. In such cases, we cannot
351  * get access the parameter correctly and the register assignment of
352  * subsequent parameters will be shifted.
353  */
regs_get_kernel_argument(struct pt_regs * regs,unsigned int n)354 static inline unsigned long regs_get_kernel_argument(struct pt_regs *regs,
355 						     unsigned int n)
356 {
357 #define NR_REG_ARGUMENTS 8
358 	if (n < NR_REG_ARGUMENTS)
359 		return pt_regs_read_reg(regs, n);
360 	return 0;
361 }
362 
363 /* We must avoid circular header include via sched.h */
364 struct task_struct;
365 int valid_user_regs(struct user_pt_regs *regs, struct task_struct *task);
366 
instruction_pointer(struct pt_regs * regs)367 static inline unsigned long instruction_pointer(struct pt_regs *regs)
368 {
369 	return regs->pc;
370 }
instruction_pointer_set(struct pt_regs * regs,unsigned long val)371 static inline void instruction_pointer_set(struct pt_regs *regs,
372 		unsigned long val)
373 {
374 	regs->pc = val;
375 }
376 
frame_pointer(struct pt_regs * regs)377 static inline unsigned long frame_pointer(struct pt_regs *regs)
378 {
379 	return regs->regs[29];
380 }
381 
382 #define procedure_link_pointer(regs)	((regs)->regs[30])
383 
procedure_link_pointer_set(struct pt_regs * regs,unsigned long val)384 static inline void procedure_link_pointer_set(struct pt_regs *regs,
385 					   unsigned long val)
386 {
387 	procedure_link_pointer(regs) = val;
388 }
389 
390 extern unsigned long profile_pc(struct pt_regs *regs);
391 
392 #endif /* __ASSEMBLY__ */
393 #endif
394