1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* Texas Instruments ICSSG Ethernet driver 3 * 4 * Copyright (C) 2022 Texas Instruments Incorporated - https://www.ti.com/ 5 * 6 */ 7 8 #ifndef __NET_TI_ICSSG_CONFIG_H 9 #define __NET_TI_ICSSG_CONFIG_H 10 11 struct icssg_buffer_pool_cfg { 12 __le32 addr; 13 __le32 len; 14 } __packed; 15 16 struct icssg_flow_cfg { 17 __le16 rx_base_flow; 18 __le16 mgm_base_flow; 19 } __packed; 20 21 #define PRUETH_PKT_TYPE_CMD 0x10 22 #define PRUETH_NAV_PS_DATA_SIZE 16 /* Protocol specific data size */ 23 #define PRUETH_NAV_SW_DATA_SIZE 16 /* SW related data size */ 24 #define PRUETH_MAX_TX_DESC 512 25 #define PRUETH_MAX_RX_DESC 512 26 #define PRUETH_MAX_RX_FLOWS 1 /* excluding default flow */ 27 #define PRUETH_RX_FLOW_DATA 0 28 29 #define PRUETH_EMAC_BUF_POOL_SIZE SZ_8K 30 #define PRUETH_EMAC_POOLS_PER_SLICE 24 31 #define PRUETH_EMAC_BUF_POOL_START 8 32 #define PRUETH_NUM_BUF_POOLS 8 33 #define PRUETH_EMAC_RX_CTX_BUF_SIZE SZ_16K /* per slice */ 34 #define MSMC_RAM_SIZE \ 35 (2 * (PRUETH_EMAC_BUF_POOL_SIZE * PRUETH_NUM_BUF_POOLS + \ 36 PRUETH_EMAC_RX_CTX_BUF_SIZE * 2)) 37 38 struct icssg_rxq_ctx { 39 __le32 start[3]; 40 __le32 end; 41 } __packed; 42 43 /* Load time Fiwmware Configuration */ 44 45 #define ICSSG_FW_MGMT_CMD_HEADER 0x81 46 #define ICSSG_FW_MGMT_FDB_CMD_TYPE 0x03 47 #define ICSSG_FW_MGMT_CMD_TYPE 0x04 48 #define ICSSG_FW_MGMT_PKT 0x80000000 49 50 struct icssg_r30_cmd { 51 u32 cmd[4]; 52 } __packed; 53 54 enum icssg_port_state_cmd { 55 ICSSG_EMAC_PORT_DISABLE = 0, 56 ICSSG_EMAC_PORT_BLOCK, 57 ICSSG_EMAC_PORT_FORWARD, 58 ICSSG_EMAC_PORT_FORWARD_WO_LEARNING, 59 ICSSG_EMAC_PORT_ACCEPT_ALL, 60 ICSSG_EMAC_PORT_ACCEPT_TAGGED, 61 ICSSG_EMAC_PORT_ACCEPT_UNTAGGED_N_PRIO, 62 ICSSG_EMAC_PORT_TAS_TRIGGER, 63 ICSSG_EMAC_PORT_TAS_ENABLE, 64 ICSSG_EMAC_PORT_TAS_RESET, 65 ICSSG_EMAC_PORT_TAS_DISABLE, 66 ICSSG_EMAC_PORT_UC_FLOODING_ENABLE, 67 ICSSG_EMAC_PORT_UC_FLOODING_DISABLE, 68 ICSSG_EMAC_PORT_MC_FLOODING_ENABLE, 69 ICSSG_EMAC_PORT_MC_FLOODING_DISABLE, 70 ICSSG_EMAC_PORT_PREMPT_TX_ENABLE, 71 ICSSG_EMAC_PORT_PREMPT_TX_DISABLE, 72 ICSSG_EMAC_PORT_VLAN_AWARE_ENABLE, 73 ICSSG_EMAC_PORT_VLAN_AWARE_DISABLE, 74 ICSSG_EMAC_PORT_MAX_COMMANDS 75 }; 76 77 #define EMAC_NONE 0xffff0000 78 #define EMAC_PRU0_P_DI 0xffff0004 79 #define EMAC_PRU1_P_DI 0xffff0040 80 #define EMAC_TX_P_DI 0xffff0100 81 82 #define EMAC_PRU0_P_EN 0xfffb0000 83 #define EMAC_PRU1_P_EN 0xffbf0000 84 #define EMAC_TX_P_EN 0xfeff0000 85 86 #define EMAC_P_BLOCK 0xffff0040 87 #define EMAC_TX_P_BLOCK 0xffff0200 88 #define EMAC_P_UNBLOCK 0xffbf0000 89 #define EMAC_TX_P_UNBLOCK 0xfdff0000 90 #define EMAC_LEAN_EN 0xfff70000 91 #define EMAC_LEAN_DI 0xffff0008 92 93 #define EMAC_ACCEPT_ALL 0xffff0001 94 #define EMAC_ACCEPT_TAG 0xfffe0002 95 #define EMAC_ACCEPT_PRIOR 0xfffc0000 96 97 /* Config area lies in DRAM */ 98 #define ICSSG_CONFIG_OFFSET 0x0 99 100 /* Config area lies in shared RAM */ 101 #define ICSSG_CONFIG_OFFSET_SLICE0 0 102 #define ICSSG_CONFIG_OFFSET_SLICE1 0x8000 103 104 #define ICSSG_NUM_NORMAL_PDS 64 105 #define ICSSG_NUM_SPECIAL_PDS 16 106 107 #define ICSSG_NORMAL_PD_SIZE 8 108 #define ICSSG_SPECIAL_PD_SIZE 20 109 110 #define ICSSG_FLAG_MASK 0xff00ffff 111 112 struct icssg_setclock_desc { 113 u8 request; 114 u8 restore; 115 u8 acknowledgment; 116 u8 cmp_status; 117 u32 margin; 118 u32 cyclecounter0_set; 119 u32 cyclecounter1_set; 120 u32 iepcount_set; 121 u32 rsvd1; 122 u32 rsvd2; 123 u32 CMP0_current; 124 u32 iepcount_current; 125 u32 difference; 126 u32 cyclecounter0_new; 127 u32 cyclecounter1_new; 128 u32 CMP0_new; 129 } __packed; 130 131 #define ICSSG_CMD_POP_SLICE0 56 132 #define ICSSG_CMD_POP_SLICE1 60 133 134 #define ICSSG_CMD_PUSH_SLICE0 57 135 #define ICSSG_CMD_PUSH_SLICE1 61 136 137 #define ICSSG_RSP_POP_SLICE0 58 138 #define ICSSG_RSP_POP_SLICE1 62 139 140 #define ICSSG_RSP_PUSH_SLICE0 56 141 #define ICSSG_RSP_PUSH_SLICE1 60 142 143 #define ICSSG_TS_POP_SLICE0 59 144 #define ICSSG_TS_POP_SLICE1 63 145 146 #define ICSSG_TS_PUSH_SLICE0 40 147 #define ICSSG_TS_PUSH_SLICE1 41 148 149 /* FDB FID_C2 flag definitions */ 150 /* Indicates host port membership.*/ 151 #define ICSSG_FDB_ENTRY_P0_MEMBERSHIP BIT(0) 152 /* Indicates that MAC ID is connected to physical port 1 */ 153 #define ICSSG_FDB_ENTRY_P1_MEMBERSHIP BIT(1) 154 /* Indicates that MAC ID is connected to physical port 2 */ 155 #define ICSSG_FDB_ENTRY_P2_MEMBERSHIP BIT(2) 156 /* Ageable bit is set for learned entries and cleared for static entries */ 157 #define ICSSG_FDB_ENTRY_AGEABLE BIT(3) 158 /* If set for DA then packet is determined to be a special packet */ 159 #define ICSSG_FDB_ENTRY_BLOCK BIT(4) 160 /* If set for DA then the SA from the packet is not learned */ 161 #define ICSSG_FDB_ENTRY_SECURE BIT(5) 162 /* If set, it means packet has been seen recently with source address + FID 163 * matching MAC address/FID of entry 164 */ 165 #define ICSSG_FDB_ENTRY_TOUCHED BIT(6) 166 /* Set if entry is valid */ 167 #define ICSSG_FDB_ENTRY_VALID BIT(7) 168 169 /** 170 * struct prueth_vlan_tbl - VLAN table entries struct in ICSSG SMEM 171 * @fid_c1: membership and forwarding rules flag to this table. See 172 * above to defines for bit definitions 173 * @fid: FDB index for this VID (there is 1-1 mapping b/w VID and FID) 174 */ 175 struct prueth_vlan_tbl { 176 u8 fid_c1; 177 u8 fid; 178 } __packed; 179 180 /** 181 * struct prueth_fdb_slot - Result of FDB slot lookup 182 * @mac: MAC address 183 * @fid: fid to be associated with MAC 184 * @fid_c2: FID_C2 entry for this MAC 185 */ 186 struct prueth_fdb_slot { 187 u8 mac[ETH_ALEN]; 188 u8 fid; 189 u8 fid_c2; 190 } __packed; 191 192 enum icssg_ietfpe_verify_states { 193 ICSSG_IETFPE_STATE_UNKNOWN = 0, 194 ICSSG_IETFPE_STATE_INITIAL, 195 ICSSG_IETFPE_STATE_VERIFYING, 196 ICSSG_IETFPE_STATE_SUCCEEDED, 197 ICSSG_IETFPE_STATE_FAILED, 198 ICSSG_IETFPE_STATE_DISABLED 199 }; 200 #endif /* __NET_TI_ICSSG_CONFIG_H */ 201