xref: /openbmc/linux/drivers/gpu/drm/i915/gvt/interrupt.h (revision ce2fce25)
1 /*
2  * Copyright(c) 2011-2016 Intel Corporation. All rights reserved.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice (including the next
12  * paragraph) shall be included in all copies or substantial portions of the
13  * Software.
14  *
15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21  * SOFTWARE.
22  *
23  * Authors:
24  *    Kevin Tian <kevin.tian@intel.com>
25  *    Zhi Wang <zhi.a.wang@intel.com>
26  *
27  * Contributors:
28  *    Min he <min.he@intel.com>
29  *
30  */
31 
32 #ifndef _GVT_INTERRUPT_H_
33 #define _GVT_INTERRUPT_H_
34 
35 #include <linux/hrtimer.h>
36 #include <linux/kernel.h>
37 
38 #include "i915_reg_defs.h"
39 
40 enum intel_gvt_event_type {
41 	RCS_MI_USER_INTERRUPT = 0,
42 	RCS_DEBUG,
43 	RCS_MMIO_SYNC_FLUSH,
44 	RCS_CMD_STREAMER_ERR,
45 	RCS_PIPE_CONTROL,
46 	RCS_L3_PARITY_ERR,
47 	RCS_WATCHDOG_EXCEEDED,
48 	RCS_PAGE_DIRECTORY_FAULT,
49 	RCS_AS_CONTEXT_SWITCH,
50 	RCS_MONITOR_BUFF_HALF_FULL,
51 
52 	VCS_MI_USER_INTERRUPT,
53 	VCS_MMIO_SYNC_FLUSH,
54 	VCS_CMD_STREAMER_ERR,
55 	VCS_MI_FLUSH_DW,
56 	VCS_WATCHDOG_EXCEEDED,
57 	VCS_PAGE_DIRECTORY_FAULT,
58 	VCS_AS_CONTEXT_SWITCH,
59 
60 	VCS2_MI_USER_INTERRUPT,
61 	VCS2_MI_FLUSH_DW,
62 	VCS2_AS_CONTEXT_SWITCH,
63 
64 	BCS_MI_USER_INTERRUPT,
65 	BCS_MMIO_SYNC_FLUSH,
66 	BCS_CMD_STREAMER_ERR,
67 	BCS_MI_FLUSH_DW,
68 	BCS_PAGE_DIRECTORY_FAULT,
69 	BCS_AS_CONTEXT_SWITCH,
70 
71 	VECS_MI_USER_INTERRUPT,
72 	VECS_MI_FLUSH_DW,
73 	VECS_AS_CONTEXT_SWITCH,
74 
75 	PIPE_A_FIFO_UNDERRUN,
76 	PIPE_B_FIFO_UNDERRUN,
77 	PIPE_A_CRC_ERR,
78 	PIPE_B_CRC_ERR,
79 	PIPE_A_CRC_DONE,
80 	PIPE_B_CRC_DONE,
81 	PIPE_A_ODD_FIELD,
82 	PIPE_B_ODD_FIELD,
83 	PIPE_A_EVEN_FIELD,
84 	PIPE_B_EVEN_FIELD,
85 	PIPE_A_LINE_COMPARE,
86 	PIPE_B_LINE_COMPARE,
87 	PIPE_C_LINE_COMPARE,
88 	PIPE_A_VBLANK,
89 	PIPE_B_VBLANK,
90 	PIPE_C_VBLANK,
91 	PIPE_A_VSYNC,
92 	PIPE_B_VSYNC,
93 	PIPE_C_VSYNC,
94 	PRIMARY_A_FLIP_DONE,
95 	PRIMARY_B_FLIP_DONE,
96 	PRIMARY_C_FLIP_DONE,
97 	SPRITE_A_FLIP_DONE,
98 	SPRITE_B_FLIP_DONE,
99 	SPRITE_C_FLIP_DONE,
100 
101 	PCU_THERMAL,
102 	PCU_PCODE2DRIVER_MAILBOX,
103 
104 	DPST_PHASE_IN,
105 	DPST_HISTOGRAM,
106 	GSE,
107 	DP_A_HOTPLUG,
108 	AUX_CHANNEL_A,
109 	PERF_COUNTER,
110 	POISON,
111 	GTT_FAULT,
112 	ERROR_INTERRUPT_COMBINED,
113 
114 	FDI_RX_INTERRUPTS_TRANSCODER_A,
115 	AUDIO_CP_CHANGE_TRANSCODER_A,
116 	AUDIO_CP_REQUEST_TRANSCODER_A,
117 	FDI_RX_INTERRUPTS_TRANSCODER_B,
118 	AUDIO_CP_CHANGE_TRANSCODER_B,
119 	AUDIO_CP_REQUEST_TRANSCODER_B,
120 	FDI_RX_INTERRUPTS_TRANSCODER_C,
121 	AUDIO_CP_CHANGE_TRANSCODER_C,
122 	AUDIO_CP_REQUEST_TRANSCODER_C,
123 	ERR_AND_DBG,
124 	GMBUS,
125 	SDVO_B_HOTPLUG,
126 	CRT_HOTPLUG,
127 	DP_B_HOTPLUG,
128 	DP_C_HOTPLUG,
129 	DP_D_HOTPLUG,
130 	AUX_CHANNEL_B,
131 	AUX_CHANNEL_C,
132 	AUX_CHANNEL_D,
133 	AUDIO_POWER_STATE_CHANGE_B,
134 	AUDIO_POWER_STATE_CHANGE_C,
135 	AUDIO_POWER_STATE_CHANGE_D,
136 
137 	INTEL_GVT_EVENT_RESERVED,
138 	INTEL_GVT_EVENT_MAX,
139 };
140 
141 struct intel_gvt_irq;
142 struct intel_gvt;
143 struct intel_vgpu;
144 
145 typedef void (*gvt_event_virt_handler_t)(struct intel_gvt_irq *irq,
146 	enum intel_gvt_event_type event, struct intel_vgpu *vgpu);
147 
148 struct intel_gvt_irq_ops {
149 	void (*init_irq)(struct intel_gvt_irq *irq);
150 	void (*check_pending_irq)(struct intel_vgpu *vgpu);
151 };
152 
153 /* the list of physical interrupt control register groups */
154 enum intel_gvt_irq_type {
155 	INTEL_GVT_IRQ_INFO_GT,
156 	INTEL_GVT_IRQ_INFO_DPY,
157 	INTEL_GVT_IRQ_INFO_PCH,
158 	INTEL_GVT_IRQ_INFO_PM,
159 
160 	INTEL_GVT_IRQ_INFO_MASTER,
161 	INTEL_GVT_IRQ_INFO_GT0,
162 	INTEL_GVT_IRQ_INFO_GT1,
163 	INTEL_GVT_IRQ_INFO_GT2,
164 	INTEL_GVT_IRQ_INFO_GT3,
165 	INTEL_GVT_IRQ_INFO_DE_PIPE_A,
166 	INTEL_GVT_IRQ_INFO_DE_PIPE_B,
167 	INTEL_GVT_IRQ_INFO_DE_PIPE_C,
168 	INTEL_GVT_IRQ_INFO_DE_PORT,
169 	INTEL_GVT_IRQ_INFO_DE_MISC,
170 	INTEL_GVT_IRQ_INFO_AUD,
171 	INTEL_GVT_IRQ_INFO_PCU,
172 
173 	INTEL_GVT_IRQ_INFO_MAX,
174 };
175 
176 #define INTEL_GVT_IRQ_BITWIDTH	32
177 
178 /* device specific interrupt bit definitions */
179 struct intel_gvt_irq_info {
180 	char *name;
181 	i915_reg_t reg_base;
182 	enum intel_gvt_event_type bit_to_event[INTEL_GVT_IRQ_BITWIDTH];
183 	unsigned long warned;
184 	int group;
185 	DECLARE_BITMAP(downstream_irq_bitmap, INTEL_GVT_IRQ_BITWIDTH);
186 	bool has_upstream_irq;
187 };
188 
189 /* per-event information */
190 struct intel_gvt_event_info {
191 	int bit;				/* map to register bit */
192 	int policy;				/* forwarding policy */
193 	struct intel_gvt_irq_info *info;	/* register info */
194 	gvt_event_virt_handler_t v_handler;	/* for v_event */
195 };
196 
197 struct intel_gvt_irq_map {
198 	int up_irq_group;
199 	int up_irq_bit;
200 	int down_irq_group;
201 	u32 down_irq_bitmask;
202 };
203 
204 /* structure containing device specific IRQ state */
205 struct intel_gvt_irq {
206 	const struct intel_gvt_irq_ops *ops;
207 	struct intel_gvt_irq_info *info[INTEL_GVT_IRQ_INFO_MAX];
208 	DECLARE_BITMAP(irq_info_bitmap, INTEL_GVT_IRQ_INFO_MAX);
209 	struct intel_gvt_event_info events[INTEL_GVT_EVENT_MAX];
210 	DECLARE_BITMAP(pending_events, INTEL_GVT_EVENT_MAX);
211 	struct intel_gvt_irq_map *irq_map;
212 };
213 
214 int intel_gvt_init_irq(struct intel_gvt *gvt);
215 
216 void intel_vgpu_trigger_virtual_event(struct intel_vgpu *vgpu,
217 	enum intel_gvt_event_type event);
218 
219 int intel_vgpu_reg_iir_handler(struct intel_vgpu *vgpu, unsigned int reg,
220 	void *p_data, unsigned int bytes);
221 int intel_vgpu_reg_ier_handler(struct intel_vgpu *vgpu,
222 	unsigned int reg, void *p_data, unsigned int bytes);
223 int intel_vgpu_reg_master_irq_handler(struct intel_vgpu *vgpu,
224 	unsigned int reg, void *p_data, unsigned int bytes);
225 int intel_vgpu_reg_imr_handler(struct intel_vgpu *vgpu,
226 	unsigned int reg, void *p_data, unsigned int bytes);
227 
228 int gvt_ring_id_to_pipe_control_notify_event(int ring_id);
229 int gvt_ring_id_to_mi_flush_dw_event(int ring_id);
230 int gvt_ring_id_to_mi_user_interrupt_event(int ring_id);
231 
232 #endif /* _GVT_INTERRUPT_H_ */
233