1 /*
2  * Copyright 2022 Advanced Micro Devices, Inc.
3  *
4  * Permission is hereby granted, free of charge, to any person obtaining a
5  * copy of this software and associated documentation files (the "Software"),
6  * to deal in the Software without restriction, including without limitation
7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8  * and/or sell copies of the Software, and to permit persons to whom the
9  * Software is furnished to do so, subject to the following conditions:
10  *
11  * The above copyright notice and this permission notice shall be included in
12  * all copies or substantial portions of the Software.
13  *
14  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
17  * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18  * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19  * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20  * OTHER DEALINGS IN THE SOFTWARE.
21  *
22  */
23 
24 #ifndef __SMU_V13_0_5_PPSMC_H__
25 #define __SMU_V13_0_5_PPSMC_H__
26 
27 // SMU Response Codes:
28 #define PPSMC_Result_OK                    0x1
29 #define PPSMC_Result_Failed                0xFF
30 #define PPSMC_Result_UnknownCmd            0xFE
31 #define PPSMC_Result_CmdRejectedPrereq     0xFD
32 #define PPSMC_Result_CmdRejectedBusy       0xFC
33 
34 
35 // Message Definitions:
36 #define PPSMC_MSG_TestMessage               1
37 #define PPSMC_MSG_GetSmuVersion             2
38 #define PPSMC_MSG_EnableGfxOff              3  ///< Enable GFXOFF
39 #define PPSMC_MSG_DisableGfxOff             4  ///< Disable GFXOFF
40 #define PPSMC_MSG_PowerDownVcn              5  ///< Power down VCN
41 #define PPSMC_MSG_PowerUpVcn                6  ///< Power up VCN; VCN is power gated by default
42 #define PPSMC_MSG_SetHardMinVcn             7  ///< For wireless display
43 #define PPSMC_MSG_SetSoftMinGfxclk          8  ///< Set SoftMin for GFXCLK, argument is frequency in MHz
44 #define PPSMC_MSG_Spare0                    9  ///< Spare
45 #define PPSMC_MSG_GfxDeviceDriverReset      10 ///< Request GFX mode 2 reset
46 #define PPSMC_MSG_SetDriverDramAddrHigh     11 ///< Set high 32 bits of DRAM address for Driver table transfer
47 #define PPSMC_MSG_SetDriverDramAddrLow      12 ///< Set low 32 bits of DRAM address for Driver table transfer
48 #define PPSMC_MSG_TransferTableSmu2Dram     13 ///< Transfer driver interface table from PMFW SRAM to DRAM
49 #define PPSMC_MSG_TransferTableDram2Smu     14 ///< Transfer driver interface table from DRAM to PMFW SRAM
50 #define PPSMC_MSG_GetGfxclkFrequency        15 ///< Get GFX clock frequency
51 #define PPSMC_MSG_GetEnabledSmuFeatures     16 ///< Get enabled features in PMFW
52 #define PPSMC_MSG_SetSoftMaxVcn             17 ///< Set soft max for VCN clocks (VCLK and DCLK)
53 #define PPSMC_MSG_PowerDownJpeg             18 ///< Power down Jpeg
54 #define PPSMC_MSG_PowerUpJpeg               19 ///< Power up Jpeg; VCN is power gated by default
55 #define PPSMC_MSG_SetSoftMaxGfxClk          20
56 #define PPSMC_MSG_SetHardMinGfxClk          21 ///< Set hard min for GFX CLK
57 #define PPSMC_MSG_AllowGfxOff               22 ///< Inform PMFW of allowing GFXOFF entry
58 #define PPSMC_MSG_DisallowGfxOff            23 ///< Inform PMFW of disallowing GFXOFF entry
59 #define PPSMC_MSG_SetSoftMinVcn             24 ///< Set soft min for VCN clocks (VCLK and DCLK)
60 #define PPSMC_MSG_GetDriverIfVersion        25 ///< Get PMFW_DRIVER_IF version
61 #define PPSMC_MSG_PrepareMp1ForUnload        26 ///< Prepare PMFW for GFX driver unload
62 #define PPSMC_Message_Count                 27
63 
64 /** @enum Mode_Reset_e
65 * Mode reset type, argument for PPSMC_MSG_GfxDeviceDriverReset
66 */
67 typedef enum {
68   MODE1_RESET = 1,  ///< Mode reset type 1
69   MODE2_RESET = 2   ///< Mode reset type 2
70 } Mode_Reset_e;
71 /** @}*/
72 
73 #endif
74 
75