1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * Copyright (C) 2012,2013 - ARM Ltd
4 * Author: Marc Zyngier <marc.zyngier@arm.com>
5 *
6 * Derived from arch/arm/kvm/coproc.c:
7 * Copyright (C) 2012 - Virtual Open Systems and Columbia University
8 * Authors: Rusty Russell <rusty@rustcorp.com.au>
9 * Christoffer Dall <c.dall@virtualopensystems.com>
10 */
11
12 #include <linux/bitfield.h>
13 #include <linux/bsearch.h>
14 #include <linux/cacheinfo.h>
15 #include <linux/kvm_host.h>
16 #include <linux/mm.h>
17 #include <linux/printk.h>
18 #include <linux/uaccess.h>
19
20 #include <asm/cacheflush.h>
21 #include <asm/cputype.h>
22 #include <asm/debug-monitors.h>
23 #include <asm/esr.h>
24 #include <asm/kvm_arm.h>
25 #include <asm/kvm_emulate.h>
26 #include <asm/kvm_hyp.h>
27 #include <asm/kvm_mmu.h>
28 #include <asm/kvm_nested.h>
29 #include <asm/perf_event.h>
30 #include <asm/sysreg.h>
31
32 #include <trace/events/kvm.h>
33
34 #include "sys_regs.h"
35 #include "vgic/vgic.h"
36
37 #include "trace.h"
38
39 /*
40 * For AArch32, we only take care of what is being trapped. Anything
41 * that has to do with init and userspace access has to go via the
42 * 64bit interface.
43 */
44
45 static u64 sys_reg_to_index(const struct sys_reg_desc *reg);
46 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
47 u64 val);
48
read_from_write_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)49 static bool read_from_write_only(struct kvm_vcpu *vcpu,
50 struct sys_reg_params *params,
51 const struct sys_reg_desc *r)
52 {
53 WARN_ONCE(1, "Unexpected sys_reg read to write-only register\n");
54 print_sys_reg_instr(params);
55 kvm_inject_undefined(vcpu);
56 return false;
57 }
58
write_to_read_only(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)59 static bool write_to_read_only(struct kvm_vcpu *vcpu,
60 struct sys_reg_params *params,
61 const struct sys_reg_desc *r)
62 {
63 WARN_ONCE(1, "Unexpected sys_reg write to read-only register\n");
64 print_sys_reg_instr(params);
65 kvm_inject_undefined(vcpu);
66 return false;
67 }
68
vcpu_read_sys_reg(const struct kvm_vcpu * vcpu,int reg)69 u64 vcpu_read_sys_reg(const struct kvm_vcpu *vcpu, int reg)
70 {
71 u64 val = 0x8badf00d8badf00d;
72
73 if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) &&
74 __vcpu_read_sys_reg_from_cpu(reg, &val))
75 return val;
76
77 return __vcpu_sys_reg(vcpu, reg);
78 }
79
vcpu_write_sys_reg(struct kvm_vcpu * vcpu,u64 val,int reg)80 void vcpu_write_sys_reg(struct kvm_vcpu *vcpu, u64 val, int reg)
81 {
82 if (vcpu_get_flag(vcpu, SYSREGS_ON_CPU) &&
83 __vcpu_write_sys_reg_to_cpu(val, reg))
84 return;
85
86 __vcpu_sys_reg(vcpu, reg) = val;
87 }
88
89 /* CSSELR values; used to index KVM_REG_ARM_DEMUX_ID_CCSIDR */
90 #define CSSELR_MAX 14
91
92 /*
93 * Returns the minimum line size for the selected cache, expressed as
94 * Log2(bytes).
95 */
get_min_cache_line_size(bool icache)96 static u8 get_min_cache_line_size(bool icache)
97 {
98 u64 ctr = read_sanitised_ftr_reg(SYS_CTR_EL0);
99 u8 field;
100
101 if (icache)
102 field = SYS_FIELD_GET(CTR_EL0, IminLine, ctr);
103 else
104 field = SYS_FIELD_GET(CTR_EL0, DminLine, ctr);
105
106 /*
107 * Cache line size is represented as Log2(words) in CTR_EL0.
108 * Log2(bytes) can be derived with the following:
109 *
110 * Log2(words) + 2 = Log2(bytes / 4) + 2
111 * = Log2(bytes) - 2 + 2
112 * = Log2(bytes)
113 */
114 return field + 2;
115 }
116
117 /* Which cache CCSIDR represents depends on CSSELR value. */
get_ccsidr(struct kvm_vcpu * vcpu,u32 csselr)118 static u32 get_ccsidr(struct kvm_vcpu *vcpu, u32 csselr)
119 {
120 u8 line_size;
121
122 if (vcpu->arch.ccsidr)
123 return vcpu->arch.ccsidr[csselr];
124
125 line_size = get_min_cache_line_size(csselr & CSSELR_EL1_InD);
126
127 /*
128 * Fabricate a CCSIDR value as the overriding value does not exist.
129 * The real CCSIDR value will not be used as it can vary by the
130 * physical CPU which the vcpu currently resides in.
131 *
132 * The line size is determined with get_min_cache_line_size(), which
133 * should be valid for all CPUs even if they have different cache
134 * configuration.
135 *
136 * The associativity bits are cleared, meaning the geometry of all data
137 * and unified caches (which are guaranteed to be PIPT and thus
138 * non-aliasing) are 1 set and 1 way.
139 * Guests should not be doing cache operations by set/way at all, and
140 * for this reason, we trap them and attempt to infer the intent, so
141 * that we can flush the entire guest's address space at the appropriate
142 * time. The exposed geometry minimizes the number of the traps.
143 * [If guests should attempt to infer aliasing properties from the
144 * geometry (which is not permitted by the architecture), they would
145 * only do so for virtually indexed caches.]
146 *
147 * We don't check if the cache level exists as it is allowed to return
148 * an UNKNOWN value if not.
149 */
150 return SYS_FIELD_PREP(CCSIDR_EL1, LineSize, line_size - 4);
151 }
152
set_ccsidr(struct kvm_vcpu * vcpu,u32 csselr,u32 val)153 static int set_ccsidr(struct kvm_vcpu *vcpu, u32 csselr, u32 val)
154 {
155 u8 line_size = FIELD_GET(CCSIDR_EL1_LineSize, val) + 4;
156 u32 *ccsidr = vcpu->arch.ccsidr;
157 u32 i;
158
159 if ((val & CCSIDR_EL1_RES0) ||
160 line_size < get_min_cache_line_size(csselr & CSSELR_EL1_InD))
161 return -EINVAL;
162
163 if (!ccsidr) {
164 if (val == get_ccsidr(vcpu, csselr))
165 return 0;
166
167 ccsidr = kmalloc_array(CSSELR_MAX, sizeof(u32), GFP_KERNEL_ACCOUNT);
168 if (!ccsidr)
169 return -ENOMEM;
170
171 for (i = 0; i < CSSELR_MAX; i++)
172 ccsidr[i] = get_ccsidr(vcpu, i);
173
174 vcpu->arch.ccsidr = ccsidr;
175 }
176
177 ccsidr[csselr] = val;
178
179 return 0;
180 }
181
access_rw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)182 static bool access_rw(struct kvm_vcpu *vcpu,
183 struct sys_reg_params *p,
184 const struct sys_reg_desc *r)
185 {
186 if (p->is_write)
187 vcpu_write_sys_reg(vcpu, p->regval, r->reg);
188 else
189 p->regval = vcpu_read_sys_reg(vcpu, r->reg);
190
191 return true;
192 }
193
194 /*
195 * See note at ARMv7 ARM B1.14.4 (TL;DR: S/W ops are not easily virtualized).
196 */
access_dcsw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)197 static bool access_dcsw(struct kvm_vcpu *vcpu,
198 struct sys_reg_params *p,
199 const struct sys_reg_desc *r)
200 {
201 if (!p->is_write)
202 return read_from_write_only(vcpu, p, r);
203
204 /*
205 * Only track S/W ops if we don't have FWB. It still indicates
206 * that the guest is a bit broken (S/W operations should only
207 * be done by firmware, knowing that there is only a single
208 * CPU left in the system, and certainly not from non-secure
209 * software).
210 */
211 if (!cpus_have_const_cap(ARM64_HAS_STAGE2_FWB))
212 kvm_set_way_flush(vcpu);
213
214 return true;
215 }
216
access_dcgsw(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)217 static bool access_dcgsw(struct kvm_vcpu *vcpu,
218 struct sys_reg_params *p,
219 const struct sys_reg_desc *r)
220 {
221 if (!kvm_has_mte(vcpu->kvm)) {
222 kvm_inject_undefined(vcpu);
223 return false;
224 }
225
226 /* Treat MTE S/W ops as we treat the classic ones: with contempt */
227 return access_dcsw(vcpu, p, r);
228 }
229
get_access_mask(const struct sys_reg_desc * r,u64 * mask,u64 * shift)230 static void get_access_mask(const struct sys_reg_desc *r, u64 *mask, u64 *shift)
231 {
232 switch (r->aarch32_map) {
233 case AA32_LO:
234 *mask = GENMASK_ULL(31, 0);
235 *shift = 0;
236 break;
237 case AA32_HI:
238 *mask = GENMASK_ULL(63, 32);
239 *shift = 32;
240 break;
241 default:
242 *mask = GENMASK_ULL(63, 0);
243 *shift = 0;
244 break;
245 }
246 }
247
248 /*
249 * Generic accessor for VM registers. Only called as long as HCR_TVM
250 * is set. If the guest enables the MMU, we stop trapping the VM
251 * sys_regs and leave it in complete control of the caches.
252 */
access_vm_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)253 static bool access_vm_reg(struct kvm_vcpu *vcpu,
254 struct sys_reg_params *p,
255 const struct sys_reg_desc *r)
256 {
257 bool was_enabled = vcpu_has_cache_enabled(vcpu);
258 u64 val, mask, shift;
259
260 BUG_ON(!p->is_write);
261
262 get_access_mask(r, &mask, &shift);
263
264 if (~mask) {
265 val = vcpu_read_sys_reg(vcpu, r->reg);
266 val &= ~mask;
267 } else {
268 val = 0;
269 }
270
271 val |= (p->regval & (mask >> shift)) << shift;
272 vcpu_write_sys_reg(vcpu, val, r->reg);
273
274 kvm_toggle_cache(vcpu, was_enabled);
275 return true;
276 }
277
access_actlr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)278 static bool access_actlr(struct kvm_vcpu *vcpu,
279 struct sys_reg_params *p,
280 const struct sys_reg_desc *r)
281 {
282 u64 mask, shift;
283
284 if (p->is_write)
285 return ignore_write(vcpu, p);
286
287 get_access_mask(r, &mask, &shift);
288 p->regval = (vcpu_read_sys_reg(vcpu, r->reg) & mask) >> shift;
289
290 return true;
291 }
292
293 /*
294 * Trap handler for the GICv3 SGI generation system register.
295 * Forward the request to the VGIC emulation.
296 * The cp15_64 code makes sure this automatically works
297 * for both AArch64 and AArch32 accesses.
298 */
access_gic_sgi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)299 static bool access_gic_sgi(struct kvm_vcpu *vcpu,
300 struct sys_reg_params *p,
301 const struct sys_reg_desc *r)
302 {
303 bool g1;
304
305 if (!kvm_has_gicv3(vcpu->kvm)) {
306 kvm_inject_undefined(vcpu);
307 return false;
308 }
309
310 if (!p->is_write)
311 return read_from_write_only(vcpu, p, r);
312
313 /*
314 * In a system where GICD_CTLR.DS=1, a ICC_SGI0R_EL1 access generates
315 * Group0 SGIs only, while ICC_SGI1R_EL1 can generate either group,
316 * depending on the SGI configuration. ICC_ASGI1R_EL1 is effectively
317 * equivalent to ICC_SGI0R_EL1, as there is no "alternative" secure
318 * group.
319 */
320 if (p->Op0 == 0) { /* AArch32 */
321 switch (p->Op1) {
322 default: /* Keep GCC quiet */
323 case 0: /* ICC_SGI1R */
324 g1 = true;
325 break;
326 case 1: /* ICC_ASGI1R */
327 case 2: /* ICC_SGI0R */
328 g1 = false;
329 break;
330 }
331 } else { /* AArch64 */
332 switch (p->Op2) {
333 default: /* Keep GCC quiet */
334 case 5: /* ICC_SGI1R_EL1 */
335 g1 = true;
336 break;
337 case 6: /* ICC_ASGI1R_EL1 */
338 case 7: /* ICC_SGI0R_EL1 */
339 g1 = false;
340 break;
341 }
342 }
343
344 vgic_v3_dispatch_sgi(vcpu, p->regval, g1);
345
346 return true;
347 }
348
access_gic_sre(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)349 static bool access_gic_sre(struct kvm_vcpu *vcpu,
350 struct sys_reg_params *p,
351 const struct sys_reg_desc *r)
352 {
353 if (p->is_write)
354 return ignore_write(vcpu, p);
355
356 p->regval = vcpu->arch.vgic_cpu.vgic_v3.vgic_sre;
357 return true;
358 }
359
trap_raz_wi(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)360 static bool trap_raz_wi(struct kvm_vcpu *vcpu,
361 struct sys_reg_params *p,
362 const struct sys_reg_desc *r)
363 {
364 if (p->is_write)
365 return ignore_write(vcpu, p);
366 else
367 return read_zero(vcpu, p);
368 }
369
trap_undef(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)370 static bool trap_undef(struct kvm_vcpu *vcpu,
371 struct sys_reg_params *p,
372 const struct sys_reg_desc *r)
373 {
374 kvm_inject_undefined(vcpu);
375 return false;
376 }
377
378 /*
379 * ARMv8.1 mandates at least a trivial LORegion implementation, where all the
380 * RW registers are RES0 (which we can implement as RAZ/WI). On an ARMv8.0
381 * system, these registers should UNDEF. LORID_EL1 being a RO register, we
382 * treat it separately.
383 */
trap_loregion(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)384 static bool trap_loregion(struct kvm_vcpu *vcpu,
385 struct sys_reg_params *p,
386 const struct sys_reg_desc *r)
387 {
388 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64MMFR1_EL1);
389 u32 sr = reg_to_encoding(r);
390
391 if (!(val & (0xfUL << ID_AA64MMFR1_EL1_LO_SHIFT))) {
392 kvm_inject_undefined(vcpu);
393 return false;
394 }
395
396 if (p->is_write && sr == SYS_LORID_EL1)
397 return write_to_read_only(vcpu, p, r);
398
399 return trap_raz_wi(vcpu, p, r);
400 }
401
trap_oslar_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)402 static bool trap_oslar_el1(struct kvm_vcpu *vcpu,
403 struct sys_reg_params *p,
404 const struct sys_reg_desc *r)
405 {
406 u64 oslsr;
407
408 if (!p->is_write)
409 return read_from_write_only(vcpu, p, r);
410
411 /* Forward the OSLK bit to OSLSR */
412 oslsr = __vcpu_sys_reg(vcpu, OSLSR_EL1) & ~OSLSR_EL1_OSLK;
413 if (p->regval & OSLAR_EL1_OSLK)
414 oslsr |= OSLSR_EL1_OSLK;
415
416 __vcpu_sys_reg(vcpu, OSLSR_EL1) = oslsr;
417 return true;
418 }
419
trap_oslsr_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)420 static bool trap_oslsr_el1(struct kvm_vcpu *vcpu,
421 struct sys_reg_params *p,
422 const struct sys_reg_desc *r)
423 {
424 if (p->is_write)
425 return write_to_read_only(vcpu, p, r);
426
427 p->regval = __vcpu_sys_reg(vcpu, r->reg);
428 return true;
429 }
430
set_oslsr_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)431 static int set_oslsr_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
432 u64 val)
433 {
434 /*
435 * The only modifiable bit is the OSLK bit. Refuse the write if
436 * userspace attempts to change any other bit in the register.
437 */
438 if ((val ^ rd->val) & ~OSLSR_EL1_OSLK)
439 return -EINVAL;
440
441 __vcpu_sys_reg(vcpu, rd->reg) = val;
442 return 0;
443 }
444
trap_dbgauthstatus_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)445 static bool trap_dbgauthstatus_el1(struct kvm_vcpu *vcpu,
446 struct sys_reg_params *p,
447 const struct sys_reg_desc *r)
448 {
449 if (p->is_write) {
450 return ignore_write(vcpu, p);
451 } else {
452 p->regval = read_sysreg(dbgauthstatus_el1);
453 return true;
454 }
455 }
456
457 /*
458 * We want to avoid world-switching all the DBG registers all the
459 * time:
460 *
461 * - If we've touched any debug register, it is likely that we're
462 * going to touch more of them. It then makes sense to disable the
463 * traps and start doing the save/restore dance
464 * - If debug is active (DBG_MDSCR_KDE or DBG_MDSCR_MDE set), it is
465 * then mandatory to save/restore the registers, as the guest
466 * depends on them.
467 *
468 * For this, we use a DIRTY bit, indicating the guest has modified the
469 * debug registers, used as follow:
470 *
471 * On guest entry:
472 * - If the dirty bit is set (because we're coming back from trapping),
473 * disable the traps, save host registers, restore guest registers.
474 * - If debug is actively in use (DBG_MDSCR_KDE or DBG_MDSCR_MDE set),
475 * set the dirty bit, disable the traps, save host registers,
476 * restore guest registers.
477 * - Otherwise, enable the traps
478 *
479 * On guest exit:
480 * - If the dirty bit is set, save guest registers, restore host
481 * registers and clear the dirty bit. This ensure that the host can
482 * now use the debug registers.
483 */
trap_debug_regs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)484 static bool trap_debug_regs(struct kvm_vcpu *vcpu,
485 struct sys_reg_params *p,
486 const struct sys_reg_desc *r)
487 {
488 access_rw(vcpu, p, r);
489 if (p->is_write)
490 vcpu_set_flag(vcpu, DEBUG_DIRTY);
491
492 trace_trap_reg(__func__, r->reg, p->is_write, p->regval);
493
494 return true;
495 }
496
497 /*
498 * reg_to_dbg/dbg_to_reg
499 *
500 * A 32 bit write to a debug register leave top bits alone
501 * A 32 bit read from a debug register only returns the bottom bits
502 *
503 * All writes will set the DEBUG_DIRTY flag to ensure the hyp code
504 * switches between host and guest values in future.
505 */
reg_to_dbg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd,u64 * dbg_reg)506 static void reg_to_dbg(struct kvm_vcpu *vcpu,
507 struct sys_reg_params *p,
508 const struct sys_reg_desc *rd,
509 u64 *dbg_reg)
510 {
511 u64 mask, shift, val;
512
513 get_access_mask(rd, &mask, &shift);
514
515 val = *dbg_reg;
516 val &= ~mask;
517 val |= (p->regval & (mask >> shift)) << shift;
518 *dbg_reg = val;
519
520 vcpu_set_flag(vcpu, DEBUG_DIRTY);
521 }
522
dbg_to_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd,u64 * dbg_reg)523 static void dbg_to_reg(struct kvm_vcpu *vcpu,
524 struct sys_reg_params *p,
525 const struct sys_reg_desc *rd,
526 u64 *dbg_reg)
527 {
528 u64 mask, shift;
529
530 get_access_mask(rd, &mask, &shift);
531 p->regval = (*dbg_reg & mask) >> shift;
532 }
533
trap_bvr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)534 static bool trap_bvr(struct kvm_vcpu *vcpu,
535 struct sys_reg_params *p,
536 const struct sys_reg_desc *rd)
537 {
538 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
539
540 if (p->is_write)
541 reg_to_dbg(vcpu, p, rd, dbg_reg);
542 else
543 dbg_to_reg(vcpu, p, rd, dbg_reg);
544
545 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
546
547 return true;
548 }
549
set_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)550 static int set_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
551 u64 val)
552 {
553 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = val;
554 return 0;
555 }
556
get_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)557 static int get_bvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
558 u64 *val)
559 {
560 *val = vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm];
561 return 0;
562 }
563
reset_bvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)564 static u64 reset_bvr(struct kvm_vcpu *vcpu,
565 const struct sys_reg_desc *rd)
566 {
567 vcpu->arch.vcpu_debug_state.dbg_bvr[rd->CRm] = rd->val;
568 return rd->val;
569 }
570
trap_bcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)571 static bool trap_bcr(struct kvm_vcpu *vcpu,
572 struct sys_reg_params *p,
573 const struct sys_reg_desc *rd)
574 {
575 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
576
577 if (p->is_write)
578 reg_to_dbg(vcpu, p, rd, dbg_reg);
579 else
580 dbg_to_reg(vcpu, p, rd, dbg_reg);
581
582 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
583
584 return true;
585 }
586
set_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)587 static int set_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
588 u64 val)
589 {
590 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = val;
591 return 0;
592 }
593
get_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)594 static int get_bcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
595 u64 *val)
596 {
597 *val = vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm];
598 return 0;
599 }
600
reset_bcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)601 static u64 reset_bcr(struct kvm_vcpu *vcpu,
602 const struct sys_reg_desc *rd)
603 {
604 vcpu->arch.vcpu_debug_state.dbg_bcr[rd->CRm] = rd->val;
605 return rd->val;
606 }
607
trap_wvr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)608 static bool trap_wvr(struct kvm_vcpu *vcpu,
609 struct sys_reg_params *p,
610 const struct sys_reg_desc *rd)
611 {
612 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
613
614 if (p->is_write)
615 reg_to_dbg(vcpu, p, rd, dbg_reg);
616 else
617 dbg_to_reg(vcpu, p, rd, dbg_reg);
618
619 trace_trap_reg(__func__, rd->CRm, p->is_write,
620 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm]);
621
622 return true;
623 }
624
set_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)625 static int set_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
626 u64 val)
627 {
628 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = val;
629 return 0;
630 }
631
get_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)632 static int get_wvr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
633 u64 *val)
634 {
635 *val = vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm];
636 return 0;
637 }
638
reset_wvr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)639 static u64 reset_wvr(struct kvm_vcpu *vcpu,
640 const struct sys_reg_desc *rd)
641 {
642 vcpu->arch.vcpu_debug_state.dbg_wvr[rd->CRm] = rd->val;
643 return rd->val;
644 }
645
trap_wcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * rd)646 static bool trap_wcr(struct kvm_vcpu *vcpu,
647 struct sys_reg_params *p,
648 const struct sys_reg_desc *rd)
649 {
650 u64 *dbg_reg = &vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
651
652 if (p->is_write)
653 reg_to_dbg(vcpu, p, rd, dbg_reg);
654 else
655 dbg_to_reg(vcpu, p, rd, dbg_reg);
656
657 trace_trap_reg(__func__, rd->CRm, p->is_write, *dbg_reg);
658
659 return true;
660 }
661
set_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)662 static int set_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
663 u64 val)
664 {
665 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = val;
666 return 0;
667 }
668
get_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)669 static int get_wcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
670 u64 *val)
671 {
672 *val = vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm];
673 return 0;
674 }
675
reset_wcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)676 static u64 reset_wcr(struct kvm_vcpu *vcpu,
677 const struct sys_reg_desc *rd)
678 {
679 vcpu->arch.vcpu_debug_state.dbg_wcr[rd->CRm] = rd->val;
680 return rd->val;
681 }
682
reset_amair_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)683 static u64 reset_amair_el1(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
684 {
685 u64 amair = read_sysreg(amair_el1);
686 vcpu_write_sys_reg(vcpu, amair, AMAIR_EL1);
687 return amair;
688 }
689
reset_actlr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)690 static u64 reset_actlr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
691 {
692 u64 actlr = read_sysreg(actlr_el1);
693 vcpu_write_sys_reg(vcpu, actlr, ACTLR_EL1);
694 return actlr;
695 }
696
reset_mpidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)697 static u64 reset_mpidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
698 {
699 u64 mpidr;
700
701 /*
702 * Map the vcpu_id into the first three affinity level fields of
703 * the MPIDR. We limit the number of VCPUs in level 0 due to a
704 * limitation to 16 CPUs in that level in the ICC_SGIxR registers
705 * of the GICv3 to be able to address each CPU directly when
706 * sending IPIs.
707 */
708 mpidr = (vcpu->vcpu_id & 0x0f) << MPIDR_LEVEL_SHIFT(0);
709 mpidr |= ((vcpu->vcpu_id >> 4) & 0xff) << MPIDR_LEVEL_SHIFT(1);
710 mpidr |= ((vcpu->vcpu_id >> 12) & 0xff) << MPIDR_LEVEL_SHIFT(2);
711 mpidr |= (1ULL << 31);
712 vcpu_write_sys_reg(vcpu, mpidr, MPIDR_EL1);
713
714 return mpidr;
715 }
716
pmu_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)717 static unsigned int pmu_visibility(const struct kvm_vcpu *vcpu,
718 const struct sys_reg_desc *r)
719 {
720 if (kvm_vcpu_has_pmu(vcpu))
721 return 0;
722
723 return REG_HIDDEN;
724 }
725
reset_pmu_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)726 static u64 reset_pmu_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
727 {
728 u64 n, mask = BIT(ARMV8_PMU_CYCLE_IDX);
729
730 /* No PMU available, any PMU reg may UNDEF... */
731 if (!kvm_arm_support_pmu_v3())
732 return 0;
733
734 n = read_sysreg(pmcr_el0) >> ARMV8_PMU_PMCR_N_SHIFT;
735 n &= ARMV8_PMU_PMCR_N_MASK;
736 if (n)
737 mask |= GENMASK(n - 1, 0);
738
739 reset_unknown(vcpu, r);
740 __vcpu_sys_reg(vcpu, r->reg) &= mask;
741
742 return __vcpu_sys_reg(vcpu, r->reg);
743 }
744
reset_pmevcntr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)745 static u64 reset_pmevcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
746 {
747 reset_unknown(vcpu, r);
748 __vcpu_sys_reg(vcpu, r->reg) &= GENMASK(31, 0);
749
750 return __vcpu_sys_reg(vcpu, r->reg);
751 }
752
reset_pmevtyper(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)753 static u64 reset_pmevtyper(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
754 {
755 reset_unknown(vcpu, r);
756 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_EVTYPE_MASK;
757
758 return __vcpu_sys_reg(vcpu, r->reg);
759 }
760
reset_pmselr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)761 static u64 reset_pmselr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
762 {
763 reset_unknown(vcpu, r);
764 __vcpu_sys_reg(vcpu, r->reg) &= ARMV8_PMU_COUNTER_MASK;
765
766 return __vcpu_sys_reg(vcpu, r->reg);
767 }
768
reset_pmcr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)769 static u64 reset_pmcr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
770 {
771 u64 pmcr;
772
773 /* No PMU available, PMCR_EL0 may UNDEF... */
774 if (!kvm_arm_support_pmu_v3())
775 return 0;
776
777 /* Only preserve PMCR_EL0.N, and reset the rest to 0 */
778 pmcr = read_sysreg(pmcr_el0) & (ARMV8_PMU_PMCR_N_MASK << ARMV8_PMU_PMCR_N_SHIFT);
779 if (!kvm_supports_32bit_el0())
780 pmcr |= ARMV8_PMU_PMCR_LC;
781
782 __vcpu_sys_reg(vcpu, r->reg) = pmcr;
783
784 return __vcpu_sys_reg(vcpu, r->reg);
785 }
786
check_pmu_access_disabled(struct kvm_vcpu * vcpu,u64 flags)787 static bool check_pmu_access_disabled(struct kvm_vcpu *vcpu, u64 flags)
788 {
789 u64 reg = __vcpu_sys_reg(vcpu, PMUSERENR_EL0);
790 bool enabled = (reg & flags) || vcpu_mode_priv(vcpu);
791
792 if (!enabled)
793 kvm_inject_undefined(vcpu);
794
795 return !enabled;
796 }
797
pmu_access_el0_disabled(struct kvm_vcpu * vcpu)798 static bool pmu_access_el0_disabled(struct kvm_vcpu *vcpu)
799 {
800 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_EN);
801 }
802
pmu_write_swinc_el0_disabled(struct kvm_vcpu * vcpu)803 static bool pmu_write_swinc_el0_disabled(struct kvm_vcpu *vcpu)
804 {
805 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_SW | ARMV8_PMU_USERENR_EN);
806 }
807
pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu * vcpu)808 static bool pmu_access_cycle_counter_el0_disabled(struct kvm_vcpu *vcpu)
809 {
810 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_CR | ARMV8_PMU_USERENR_EN);
811 }
812
pmu_access_event_counter_el0_disabled(struct kvm_vcpu * vcpu)813 static bool pmu_access_event_counter_el0_disabled(struct kvm_vcpu *vcpu)
814 {
815 return check_pmu_access_disabled(vcpu, ARMV8_PMU_USERENR_ER | ARMV8_PMU_USERENR_EN);
816 }
817
access_pmcr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)818 static bool access_pmcr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
819 const struct sys_reg_desc *r)
820 {
821 u64 val;
822
823 if (pmu_access_el0_disabled(vcpu))
824 return false;
825
826 if (p->is_write) {
827 /*
828 * Only update writeable bits of PMCR (continuing into
829 * kvm_pmu_handle_pmcr() as well)
830 */
831 val = __vcpu_sys_reg(vcpu, PMCR_EL0);
832 val &= ~ARMV8_PMU_PMCR_MASK;
833 val |= p->regval & ARMV8_PMU_PMCR_MASK;
834 if (!kvm_supports_32bit_el0())
835 val |= ARMV8_PMU_PMCR_LC;
836 kvm_pmu_handle_pmcr(vcpu, val);
837 } else {
838 /* PMCR.P & PMCR.C are RAZ */
839 val = __vcpu_sys_reg(vcpu, PMCR_EL0)
840 & ~(ARMV8_PMU_PMCR_P | ARMV8_PMU_PMCR_C);
841 p->regval = val;
842 }
843
844 return true;
845 }
846
access_pmselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)847 static bool access_pmselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
848 const struct sys_reg_desc *r)
849 {
850 if (pmu_access_event_counter_el0_disabled(vcpu))
851 return false;
852
853 if (p->is_write)
854 __vcpu_sys_reg(vcpu, PMSELR_EL0) = p->regval;
855 else
856 /* return PMSELR.SEL field */
857 p->regval = __vcpu_sys_reg(vcpu, PMSELR_EL0)
858 & ARMV8_PMU_COUNTER_MASK;
859
860 return true;
861 }
862
access_pmceid(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)863 static bool access_pmceid(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
864 const struct sys_reg_desc *r)
865 {
866 u64 pmceid, mask, shift;
867
868 BUG_ON(p->is_write);
869
870 if (pmu_access_el0_disabled(vcpu))
871 return false;
872
873 get_access_mask(r, &mask, &shift);
874
875 pmceid = kvm_pmu_get_pmceid(vcpu, (p->Op2 & 1));
876 pmceid &= mask;
877 pmceid >>= shift;
878
879 p->regval = pmceid;
880
881 return true;
882 }
883
pmu_counter_idx_valid(struct kvm_vcpu * vcpu,u64 idx)884 static bool pmu_counter_idx_valid(struct kvm_vcpu *vcpu, u64 idx)
885 {
886 u64 pmcr, val;
887
888 pmcr = __vcpu_sys_reg(vcpu, PMCR_EL0);
889 val = (pmcr >> ARMV8_PMU_PMCR_N_SHIFT) & ARMV8_PMU_PMCR_N_MASK;
890 if (idx >= val && idx != ARMV8_PMU_CYCLE_IDX) {
891 kvm_inject_undefined(vcpu);
892 return false;
893 }
894
895 return true;
896 }
897
get_pmu_evcntr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r,u64 * val)898 static int get_pmu_evcntr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r,
899 u64 *val)
900 {
901 u64 idx;
902
903 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 0)
904 /* PMCCNTR_EL0 */
905 idx = ARMV8_PMU_CYCLE_IDX;
906 else
907 /* PMEVCNTRn_EL0 */
908 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
909
910 *val = kvm_pmu_get_counter_value(vcpu, idx);
911 return 0;
912 }
913
access_pmu_evcntr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)914 static bool access_pmu_evcntr(struct kvm_vcpu *vcpu,
915 struct sys_reg_params *p,
916 const struct sys_reg_desc *r)
917 {
918 u64 idx = ~0UL;
919
920 if (r->CRn == 9 && r->CRm == 13) {
921 if (r->Op2 == 2) {
922 /* PMXEVCNTR_EL0 */
923 if (pmu_access_event_counter_el0_disabled(vcpu))
924 return false;
925
926 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0)
927 & ARMV8_PMU_COUNTER_MASK;
928 } else if (r->Op2 == 0) {
929 /* PMCCNTR_EL0 */
930 if (pmu_access_cycle_counter_el0_disabled(vcpu))
931 return false;
932
933 idx = ARMV8_PMU_CYCLE_IDX;
934 }
935 } else if (r->CRn == 0 && r->CRm == 9) {
936 /* PMCCNTR */
937 if (pmu_access_event_counter_el0_disabled(vcpu))
938 return false;
939
940 idx = ARMV8_PMU_CYCLE_IDX;
941 } else if (r->CRn == 14 && (r->CRm & 12) == 8) {
942 /* PMEVCNTRn_EL0 */
943 if (pmu_access_event_counter_el0_disabled(vcpu))
944 return false;
945
946 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
947 }
948
949 /* Catch any decoding mistake */
950 WARN_ON(idx == ~0UL);
951
952 if (!pmu_counter_idx_valid(vcpu, idx))
953 return false;
954
955 if (p->is_write) {
956 if (pmu_access_el0_disabled(vcpu))
957 return false;
958
959 kvm_pmu_set_counter_value(vcpu, idx, p->regval);
960 } else {
961 p->regval = kvm_pmu_get_counter_value(vcpu, idx);
962 }
963
964 return true;
965 }
966
access_pmu_evtyper(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)967 static bool access_pmu_evtyper(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
968 const struct sys_reg_desc *r)
969 {
970 u64 idx, reg;
971
972 if (pmu_access_el0_disabled(vcpu))
973 return false;
974
975 if (r->CRn == 9 && r->CRm == 13 && r->Op2 == 1) {
976 /* PMXEVTYPER_EL0 */
977 idx = __vcpu_sys_reg(vcpu, PMSELR_EL0) & ARMV8_PMU_COUNTER_MASK;
978 reg = PMEVTYPER0_EL0 + idx;
979 } else if (r->CRn == 14 && (r->CRm & 12) == 12) {
980 idx = ((r->CRm & 3) << 3) | (r->Op2 & 7);
981 if (idx == ARMV8_PMU_CYCLE_IDX)
982 reg = PMCCFILTR_EL0;
983 else
984 /* PMEVTYPERn_EL0 */
985 reg = PMEVTYPER0_EL0 + idx;
986 } else {
987 BUG();
988 }
989
990 if (!pmu_counter_idx_valid(vcpu, idx))
991 return false;
992
993 if (p->is_write) {
994 kvm_pmu_set_counter_event_type(vcpu, p->regval, idx);
995 kvm_vcpu_pmu_restore_guest(vcpu);
996 } else {
997 p->regval = __vcpu_sys_reg(vcpu, reg) & ARMV8_PMU_EVTYPE_MASK;
998 }
999
1000 return true;
1001 }
1002
access_pmcnten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1003 static bool access_pmcnten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1004 const struct sys_reg_desc *r)
1005 {
1006 u64 val, mask;
1007
1008 if (pmu_access_el0_disabled(vcpu))
1009 return false;
1010
1011 mask = kvm_pmu_valid_counter_mask(vcpu);
1012 if (p->is_write) {
1013 val = p->regval & mask;
1014 if (r->Op2 & 0x1) {
1015 /* accessing PMCNTENSET_EL0 */
1016 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) |= val;
1017 kvm_pmu_enable_counter_mask(vcpu, val);
1018 kvm_vcpu_pmu_restore_guest(vcpu);
1019 } else {
1020 /* accessing PMCNTENCLR_EL0 */
1021 __vcpu_sys_reg(vcpu, PMCNTENSET_EL0) &= ~val;
1022 kvm_pmu_disable_counter_mask(vcpu, val);
1023 }
1024 } else {
1025 p->regval = __vcpu_sys_reg(vcpu, PMCNTENSET_EL0);
1026 }
1027
1028 return true;
1029 }
1030
access_pminten(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1031 static bool access_pminten(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1032 const struct sys_reg_desc *r)
1033 {
1034 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
1035
1036 if (check_pmu_access_disabled(vcpu, 0))
1037 return false;
1038
1039 if (p->is_write) {
1040 u64 val = p->regval & mask;
1041
1042 if (r->Op2 & 0x1)
1043 /* accessing PMINTENSET_EL1 */
1044 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) |= val;
1045 else
1046 /* accessing PMINTENCLR_EL1 */
1047 __vcpu_sys_reg(vcpu, PMINTENSET_EL1) &= ~val;
1048 } else {
1049 p->regval = __vcpu_sys_reg(vcpu, PMINTENSET_EL1);
1050 }
1051
1052 return true;
1053 }
1054
access_pmovs(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1055 static bool access_pmovs(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1056 const struct sys_reg_desc *r)
1057 {
1058 u64 mask = kvm_pmu_valid_counter_mask(vcpu);
1059
1060 if (pmu_access_el0_disabled(vcpu))
1061 return false;
1062
1063 if (p->is_write) {
1064 if (r->CRm & 0x2)
1065 /* accessing PMOVSSET_EL0 */
1066 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) |= (p->regval & mask);
1067 else
1068 /* accessing PMOVSCLR_EL0 */
1069 __vcpu_sys_reg(vcpu, PMOVSSET_EL0) &= ~(p->regval & mask);
1070 } else {
1071 p->regval = __vcpu_sys_reg(vcpu, PMOVSSET_EL0);
1072 }
1073
1074 return true;
1075 }
1076
access_pmswinc(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1077 static bool access_pmswinc(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1078 const struct sys_reg_desc *r)
1079 {
1080 u64 mask;
1081
1082 if (!p->is_write)
1083 return read_from_write_only(vcpu, p, r);
1084
1085 if (pmu_write_swinc_el0_disabled(vcpu))
1086 return false;
1087
1088 mask = kvm_pmu_valid_counter_mask(vcpu);
1089 kvm_pmu_software_increment(vcpu, p->regval & mask);
1090 return true;
1091 }
1092
access_pmuserenr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1093 static bool access_pmuserenr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1094 const struct sys_reg_desc *r)
1095 {
1096 if (p->is_write) {
1097 if (!vcpu_mode_priv(vcpu)) {
1098 kvm_inject_undefined(vcpu);
1099 return false;
1100 }
1101
1102 __vcpu_sys_reg(vcpu, PMUSERENR_EL0) =
1103 p->regval & ARMV8_PMU_USERENR_MASK;
1104 } else {
1105 p->regval = __vcpu_sys_reg(vcpu, PMUSERENR_EL0)
1106 & ARMV8_PMU_USERENR_MASK;
1107 }
1108
1109 return true;
1110 }
1111
1112 /* Silly macro to expand the DBG{BCR,BVR,WVR,WCR}n_EL1 registers in one go */
1113 #define DBG_BCR_BVR_WCR_WVR_EL1(n) \
1114 { SYS_DESC(SYS_DBGBVRn_EL1(n)), \
1115 trap_bvr, reset_bvr, 0, 0, get_bvr, set_bvr }, \
1116 { SYS_DESC(SYS_DBGBCRn_EL1(n)), \
1117 trap_bcr, reset_bcr, 0, 0, get_bcr, set_bcr }, \
1118 { SYS_DESC(SYS_DBGWVRn_EL1(n)), \
1119 trap_wvr, reset_wvr, 0, 0, get_wvr, set_wvr }, \
1120 { SYS_DESC(SYS_DBGWCRn_EL1(n)), \
1121 trap_wcr, reset_wcr, 0, 0, get_wcr, set_wcr }
1122
1123 #define PMU_SYS_REG(name) \
1124 SYS_DESC(SYS_##name), .reset = reset_pmu_reg, \
1125 .visibility = pmu_visibility
1126
1127 /* Macro to expand the PMEVCNTRn_EL0 register */
1128 #define PMU_PMEVCNTR_EL0(n) \
1129 { PMU_SYS_REG(PMEVCNTRn_EL0(n)), \
1130 .reset = reset_pmevcntr, .get_user = get_pmu_evcntr, \
1131 .access = access_pmu_evcntr, .reg = (PMEVCNTR0_EL0 + n), }
1132
1133 /* Macro to expand the PMEVTYPERn_EL0 register */
1134 #define PMU_PMEVTYPER_EL0(n) \
1135 { PMU_SYS_REG(PMEVTYPERn_EL0(n)), \
1136 .reset = reset_pmevtyper, \
1137 .access = access_pmu_evtyper, .reg = (PMEVTYPER0_EL0 + n), }
1138
undef_access(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1139 static bool undef_access(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1140 const struct sys_reg_desc *r)
1141 {
1142 kvm_inject_undefined(vcpu);
1143
1144 return false;
1145 }
1146
1147 /* Macro to expand the AMU counter and type registers*/
1148 #define AMU_AMEVCNTR0_EL0(n) { SYS_DESC(SYS_AMEVCNTR0_EL0(n)), undef_access }
1149 #define AMU_AMEVTYPER0_EL0(n) { SYS_DESC(SYS_AMEVTYPER0_EL0(n)), undef_access }
1150 #define AMU_AMEVCNTR1_EL0(n) { SYS_DESC(SYS_AMEVCNTR1_EL0(n)), undef_access }
1151 #define AMU_AMEVTYPER1_EL0(n) { SYS_DESC(SYS_AMEVTYPER1_EL0(n)), undef_access }
1152
ptrauth_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1153 static unsigned int ptrauth_visibility(const struct kvm_vcpu *vcpu,
1154 const struct sys_reg_desc *rd)
1155 {
1156 return vcpu_has_ptrauth(vcpu) ? 0 : REG_HIDDEN;
1157 }
1158
1159 /*
1160 * If we land here on a PtrAuth access, that is because we didn't
1161 * fixup the access on exit by allowing the PtrAuth sysregs. The only
1162 * way this happens is when the guest does not have PtrAuth support
1163 * enabled.
1164 */
1165 #define __PTRAUTH_KEY(k) \
1166 { SYS_DESC(SYS_## k), undef_access, reset_unknown, k, \
1167 .visibility = ptrauth_visibility}
1168
1169 #define PTRAUTH_KEY(k) \
1170 __PTRAUTH_KEY(k ## KEYLO_EL1), \
1171 __PTRAUTH_KEY(k ## KEYHI_EL1)
1172
access_arch_timer(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1173 static bool access_arch_timer(struct kvm_vcpu *vcpu,
1174 struct sys_reg_params *p,
1175 const struct sys_reg_desc *r)
1176 {
1177 enum kvm_arch_timers tmr;
1178 enum kvm_arch_timer_regs treg;
1179 u64 reg = reg_to_encoding(r);
1180
1181 switch (reg) {
1182 case SYS_CNTP_TVAL_EL0:
1183 case SYS_AARCH32_CNTP_TVAL:
1184 tmr = TIMER_PTIMER;
1185 treg = TIMER_REG_TVAL;
1186 break;
1187 case SYS_CNTP_CTL_EL0:
1188 case SYS_AARCH32_CNTP_CTL:
1189 tmr = TIMER_PTIMER;
1190 treg = TIMER_REG_CTL;
1191 break;
1192 case SYS_CNTP_CVAL_EL0:
1193 case SYS_AARCH32_CNTP_CVAL:
1194 tmr = TIMER_PTIMER;
1195 treg = TIMER_REG_CVAL;
1196 break;
1197 case SYS_CNTPCT_EL0:
1198 case SYS_CNTPCTSS_EL0:
1199 case SYS_AARCH32_CNTPCT:
1200 tmr = TIMER_PTIMER;
1201 treg = TIMER_REG_CNT;
1202 break;
1203 default:
1204 print_sys_reg_msg(p, "%s", "Unhandled trapped timer register");
1205 kvm_inject_undefined(vcpu);
1206 return false;
1207 }
1208
1209 if (p->is_write)
1210 kvm_arm_timer_write_sysreg(vcpu, tmr, treg, p->regval);
1211 else
1212 p->regval = kvm_arm_timer_read_sysreg(vcpu, tmr, treg);
1213
1214 return true;
1215 }
1216
kvm_arm64_ftr_safe_value(u32 id,const struct arm64_ftr_bits * ftrp,s64 new,s64 cur)1217 static s64 kvm_arm64_ftr_safe_value(u32 id, const struct arm64_ftr_bits *ftrp,
1218 s64 new, s64 cur)
1219 {
1220 struct arm64_ftr_bits kvm_ftr = *ftrp;
1221
1222 /* Some features have different safe value type in KVM than host features */
1223 switch (id) {
1224 case SYS_ID_AA64DFR0_EL1:
1225 if (kvm_ftr.shift == ID_AA64DFR0_EL1_PMUVer_SHIFT)
1226 kvm_ftr.type = FTR_LOWER_SAFE;
1227 break;
1228 case SYS_ID_DFR0_EL1:
1229 if (kvm_ftr.shift == ID_DFR0_EL1_PerfMon_SHIFT)
1230 kvm_ftr.type = FTR_LOWER_SAFE;
1231 break;
1232 }
1233
1234 return arm64_ftr_safe_value(&kvm_ftr, new, cur);
1235 }
1236
1237 /**
1238 * arm64_check_features() - Check if a feature register value constitutes
1239 * a subset of features indicated by the idreg's KVM sanitised limit.
1240 *
1241 * This function will check if each feature field of @val is the "safe" value
1242 * against idreg's KVM sanitised limit return from reset() callback.
1243 * If a field value in @val is the same as the one in limit, it is always
1244 * considered the safe value regardless For register fields that are not in
1245 * writable, only the value in limit is considered the safe value.
1246 *
1247 * Return: 0 if all the fields are safe. Otherwise, return negative errno.
1248 */
arm64_check_features(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1249 static int arm64_check_features(struct kvm_vcpu *vcpu,
1250 const struct sys_reg_desc *rd,
1251 u64 val)
1252 {
1253 const struct arm64_ftr_reg *ftr_reg;
1254 const struct arm64_ftr_bits *ftrp = NULL;
1255 u32 id = reg_to_encoding(rd);
1256 u64 writable_mask = rd->val;
1257 u64 limit = rd->reset(vcpu, rd);
1258 u64 mask = 0;
1259
1260 /*
1261 * Hidden and unallocated ID registers may not have a corresponding
1262 * struct arm64_ftr_reg. Of course, if the register is RAZ we know the
1263 * only safe value is 0.
1264 */
1265 if (sysreg_visible_as_raz(vcpu, rd))
1266 return val ? -E2BIG : 0;
1267
1268 ftr_reg = get_arm64_ftr_reg(id);
1269 if (!ftr_reg)
1270 return -EINVAL;
1271
1272 ftrp = ftr_reg->ftr_bits;
1273
1274 for (; ftrp && ftrp->width; ftrp++) {
1275 s64 f_val, f_lim, safe_val;
1276 u64 ftr_mask;
1277
1278 ftr_mask = arm64_ftr_mask(ftrp);
1279 if ((ftr_mask & writable_mask) != ftr_mask)
1280 continue;
1281
1282 f_val = arm64_ftr_value(ftrp, val);
1283 f_lim = arm64_ftr_value(ftrp, limit);
1284 mask |= ftr_mask;
1285
1286 if (f_val == f_lim)
1287 safe_val = f_val;
1288 else
1289 safe_val = kvm_arm64_ftr_safe_value(id, ftrp, f_val, f_lim);
1290
1291 if (safe_val != f_val)
1292 return -E2BIG;
1293 }
1294
1295 /* For fields that are not writable, values in limit are the safe values. */
1296 if ((val & ~mask) != (limit & ~mask))
1297 return -E2BIG;
1298
1299 return 0;
1300 }
1301
pmuver_to_perfmon(u8 pmuver)1302 static u8 pmuver_to_perfmon(u8 pmuver)
1303 {
1304 switch (pmuver) {
1305 case ID_AA64DFR0_EL1_PMUVer_IMP:
1306 return ID_DFR0_EL1_PerfMon_PMUv3;
1307 case ID_AA64DFR0_EL1_PMUVer_IMP_DEF:
1308 return ID_DFR0_EL1_PerfMon_IMPDEF;
1309 default:
1310 /* Anything ARMv8.1+ and NI have the same value. For now. */
1311 return pmuver;
1312 }
1313 }
1314
1315 /* Read a sanitised cpufeature ID register by sys_reg_desc */
__kvm_read_sanitised_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1316 static u64 __kvm_read_sanitised_id_reg(const struct kvm_vcpu *vcpu,
1317 const struct sys_reg_desc *r)
1318 {
1319 u32 id = reg_to_encoding(r);
1320 u64 val;
1321
1322 if (sysreg_visible_as_raz(vcpu, r))
1323 return 0;
1324
1325 val = read_sanitised_ftr_reg(id);
1326
1327 switch (id) {
1328 case SYS_ID_AA64PFR1_EL1:
1329 if (!kvm_has_mte(vcpu->kvm))
1330 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_MTE);
1331
1332 val &= ~ARM64_FEATURE_MASK(ID_AA64PFR1_EL1_SME);
1333 break;
1334 case SYS_ID_AA64ISAR1_EL1:
1335 if (!vcpu_has_ptrauth(vcpu))
1336 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_APA) |
1337 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_API) |
1338 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPA) |
1339 ARM64_FEATURE_MASK(ID_AA64ISAR1_EL1_GPI));
1340 break;
1341 case SYS_ID_AA64ISAR2_EL1:
1342 if (!vcpu_has_ptrauth(vcpu))
1343 val &= ~(ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_APA3) |
1344 ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_GPA3));
1345 if (!cpus_have_final_cap(ARM64_HAS_WFXT))
1346 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_WFxT);
1347 val &= ~ARM64_FEATURE_MASK(ID_AA64ISAR2_EL1_MOPS);
1348 break;
1349 case SYS_ID_AA64MMFR2_EL1:
1350 val &= ~ID_AA64MMFR2_EL1_CCIDX_MASK;
1351 break;
1352 case SYS_ID_MMFR4_EL1:
1353 val &= ~ARM64_FEATURE_MASK(ID_MMFR4_EL1_CCIDX);
1354 break;
1355 }
1356
1357 return val;
1358 }
1359
kvm_read_sanitised_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1360 static u64 kvm_read_sanitised_id_reg(struct kvm_vcpu *vcpu,
1361 const struct sys_reg_desc *r)
1362 {
1363 return __kvm_read_sanitised_id_reg(vcpu, r);
1364 }
1365
read_id_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1366 static u64 read_id_reg(const struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
1367 {
1368 return IDREG(vcpu->kvm, reg_to_encoding(r));
1369 }
1370
1371 /*
1372 * Return true if the register's (Op0, Op1, CRn, CRm, Op2) is
1373 * (3, 0, 0, crm, op2), where 1<=crm<8, 0<=op2<8.
1374 */
is_id_reg(u32 id)1375 static inline bool is_id_reg(u32 id)
1376 {
1377 return (sys_reg_Op0(id) == 3 && sys_reg_Op1(id) == 0 &&
1378 sys_reg_CRn(id) == 0 && sys_reg_CRm(id) >= 1 &&
1379 sys_reg_CRm(id) < 8);
1380 }
1381
id_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1382 static unsigned int id_visibility(const struct kvm_vcpu *vcpu,
1383 const struct sys_reg_desc *r)
1384 {
1385 u32 id = reg_to_encoding(r);
1386
1387 switch (id) {
1388 case SYS_ID_AA64ZFR0_EL1:
1389 if (!vcpu_has_sve(vcpu))
1390 return REG_RAZ;
1391 break;
1392 }
1393
1394 return 0;
1395 }
1396
aa32_id_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1397 static unsigned int aa32_id_visibility(const struct kvm_vcpu *vcpu,
1398 const struct sys_reg_desc *r)
1399 {
1400 /*
1401 * AArch32 ID registers are UNKNOWN if AArch32 isn't implemented at any
1402 * EL. Promote to RAZ/WI in order to guarantee consistency between
1403 * systems.
1404 */
1405 if (!kvm_supports_32bit_el0())
1406 return REG_RAZ | REG_USER_WI;
1407
1408 return id_visibility(vcpu, r);
1409 }
1410
raz_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1411 static unsigned int raz_visibility(const struct kvm_vcpu *vcpu,
1412 const struct sys_reg_desc *r)
1413 {
1414 return REG_RAZ;
1415 }
1416
1417 /* cpufeature ID register access trap handlers */
1418
access_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1419 static bool access_id_reg(struct kvm_vcpu *vcpu,
1420 struct sys_reg_params *p,
1421 const struct sys_reg_desc *r)
1422 {
1423 if (p->is_write)
1424 return write_to_read_only(vcpu, p, r);
1425
1426 p->regval = read_id_reg(vcpu, r);
1427 if (vcpu_has_nv(vcpu))
1428 access_nested_id_reg(vcpu, p, r);
1429
1430 return true;
1431 }
1432
1433 /* Visibility overrides for SVE-specific control registers */
sve_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1434 static unsigned int sve_visibility(const struct kvm_vcpu *vcpu,
1435 const struct sys_reg_desc *rd)
1436 {
1437 if (vcpu_has_sve(vcpu))
1438 return 0;
1439
1440 return REG_HIDDEN;
1441 }
1442
read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1443 static u64 read_sanitised_id_aa64pfr0_el1(struct kvm_vcpu *vcpu,
1444 const struct sys_reg_desc *rd)
1445 {
1446 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
1447
1448 if (!vcpu_has_sve(vcpu))
1449 val &= ~ID_AA64PFR0_EL1_SVE_MASK;
1450
1451 /*
1452 * The default is to expose CSV2 == 1 if the HW isn't affected.
1453 * Although this is a per-CPU feature, we make it global because
1454 * asymmetric systems are just a nuisance.
1455 *
1456 * Userspace can override this as long as it doesn't promise
1457 * the impossible.
1458 */
1459 if (arm64_get_spectre_v2_state() == SPECTRE_UNAFFECTED) {
1460 val &= ~ID_AA64PFR0_EL1_CSV2_MASK;
1461 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV2, IMP);
1462 }
1463 if (arm64_get_meltdown_state() == SPECTRE_UNAFFECTED) {
1464 val &= ~ID_AA64PFR0_EL1_CSV3_MASK;
1465 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, CSV3, IMP);
1466 }
1467
1468 if (kvm_vgic_global_state.type == VGIC_V3) {
1469 val &= ~ID_AA64PFR0_EL1_GIC_MASK;
1470 val |= SYS_FIELD_PREP_ENUM(ID_AA64PFR0_EL1, GIC, IMP);
1471 }
1472
1473 val &= ~ID_AA64PFR0_EL1_AMU_MASK;
1474
1475 return val;
1476 }
1477
read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1478 static u64 read_sanitised_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
1479 const struct sys_reg_desc *rd)
1480 {
1481 u64 val = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
1482
1483 /* Limit debug to ARMv8.0 */
1484 val &= ~ID_AA64DFR0_EL1_DebugVer_MASK;
1485 val |= SYS_FIELD_PREP_ENUM(ID_AA64DFR0_EL1, DebugVer, IMP);
1486
1487 /*
1488 * Only initialize the PMU version if the vCPU was configured with one.
1489 */
1490 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
1491 if (kvm_vcpu_has_pmu(vcpu))
1492 val |= SYS_FIELD_PREP(ID_AA64DFR0_EL1, PMUVer,
1493 kvm_arm_pmu_get_pmuver_limit());
1494
1495 /* Hide SPE from guests */
1496 val &= ~ID_AA64DFR0_EL1_PMSVer_MASK;
1497
1498 return val;
1499 }
1500
set_id_aa64dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1501 static int set_id_aa64dfr0_el1(struct kvm_vcpu *vcpu,
1502 const struct sys_reg_desc *rd,
1503 u64 val)
1504 {
1505 u8 pmuver = SYS_FIELD_GET(ID_AA64DFR0_EL1, PMUVer, val);
1506
1507 /*
1508 * Prior to commit 3d0dba5764b9 ("KVM: arm64: PMU: Move the
1509 * ID_AA64DFR0_EL1.PMUver limit to VM creation"), KVM erroneously
1510 * exposed an IMP_DEF PMU to userspace and the guest on systems w/
1511 * non-architectural PMUs. Of course, PMUv3 is the only game in town for
1512 * PMU virtualization, so the IMP_DEF value was rather user-hostile.
1513 *
1514 * At minimum, we're on the hook to allow values that were given to
1515 * userspace by KVM. Cover our tracks here and replace the IMP_DEF value
1516 * with a more sensible NI. The value of an ID register changing under
1517 * the nose of the guest is unfortunate, but is certainly no more
1518 * surprising than an ill-guided PMU driver poking at impdef system
1519 * registers that end in an UNDEF...
1520 */
1521 if (pmuver == ID_AA64DFR0_EL1_PMUVer_IMP_DEF)
1522 val &= ~ID_AA64DFR0_EL1_PMUVer_MASK;
1523
1524 return set_id_reg(vcpu, rd, val);
1525 }
1526
read_sanitised_id_dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1527 static u64 read_sanitised_id_dfr0_el1(struct kvm_vcpu *vcpu,
1528 const struct sys_reg_desc *rd)
1529 {
1530 u8 perfmon = pmuver_to_perfmon(kvm_arm_pmu_get_pmuver_limit());
1531 u64 val = read_sanitised_ftr_reg(SYS_ID_DFR0_EL1);
1532
1533 val &= ~ID_DFR0_EL1_PerfMon_MASK;
1534 if (kvm_vcpu_has_pmu(vcpu))
1535 val |= SYS_FIELD_PREP(ID_DFR0_EL1, PerfMon, perfmon);
1536
1537 return val;
1538 }
1539
set_id_dfr0_el1(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1540 static int set_id_dfr0_el1(struct kvm_vcpu *vcpu,
1541 const struct sys_reg_desc *rd,
1542 u64 val)
1543 {
1544 u8 perfmon = SYS_FIELD_GET(ID_DFR0_EL1, PerfMon, val);
1545
1546 if (perfmon == ID_DFR0_EL1_PerfMon_IMPDEF) {
1547 val &= ~ID_DFR0_EL1_PerfMon_MASK;
1548 perfmon = 0;
1549 }
1550
1551 /*
1552 * Allow DFR0_EL1.PerfMon to be set from userspace as long as
1553 * it doesn't promise more than what the HW gives us on the
1554 * AArch64 side (as everything is emulated with that), and
1555 * that this is a PMUv3.
1556 */
1557 if (perfmon != 0 && perfmon < ID_DFR0_EL1_PerfMon_PMUv3)
1558 return -EINVAL;
1559
1560 return set_id_reg(vcpu, rd, val);
1561 }
1562
1563 /*
1564 * cpufeature ID register user accessors
1565 *
1566 * For now, these registers are immutable for userspace, so no values
1567 * are stored, and for set_id_reg() we don't allow the effective value
1568 * to be changed.
1569 */
get_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)1570 static int get_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1571 u64 *val)
1572 {
1573 /*
1574 * Avoid locking if the VM has already started, as the ID registers are
1575 * guaranteed to be invariant at that point.
1576 */
1577 if (kvm_vm_has_ran_once(vcpu->kvm)) {
1578 *val = read_id_reg(vcpu, rd);
1579 return 0;
1580 }
1581
1582 mutex_lock(&vcpu->kvm->arch.config_lock);
1583 *val = read_id_reg(vcpu, rd);
1584 mutex_unlock(&vcpu->kvm->arch.config_lock);
1585
1586 return 0;
1587 }
1588
set_id_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1589 static int set_id_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1590 u64 val)
1591 {
1592 u32 id = reg_to_encoding(rd);
1593 int ret;
1594
1595 mutex_lock(&vcpu->kvm->arch.config_lock);
1596
1597 /*
1598 * Once the VM has started the ID registers are immutable. Reject any
1599 * write that does not match the final register value.
1600 */
1601 if (kvm_vm_has_ran_once(vcpu->kvm)) {
1602 if (val != read_id_reg(vcpu, rd))
1603 ret = -EBUSY;
1604 else
1605 ret = 0;
1606
1607 mutex_unlock(&vcpu->kvm->arch.config_lock);
1608 return ret;
1609 }
1610
1611 ret = arm64_check_features(vcpu, rd, val);
1612 if (!ret)
1613 IDREG(vcpu->kvm, id) = val;
1614
1615 mutex_unlock(&vcpu->kvm->arch.config_lock);
1616
1617 /*
1618 * arm64_check_features() returns -E2BIG to indicate the register's
1619 * feature set is a superset of the maximally-allowed register value.
1620 * While it would be nice to precisely describe this to userspace, the
1621 * existing UAPI for KVM_SET_ONE_REG has it that invalid register
1622 * writes return -EINVAL.
1623 */
1624 if (ret == -E2BIG)
1625 ret = -EINVAL;
1626 return ret;
1627 }
1628
get_raz_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 * val)1629 static int get_raz_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1630 u64 *val)
1631 {
1632 *val = 0;
1633 return 0;
1634 }
1635
set_wi_reg(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1636 static int set_wi_reg(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1637 u64 val)
1638 {
1639 return 0;
1640 }
1641
access_ctr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1642 static bool access_ctr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1643 const struct sys_reg_desc *r)
1644 {
1645 if (p->is_write)
1646 return write_to_read_only(vcpu, p, r);
1647
1648 p->regval = read_sanitised_ftr_reg(SYS_CTR_EL0);
1649 return true;
1650 }
1651
access_clidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1652 static bool access_clidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1653 const struct sys_reg_desc *r)
1654 {
1655 if (p->is_write)
1656 return write_to_read_only(vcpu, p, r);
1657
1658 p->regval = __vcpu_sys_reg(vcpu, r->reg);
1659 return true;
1660 }
1661
1662 /*
1663 * Fabricate a CLIDR_EL1 value instead of using the real value, which can vary
1664 * by the physical CPU which the vcpu currently resides in.
1665 */
reset_clidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * r)1666 static u64 reset_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *r)
1667 {
1668 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
1669 u64 clidr;
1670 u8 loc;
1671
1672 if ((ctr_el0 & CTR_EL0_IDC)) {
1673 /*
1674 * Data cache clean to the PoU is not required so LoUU and LoUIS
1675 * will not be set and a unified cache, which will be marked as
1676 * LoC, will be added.
1677 *
1678 * If not DIC, let the unified cache L2 so that an instruction
1679 * cache can be added as L1 later.
1680 */
1681 loc = (ctr_el0 & CTR_EL0_DIC) ? 1 : 2;
1682 clidr = CACHE_TYPE_UNIFIED << CLIDR_CTYPE_SHIFT(loc);
1683 } else {
1684 /*
1685 * Data cache clean to the PoU is required so let L1 have a data
1686 * cache and mark it as LoUU and LoUIS. As L1 has a data cache,
1687 * it can be marked as LoC too.
1688 */
1689 loc = 1;
1690 clidr = 1 << CLIDR_LOUU_SHIFT;
1691 clidr |= 1 << CLIDR_LOUIS_SHIFT;
1692 clidr |= CACHE_TYPE_DATA << CLIDR_CTYPE_SHIFT(1);
1693 }
1694
1695 /*
1696 * Instruction cache invalidation to the PoU is required so let L1 have
1697 * an instruction cache. If L1 already has a data cache, it will be
1698 * CACHE_TYPE_SEPARATE.
1699 */
1700 if (!(ctr_el0 & CTR_EL0_DIC))
1701 clidr |= CACHE_TYPE_INST << CLIDR_CTYPE_SHIFT(1);
1702
1703 clidr |= loc << CLIDR_LOC_SHIFT;
1704
1705 /*
1706 * Add tag cache unified to data cache. Allocation tags and data are
1707 * unified in a cache line so that it looks valid even if there is only
1708 * one cache line.
1709 */
1710 if (kvm_has_mte(vcpu->kvm))
1711 clidr |= 2ULL << CLIDR_TTYPE_SHIFT(loc);
1712
1713 __vcpu_sys_reg(vcpu, r->reg) = clidr;
1714
1715 return __vcpu_sys_reg(vcpu, r->reg);
1716 }
1717
set_clidr(struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 val)1718 static int set_clidr(struct kvm_vcpu *vcpu, const struct sys_reg_desc *rd,
1719 u64 val)
1720 {
1721 u64 ctr_el0 = read_sanitised_ftr_reg(SYS_CTR_EL0);
1722 u64 idc = !CLIDR_LOC(val) || (!CLIDR_LOUIS(val) && !CLIDR_LOUU(val));
1723
1724 if ((val & CLIDR_EL1_RES0) || (!(ctr_el0 & CTR_EL0_IDC) && idc))
1725 return -EINVAL;
1726
1727 __vcpu_sys_reg(vcpu, rd->reg) = val;
1728
1729 return 0;
1730 }
1731
access_csselr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1732 static bool access_csselr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1733 const struct sys_reg_desc *r)
1734 {
1735 int reg = r->reg;
1736
1737 if (p->is_write)
1738 vcpu_write_sys_reg(vcpu, p->regval, reg);
1739 else
1740 p->regval = vcpu_read_sys_reg(vcpu, reg);
1741 return true;
1742 }
1743
access_ccsidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1744 static bool access_ccsidr(struct kvm_vcpu *vcpu, struct sys_reg_params *p,
1745 const struct sys_reg_desc *r)
1746 {
1747 u32 csselr;
1748
1749 if (p->is_write)
1750 return write_to_read_only(vcpu, p, r);
1751
1752 csselr = vcpu_read_sys_reg(vcpu, CSSELR_EL1);
1753 csselr &= CSSELR_EL1_Level | CSSELR_EL1_InD;
1754 if (csselr < CSSELR_MAX)
1755 p->regval = get_ccsidr(vcpu, csselr);
1756
1757 return true;
1758 }
1759
mte_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1760 static unsigned int mte_visibility(const struct kvm_vcpu *vcpu,
1761 const struct sys_reg_desc *rd)
1762 {
1763 if (kvm_has_mte(vcpu->kvm))
1764 return 0;
1765
1766 return REG_HIDDEN;
1767 }
1768
1769 #define MTE_REG(name) { \
1770 SYS_DESC(SYS_##name), \
1771 .access = undef_access, \
1772 .reset = reset_unknown, \
1773 .reg = name, \
1774 .visibility = mte_visibility, \
1775 }
1776
el2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1777 static unsigned int el2_visibility(const struct kvm_vcpu *vcpu,
1778 const struct sys_reg_desc *rd)
1779 {
1780 if (vcpu_has_nv(vcpu))
1781 return 0;
1782
1783 return REG_HIDDEN;
1784 }
1785
1786 #define EL2_REG(name, acc, rst, v) { \
1787 SYS_DESC(SYS_##name), \
1788 .access = acc, \
1789 .reset = rst, \
1790 .reg = name, \
1791 .visibility = el2_visibility, \
1792 .val = v, \
1793 }
1794
1795 /*
1796 * EL{0,1}2 registers are the EL2 view on an EL0 or EL1 register when
1797 * HCR_EL2.E2H==1, and only in the sysreg table for convenience of
1798 * handling traps. Given that, they are always hidden from userspace.
1799 */
elx2_visibility(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd)1800 static unsigned int elx2_visibility(const struct kvm_vcpu *vcpu,
1801 const struct sys_reg_desc *rd)
1802 {
1803 return REG_HIDDEN_USER;
1804 }
1805
1806 #define EL12_REG(name, acc, rst, v) { \
1807 SYS_DESC(SYS_##name##_EL12), \
1808 .access = acc, \
1809 .reset = rst, \
1810 .reg = name##_EL1, \
1811 .val = v, \
1812 .visibility = elx2_visibility, \
1813 }
1814
1815 /*
1816 * Since reset() callback and field val are not used for idregs, they will be
1817 * used for specific purposes for idregs.
1818 * The reset() would return KVM sanitised register value. The value would be the
1819 * same as the host kernel sanitised value if there is no KVM sanitisation.
1820 * The val would be used as a mask indicating writable fields for the idreg.
1821 * Only bits with 1 are writable from userspace. This mask might not be
1822 * necessary in the future whenever all ID registers are enabled as writable
1823 * from userspace.
1824 */
1825
1826 /* sys_reg_desc initialiser for known cpufeature ID registers */
1827 #define ID_SANITISED(name) { \
1828 SYS_DESC(SYS_##name), \
1829 .access = access_id_reg, \
1830 .get_user = get_id_reg, \
1831 .set_user = set_id_reg, \
1832 .visibility = id_visibility, \
1833 .reset = kvm_read_sanitised_id_reg, \
1834 .val = 0, \
1835 }
1836
1837 /* sys_reg_desc initialiser for known cpufeature ID registers */
1838 #define AA32_ID_SANITISED(name) { \
1839 SYS_DESC(SYS_##name), \
1840 .access = access_id_reg, \
1841 .get_user = get_id_reg, \
1842 .set_user = set_id_reg, \
1843 .visibility = aa32_id_visibility, \
1844 .reset = kvm_read_sanitised_id_reg, \
1845 .val = 0, \
1846 }
1847
1848 /*
1849 * sys_reg_desc initialiser for architecturally unallocated cpufeature ID
1850 * register with encoding Op0=3, Op1=0, CRn=0, CRm=crm, Op2=op2
1851 * (1 <= crm < 8, 0 <= Op2 < 8).
1852 */
1853 #define ID_UNALLOCATED(crm, op2) { \
1854 Op0(3), Op1(0), CRn(0), CRm(crm), Op2(op2), \
1855 .access = access_id_reg, \
1856 .get_user = get_id_reg, \
1857 .set_user = set_id_reg, \
1858 .visibility = raz_visibility, \
1859 .reset = kvm_read_sanitised_id_reg, \
1860 .val = 0, \
1861 }
1862
1863 /*
1864 * sys_reg_desc initialiser for known ID registers that we hide from guests.
1865 * For now, these are exposed just like unallocated ID regs: they appear
1866 * RAZ for the guest.
1867 */
1868 #define ID_HIDDEN(name) { \
1869 SYS_DESC(SYS_##name), \
1870 .access = access_id_reg, \
1871 .get_user = get_id_reg, \
1872 .set_user = set_id_reg, \
1873 .visibility = raz_visibility, \
1874 .reset = kvm_read_sanitised_id_reg, \
1875 .val = 0, \
1876 }
1877
access_sp_el1(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1878 static bool access_sp_el1(struct kvm_vcpu *vcpu,
1879 struct sys_reg_params *p,
1880 const struct sys_reg_desc *r)
1881 {
1882 if (p->is_write)
1883 __vcpu_sys_reg(vcpu, SP_EL1) = p->regval;
1884 else
1885 p->regval = __vcpu_sys_reg(vcpu, SP_EL1);
1886
1887 return true;
1888 }
1889
access_elr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1890 static bool access_elr(struct kvm_vcpu *vcpu,
1891 struct sys_reg_params *p,
1892 const struct sys_reg_desc *r)
1893 {
1894 if (p->is_write)
1895 vcpu_write_sys_reg(vcpu, p->regval, ELR_EL1);
1896 else
1897 p->regval = vcpu_read_sys_reg(vcpu, ELR_EL1);
1898
1899 return true;
1900 }
1901
access_spsr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)1902 static bool access_spsr(struct kvm_vcpu *vcpu,
1903 struct sys_reg_params *p,
1904 const struct sys_reg_desc *r)
1905 {
1906 if (p->is_write)
1907 __vcpu_sys_reg(vcpu, SPSR_EL1) = p->regval;
1908 else
1909 p->regval = __vcpu_sys_reg(vcpu, SPSR_EL1);
1910
1911 return true;
1912 }
1913
1914 /*
1915 * Architected system registers.
1916 * Important: Must be sorted ascending by Op0, Op1, CRn, CRm, Op2
1917 *
1918 * Debug handling: We do trap most, if not all debug related system
1919 * registers. The implementation is good enough to ensure that a guest
1920 * can use these with minimal performance degradation. The drawback is
1921 * that we don't implement any of the external debug architecture.
1922 * This should be revisited if we ever encounter a more demanding
1923 * guest...
1924 */
1925 static const struct sys_reg_desc sys_reg_descs[] = {
1926 { SYS_DESC(SYS_DC_ISW), access_dcsw },
1927 { SYS_DESC(SYS_DC_IGSW), access_dcgsw },
1928 { SYS_DESC(SYS_DC_IGDSW), access_dcgsw },
1929 { SYS_DESC(SYS_DC_CSW), access_dcsw },
1930 { SYS_DESC(SYS_DC_CGSW), access_dcgsw },
1931 { SYS_DESC(SYS_DC_CGDSW), access_dcgsw },
1932 { SYS_DESC(SYS_DC_CISW), access_dcsw },
1933 { SYS_DESC(SYS_DC_CIGSW), access_dcgsw },
1934 { SYS_DESC(SYS_DC_CIGDSW), access_dcgsw },
1935
1936 DBG_BCR_BVR_WCR_WVR_EL1(0),
1937 DBG_BCR_BVR_WCR_WVR_EL1(1),
1938 { SYS_DESC(SYS_MDCCINT_EL1), trap_debug_regs, reset_val, MDCCINT_EL1, 0 },
1939 { SYS_DESC(SYS_MDSCR_EL1), trap_debug_regs, reset_val, MDSCR_EL1, 0 },
1940 DBG_BCR_BVR_WCR_WVR_EL1(2),
1941 DBG_BCR_BVR_WCR_WVR_EL1(3),
1942 DBG_BCR_BVR_WCR_WVR_EL1(4),
1943 DBG_BCR_BVR_WCR_WVR_EL1(5),
1944 DBG_BCR_BVR_WCR_WVR_EL1(6),
1945 DBG_BCR_BVR_WCR_WVR_EL1(7),
1946 DBG_BCR_BVR_WCR_WVR_EL1(8),
1947 DBG_BCR_BVR_WCR_WVR_EL1(9),
1948 DBG_BCR_BVR_WCR_WVR_EL1(10),
1949 DBG_BCR_BVR_WCR_WVR_EL1(11),
1950 DBG_BCR_BVR_WCR_WVR_EL1(12),
1951 DBG_BCR_BVR_WCR_WVR_EL1(13),
1952 DBG_BCR_BVR_WCR_WVR_EL1(14),
1953 DBG_BCR_BVR_WCR_WVR_EL1(15),
1954
1955 { SYS_DESC(SYS_MDRAR_EL1), trap_raz_wi },
1956 { SYS_DESC(SYS_OSLAR_EL1), trap_oslar_el1 },
1957 { SYS_DESC(SYS_OSLSR_EL1), trap_oslsr_el1, reset_val, OSLSR_EL1,
1958 OSLSR_EL1_OSLM_IMPLEMENTED, .set_user = set_oslsr_el1, },
1959 { SYS_DESC(SYS_OSDLR_EL1), trap_raz_wi },
1960 { SYS_DESC(SYS_DBGPRCR_EL1), trap_raz_wi },
1961 { SYS_DESC(SYS_DBGCLAIMSET_EL1), trap_raz_wi },
1962 { SYS_DESC(SYS_DBGCLAIMCLR_EL1), trap_raz_wi },
1963 { SYS_DESC(SYS_DBGAUTHSTATUS_EL1), trap_dbgauthstatus_el1 },
1964
1965 { SYS_DESC(SYS_MDCCSR_EL0), trap_raz_wi },
1966 { SYS_DESC(SYS_DBGDTR_EL0), trap_raz_wi },
1967 // DBGDTR[TR]X_EL0 share the same encoding
1968 { SYS_DESC(SYS_DBGDTRTX_EL0), trap_raz_wi },
1969
1970 { SYS_DESC(SYS_DBGVCR32_EL2), NULL, reset_val, DBGVCR32_EL2, 0 },
1971
1972 { SYS_DESC(SYS_MPIDR_EL1), NULL, reset_mpidr, MPIDR_EL1 },
1973
1974 /*
1975 * ID regs: all ID_SANITISED() entries here must have corresponding
1976 * entries in arm64_ftr_regs[].
1977 */
1978
1979 /* AArch64 mappings of the AArch32 ID registers */
1980 /* CRm=1 */
1981 AA32_ID_SANITISED(ID_PFR0_EL1),
1982 AA32_ID_SANITISED(ID_PFR1_EL1),
1983 { SYS_DESC(SYS_ID_DFR0_EL1),
1984 .access = access_id_reg,
1985 .get_user = get_id_reg,
1986 .set_user = set_id_dfr0_el1,
1987 .visibility = aa32_id_visibility,
1988 .reset = read_sanitised_id_dfr0_el1,
1989 .val = ID_DFR0_EL1_PerfMon_MASK, },
1990 ID_HIDDEN(ID_AFR0_EL1),
1991 AA32_ID_SANITISED(ID_MMFR0_EL1),
1992 AA32_ID_SANITISED(ID_MMFR1_EL1),
1993 AA32_ID_SANITISED(ID_MMFR2_EL1),
1994 AA32_ID_SANITISED(ID_MMFR3_EL1),
1995
1996 /* CRm=2 */
1997 AA32_ID_SANITISED(ID_ISAR0_EL1),
1998 AA32_ID_SANITISED(ID_ISAR1_EL1),
1999 AA32_ID_SANITISED(ID_ISAR2_EL1),
2000 AA32_ID_SANITISED(ID_ISAR3_EL1),
2001 AA32_ID_SANITISED(ID_ISAR4_EL1),
2002 AA32_ID_SANITISED(ID_ISAR5_EL1),
2003 AA32_ID_SANITISED(ID_MMFR4_EL1),
2004 AA32_ID_SANITISED(ID_ISAR6_EL1),
2005
2006 /* CRm=3 */
2007 AA32_ID_SANITISED(MVFR0_EL1),
2008 AA32_ID_SANITISED(MVFR1_EL1),
2009 AA32_ID_SANITISED(MVFR2_EL1),
2010 ID_UNALLOCATED(3,3),
2011 AA32_ID_SANITISED(ID_PFR2_EL1),
2012 ID_HIDDEN(ID_DFR1_EL1),
2013 AA32_ID_SANITISED(ID_MMFR5_EL1),
2014 ID_UNALLOCATED(3,7),
2015
2016 /* AArch64 ID registers */
2017 /* CRm=4 */
2018 { SYS_DESC(SYS_ID_AA64PFR0_EL1),
2019 .access = access_id_reg,
2020 .get_user = get_id_reg,
2021 .set_user = set_id_reg,
2022 .reset = read_sanitised_id_aa64pfr0_el1,
2023 .val = ID_AA64PFR0_EL1_CSV2_MASK | ID_AA64PFR0_EL1_CSV3_MASK, },
2024 ID_SANITISED(ID_AA64PFR1_EL1),
2025 ID_UNALLOCATED(4,2),
2026 ID_UNALLOCATED(4,3),
2027 ID_SANITISED(ID_AA64ZFR0_EL1),
2028 ID_HIDDEN(ID_AA64SMFR0_EL1),
2029 ID_UNALLOCATED(4,6),
2030 ID_UNALLOCATED(4,7),
2031
2032 /* CRm=5 */
2033 { SYS_DESC(SYS_ID_AA64DFR0_EL1),
2034 .access = access_id_reg,
2035 .get_user = get_id_reg,
2036 .set_user = set_id_aa64dfr0_el1,
2037 .reset = read_sanitised_id_aa64dfr0_el1,
2038 .val = ID_AA64DFR0_EL1_PMUVer_MASK, },
2039 ID_SANITISED(ID_AA64DFR1_EL1),
2040 ID_UNALLOCATED(5,2),
2041 ID_UNALLOCATED(5,3),
2042 ID_HIDDEN(ID_AA64AFR0_EL1),
2043 ID_HIDDEN(ID_AA64AFR1_EL1),
2044 ID_UNALLOCATED(5,6),
2045 ID_UNALLOCATED(5,7),
2046
2047 /* CRm=6 */
2048 ID_SANITISED(ID_AA64ISAR0_EL1),
2049 ID_SANITISED(ID_AA64ISAR1_EL1),
2050 ID_SANITISED(ID_AA64ISAR2_EL1),
2051 ID_UNALLOCATED(6,3),
2052 ID_UNALLOCATED(6,4),
2053 ID_UNALLOCATED(6,5),
2054 ID_UNALLOCATED(6,6),
2055 ID_UNALLOCATED(6,7),
2056
2057 /* CRm=7 */
2058 ID_SANITISED(ID_AA64MMFR0_EL1),
2059 ID_SANITISED(ID_AA64MMFR1_EL1),
2060 ID_SANITISED(ID_AA64MMFR2_EL1),
2061 ID_SANITISED(ID_AA64MMFR3_EL1),
2062 ID_UNALLOCATED(7,4),
2063 ID_UNALLOCATED(7,5),
2064 ID_UNALLOCATED(7,6),
2065 ID_UNALLOCATED(7,7),
2066
2067 { SYS_DESC(SYS_SCTLR_EL1), access_vm_reg, reset_val, SCTLR_EL1, 0x00C50078 },
2068 { SYS_DESC(SYS_ACTLR_EL1), access_actlr, reset_actlr, ACTLR_EL1 },
2069 { SYS_DESC(SYS_CPACR_EL1), NULL, reset_val, CPACR_EL1, 0 },
2070
2071 MTE_REG(RGSR_EL1),
2072 MTE_REG(GCR_EL1),
2073
2074 { SYS_DESC(SYS_ZCR_EL1), NULL, reset_val, ZCR_EL1, 0, .visibility = sve_visibility },
2075 { SYS_DESC(SYS_TRFCR_EL1), undef_access },
2076 { SYS_DESC(SYS_SMPRI_EL1), undef_access },
2077 { SYS_DESC(SYS_SMCR_EL1), undef_access },
2078 { SYS_DESC(SYS_TTBR0_EL1), access_vm_reg, reset_unknown, TTBR0_EL1 },
2079 { SYS_DESC(SYS_TTBR1_EL1), access_vm_reg, reset_unknown, TTBR1_EL1 },
2080 { SYS_DESC(SYS_TCR_EL1), access_vm_reg, reset_val, TCR_EL1, 0 },
2081 { SYS_DESC(SYS_TCR2_EL1), access_vm_reg, reset_val, TCR2_EL1, 0 },
2082
2083 PTRAUTH_KEY(APIA),
2084 PTRAUTH_KEY(APIB),
2085 PTRAUTH_KEY(APDA),
2086 PTRAUTH_KEY(APDB),
2087 PTRAUTH_KEY(APGA),
2088
2089 { SYS_DESC(SYS_SPSR_EL1), access_spsr},
2090 { SYS_DESC(SYS_ELR_EL1), access_elr},
2091
2092 { SYS_DESC(SYS_AFSR0_EL1), access_vm_reg, reset_unknown, AFSR0_EL1 },
2093 { SYS_DESC(SYS_AFSR1_EL1), access_vm_reg, reset_unknown, AFSR1_EL1 },
2094 { SYS_DESC(SYS_ESR_EL1), access_vm_reg, reset_unknown, ESR_EL1 },
2095
2096 { SYS_DESC(SYS_ERRIDR_EL1), trap_raz_wi },
2097 { SYS_DESC(SYS_ERRSELR_EL1), trap_raz_wi },
2098 { SYS_DESC(SYS_ERXFR_EL1), trap_raz_wi },
2099 { SYS_DESC(SYS_ERXCTLR_EL1), trap_raz_wi },
2100 { SYS_DESC(SYS_ERXSTATUS_EL1), trap_raz_wi },
2101 { SYS_DESC(SYS_ERXADDR_EL1), trap_raz_wi },
2102 { SYS_DESC(SYS_ERXMISC0_EL1), trap_raz_wi },
2103 { SYS_DESC(SYS_ERXMISC1_EL1), trap_raz_wi },
2104
2105 MTE_REG(TFSR_EL1),
2106 MTE_REG(TFSRE0_EL1),
2107
2108 { SYS_DESC(SYS_FAR_EL1), access_vm_reg, reset_unknown, FAR_EL1 },
2109 { SYS_DESC(SYS_PAR_EL1), NULL, reset_unknown, PAR_EL1 },
2110
2111 { SYS_DESC(SYS_PMSCR_EL1), undef_access },
2112 { SYS_DESC(SYS_PMSNEVFR_EL1), undef_access },
2113 { SYS_DESC(SYS_PMSICR_EL1), undef_access },
2114 { SYS_DESC(SYS_PMSIRR_EL1), undef_access },
2115 { SYS_DESC(SYS_PMSFCR_EL1), undef_access },
2116 { SYS_DESC(SYS_PMSEVFR_EL1), undef_access },
2117 { SYS_DESC(SYS_PMSLATFR_EL1), undef_access },
2118 { SYS_DESC(SYS_PMSIDR_EL1), undef_access },
2119 { SYS_DESC(SYS_PMBLIMITR_EL1), undef_access },
2120 { SYS_DESC(SYS_PMBPTR_EL1), undef_access },
2121 { SYS_DESC(SYS_PMBSR_EL1), undef_access },
2122 /* PMBIDR_EL1 is not trapped */
2123
2124 { PMU_SYS_REG(PMINTENSET_EL1),
2125 .access = access_pminten, .reg = PMINTENSET_EL1 },
2126 { PMU_SYS_REG(PMINTENCLR_EL1),
2127 .access = access_pminten, .reg = PMINTENSET_EL1 },
2128 { SYS_DESC(SYS_PMMIR_EL1), trap_raz_wi },
2129
2130 { SYS_DESC(SYS_MAIR_EL1), access_vm_reg, reset_unknown, MAIR_EL1 },
2131 { SYS_DESC(SYS_PIRE0_EL1), NULL, reset_unknown, PIRE0_EL1 },
2132 { SYS_DESC(SYS_PIR_EL1), NULL, reset_unknown, PIR_EL1 },
2133 { SYS_DESC(SYS_AMAIR_EL1), access_vm_reg, reset_amair_el1, AMAIR_EL1 },
2134
2135 { SYS_DESC(SYS_LORSA_EL1), trap_loregion },
2136 { SYS_DESC(SYS_LOREA_EL1), trap_loregion },
2137 { SYS_DESC(SYS_LORN_EL1), trap_loregion },
2138 { SYS_DESC(SYS_LORC_EL1), trap_loregion },
2139 { SYS_DESC(SYS_LORID_EL1), trap_loregion },
2140
2141 { SYS_DESC(SYS_VBAR_EL1), access_rw, reset_val, VBAR_EL1, 0 },
2142 { SYS_DESC(SYS_DISR_EL1), NULL, reset_val, DISR_EL1, 0 },
2143
2144 { SYS_DESC(SYS_ICC_IAR0_EL1), write_to_read_only },
2145 { SYS_DESC(SYS_ICC_EOIR0_EL1), read_from_write_only },
2146 { SYS_DESC(SYS_ICC_HPPIR0_EL1), write_to_read_only },
2147 { SYS_DESC(SYS_ICC_DIR_EL1), read_from_write_only },
2148 { SYS_DESC(SYS_ICC_RPR_EL1), write_to_read_only },
2149 { SYS_DESC(SYS_ICC_SGI1R_EL1), access_gic_sgi },
2150 { SYS_DESC(SYS_ICC_ASGI1R_EL1), access_gic_sgi },
2151 { SYS_DESC(SYS_ICC_SGI0R_EL1), access_gic_sgi },
2152 { SYS_DESC(SYS_ICC_IAR1_EL1), write_to_read_only },
2153 { SYS_DESC(SYS_ICC_EOIR1_EL1), read_from_write_only },
2154 { SYS_DESC(SYS_ICC_HPPIR1_EL1), write_to_read_only },
2155 { SYS_DESC(SYS_ICC_SRE_EL1), access_gic_sre },
2156
2157 { SYS_DESC(SYS_CONTEXTIDR_EL1), access_vm_reg, reset_val, CONTEXTIDR_EL1, 0 },
2158 { SYS_DESC(SYS_TPIDR_EL1), NULL, reset_unknown, TPIDR_EL1 },
2159
2160 { SYS_DESC(SYS_ACCDATA_EL1), undef_access },
2161
2162 { SYS_DESC(SYS_SCXTNUM_EL1), undef_access },
2163
2164 { SYS_DESC(SYS_CNTKCTL_EL1), NULL, reset_val, CNTKCTL_EL1, 0},
2165
2166 { SYS_DESC(SYS_CCSIDR_EL1), access_ccsidr },
2167 { SYS_DESC(SYS_CLIDR_EL1), access_clidr, reset_clidr, CLIDR_EL1,
2168 .set_user = set_clidr },
2169 { SYS_DESC(SYS_CCSIDR2_EL1), undef_access },
2170 { SYS_DESC(SYS_SMIDR_EL1), undef_access },
2171 { SYS_DESC(SYS_CSSELR_EL1), access_csselr, reset_unknown, CSSELR_EL1 },
2172 { SYS_DESC(SYS_CTR_EL0), access_ctr },
2173 { SYS_DESC(SYS_SVCR), undef_access },
2174
2175 { PMU_SYS_REG(PMCR_EL0), .access = access_pmcr,
2176 .reset = reset_pmcr, .reg = PMCR_EL0 },
2177 { PMU_SYS_REG(PMCNTENSET_EL0),
2178 .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
2179 { PMU_SYS_REG(PMCNTENCLR_EL0),
2180 .access = access_pmcnten, .reg = PMCNTENSET_EL0 },
2181 { PMU_SYS_REG(PMOVSCLR_EL0),
2182 .access = access_pmovs, .reg = PMOVSSET_EL0 },
2183 /*
2184 * PM_SWINC_EL0 is exposed to userspace as RAZ/WI, as it was
2185 * previously (and pointlessly) advertised in the past...
2186 */
2187 { PMU_SYS_REG(PMSWINC_EL0),
2188 .get_user = get_raz_reg, .set_user = set_wi_reg,
2189 .access = access_pmswinc, .reset = NULL },
2190 { PMU_SYS_REG(PMSELR_EL0),
2191 .access = access_pmselr, .reset = reset_pmselr, .reg = PMSELR_EL0 },
2192 { PMU_SYS_REG(PMCEID0_EL0),
2193 .access = access_pmceid, .reset = NULL },
2194 { PMU_SYS_REG(PMCEID1_EL0),
2195 .access = access_pmceid, .reset = NULL },
2196 { PMU_SYS_REG(PMCCNTR_EL0),
2197 .access = access_pmu_evcntr, .reset = reset_unknown,
2198 .reg = PMCCNTR_EL0, .get_user = get_pmu_evcntr},
2199 { PMU_SYS_REG(PMXEVTYPER_EL0),
2200 .access = access_pmu_evtyper, .reset = NULL },
2201 { PMU_SYS_REG(PMXEVCNTR_EL0),
2202 .access = access_pmu_evcntr, .reset = NULL },
2203 /*
2204 * PMUSERENR_EL0 resets as unknown in 64bit mode while it resets as zero
2205 * in 32bit mode. Here we choose to reset it as zero for consistency.
2206 */
2207 { PMU_SYS_REG(PMUSERENR_EL0), .access = access_pmuserenr,
2208 .reset = reset_val, .reg = PMUSERENR_EL0, .val = 0 },
2209 { PMU_SYS_REG(PMOVSSET_EL0),
2210 .access = access_pmovs, .reg = PMOVSSET_EL0 },
2211
2212 { SYS_DESC(SYS_TPIDR_EL0), NULL, reset_unknown, TPIDR_EL0 },
2213 { SYS_DESC(SYS_TPIDRRO_EL0), NULL, reset_unknown, TPIDRRO_EL0 },
2214 { SYS_DESC(SYS_TPIDR2_EL0), undef_access },
2215
2216 { SYS_DESC(SYS_SCXTNUM_EL0), undef_access },
2217
2218 { SYS_DESC(SYS_AMCR_EL0), undef_access },
2219 { SYS_DESC(SYS_AMCFGR_EL0), undef_access },
2220 { SYS_DESC(SYS_AMCGCR_EL0), undef_access },
2221 { SYS_DESC(SYS_AMUSERENR_EL0), undef_access },
2222 { SYS_DESC(SYS_AMCNTENCLR0_EL0), undef_access },
2223 { SYS_DESC(SYS_AMCNTENSET0_EL0), undef_access },
2224 { SYS_DESC(SYS_AMCNTENCLR1_EL0), undef_access },
2225 { SYS_DESC(SYS_AMCNTENSET1_EL0), undef_access },
2226 AMU_AMEVCNTR0_EL0(0),
2227 AMU_AMEVCNTR0_EL0(1),
2228 AMU_AMEVCNTR0_EL0(2),
2229 AMU_AMEVCNTR0_EL0(3),
2230 AMU_AMEVCNTR0_EL0(4),
2231 AMU_AMEVCNTR0_EL0(5),
2232 AMU_AMEVCNTR0_EL0(6),
2233 AMU_AMEVCNTR0_EL0(7),
2234 AMU_AMEVCNTR0_EL0(8),
2235 AMU_AMEVCNTR0_EL0(9),
2236 AMU_AMEVCNTR0_EL0(10),
2237 AMU_AMEVCNTR0_EL0(11),
2238 AMU_AMEVCNTR0_EL0(12),
2239 AMU_AMEVCNTR0_EL0(13),
2240 AMU_AMEVCNTR0_EL0(14),
2241 AMU_AMEVCNTR0_EL0(15),
2242 AMU_AMEVTYPER0_EL0(0),
2243 AMU_AMEVTYPER0_EL0(1),
2244 AMU_AMEVTYPER0_EL0(2),
2245 AMU_AMEVTYPER0_EL0(3),
2246 AMU_AMEVTYPER0_EL0(4),
2247 AMU_AMEVTYPER0_EL0(5),
2248 AMU_AMEVTYPER0_EL0(6),
2249 AMU_AMEVTYPER0_EL0(7),
2250 AMU_AMEVTYPER0_EL0(8),
2251 AMU_AMEVTYPER0_EL0(9),
2252 AMU_AMEVTYPER0_EL0(10),
2253 AMU_AMEVTYPER0_EL0(11),
2254 AMU_AMEVTYPER0_EL0(12),
2255 AMU_AMEVTYPER0_EL0(13),
2256 AMU_AMEVTYPER0_EL0(14),
2257 AMU_AMEVTYPER0_EL0(15),
2258 AMU_AMEVCNTR1_EL0(0),
2259 AMU_AMEVCNTR1_EL0(1),
2260 AMU_AMEVCNTR1_EL0(2),
2261 AMU_AMEVCNTR1_EL0(3),
2262 AMU_AMEVCNTR1_EL0(4),
2263 AMU_AMEVCNTR1_EL0(5),
2264 AMU_AMEVCNTR1_EL0(6),
2265 AMU_AMEVCNTR1_EL0(7),
2266 AMU_AMEVCNTR1_EL0(8),
2267 AMU_AMEVCNTR1_EL0(9),
2268 AMU_AMEVCNTR1_EL0(10),
2269 AMU_AMEVCNTR1_EL0(11),
2270 AMU_AMEVCNTR1_EL0(12),
2271 AMU_AMEVCNTR1_EL0(13),
2272 AMU_AMEVCNTR1_EL0(14),
2273 AMU_AMEVCNTR1_EL0(15),
2274 AMU_AMEVTYPER1_EL0(0),
2275 AMU_AMEVTYPER1_EL0(1),
2276 AMU_AMEVTYPER1_EL0(2),
2277 AMU_AMEVTYPER1_EL0(3),
2278 AMU_AMEVTYPER1_EL0(4),
2279 AMU_AMEVTYPER1_EL0(5),
2280 AMU_AMEVTYPER1_EL0(6),
2281 AMU_AMEVTYPER1_EL0(7),
2282 AMU_AMEVTYPER1_EL0(8),
2283 AMU_AMEVTYPER1_EL0(9),
2284 AMU_AMEVTYPER1_EL0(10),
2285 AMU_AMEVTYPER1_EL0(11),
2286 AMU_AMEVTYPER1_EL0(12),
2287 AMU_AMEVTYPER1_EL0(13),
2288 AMU_AMEVTYPER1_EL0(14),
2289 AMU_AMEVTYPER1_EL0(15),
2290
2291 { SYS_DESC(SYS_CNTPCT_EL0), access_arch_timer },
2292 { SYS_DESC(SYS_CNTPCTSS_EL0), access_arch_timer },
2293 { SYS_DESC(SYS_CNTP_TVAL_EL0), access_arch_timer },
2294 { SYS_DESC(SYS_CNTP_CTL_EL0), access_arch_timer },
2295 { SYS_DESC(SYS_CNTP_CVAL_EL0), access_arch_timer },
2296
2297 /* PMEVCNTRn_EL0 */
2298 PMU_PMEVCNTR_EL0(0),
2299 PMU_PMEVCNTR_EL0(1),
2300 PMU_PMEVCNTR_EL0(2),
2301 PMU_PMEVCNTR_EL0(3),
2302 PMU_PMEVCNTR_EL0(4),
2303 PMU_PMEVCNTR_EL0(5),
2304 PMU_PMEVCNTR_EL0(6),
2305 PMU_PMEVCNTR_EL0(7),
2306 PMU_PMEVCNTR_EL0(8),
2307 PMU_PMEVCNTR_EL0(9),
2308 PMU_PMEVCNTR_EL0(10),
2309 PMU_PMEVCNTR_EL0(11),
2310 PMU_PMEVCNTR_EL0(12),
2311 PMU_PMEVCNTR_EL0(13),
2312 PMU_PMEVCNTR_EL0(14),
2313 PMU_PMEVCNTR_EL0(15),
2314 PMU_PMEVCNTR_EL0(16),
2315 PMU_PMEVCNTR_EL0(17),
2316 PMU_PMEVCNTR_EL0(18),
2317 PMU_PMEVCNTR_EL0(19),
2318 PMU_PMEVCNTR_EL0(20),
2319 PMU_PMEVCNTR_EL0(21),
2320 PMU_PMEVCNTR_EL0(22),
2321 PMU_PMEVCNTR_EL0(23),
2322 PMU_PMEVCNTR_EL0(24),
2323 PMU_PMEVCNTR_EL0(25),
2324 PMU_PMEVCNTR_EL0(26),
2325 PMU_PMEVCNTR_EL0(27),
2326 PMU_PMEVCNTR_EL0(28),
2327 PMU_PMEVCNTR_EL0(29),
2328 PMU_PMEVCNTR_EL0(30),
2329 /* PMEVTYPERn_EL0 */
2330 PMU_PMEVTYPER_EL0(0),
2331 PMU_PMEVTYPER_EL0(1),
2332 PMU_PMEVTYPER_EL0(2),
2333 PMU_PMEVTYPER_EL0(3),
2334 PMU_PMEVTYPER_EL0(4),
2335 PMU_PMEVTYPER_EL0(5),
2336 PMU_PMEVTYPER_EL0(6),
2337 PMU_PMEVTYPER_EL0(7),
2338 PMU_PMEVTYPER_EL0(8),
2339 PMU_PMEVTYPER_EL0(9),
2340 PMU_PMEVTYPER_EL0(10),
2341 PMU_PMEVTYPER_EL0(11),
2342 PMU_PMEVTYPER_EL0(12),
2343 PMU_PMEVTYPER_EL0(13),
2344 PMU_PMEVTYPER_EL0(14),
2345 PMU_PMEVTYPER_EL0(15),
2346 PMU_PMEVTYPER_EL0(16),
2347 PMU_PMEVTYPER_EL0(17),
2348 PMU_PMEVTYPER_EL0(18),
2349 PMU_PMEVTYPER_EL0(19),
2350 PMU_PMEVTYPER_EL0(20),
2351 PMU_PMEVTYPER_EL0(21),
2352 PMU_PMEVTYPER_EL0(22),
2353 PMU_PMEVTYPER_EL0(23),
2354 PMU_PMEVTYPER_EL0(24),
2355 PMU_PMEVTYPER_EL0(25),
2356 PMU_PMEVTYPER_EL0(26),
2357 PMU_PMEVTYPER_EL0(27),
2358 PMU_PMEVTYPER_EL0(28),
2359 PMU_PMEVTYPER_EL0(29),
2360 PMU_PMEVTYPER_EL0(30),
2361 /*
2362 * PMCCFILTR_EL0 resets as unknown in 64bit mode while it resets as zero
2363 * in 32bit mode. Here we choose to reset it as zero for consistency.
2364 */
2365 { PMU_SYS_REG(PMCCFILTR_EL0), .access = access_pmu_evtyper,
2366 .reset = reset_val, .reg = PMCCFILTR_EL0, .val = 0 },
2367
2368 EL2_REG(VPIDR_EL2, access_rw, reset_unknown, 0),
2369 EL2_REG(VMPIDR_EL2, access_rw, reset_unknown, 0),
2370 EL2_REG(SCTLR_EL2, access_rw, reset_val, SCTLR_EL2_RES1),
2371 EL2_REG(ACTLR_EL2, access_rw, reset_val, 0),
2372 EL2_REG(HCR_EL2, access_rw, reset_val, 0),
2373 EL2_REG(MDCR_EL2, access_rw, reset_val, 0),
2374 EL2_REG(CPTR_EL2, access_rw, reset_val, CPTR_NVHE_EL2_RES1),
2375 EL2_REG(HSTR_EL2, access_rw, reset_val, 0),
2376 EL2_REG(HFGRTR_EL2, access_rw, reset_val, 0),
2377 EL2_REG(HFGWTR_EL2, access_rw, reset_val, 0),
2378 EL2_REG(HFGITR_EL2, access_rw, reset_val, 0),
2379 EL2_REG(HACR_EL2, access_rw, reset_val, 0),
2380
2381 EL2_REG(HCRX_EL2, access_rw, reset_val, 0),
2382
2383 EL2_REG(TTBR0_EL2, access_rw, reset_val, 0),
2384 EL2_REG(TTBR1_EL2, access_rw, reset_val, 0),
2385 EL2_REG(TCR_EL2, access_rw, reset_val, TCR_EL2_RES1),
2386 EL2_REG(VTTBR_EL2, access_rw, reset_val, 0),
2387 EL2_REG(VTCR_EL2, access_rw, reset_val, 0),
2388
2389 { SYS_DESC(SYS_DACR32_EL2), NULL, reset_unknown, DACR32_EL2 },
2390 EL2_REG(HDFGRTR_EL2, access_rw, reset_val, 0),
2391 EL2_REG(HDFGWTR_EL2, access_rw, reset_val, 0),
2392 EL2_REG(SPSR_EL2, access_rw, reset_val, 0),
2393 EL2_REG(ELR_EL2, access_rw, reset_val, 0),
2394 { SYS_DESC(SYS_SP_EL1), access_sp_el1},
2395
2396 { SYS_DESC(SYS_IFSR32_EL2), NULL, reset_unknown, IFSR32_EL2 },
2397 EL2_REG(AFSR0_EL2, access_rw, reset_val, 0),
2398 EL2_REG(AFSR1_EL2, access_rw, reset_val, 0),
2399 EL2_REG(ESR_EL2, access_rw, reset_val, 0),
2400 { SYS_DESC(SYS_FPEXC32_EL2), NULL, reset_val, FPEXC32_EL2, 0x700 },
2401
2402 EL2_REG(FAR_EL2, access_rw, reset_val, 0),
2403 EL2_REG(HPFAR_EL2, access_rw, reset_val, 0),
2404
2405 EL2_REG(MAIR_EL2, access_rw, reset_val, 0),
2406 EL2_REG(AMAIR_EL2, access_rw, reset_val, 0),
2407
2408 EL2_REG(VBAR_EL2, access_rw, reset_val, 0),
2409 EL2_REG(RVBAR_EL2, access_rw, reset_val, 0),
2410 { SYS_DESC(SYS_RMR_EL2), trap_undef },
2411
2412 EL2_REG(CONTEXTIDR_EL2, access_rw, reset_val, 0),
2413 EL2_REG(TPIDR_EL2, access_rw, reset_val, 0),
2414
2415 EL2_REG(CNTVOFF_EL2, access_rw, reset_val, 0),
2416 EL2_REG(CNTHCTL_EL2, access_rw, reset_val, 0),
2417
2418 EL12_REG(SCTLR, access_vm_reg, reset_val, 0x00C50078),
2419 EL12_REG(CPACR, access_rw, reset_val, 0),
2420 EL12_REG(TTBR0, access_vm_reg, reset_unknown, 0),
2421 EL12_REG(TTBR1, access_vm_reg, reset_unknown, 0),
2422 EL12_REG(TCR, access_vm_reg, reset_val, 0),
2423 { SYS_DESC(SYS_SPSR_EL12), access_spsr},
2424 { SYS_DESC(SYS_ELR_EL12), access_elr},
2425 EL12_REG(AFSR0, access_vm_reg, reset_unknown, 0),
2426 EL12_REG(AFSR1, access_vm_reg, reset_unknown, 0),
2427 EL12_REG(ESR, access_vm_reg, reset_unknown, 0),
2428 EL12_REG(FAR, access_vm_reg, reset_unknown, 0),
2429 EL12_REG(MAIR, access_vm_reg, reset_unknown, 0),
2430 EL12_REG(AMAIR, access_vm_reg, reset_amair_el1, 0),
2431 EL12_REG(VBAR, access_rw, reset_val, 0),
2432 EL12_REG(CONTEXTIDR, access_vm_reg, reset_val, 0),
2433 EL12_REG(CNTKCTL, access_rw, reset_val, 0),
2434
2435 EL2_REG(SP_EL2, NULL, reset_unknown, 0),
2436 };
2437
2438 static const struct sys_reg_desc *first_idreg;
2439
trap_dbgdidr(struct kvm_vcpu * vcpu,struct sys_reg_params * p,const struct sys_reg_desc * r)2440 static bool trap_dbgdidr(struct kvm_vcpu *vcpu,
2441 struct sys_reg_params *p,
2442 const struct sys_reg_desc *r)
2443 {
2444 if (p->is_write) {
2445 return ignore_write(vcpu, p);
2446 } else {
2447 u64 dfr = read_sanitised_ftr_reg(SYS_ID_AA64DFR0_EL1);
2448 u64 pfr = read_sanitised_ftr_reg(SYS_ID_AA64PFR0_EL1);
2449 u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL1_EL3_SHIFT);
2450
2451 p->regval = ((((dfr >> ID_AA64DFR0_EL1_WRPs_SHIFT) & 0xf) << 28) |
2452 (((dfr >> ID_AA64DFR0_EL1_BRPs_SHIFT) & 0xf) << 24) |
2453 (((dfr >> ID_AA64DFR0_EL1_CTX_CMPs_SHIFT) & 0xf) << 20)
2454 | (6 << 16) | (1 << 15) | (el3 << 14) | (el3 << 12));
2455 return true;
2456 }
2457 }
2458
2459 /*
2460 * AArch32 debug register mappings
2461 *
2462 * AArch32 DBGBVRn is mapped to DBGBVRn_EL1[31:0]
2463 * AArch32 DBGBXVRn is mapped to DBGBVRn_EL1[63:32]
2464 *
2465 * None of the other registers share their location, so treat them as
2466 * if they were 64bit.
2467 */
2468 #define DBG_BCR_BVR_WCR_WVR(n) \
2469 /* DBGBVRn */ \
2470 { AA32(LO), Op1( 0), CRn( 0), CRm((n)), Op2( 4), trap_bvr, NULL, n }, \
2471 /* DBGBCRn */ \
2472 { Op1( 0), CRn( 0), CRm((n)), Op2( 5), trap_bcr, NULL, n }, \
2473 /* DBGWVRn */ \
2474 { Op1( 0), CRn( 0), CRm((n)), Op2( 6), trap_wvr, NULL, n }, \
2475 /* DBGWCRn */ \
2476 { Op1( 0), CRn( 0), CRm((n)), Op2( 7), trap_wcr, NULL, n }
2477
2478 #define DBGBXVR(n) \
2479 { AA32(HI), Op1( 0), CRn( 1), CRm((n)), Op2( 1), trap_bvr, NULL, n }
2480
2481 /*
2482 * Trapped cp14 registers. We generally ignore most of the external
2483 * debug, on the principle that they don't really make sense to a
2484 * guest. Revisit this one day, would this principle change.
2485 */
2486 static const struct sys_reg_desc cp14_regs[] = {
2487 /* DBGDIDR */
2488 { Op1( 0), CRn( 0), CRm( 0), Op2( 0), trap_dbgdidr },
2489 /* DBGDTRRXext */
2490 { Op1( 0), CRn( 0), CRm( 0), Op2( 2), trap_raz_wi },
2491
2492 DBG_BCR_BVR_WCR_WVR(0),
2493 /* DBGDSCRint */
2494 { Op1( 0), CRn( 0), CRm( 1), Op2( 0), trap_raz_wi },
2495 DBG_BCR_BVR_WCR_WVR(1),
2496 /* DBGDCCINT */
2497 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), trap_debug_regs, NULL, MDCCINT_EL1 },
2498 /* DBGDSCRext */
2499 { Op1( 0), CRn( 0), CRm( 2), Op2( 2), trap_debug_regs, NULL, MDSCR_EL1 },
2500 DBG_BCR_BVR_WCR_WVR(2),
2501 /* DBGDTR[RT]Xint */
2502 { Op1( 0), CRn( 0), CRm( 3), Op2( 0), trap_raz_wi },
2503 /* DBGDTR[RT]Xext */
2504 { Op1( 0), CRn( 0), CRm( 3), Op2( 2), trap_raz_wi },
2505 DBG_BCR_BVR_WCR_WVR(3),
2506 DBG_BCR_BVR_WCR_WVR(4),
2507 DBG_BCR_BVR_WCR_WVR(5),
2508 /* DBGWFAR */
2509 { Op1( 0), CRn( 0), CRm( 6), Op2( 0), trap_raz_wi },
2510 /* DBGOSECCR */
2511 { Op1( 0), CRn( 0), CRm( 6), Op2( 2), trap_raz_wi },
2512 DBG_BCR_BVR_WCR_WVR(6),
2513 /* DBGVCR */
2514 { Op1( 0), CRn( 0), CRm( 7), Op2( 0), trap_debug_regs, NULL, DBGVCR32_EL2 },
2515 DBG_BCR_BVR_WCR_WVR(7),
2516 DBG_BCR_BVR_WCR_WVR(8),
2517 DBG_BCR_BVR_WCR_WVR(9),
2518 DBG_BCR_BVR_WCR_WVR(10),
2519 DBG_BCR_BVR_WCR_WVR(11),
2520 DBG_BCR_BVR_WCR_WVR(12),
2521 DBG_BCR_BVR_WCR_WVR(13),
2522 DBG_BCR_BVR_WCR_WVR(14),
2523 DBG_BCR_BVR_WCR_WVR(15),
2524
2525 /* DBGDRAR (32bit) */
2526 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), trap_raz_wi },
2527
2528 DBGBXVR(0),
2529 /* DBGOSLAR */
2530 { Op1( 0), CRn( 1), CRm( 0), Op2( 4), trap_oslar_el1 },
2531 DBGBXVR(1),
2532 /* DBGOSLSR */
2533 { Op1( 0), CRn( 1), CRm( 1), Op2( 4), trap_oslsr_el1, NULL, OSLSR_EL1 },
2534 DBGBXVR(2),
2535 DBGBXVR(3),
2536 /* DBGOSDLR */
2537 { Op1( 0), CRn( 1), CRm( 3), Op2( 4), trap_raz_wi },
2538 DBGBXVR(4),
2539 /* DBGPRCR */
2540 { Op1( 0), CRn( 1), CRm( 4), Op2( 4), trap_raz_wi },
2541 DBGBXVR(5),
2542 DBGBXVR(6),
2543 DBGBXVR(7),
2544 DBGBXVR(8),
2545 DBGBXVR(9),
2546 DBGBXVR(10),
2547 DBGBXVR(11),
2548 DBGBXVR(12),
2549 DBGBXVR(13),
2550 DBGBXVR(14),
2551 DBGBXVR(15),
2552
2553 /* DBGDSAR (32bit) */
2554 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), trap_raz_wi },
2555
2556 /* DBGDEVID2 */
2557 { Op1( 0), CRn( 7), CRm( 0), Op2( 7), trap_raz_wi },
2558 /* DBGDEVID1 */
2559 { Op1( 0), CRn( 7), CRm( 1), Op2( 7), trap_raz_wi },
2560 /* DBGDEVID */
2561 { Op1( 0), CRn( 7), CRm( 2), Op2( 7), trap_raz_wi },
2562 /* DBGCLAIMSET */
2563 { Op1( 0), CRn( 7), CRm( 8), Op2( 6), trap_raz_wi },
2564 /* DBGCLAIMCLR */
2565 { Op1( 0), CRn( 7), CRm( 9), Op2( 6), trap_raz_wi },
2566 /* DBGAUTHSTATUS */
2567 { Op1( 0), CRn( 7), CRm(14), Op2( 6), trap_dbgauthstatus_el1 },
2568 };
2569
2570 /* Trapped cp14 64bit registers */
2571 static const struct sys_reg_desc cp14_64_regs[] = {
2572 /* DBGDRAR (64bit) */
2573 { Op1( 0), CRm( 1), .access = trap_raz_wi },
2574
2575 /* DBGDSAR (64bit) */
2576 { Op1( 0), CRm( 2), .access = trap_raz_wi },
2577 };
2578
2579 #define CP15_PMU_SYS_REG(_map, _Op1, _CRn, _CRm, _Op2) \
2580 AA32(_map), \
2581 Op1(_Op1), CRn(_CRn), CRm(_CRm), Op2(_Op2), \
2582 .visibility = pmu_visibility
2583
2584 /* Macro to expand the PMEVCNTRn register */
2585 #define PMU_PMEVCNTR(n) \
2586 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \
2587 (0b1000 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \
2588 .access = access_pmu_evcntr }
2589
2590 /* Macro to expand the PMEVTYPERn register */
2591 #define PMU_PMEVTYPER(n) \
2592 { CP15_PMU_SYS_REG(DIRECT, 0, 0b1110, \
2593 (0b1100 | (((n) >> 3) & 0x3)), ((n) & 0x7)), \
2594 .access = access_pmu_evtyper }
2595 /*
2596 * Trapped cp15 registers. TTBR0/TTBR1 get a double encoding,
2597 * depending on the way they are accessed (as a 32bit or a 64bit
2598 * register).
2599 */
2600 static const struct sys_reg_desc cp15_regs[] = {
2601 { Op1( 0), CRn( 0), CRm( 0), Op2( 1), access_ctr },
2602 { Op1( 0), CRn( 1), CRm( 0), Op2( 0), access_vm_reg, NULL, SCTLR_EL1 },
2603 /* ACTLR */
2604 { AA32(LO), Op1( 0), CRn( 1), CRm( 0), Op2( 1), access_actlr, NULL, ACTLR_EL1 },
2605 /* ACTLR2 */
2606 { AA32(HI), Op1( 0), CRn( 1), CRm( 0), Op2( 3), access_actlr, NULL, ACTLR_EL1 },
2607 { Op1( 0), CRn( 2), CRm( 0), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
2608 { Op1( 0), CRn( 2), CRm( 0), Op2( 1), access_vm_reg, NULL, TTBR1_EL1 },
2609 /* TTBCR */
2610 { AA32(LO), Op1( 0), CRn( 2), CRm( 0), Op2( 2), access_vm_reg, NULL, TCR_EL1 },
2611 /* TTBCR2 */
2612 { AA32(HI), Op1( 0), CRn( 2), CRm( 0), Op2( 3), access_vm_reg, NULL, TCR_EL1 },
2613 { Op1( 0), CRn( 3), CRm( 0), Op2( 0), access_vm_reg, NULL, DACR32_EL2 },
2614 /* DFSR */
2615 { Op1( 0), CRn( 5), CRm( 0), Op2( 0), access_vm_reg, NULL, ESR_EL1 },
2616 { Op1( 0), CRn( 5), CRm( 0), Op2( 1), access_vm_reg, NULL, IFSR32_EL2 },
2617 /* ADFSR */
2618 { Op1( 0), CRn( 5), CRm( 1), Op2( 0), access_vm_reg, NULL, AFSR0_EL1 },
2619 /* AIFSR */
2620 { Op1( 0), CRn( 5), CRm( 1), Op2( 1), access_vm_reg, NULL, AFSR1_EL1 },
2621 /* DFAR */
2622 { AA32(LO), Op1( 0), CRn( 6), CRm( 0), Op2( 0), access_vm_reg, NULL, FAR_EL1 },
2623 /* IFAR */
2624 { AA32(HI), Op1( 0), CRn( 6), CRm( 0), Op2( 2), access_vm_reg, NULL, FAR_EL1 },
2625
2626 /*
2627 * DC{C,I,CI}SW operations:
2628 */
2629 { Op1( 0), CRn( 7), CRm( 6), Op2( 2), access_dcsw },
2630 { Op1( 0), CRn( 7), CRm(10), Op2( 2), access_dcsw },
2631 { Op1( 0), CRn( 7), CRm(14), Op2( 2), access_dcsw },
2632
2633 /* PMU */
2634 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 0), .access = access_pmcr },
2635 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 1), .access = access_pmcnten },
2636 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 2), .access = access_pmcnten },
2637 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 3), .access = access_pmovs },
2638 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 4), .access = access_pmswinc },
2639 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 12, 5), .access = access_pmselr },
2640 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 6), .access = access_pmceid },
2641 { CP15_PMU_SYS_REG(LO, 0, 9, 12, 7), .access = access_pmceid },
2642 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 0), .access = access_pmu_evcntr },
2643 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 1), .access = access_pmu_evtyper },
2644 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 13, 2), .access = access_pmu_evcntr },
2645 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 0), .access = access_pmuserenr },
2646 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 1), .access = access_pminten },
2647 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 2), .access = access_pminten },
2648 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 3), .access = access_pmovs },
2649 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 4), .access = access_pmceid },
2650 { CP15_PMU_SYS_REG(HI, 0, 9, 14, 5), .access = access_pmceid },
2651 /* PMMIR */
2652 { CP15_PMU_SYS_REG(DIRECT, 0, 9, 14, 6), .access = trap_raz_wi },
2653
2654 /* PRRR/MAIR0 */
2655 { AA32(LO), Op1( 0), CRn(10), CRm( 2), Op2( 0), access_vm_reg, NULL, MAIR_EL1 },
2656 /* NMRR/MAIR1 */
2657 { AA32(HI), Op1( 0), CRn(10), CRm( 2), Op2( 1), access_vm_reg, NULL, MAIR_EL1 },
2658 /* AMAIR0 */
2659 { AA32(LO), Op1( 0), CRn(10), CRm( 3), Op2( 0), access_vm_reg, NULL, AMAIR_EL1 },
2660 /* AMAIR1 */
2661 { AA32(HI), Op1( 0), CRn(10), CRm( 3), Op2( 1), access_vm_reg, NULL, AMAIR_EL1 },
2662
2663 /* ICC_SRE */
2664 { Op1( 0), CRn(12), CRm(12), Op2( 5), access_gic_sre },
2665
2666 { Op1( 0), CRn(13), CRm( 0), Op2( 1), access_vm_reg, NULL, CONTEXTIDR_EL1 },
2667
2668 /* Arch Tmers */
2669 { SYS_DESC(SYS_AARCH32_CNTP_TVAL), access_arch_timer },
2670 { SYS_DESC(SYS_AARCH32_CNTP_CTL), access_arch_timer },
2671
2672 /* PMEVCNTRn */
2673 PMU_PMEVCNTR(0),
2674 PMU_PMEVCNTR(1),
2675 PMU_PMEVCNTR(2),
2676 PMU_PMEVCNTR(3),
2677 PMU_PMEVCNTR(4),
2678 PMU_PMEVCNTR(5),
2679 PMU_PMEVCNTR(6),
2680 PMU_PMEVCNTR(7),
2681 PMU_PMEVCNTR(8),
2682 PMU_PMEVCNTR(9),
2683 PMU_PMEVCNTR(10),
2684 PMU_PMEVCNTR(11),
2685 PMU_PMEVCNTR(12),
2686 PMU_PMEVCNTR(13),
2687 PMU_PMEVCNTR(14),
2688 PMU_PMEVCNTR(15),
2689 PMU_PMEVCNTR(16),
2690 PMU_PMEVCNTR(17),
2691 PMU_PMEVCNTR(18),
2692 PMU_PMEVCNTR(19),
2693 PMU_PMEVCNTR(20),
2694 PMU_PMEVCNTR(21),
2695 PMU_PMEVCNTR(22),
2696 PMU_PMEVCNTR(23),
2697 PMU_PMEVCNTR(24),
2698 PMU_PMEVCNTR(25),
2699 PMU_PMEVCNTR(26),
2700 PMU_PMEVCNTR(27),
2701 PMU_PMEVCNTR(28),
2702 PMU_PMEVCNTR(29),
2703 PMU_PMEVCNTR(30),
2704 /* PMEVTYPERn */
2705 PMU_PMEVTYPER(0),
2706 PMU_PMEVTYPER(1),
2707 PMU_PMEVTYPER(2),
2708 PMU_PMEVTYPER(3),
2709 PMU_PMEVTYPER(4),
2710 PMU_PMEVTYPER(5),
2711 PMU_PMEVTYPER(6),
2712 PMU_PMEVTYPER(7),
2713 PMU_PMEVTYPER(8),
2714 PMU_PMEVTYPER(9),
2715 PMU_PMEVTYPER(10),
2716 PMU_PMEVTYPER(11),
2717 PMU_PMEVTYPER(12),
2718 PMU_PMEVTYPER(13),
2719 PMU_PMEVTYPER(14),
2720 PMU_PMEVTYPER(15),
2721 PMU_PMEVTYPER(16),
2722 PMU_PMEVTYPER(17),
2723 PMU_PMEVTYPER(18),
2724 PMU_PMEVTYPER(19),
2725 PMU_PMEVTYPER(20),
2726 PMU_PMEVTYPER(21),
2727 PMU_PMEVTYPER(22),
2728 PMU_PMEVTYPER(23),
2729 PMU_PMEVTYPER(24),
2730 PMU_PMEVTYPER(25),
2731 PMU_PMEVTYPER(26),
2732 PMU_PMEVTYPER(27),
2733 PMU_PMEVTYPER(28),
2734 PMU_PMEVTYPER(29),
2735 PMU_PMEVTYPER(30),
2736 /* PMCCFILTR */
2737 { CP15_PMU_SYS_REG(DIRECT, 0, 14, 15, 7), .access = access_pmu_evtyper },
2738
2739 { Op1(1), CRn( 0), CRm( 0), Op2(0), access_ccsidr },
2740 { Op1(1), CRn( 0), CRm( 0), Op2(1), access_clidr },
2741
2742 /* CCSIDR2 */
2743 { Op1(1), CRn( 0), CRm( 0), Op2(2), undef_access },
2744
2745 { Op1(2), CRn( 0), CRm( 0), Op2(0), access_csselr, NULL, CSSELR_EL1 },
2746 };
2747
2748 static const struct sys_reg_desc cp15_64_regs[] = {
2749 { Op1( 0), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR0_EL1 },
2750 { CP15_PMU_SYS_REG(DIRECT, 0, 0, 9, 0), .access = access_pmu_evcntr },
2751 { Op1( 0), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI1R */
2752 { SYS_DESC(SYS_AARCH32_CNTPCT), access_arch_timer },
2753 { Op1( 1), CRn( 0), CRm( 2), Op2( 0), access_vm_reg, NULL, TTBR1_EL1 },
2754 { Op1( 1), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_ASGI1R */
2755 { Op1( 2), CRn( 0), CRm(12), Op2( 0), access_gic_sgi }, /* ICC_SGI0R */
2756 { SYS_DESC(SYS_AARCH32_CNTP_CVAL), access_arch_timer },
2757 { SYS_DESC(SYS_AARCH32_CNTPCTSS), access_arch_timer },
2758 };
2759
check_sysreg_table(const struct sys_reg_desc * table,unsigned int n,bool is_32)2760 static bool check_sysreg_table(const struct sys_reg_desc *table, unsigned int n,
2761 bool is_32)
2762 {
2763 unsigned int i;
2764
2765 for (i = 0; i < n; i++) {
2766 if (!is_32 && table[i].reg && !table[i].reset) {
2767 kvm_err("sys_reg table %pS entry %d lacks reset\n", &table[i], i);
2768 return false;
2769 }
2770
2771 if (i && cmp_sys_reg(&table[i-1], &table[i]) >= 0) {
2772 kvm_err("sys_reg table %pS entry %d out of order\n", &table[i - 1], i - 1);
2773 return false;
2774 }
2775 }
2776
2777 return true;
2778 }
2779
kvm_handle_cp14_load_store(struct kvm_vcpu * vcpu)2780 int kvm_handle_cp14_load_store(struct kvm_vcpu *vcpu)
2781 {
2782 kvm_inject_undefined(vcpu);
2783 return 1;
2784 }
2785
perform_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * r)2786 static void perform_access(struct kvm_vcpu *vcpu,
2787 struct sys_reg_params *params,
2788 const struct sys_reg_desc *r)
2789 {
2790 trace_kvm_sys_access(*vcpu_pc(vcpu), params, r);
2791
2792 /* Check for regs disabled by runtime config */
2793 if (sysreg_hidden(vcpu, r)) {
2794 kvm_inject_undefined(vcpu);
2795 return;
2796 }
2797
2798 /*
2799 * Not having an accessor means that we have configured a trap
2800 * that we don't know how to handle. This certainly qualifies
2801 * as a gross bug that should be fixed right away.
2802 */
2803 BUG_ON(!r->access);
2804
2805 /* Skip instruction if instructed so */
2806 if (likely(r->access(vcpu, params, r)))
2807 kvm_incr_pc(vcpu);
2808 }
2809
2810 /*
2811 * emulate_cp -- tries to match a sys_reg access in a handling table, and
2812 * call the corresponding trap handler.
2813 *
2814 * @params: pointer to the descriptor of the access
2815 * @table: array of trap descriptors
2816 * @num: size of the trap descriptor array
2817 *
2818 * Return true if the access has been handled, false if not.
2819 */
emulate_cp(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * table,size_t num)2820 static bool emulate_cp(struct kvm_vcpu *vcpu,
2821 struct sys_reg_params *params,
2822 const struct sys_reg_desc *table,
2823 size_t num)
2824 {
2825 const struct sys_reg_desc *r;
2826
2827 if (!table)
2828 return false; /* Not handled */
2829
2830 r = find_reg(params, table, num);
2831
2832 if (r) {
2833 perform_access(vcpu, params, r);
2834 return true;
2835 }
2836
2837 /* Not handled */
2838 return false;
2839 }
2840
unhandled_cp_access(struct kvm_vcpu * vcpu,struct sys_reg_params * params)2841 static void unhandled_cp_access(struct kvm_vcpu *vcpu,
2842 struct sys_reg_params *params)
2843 {
2844 u8 esr_ec = kvm_vcpu_trap_get_class(vcpu);
2845 int cp = -1;
2846
2847 switch (esr_ec) {
2848 case ESR_ELx_EC_CP15_32:
2849 case ESR_ELx_EC_CP15_64:
2850 cp = 15;
2851 break;
2852 case ESR_ELx_EC_CP14_MR:
2853 case ESR_ELx_EC_CP14_64:
2854 cp = 14;
2855 break;
2856 default:
2857 WARN_ON(1);
2858 }
2859
2860 print_sys_reg_msg(params,
2861 "Unsupported guest CP%d access at: %08lx [%08lx]\n",
2862 cp, *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
2863 kvm_inject_undefined(vcpu);
2864 }
2865
2866 /**
2867 * kvm_handle_cp_64 -- handles a mrrc/mcrr trap on a guest CP14/CP15 access
2868 * @vcpu: The VCPU pointer
2869 * @run: The kvm_run struct
2870 */
kvm_handle_cp_64(struct kvm_vcpu * vcpu,const struct sys_reg_desc * global,size_t nr_global)2871 static int kvm_handle_cp_64(struct kvm_vcpu *vcpu,
2872 const struct sys_reg_desc *global,
2873 size_t nr_global)
2874 {
2875 struct sys_reg_params params;
2876 u64 esr = kvm_vcpu_get_esr(vcpu);
2877 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2878 int Rt2 = (esr >> 10) & 0x1f;
2879
2880 params.CRm = (esr >> 1) & 0xf;
2881 params.is_write = ((esr & 1) == 0);
2882
2883 params.Op0 = 0;
2884 params.Op1 = (esr >> 16) & 0xf;
2885 params.Op2 = 0;
2886 params.CRn = 0;
2887
2888 /*
2889 * Make a 64-bit value out of Rt and Rt2. As we use the same trap
2890 * backends between AArch32 and AArch64, we get away with it.
2891 */
2892 if (params.is_write) {
2893 params.regval = vcpu_get_reg(vcpu, Rt) & 0xffffffff;
2894 params.regval |= vcpu_get_reg(vcpu, Rt2) << 32;
2895 }
2896
2897 /*
2898 * If the table contains a handler, handle the
2899 * potential register operation in the case of a read and return
2900 * with success.
2901 */
2902 if (emulate_cp(vcpu, ¶ms, global, nr_global)) {
2903 /* Split up the value between registers for the read side */
2904 if (!params.is_write) {
2905 vcpu_set_reg(vcpu, Rt, lower_32_bits(params.regval));
2906 vcpu_set_reg(vcpu, Rt2, upper_32_bits(params.regval));
2907 }
2908
2909 return 1;
2910 }
2911
2912 unhandled_cp_access(vcpu, ¶ms);
2913 return 1;
2914 }
2915
2916 static bool emulate_sys_reg(struct kvm_vcpu *vcpu, struct sys_reg_params *params);
2917
2918 /*
2919 * The CP10 ID registers are architecturally mapped to AArch64 feature
2920 * registers. Abuse that fact so we can rely on the AArch64 handler for accesses
2921 * from AArch32.
2922 */
kvm_esr_cp10_id_to_sys64(u64 esr,struct sys_reg_params * params)2923 static bool kvm_esr_cp10_id_to_sys64(u64 esr, struct sys_reg_params *params)
2924 {
2925 u8 reg_id = (esr >> 10) & 0xf;
2926 bool valid;
2927
2928 params->is_write = ((esr & 1) == 0);
2929 params->Op0 = 3;
2930 params->Op1 = 0;
2931 params->CRn = 0;
2932 params->CRm = 3;
2933
2934 /* CP10 ID registers are read-only */
2935 valid = !params->is_write;
2936
2937 switch (reg_id) {
2938 /* MVFR0 */
2939 case 0b0111:
2940 params->Op2 = 0;
2941 break;
2942 /* MVFR1 */
2943 case 0b0110:
2944 params->Op2 = 1;
2945 break;
2946 /* MVFR2 */
2947 case 0b0101:
2948 params->Op2 = 2;
2949 break;
2950 default:
2951 valid = false;
2952 }
2953
2954 if (valid)
2955 return true;
2956
2957 kvm_pr_unimpl("Unhandled cp10 register %s: %u\n",
2958 params->is_write ? "write" : "read", reg_id);
2959 return false;
2960 }
2961
2962 /**
2963 * kvm_handle_cp10_id() - Handles a VMRS trap on guest access to a 'Media and
2964 * VFP Register' from AArch32.
2965 * @vcpu: The vCPU pointer
2966 *
2967 * MVFR{0-2} are architecturally mapped to the AArch64 MVFR{0-2}_EL1 registers.
2968 * Work out the correct AArch64 system register encoding and reroute to the
2969 * AArch64 system register emulation.
2970 */
kvm_handle_cp10_id(struct kvm_vcpu * vcpu)2971 int kvm_handle_cp10_id(struct kvm_vcpu *vcpu)
2972 {
2973 int Rt = kvm_vcpu_sys_get_rt(vcpu);
2974 u64 esr = kvm_vcpu_get_esr(vcpu);
2975 struct sys_reg_params params;
2976
2977 /* UNDEF on any unhandled register access */
2978 if (!kvm_esr_cp10_id_to_sys64(esr, ¶ms)) {
2979 kvm_inject_undefined(vcpu);
2980 return 1;
2981 }
2982
2983 if (emulate_sys_reg(vcpu, ¶ms))
2984 vcpu_set_reg(vcpu, Rt, params.regval);
2985
2986 return 1;
2987 }
2988
2989 /**
2990 * kvm_emulate_cp15_id_reg() - Handles an MRC trap on a guest CP15 access where
2991 * CRn=0, which corresponds to the AArch32 feature
2992 * registers.
2993 * @vcpu: the vCPU pointer
2994 * @params: the system register access parameters.
2995 *
2996 * Our cp15 system register tables do not enumerate the AArch32 feature
2997 * registers. Conveniently, our AArch64 table does, and the AArch32 system
2998 * register encoding can be trivially remapped into the AArch64 for the feature
2999 * registers: Append op0=3, leaving op1, CRn, CRm, and op2 the same.
3000 *
3001 * According to DDI0487G.b G7.3.1, paragraph "Behavior of VMSAv8-32 32-bit
3002 * System registers with (coproc=0b1111, CRn==c0)", read accesses from this
3003 * range are either UNKNOWN or RES0. Rerouting remains architectural as we
3004 * treat undefined registers in this range as RAZ.
3005 */
kvm_emulate_cp15_id_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * params)3006 static int kvm_emulate_cp15_id_reg(struct kvm_vcpu *vcpu,
3007 struct sys_reg_params *params)
3008 {
3009 int Rt = kvm_vcpu_sys_get_rt(vcpu);
3010
3011 /* Treat impossible writes to RO registers as UNDEFINED */
3012 if (params->is_write) {
3013 unhandled_cp_access(vcpu, params);
3014 return 1;
3015 }
3016
3017 params->Op0 = 3;
3018
3019 /*
3020 * All registers where CRm > 3 are known to be UNKNOWN/RAZ from AArch32.
3021 * Avoid conflicting with future expansion of AArch64 feature registers
3022 * and simply treat them as RAZ here.
3023 */
3024 if (params->CRm > 3)
3025 params->regval = 0;
3026 else if (!emulate_sys_reg(vcpu, params))
3027 return 1;
3028
3029 vcpu_set_reg(vcpu, Rt, params->regval);
3030 return 1;
3031 }
3032
3033 /**
3034 * kvm_handle_cp_32 -- handles a mrc/mcr trap on a guest CP14/CP15 access
3035 * @vcpu: The VCPU pointer
3036 * @run: The kvm_run struct
3037 */
kvm_handle_cp_32(struct kvm_vcpu * vcpu,struct sys_reg_params * params,const struct sys_reg_desc * global,size_t nr_global)3038 static int kvm_handle_cp_32(struct kvm_vcpu *vcpu,
3039 struct sys_reg_params *params,
3040 const struct sys_reg_desc *global,
3041 size_t nr_global)
3042 {
3043 int Rt = kvm_vcpu_sys_get_rt(vcpu);
3044
3045 params->regval = vcpu_get_reg(vcpu, Rt);
3046
3047 if (emulate_cp(vcpu, params, global, nr_global)) {
3048 if (!params->is_write)
3049 vcpu_set_reg(vcpu, Rt, params->regval);
3050 return 1;
3051 }
3052
3053 unhandled_cp_access(vcpu, params);
3054 return 1;
3055 }
3056
kvm_handle_cp15_64(struct kvm_vcpu * vcpu)3057 int kvm_handle_cp15_64(struct kvm_vcpu *vcpu)
3058 {
3059 return kvm_handle_cp_64(vcpu, cp15_64_regs, ARRAY_SIZE(cp15_64_regs));
3060 }
3061
kvm_handle_cp15_32(struct kvm_vcpu * vcpu)3062 int kvm_handle_cp15_32(struct kvm_vcpu *vcpu)
3063 {
3064 struct sys_reg_params params;
3065
3066 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
3067
3068 /*
3069 * Certain AArch32 ID registers are handled by rerouting to the AArch64
3070 * system register table. Registers in the ID range where CRm=0 are
3071 * excluded from this scheme as they do not trivially map into AArch64
3072 * system register encodings.
3073 */
3074 if (params.Op1 == 0 && params.CRn == 0 && params.CRm)
3075 return kvm_emulate_cp15_id_reg(vcpu, ¶ms);
3076
3077 return kvm_handle_cp_32(vcpu, ¶ms, cp15_regs, ARRAY_SIZE(cp15_regs));
3078 }
3079
kvm_handle_cp14_64(struct kvm_vcpu * vcpu)3080 int kvm_handle_cp14_64(struct kvm_vcpu *vcpu)
3081 {
3082 return kvm_handle_cp_64(vcpu, cp14_64_regs, ARRAY_SIZE(cp14_64_regs));
3083 }
3084
kvm_handle_cp14_32(struct kvm_vcpu * vcpu)3085 int kvm_handle_cp14_32(struct kvm_vcpu *vcpu)
3086 {
3087 struct sys_reg_params params;
3088
3089 params = esr_cp1x_32_to_params(kvm_vcpu_get_esr(vcpu));
3090
3091 return kvm_handle_cp_32(vcpu, ¶ms, cp14_regs, ARRAY_SIZE(cp14_regs));
3092 }
3093
is_imp_def_sys_reg(struct sys_reg_params * params)3094 static bool is_imp_def_sys_reg(struct sys_reg_params *params)
3095 {
3096 // See ARM DDI 0487E.a, section D12.3.2
3097 return params->Op0 == 3 && (params->CRn & 0b1011) == 0b1011;
3098 }
3099
3100 /**
3101 * emulate_sys_reg - Emulate a guest access to an AArch64 system register
3102 * @vcpu: The VCPU pointer
3103 * @params: Decoded system register parameters
3104 *
3105 * Return: true if the system register access was successful, false otherwise.
3106 */
emulate_sys_reg(struct kvm_vcpu * vcpu,struct sys_reg_params * params)3107 static bool emulate_sys_reg(struct kvm_vcpu *vcpu,
3108 struct sys_reg_params *params)
3109 {
3110 const struct sys_reg_desc *r;
3111
3112 r = find_reg(params, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
3113
3114 if (likely(r)) {
3115 perform_access(vcpu, params, r);
3116 return true;
3117 }
3118
3119 if (is_imp_def_sys_reg(params)) {
3120 kvm_inject_undefined(vcpu);
3121 } else {
3122 print_sys_reg_msg(params,
3123 "Unsupported guest sys_reg access at: %lx [%08lx]\n",
3124 *vcpu_pc(vcpu), *vcpu_cpsr(vcpu));
3125 kvm_inject_undefined(vcpu);
3126 }
3127 return false;
3128 }
3129
kvm_reset_id_regs(struct kvm_vcpu * vcpu)3130 static void kvm_reset_id_regs(struct kvm_vcpu *vcpu)
3131 {
3132 const struct sys_reg_desc *idreg = first_idreg;
3133 u32 id = reg_to_encoding(idreg);
3134 struct kvm *kvm = vcpu->kvm;
3135
3136 if (test_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags))
3137 return;
3138
3139 lockdep_assert_held(&kvm->arch.config_lock);
3140
3141 /* Initialize all idregs */
3142 while (is_id_reg(id)) {
3143 IDREG(kvm, id) = idreg->reset(vcpu, idreg);
3144
3145 idreg++;
3146 id = reg_to_encoding(idreg);
3147 }
3148
3149 set_bit(KVM_ARCH_FLAG_ID_REGS_INITIALIZED, &kvm->arch.flags);
3150 }
3151
3152 /**
3153 * kvm_reset_sys_regs - sets system registers to reset value
3154 * @vcpu: The VCPU pointer
3155 *
3156 * This function finds the right table above and sets the registers on the
3157 * virtual CPU struct to their architecturally defined reset values.
3158 */
kvm_reset_sys_regs(struct kvm_vcpu * vcpu)3159 void kvm_reset_sys_regs(struct kvm_vcpu *vcpu)
3160 {
3161 unsigned long i;
3162
3163 kvm_reset_id_regs(vcpu);
3164
3165 for (i = 0; i < ARRAY_SIZE(sys_reg_descs); i++) {
3166 const struct sys_reg_desc *r = &sys_reg_descs[i];
3167
3168 if (is_id_reg(reg_to_encoding(r)))
3169 continue;
3170
3171 if (r->reset)
3172 r->reset(vcpu, r);
3173 }
3174 }
3175
3176 /**
3177 * kvm_handle_sys_reg -- handles a mrs/msr trap on a guest sys_reg access
3178 * @vcpu: The VCPU pointer
3179 */
kvm_handle_sys_reg(struct kvm_vcpu * vcpu)3180 int kvm_handle_sys_reg(struct kvm_vcpu *vcpu)
3181 {
3182 struct sys_reg_params params;
3183 unsigned long esr = kvm_vcpu_get_esr(vcpu);
3184 int Rt = kvm_vcpu_sys_get_rt(vcpu);
3185
3186 trace_kvm_handle_sys_reg(esr);
3187
3188 if (__check_nv_sr_forward(vcpu))
3189 return 1;
3190
3191 params = esr_sys64_to_params(esr);
3192 params.regval = vcpu_get_reg(vcpu, Rt);
3193
3194 if (!emulate_sys_reg(vcpu, ¶ms))
3195 return 1;
3196
3197 if (!params.is_write)
3198 vcpu_set_reg(vcpu, Rt, params.regval);
3199 return 1;
3200 }
3201
3202 /******************************************************************************
3203 * Userspace API
3204 *****************************************************************************/
3205
index_to_params(u64 id,struct sys_reg_params * params)3206 static bool index_to_params(u64 id, struct sys_reg_params *params)
3207 {
3208 switch (id & KVM_REG_SIZE_MASK) {
3209 case KVM_REG_SIZE_U64:
3210 /* Any unused index bits means it's not valid. */
3211 if (id & ~(KVM_REG_ARCH_MASK | KVM_REG_SIZE_MASK
3212 | KVM_REG_ARM_COPROC_MASK
3213 | KVM_REG_ARM64_SYSREG_OP0_MASK
3214 | KVM_REG_ARM64_SYSREG_OP1_MASK
3215 | KVM_REG_ARM64_SYSREG_CRN_MASK
3216 | KVM_REG_ARM64_SYSREG_CRM_MASK
3217 | KVM_REG_ARM64_SYSREG_OP2_MASK))
3218 return false;
3219 params->Op0 = ((id & KVM_REG_ARM64_SYSREG_OP0_MASK)
3220 >> KVM_REG_ARM64_SYSREG_OP0_SHIFT);
3221 params->Op1 = ((id & KVM_REG_ARM64_SYSREG_OP1_MASK)
3222 >> KVM_REG_ARM64_SYSREG_OP1_SHIFT);
3223 params->CRn = ((id & KVM_REG_ARM64_SYSREG_CRN_MASK)
3224 >> KVM_REG_ARM64_SYSREG_CRN_SHIFT);
3225 params->CRm = ((id & KVM_REG_ARM64_SYSREG_CRM_MASK)
3226 >> KVM_REG_ARM64_SYSREG_CRM_SHIFT);
3227 params->Op2 = ((id & KVM_REG_ARM64_SYSREG_OP2_MASK)
3228 >> KVM_REG_ARM64_SYSREG_OP2_SHIFT);
3229 return true;
3230 default:
3231 return false;
3232 }
3233 }
3234
get_reg_by_id(u64 id,const struct sys_reg_desc table[],unsigned int num)3235 const struct sys_reg_desc *get_reg_by_id(u64 id,
3236 const struct sys_reg_desc table[],
3237 unsigned int num)
3238 {
3239 struct sys_reg_params params;
3240
3241 if (!index_to_params(id, ¶ms))
3242 return NULL;
3243
3244 return find_reg(¶ms, table, num);
3245 }
3246
3247 /* Decode an index value, and find the sys_reg_desc entry. */
3248 static const struct sys_reg_desc *
id_to_sys_reg_desc(struct kvm_vcpu * vcpu,u64 id,const struct sys_reg_desc table[],unsigned int num)3249 id_to_sys_reg_desc(struct kvm_vcpu *vcpu, u64 id,
3250 const struct sys_reg_desc table[], unsigned int num)
3251
3252 {
3253 const struct sys_reg_desc *r;
3254
3255 /* We only do sys_reg for now. */
3256 if ((id & KVM_REG_ARM_COPROC_MASK) != KVM_REG_ARM64_SYSREG)
3257 return NULL;
3258
3259 r = get_reg_by_id(id, table, num);
3260
3261 /* Not saved in the sys_reg array and not otherwise accessible? */
3262 if (r && (!(r->reg || r->get_user) || sysreg_hidden(vcpu, r)))
3263 r = NULL;
3264
3265 return r;
3266 }
3267
3268 /*
3269 * These are the invariant sys_reg registers: we let the guest see the
3270 * host versions of these, so they're part of the guest state.
3271 *
3272 * A future CPU may provide a mechanism to present different values to
3273 * the guest, or a future kvm may trap them.
3274 */
3275
3276 #define FUNCTION_INVARIANT(reg) \
3277 static u64 get_##reg(struct kvm_vcpu *v, \
3278 const struct sys_reg_desc *r) \
3279 { \
3280 ((struct sys_reg_desc *)r)->val = read_sysreg(reg); \
3281 return ((struct sys_reg_desc *)r)->val; \
3282 }
3283
3284 FUNCTION_INVARIANT(midr_el1)
FUNCTION_INVARIANT(revidr_el1)3285 FUNCTION_INVARIANT(revidr_el1)
3286 FUNCTION_INVARIANT(aidr_el1)
3287
3288 static u64 get_ctr_el0(struct kvm_vcpu *v, const struct sys_reg_desc *r)
3289 {
3290 ((struct sys_reg_desc *)r)->val = read_sanitised_ftr_reg(SYS_CTR_EL0);
3291 return ((struct sys_reg_desc *)r)->val;
3292 }
3293
3294 /* ->val is filled in by kvm_sys_reg_table_init() */
3295 static struct sys_reg_desc invariant_sys_regs[] __ro_after_init = {
3296 { SYS_DESC(SYS_MIDR_EL1), NULL, get_midr_el1 },
3297 { SYS_DESC(SYS_REVIDR_EL1), NULL, get_revidr_el1 },
3298 { SYS_DESC(SYS_AIDR_EL1), NULL, get_aidr_el1 },
3299 { SYS_DESC(SYS_CTR_EL0), NULL, get_ctr_el0 },
3300 };
3301
get_invariant_sys_reg(u64 id,u64 __user * uaddr)3302 static int get_invariant_sys_reg(u64 id, u64 __user *uaddr)
3303 {
3304 const struct sys_reg_desc *r;
3305
3306 r = get_reg_by_id(id, invariant_sys_regs,
3307 ARRAY_SIZE(invariant_sys_regs));
3308 if (!r)
3309 return -ENOENT;
3310
3311 return put_user(r->val, uaddr);
3312 }
3313
set_invariant_sys_reg(u64 id,u64 __user * uaddr)3314 static int set_invariant_sys_reg(u64 id, u64 __user *uaddr)
3315 {
3316 const struct sys_reg_desc *r;
3317 u64 val;
3318
3319 r = get_reg_by_id(id, invariant_sys_regs,
3320 ARRAY_SIZE(invariant_sys_regs));
3321 if (!r)
3322 return -ENOENT;
3323
3324 if (get_user(val, uaddr))
3325 return -EFAULT;
3326
3327 /* This is what we mean by invariant: you can't change it. */
3328 if (r->val != val)
3329 return -EINVAL;
3330
3331 return 0;
3332 }
3333
demux_c15_get(struct kvm_vcpu * vcpu,u64 id,void __user * uaddr)3334 static int demux_c15_get(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
3335 {
3336 u32 val;
3337 u32 __user *uval = uaddr;
3338
3339 /* Fail if we have unknown bits set. */
3340 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
3341 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
3342 return -ENOENT;
3343
3344 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
3345 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
3346 if (KVM_REG_SIZE(id) != 4)
3347 return -ENOENT;
3348 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
3349 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
3350 if (val >= CSSELR_MAX)
3351 return -ENOENT;
3352
3353 return put_user(get_ccsidr(vcpu, val), uval);
3354 default:
3355 return -ENOENT;
3356 }
3357 }
3358
demux_c15_set(struct kvm_vcpu * vcpu,u64 id,void __user * uaddr)3359 static int demux_c15_set(struct kvm_vcpu *vcpu, u64 id, void __user *uaddr)
3360 {
3361 u32 val, newval;
3362 u32 __user *uval = uaddr;
3363
3364 /* Fail if we have unknown bits set. */
3365 if (id & ~(KVM_REG_ARCH_MASK|KVM_REG_SIZE_MASK|KVM_REG_ARM_COPROC_MASK
3366 | ((1 << KVM_REG_ARM_COPROC_SHIFT)-1)))
3367 return -ENOENT;
3368
3369 switch (id & KVM_REG_ARM_DEMUX_ID_MASK) {
3370 case KVM_REG_ARM_DEMUX_ID_CCSIDR:
3371 if (KVM_REG_SIZE(id) != 4)
3372 return -ENOENT;
3373 val = (id & KVM_REG_ARM_DEMUX_VAL_MASK)
3374 >> KVM_REG_ARM_DEMUX_VAL_SHIFT;
3375 if (val >= CSSELR_MAX)
3376 return -ENOENT;
3377
3378 if (get_user(newval, uval))
3379 return -EFAULT;
3380
3381 return set_ccsidr(vcpu, val, newval);
3382 default:
3383 return -ENOENT;
3384 }
3385 }
3386
kvm_sys_reg_get_user(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg,const struct sys_reg_desc table[],unsigned int num)3387 int kvm_sys_reg_get_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
3388 const struct sys_reg_desc table[], unsigned int num)
3389 {
3390 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
3391 const struct sys_reg_desc *r;
3392 u64 val;
3393 int ret;
3394
3395 r = id_to_sys_reg_desc(vcpu, reg->id, table, num);
3396 if (!r || sysreg_hidden_user(vcpu, r))
3397 return -ENOENT;
3398
3399 if (r->get_user) {
3400 ret = (r->get_user)(vcpu, r, &val);
3401 } else {
3402 val = __vcpu_sys_reg(vcpu, r->reg);
3403 ret = 0;
3404 }
3405
3406 if (!ret)
3407 ret = put_user(val, uaddr);
3408
3409 return ret;
3410 }
3411
kvm_arm_sys_reg_get_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)3412 int kvm_arm_sys_reg_get_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
3413 {
3414 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
3415 int err;
3416
3417 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
3418 return demux_c15_get(vcpu, reg->id, uaddr);
3419
3420 err = get_invariant_sys_reg(reg->id, uaddr);
3421 if (err != -ENOENT)
3422 return err;
3423
3424 return kvm_sys_reg_get_user(vcpu, reg,
3425 sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
3426 }
3427
kvm_sys_reg_set_user(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg,const struct sys_reg_desc table[],unsigned int num)3428 int kvm_sys_reg_set_user(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg,
3429 const struct sys_reg_desc table[], unsigned int num)
3430 {
3431 u64 __user *uaddr = (u64 __user *)(unsigned long)reg->addr;
3432 const struct sys_reg_desc *r;
3433 u64 val;
3434 int ret;
3435
3436 if (get_user(val, uaddr))
3437 return -EFAULT;
3438
3439 r = id_to_sys_reg_desc(vcpu, reg->id, table, num);
3440 if (!r || sysreg_hidden_user(vcpu, r))
3441 return -ENOENT;
3442
3443 if (sysreg_user_write_ignore(vcpu, r))
3444 return 0;
3445
3446 if (r->set_user) {
3447 ret = (r->set_user)(vcpu, r, val);
3448 } else {
3449 __vcpu_sys_reg(vcpu, r->reg) = val;
3450 ret = 0;
3451 }
3452
3453 return ret;
3454 }
3455
kvm_arm_sys_reg_set_reg(struct kvm_vcpu * vcpu,const struct kvm_one_reg * reg)3456 int kvm_arm_sys_reg_set_reg(struct kvm_vcpu *vcpu, const struct kvm_one_reg *reg)
3457 {
3458 void __user *uaddr = (void __user *)(unsigned long)reg->addr;
3459 int err;
3460
3461 if ((reg->id & KVM_REG_ARM_COPROC_MASK) == KVM_REG_ARM_DEMUX)
3462 return demux_c15_set(vcpu, reg->id, uaddr);
3463
3464 err = set_invariant_sys_reg(reg->id, uaddr);
3465 if (err != -ENOENT)
3466 return err;
3467
3468 return kvm_sys_reg_set_user(vcpu, reg,
3469 sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
3470 }
3471
num_demux_regs(void)3472 static unsigned int num_demux_regs(void)
3473 {
3474 return CSSELR_MAX;
3475 }
3476
write_demux_regids(u64 __user * uindices)3477 static int write_demux_regids(u64 __user *uindices)
3478 {
3479 u64 val = KVM_REG_ARM64 | KVM_REG_SIZE_U32 | KVM_REG_ARM_DEMUX;
3480 unsigned int i;
3481
3482 val |= KVM_REG_ARM_DEMUX_ID_CCSIDR;
3483 for (i = 0; i < CSSELR_MAX; i++) {
3484 if (put_user(val | i, uindices))
3485 return -EFAULT;
3486 uindices++;
3487 }
3488 return 0;
3489 }
3490
sys_reg_to_index(const struct sys_reg_desc * reg)3491 static u64 sys_reg_to_index(const struct sys_reg_desc *reg)
3492 {
3493 return (KVM_REG_ARM64 | KVM_REG_SIZE_U64 |
3494 KVM_REG_ARM64_SYSREG |
3495 (reg->Op0 << KVM_REG_ARM64_SYSREG_OP0_SHIFT) |
3496 (reg->Op1 << KVM_REG_ARM64_SYSREG_OP1_SHIFT) |
3497 (reg->CRn << KVM_REG_ARM64_SYSREG_CRN_SHIFT) |
3498 (reg->CRm << KVM_REG_ARM64_SYSREG_CRM_SHIFT) |
3499 (reg->Op2 << KVM_REG_ARM64_SYSREG_OP2_SHIFT));
3500 }
3501
copy_reg_to_user(const struct sys_reg_desc * reg,u64 __user ** uind)3502 static bool copy_reg_to_user(const struct sys_reg_desc *reg, u64 __user **uind)
3503 {
3504 if (!*uind)
3505 return true;
3506
3507 if (put_user(sys_reg_to_index(reg), *uind))
3508 return false;
3509
3510 (*uind)++;
3511 return true;
3512 }
3513
walk_one_sys_reg(const struct kvm_vcpu * vcpu,const struct sys_reg_desc * rd,u64 __user ** uind,unsigned int * total)3514 static int walk_one_sys_reg(const struct kvm_vcpu *vcpu,
3515 const struct sys_reg_desc *rd,
3516 u64 __user **uind,
3517 unsigned int *total)
3518 {
3519 /*
3520 * Ignore registers we trap but don't save,
3521 * and for which no custom user accessor is provided.
3522 */
3523 if (!(rd->reg || rd->get_user))
3524 return 0;
3525
3526 if (sysreg_hidden_user(vcpu, rd))
3527 return 0;
3528
3529 if (!copy_reg_to_user(rd, uind))
3530 return -EFAULT;
3531
3532 (*total)++;
3533 return 0;
3534 }
3535
3536 /* Assumed ordered tables, see kvm_sys_reg_table_init. */
walk_sys_regs(struct kvm_vcpu * vcpu,u64 __user * uind)3537 static int walk_sys_regs(struct kvm_vcpu *vcpu, u64 __user *uind)
3538 {
3539 const struct sys_reg_desc *i2, *end2;
3540 unsigned int total = 0;
3541 int err;
3542
3543 i2 = sys_reg_descs;
3544 end2 = sys_reg_descs + ARRAY_SIZE(sys_reg_descs);
3545
3546 while (i2 != end2) {
3547 err = walk_one_sys_reg(vcpu, i2++, &uind, &total);
3548 if (err)
3549 return err;
3550 }
3551 return total;
3552 }
3553
kvm_arm_num_sys_reg_descs(struct kvm_vcpu * vcpu)3554 unsigned long kvm_arm_num_sys_reg_descs(struct kvm_vcpu *vcpu)
3555 {
3556 return ARRAY_SIZE(invariant_sys_regs)
3557 + num_demux_regs()
3558 + walk_sys_regs(vcpu, (u64 __user *)NULL);
3559 }
3560
kvm_arm_copy_sys_reg_indices(struct kvm_vcpu * vcpu,u64 __user * uindices)3561 int kvm_arm_copy_sys_reg_indices(struct kvm_vcpu *vcpu, u64 __user *uindices)
3562 {
3563 unsigned int i;
3564 int err;
3565
3566 /* Then give them all the invariant registers' indices. */
3567 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++) {
3568 if (put_user(sys_reg_to_index(&invariant_sys_regs[i]), uindices))
3569 return -EFAULT;
3570 uindices++;
3571 }
3572
3573 err = walk_sys_regs(vcpu, uindices);
3574 if (err < 0)
3575 return err;
3576 uindices += err;
3577
3578 return write_demux_regids(uindices);
3579 }
3580
kvm_sys_reg_table_init(void)3581 int __init kvm_sys_reg_table_init(void)
3582 {
3583 struct sys_reg_params params;
3584 bool valid = true;
3585 unsigned int i;
3586
3587 /* Make sure tables are unique and in order. */
3588 valid &= check_sysreg_table(sys_reg_descs, ARRAY_SIZE(sys_reg_descs), false);
3589 valid &= check_sysreg_table(cp14_regs, ARRAY_SIZE(cp14_regs), true);
3590 valid &= check_sysreg_table(cp14_64_regs, ARRAY_SIZE(cp14_64_regs), true);
3591 valid &= check_sysreg_table(cp15_regs, ARRAY_SIZE(cp15_regs), true);
3592 valid &= check_sysreg_table(cp15_64_regs, ARRAY_SIZE(cp15_64_regs), true);
3593 valid &= check_sysreg_table(invariant_sys_regs, ARRAY_SIZE(invariant_sys_regs), false);
3594
3595 if (!valid)
3596 return -EINVAL;
3597
3598 /* We abuse the reset function to overwrite the table itself. */
3599 for (i = 0; i < ARRAY_SIZE(invariant_sys_regs); i++)
3600 invariant_sys_regs[i].reset(NULL, &invariant_sys_regs[i]);
3601
3602 /* Find the first idreg (SYS_ID_PFR0_EL1) in sys_reg_descs. */
3603 params = encoding_to_params(SYS_ID_PFR0_EL1);
3604 first_idreg = find_reg(¶ms, sys_reg_descs, ARRAY_SIZE(sys_reg_descs));
3605 if (!first_idreg)
3606 return -EINVAL;
3607
3608 if (kvm_get_mode() == KVM_MODE_NV)
3609 return populate_nv_trap_config();
3610
3611 return 0;
3612 }
3613