1 /* SPDX-License-Identifier: GPL-2.0+ */
2 /*
3  * Copyright (c) 2010-2014, NVIDIA CORPORATION. All rights reserved.
4  */
5 
6 #ifndef _TEGRA30_PINMUX_H_
7 #define _TEGRA30_PINMUX_H_
8 
9 enum pmux_pingrp {
10 	PMUX_PINGRP_ULPI_DATA0_PO1,
11 	PMUX_PINGRP_ULPI_DATA1_PO2,
12 	PMUX_PINGRP_ULPI_DATA2_PO3,
13 	PMUX_PINGRP_ULPI_DATA3_PO4,
14 	PMUX_PINGRP_ULPI_DATA4_PO5,
15 	PMUX_PINGRP_ULPI_DATA5_PO6,
16 	PMUX_PINGRP_ULPI_DATA6_PO7,
17 	PMUX_PINGRP_ULPI_DATA7_PO0,
18 	PMUX_PINGRP_ULPI_CLK_PY0,
19 	PMUX_PINGRP_ULPI_DIR_PY1,
20 	PMUX_PINGRP_ULPI_NXT_PY2,
21 	PMUX_PINGRP_ULPI_STP_PY3,
22 	PMUX_PINGRP_DAP3_FS_PP0,
23 	PMUX_PINGRP_DAP3_DIN_PP1,
24 	PMUX_PINGRP_DAP3_DOUT_PP2,
25 	PMUX_PINGRP_DAP3_SCLK_PP3,
26 	PMUX_PINGRP_PV0,
27 	PMUX_PINGRP_PV1,
28 	PMUX_PINGRP_SDMMC1_CLK_PZ0,
29 	PMUX_PINGRP_SDMMC1_CMD_PZ1,
30 	PMUX_PINGRP_SDMMC1_DAT3_PY4,
31 	PMUX_PINGRP_SDMMC1_DAT2_PY5,
32 	PMUX_PINGRP_SDMMC1_DAT1_PY6,
33 	PMUX_PINGRP_SDMMC1_DAT0_PY7,
34 	PMUX_PINGRP_PV2,
35 	PMUX_PINGRP_PV3,
36 	PMUX_PINGRP_CLK2_OUT_PW5,
37 	PMUX_PINGRP_CLK2_REQ_PCC5,
38 	PMUX_PINGRP_LCD_PWR1_PC1,
39 	PMUX_PINGRP_LCD_PWR2_PC6,
40 	PMUX_PINGRP_LCD_SDIN_PZ2,
41 	PMUX_PINGRP_LCD_SDOUT_PN5,
42 	PMUX_PINGRP_LCD_WR_N_PZ3,
43 	PMUX_PINGRP_LCD_CS0_N_PN4,
44 	PMUX_PINGRP_LCD_DC0_PN6,
45 	PMUX_PINGRP_LCD_SCK_PZ4,
46 	PMUX_PINGRP_LCD_PWR0_PB2,
47 	PMUX_PINGRP_LCD_PCLK_PB3,
48 	PMUX_PINGRP_LCD_DE_PJ1,
49 	PMUX_PINGRP_LCD_HSYNC_PJ3,
50 	PMUX_PINGRP_LCD_VSYNC_PJ4,
51 	PMUX_PINGRP_LCD_D0_PE0,
52 	PMUX_PINGRP_LCD_D1_PE1,
53 	PMUX_PINGRP_LCD_D2_PE2,
54 	PMUX_PINGRP_LCD_D3_PE3,
55 	PMUX_PINGRP_LCD_D4_PE4,
56 	PMUX_PINGRP_LCD_D5_PE5,
57 	PMUX_PINGRP_LCD_D6_PE6,
58 	PMUX_PINGRP_LCD_D7_PE7,
59 	PMUX_PINGRP_LCD_D8_PF0,
60 	PMUX_PINGRP_LCD_D9_PF1,
61 	PMUX_PINGRP_LCD_D10_PF2,
62 	PMUX_PINGRP_LCD_D11_PF3,
63 	PMUX_PINGRP_LCD_D12_PF4,
64 	PMUX_PINGRP_LCD_D13_PF5,
65 	PMUX_PINGRP_LCD_D14_PF6,
66 	PMUX_PINGRP_LCD_D15_PF7,
67 	PMUX_PINGRP_LCD_D16_PM0,
68 	PMUX_PINGRP_LCD_D17_PM1,
69 	PMUX_PINGRP_LCD_D18_PM2,
70 	PMUX_PINGRP_LCD_D19_PM3,
71 	PMUX_PINGRP_LCD_D20_PM4,
72 	PMUX_PINGRP_LCD_D21_PM5,
73 	PMUX_PINGRP_LCD_D22_PM6,
74 	PMUX_PINGRP_LCD_D23_PM7,
75 	PMUX_PINGRP_LCD_CS1_N_PW0,
76 	PMUX_PINGRP_LCD_M1_PW1,
77 	PMUX_PINGRP_LCD_DC1_PD2,
78 	PMUX_PINGRP_HDMI_INT_PN7,
79 	PMUX_PINGRP_DDC_SCL_PV4,
80 	PMUX_PINGRP_DDC_SDA_PV5,
81 	PMUX_PINGRP_CRT_HSYNC_PV6,
82 	PMUX_PINGRP_CRT_VSYNC_PV7,
83 	PMUX_PINGRP_VI_D0_PT4,
84 	PMUX_PINGRP_VI_D1_PD5,
85 	PMUX_PINGRP_VI_D2_PL0,
86 	PMUX_PINGRP_VI_D3_PL1,
87 	PMUX_PINGRP_VI_D4_PL2,
88 	PMUX_PINGRP_VI_D5_PL3,
89 	PMUX_PINGRP_VI_D6_PL4,
90 	PMUX_PINGRP_VI_D7_PL5,
91 	PMUX_PINGRP_VI_D8_PL6,
92 	PMUX_PINGRP_VI_D9_PL7,
93 	PMUX_PINGRP_VI_D10_PT2,
94 	PMUX_PINGRP_VI_D11_PT3,
95 	PMUX_PINGRP_VI_PCLK_PT0,
96 	PMUX_PINGRP_VI_MCLK_PT1,
97 	PMUX_PINGRP_VI_VSYNC_PD6,
98 	PMUX_PINGRP_VI_HSYNC_PD7,
99 	PMUX_PINGRP_UART2_RXD_PC3,
100 	PMUX_PINGRP_UART2_TXD_PC2,
101 	PMUX_PINGRP_UART2_RTS_N_PJ6,
102 	PMUX_PINGRP_UART2_CTS_N_PJ5,
103 	PMUX_PINGRP_UART3_TXD_PW6,
104 	PMUX_PINGRP_UART3_RXD_PW7,
105 	PMUX_PINGRP_UART3_CTS_N_PA1,
106 	PMUX_PINGRP_UART3_RTS_N_PC0,
107 	PMUX_PINGRP_PU0,
108 	PMUX_PINGRP_PU1,
109 	PMUX_PINGRP_PU2,
110 	PMUX_PINGRP_PU3,
111 	PMUX_PINGRP_PU4,
112 	PMUX_PINGRP_PU5,
113 	PMUX_PINGRP_PU6,
114 	PMUX_PINGRP_GEN1_I2C_SDA_PC5,
115 	PMUX_PINGRP_GEN1_I2C_SCL_PC4,
116 	PMUX_PINGRP_DAP4_FS_PP4,
117 	PMUX_PINGRP_DAP4_DIN_PP5,
118 	PMUX_PINGRP_DAP4_DOUT_PP6,
119 	PMUX_PINGRP_DAP4_SCLK_PP7,
120 	PMUX_PINGRP_CLK3_OUT_PEE0,
121 	PMUX_PINGRP_CLK3_REQ_PEE1,
122 	PMUX_PINGRP_GMI_WP_N_PC7,
123 	PMUX_PINGRP_GMI_IORDY_PI5,
124 	PMUX_PINGRP_GMI_WAIT_PI7,
125 	PMUX_PINGRP_GMI_ADV_N_PK0,
126 	PMUX_PINGRP_GMI_CLK_PK1,
127 	PMUX_PINGRP_GMI_CS0_N_PJ0,
128 	PMUX_PINGRP_GMI_CS1_N_PJ2,
129 	PMUX_PINGRP_GMI_CS2_N_PK3,
130 	PMUX_PINGRP_GMI_CS3_N_PK4,
131 	PMUX_PINGRP_GMI_CS4_N_PK2,
132 	PMUX_PINGRP_GMI_CS6_N_PI3,
133 	PMUX_PINGRP_GMI_CS7_N_PI6,
134 	PMUX_PINGRP_GMI_AD0_PG0,
135 	PMUX_PINGRP_GMI_AD1_PG1,
136 	PMUX_PINGRP_GMI_AD2_PG2,
137 	PMUX_PINGRP_GMI_AD3_PG3,
138 	PMUX_PINGRP_GMI_AD4_PG4,
139 	PMUX_PINGRP_GMI_AD5_PG5,
140 	PMUX_PINGRP_GMI_AD6_PG6,
141 	PMUX_PINGRP_GMI_AD7_PG7,
142 	PMUX_PINGRP_GMI_AD8_PH0,
143 	PMUX_PINGRP_GMI_AD9_PH1,
144 	PMUX_PINGRP_GMI_AD10_PH2,
145 	PMUX_PINGRP_GMI_AD11_PH3,
146 	PMUX_PINGRP_GMI_AD12_PH4,
147 	PMUX_PINGRP_GMI_AD13_PH5,
148 	PMUX_PINGRP_GMI_AD14_PH6,
149 	PMUX_PINGRP_GMI_AD15_PH7,
150 	PMUX_PINGRP_GMI_A16_PJ7,
151 	PMUX_PINGRP_GMI_A17_PB0,
152 	PMUX_PINGRP_GMI_A18_PB1,
153 	PMUX_PINGRP_GMI_A19_PK7,
154 	PMUX_PINGRP_GMI_WR_N_PI0,
155 	PMUX_PINGRP_GMI_OE_N_PI1,
156 	PMUX_PINGRP_GMI_DQS_PI2,
157 	PMUX_PINGRP_GMI_RST_N_PI4,
158 	PMUX_PINGRP_GEN2_I2C_SCL_PT5,
159 	PMUX_PINGRP_GEN2_I2C_SDA_PT6,
160 	PMUX_PINGRP_SDMMC4_CLK_PCC4,
161 	PMUX_PINGRP_SDMMC4_CMD_PT7,
162 	PMUX_PINGRP_SDMMC4_DAT0_PAA0,
163 	PMUX_PINGRP_SDMMC4_DAT1_PAA1,
164 	PMUX_PINGRP_SDMMC4_DAT2_PAA2,
165 	PMUX_PINGRP_SDMMC4_DAT3_PAA3,
166 	PMUX_PINGRP_SDMMC4_DAT4_PAA4,
167 	PMUX_PINGRP_SDMMC4_DAT5_PAA5,
168 	PMUX_PINGRP_SDMMC4_DAT6_PAA6,
169 	PMUX_PINGRP_SDMMC4_DAT7_PAA7,
170 	PMUX_PINGRP_SDMMC4_RST_N_PCC3,
171 	PMUX_PINGRP_CAM_MCLK_PCC0,
172 	PMUX_PINGRP_PCC1,
173 	PMUX_PINGRP_PBB0,
174 	PMUX_PINGRP_CAM_I2C_SCL_PBB1,
175 	PMUX_PINGRP_CAM_I2C_SDA_PBB2,
176 	PMUX_PINGRP_PBB3,
177 	PMUX_PINGRP_PBB4,
178 	PMUX_PINGRP_PBB5,
179 	PMUX_PINGRP_PBB6,
180 	PMUX_PINGRP_PBB7,
181 	PMUX_PINGRP_PCC2,
182 	PMUX_PINGRP_JTAG_RTCK_PU7,
183 	PMUX_PINGRP_PWR_I2C_SCL_PZ6,
184 	PMUX_PINGRP_PWR_I2C_SDA_PZ7,
185 	PMUX_PINGRP_KB_ROW0_PR0,
186 	PMUX_PINGRP_KB_ROW1_PR1,
187 	PMUX_PINGRP_KB_ROW2_PR2,
188 	PMUX_PINGRP_KB_ROW3_PR3,
189 	PMUX_PINGRP_KB_ROW4_PR4,
190 	PMUX_PINGRP_KB_ROW5_PR5,
191 	PMUX_PINGRP_KB_ROW6_PR6,
192 	PMUX_PINGRP_KB_ROW7_PR7,
193 	PMUX_PINGRP_KB_ROW8_PS0,
194 	PMUX_PINGRP_KB_ROW9_PS1,
195 	PMUX_PINGRP_KB_ROW10_PS2,
196 	PMUX_PINGRP_KB_ROW11_PS3,
197 	PMUX_PINGRP_KB_ROW12_PS4,
198 	PMUX_PINGRP_KB_ROW13_PS5,
199 	PMUX_PINGRP_KB_ROW14_PS6,
200 	PMUX_PINGRP_KB_ROW15_PS7,
201 	PMUX_PINGRP_KB_COL0_PQ0,
202 	PMUX_PINGRP_KB_COL1_PQ1,
203 	PMUX_PINGRP_KB_COL2_PQ2,
204 	PMUX_PINGRP_KB_COL3_PQ3,
205 	PMUX_PINGRP_KB_COL4_PQ4,
206 	PMUX_PINGRP_KB_COL5_PQ5,
207 	PMUX_PINGRP_KB_COL6_PQ6,
208 	PMUX_PINGRP_KB_COL7_PQ7,
209 	PMUX_PINGRP_CLK_32K_OUT_PA0,
210 	PMUX_PINGRP_SYS_CLK_REQ_PZ5,
211 	PMUX_PINGRP_CORE_PWR_REQ,
212 	PMUX_PINGRP_CPU_PWR_REQ,
213 	PMUX_PINGRP_PWR_INT_N,
214 	PMUX_PINGRP_CLK_32K_IN,
215 	PMUX_PINGRP_OWR,
216 	PMUX_PINGRP_DAP1_FS_PN0,
217 	PMUX_PINGRP_DAP1_DIN_PN1,
218 	PMUX_PINGRP_DAP1_DOUT_PN2,
219 	PMUX_PINGRP_DAP1_SCLK_PN3,
220 	PMUX_PINGRP_CLK1_REQ_PEE2,
221 	PMUX_PINGRP_CLK1_OUT_PW4,
222 	PMUX_PINGRP_SPDIF_IN_PK6,
223 	PMUX_PINGRP_SPDIF_OUT_PK5,
224 	PMUX_PINGRP_DAP2_FS_PA2,
225 	PMUX_PINGRP_DAP2_DIN_PA4,
226 	PMUX_PINGRP_DAP2_DOUT_PA5,
227 	PMUX_PINGRP_DAP2_SCLK_PA3,
228 	PMUX_PINGRP_SPI2_MOSI_PX0,
229 	PMUX_PINGRP_SPI2_MISO_PX1,
230 	PMUX_PINGRP_SPI2_CS0_N_PX3,
231 	PMUX_PINGRP_SPI2_SCK_PX2,
232 	PMUX_PINGRP_SPI1_MOSI_PX4,
233 	PMUX_PINGRP_SPI1_SCK_PX5,
234 	PMUX_PINGRP_SPI1_CS0_N_PX6,
235 	PMUX_PINGRP_SPI1_MISO_PX7,
236 	PMUX_PINGRP_SPI2_CS1_N_PW2,
237 	PMUX_PINGRP_SPI2_CS2_N_PW3,
238 	PMUX_PINGRP_SDMMC3_CLK_PA6,
239 	PMUX_PINGRP_SDMMC3_CMD_PA7,
240 	PMUX_PINGRP_SDMMC3_DAT0_PB7,
241 	PMUX_PINGRP_SDMMC3_DAT1_PB6,
242 	PMUX_PINGRP_SDMMC3_DAT2_PB5,
243 	PMUX_PINGRP_SDMMC3_DAT3_PB4,
244 	PMUX_PINGRP_SDMMC3_DAT4_PD1,
245 	PMUX_PINGRP_SDMMC3_DAT5_PD0,
246 	PMUX_PINGRP_SDMMC3_DAT6_PD3,
247 	PMUX_PINGRP_SDMMC3_DAT7_PD4,
248 	PMUX_PINGRP_PEX_L0_PRSNT_N_PDD0,
249 	PMUX_PINGRP_PEX_L0_RST_N_PDD1,
250 	PMUX_PINGRP_PEX_L0_CLKREQ_N_PDD2,
251 	PMUX_PINGRP_PEX_WAKE_N_PDD3,
252 	PMUX_PINGRP_PEX_L1_PRSNT_N_PDD4,
253 	PMUX_PINGRP_PEX_L1_RST_N_PDD5,
254 	PMUX_PINGRP_PEX_L1_CLKREQ_N_PDD6,
255 	PMUX_PINGRP_PEX_L2_PRSNT_N_PDD7,
256 	PMUX_PINGRP_PEX_L2_RST_N_PCC6,
257 	PMUX_PINGRP_PEX_L2_CLKREQ_N_PCC7,
258 	PMUX_PINGRP_HDMI_CEC_PEE3,
259 	PMUX_PINGRP_COUNT,
260 };
261 
262 enum pmux_drvgrp {
263 	PMUX_DRVGRP_AO1,
264 	PMUX_DRVGRP_AO2,
265 	PMUX_DRVGRP_AT1,
266 	PMUX_DRVGRP_AT2,
267 	PMUX_DRVGRP_AT3,
268 	PMUX_DRVGRP_AT4,
269 	PMUX_DRVGRP_AT5,
270 	PMUX_DRVGRP_CDEV1,
271 	PMUX_DRVGRP_CDEV2,
272 	PMUX_DRVGRP_CSUS,
273 	PMUX_DRVGRP_DAP1,
274 	PMUX_DRVGRP_DAP2,
275 	PMUX_DRVGRP_DAP3,
276 	PMUX_DRVGRP_DAP4,
277 	PMUX_DRVGRP_DBG,
278 	PMUX_DRVGRP_LCD1,
279 	PMUX_DRVGRP_LCD2,
280 	PMUX_DRVGRP_SDIO2,
281 	PMUX_DRVGRP_SDIO3,
282 	PMUX_DRVGRP_SPI,
283 	PMUX_DRVGRP_UAA,
284 	PMUX_DRVGRP_UAB,
285 	PMUX_DRVGRP_UART2,
286 	PMUX_DRVGRP_UART3,
287 	PMUX_DRVGRP_VI1,
288 	PMUX_DRVGRP_SDIO1 = (0x84 / 4),
289 	PMUX_DRVGRP_CRT = (0x90 / 4),
290 	PMUX_DRVGRP_DDC,
291 	PMUX_DRVGRP_GMA,
292 	PMUX_DRVGRP_GMB,
293 	PMUX_DRVGRP_GMC,
294 	PMUX_DRVGRP_GMD,
295 	PMUX_DRVGRP_GME,
296 	PMUX_DRVGRP_GMF,
297 	PMUX_DRVGRP_GMG,
298 	PMUX_DRVGRP_GMH,
299 	PMUX_DRVGRP_OWR,
300 	PMUX_DRVGRP_UDA,
301 	PMUX_DRVGRP_GPV,
302 	PMUX_DRVGRP_DEV3,
303 	PMUX_DRVGRP_CEC = (0xd0 / 4),
304 	PMUX_DRVGRP_COUNT,
305 };
306 
307 enum pmux_func {
308 	PMUX_FUNC_DEFAULT,
309 	PMUX_FUNC_BLINK,
310 	PMUX_FUNC_CEC,
311 	PMUX_FUNC_CLK_12M_OUT,
312 	PMUX_FUNC_CLK_32K_IN,
313 	PMUX_FUNC_CORE_PWR_REQ,
314 	PMUX_FUNC_CPU_PWR_REQ,
315 	PMUX_FUNC_CRT,
316 	PMUX_FUNC_DAP,
317 	PMUX_FUNC_DDR,
318 	PMUX_FUNC_DEV3,
319 	PMUX_FUNC_DISPLAYA,
320 	PMUX_FUNC_DISPLAYB,
321 	PMUX_FUNC_DTV,
322 	PMUX_FUNC_EXTPERIPH1,
323 	PMUX_FUNC_EXTPERIPH2,
324 	PMUX_FUNC_EXTPERIPH3,
325 	PMUX_FUNC_GMI,
326 	PMUX_FUNC_GMI_ALT,
327 	PMUX_FUNC_HDA,
328 	PMUX_FUNC_HDCP,
329 	PMUX_FUNC_HDMI,
330 	PMUX_FUNC_HSI,
331 	PMUX_FUNC_I2C1,
332 	PMUX_FUNC_I2C2,
333 	PMUX_FUNC_I2C3,
334 	PMUX_FUNC_I2C4,
335 	PMUX_FUNC_I2CPWR,
336 	PMUX_FUNC_I2S0,
337 	PMUX_FUNC_I2S1,
338 	PMUX_FUNC_I2S2,
339 	PMUX_FUNC_I2S3,
340 	PMUX_FUNC_I2S4,
341 	PMUX_FUNC_INVALID,
342 	PMUX_FUNC_KBC,
343 	PMUX_FUNC_MIO,
344 	PMUX_FUNC_NAND,
345 	PMUX_FUNC_NAND_ALT,
346 	PMUX_FUNC_OWR,
347 	PMUX_FUNC_PCIE,
348 	PMUX_FUNC_PWM0,
349 	PMUX_FUNC_PWM1,
350 	PMUX_FUNC_PWM2,
351 	PMUX_FUNC_PWM3,
352 	PMUX_FUNC_PWR_INT_N,
353 	PMUX_FUNC_RTCK,
354 	PMUX_FUNC_SATA,
355 	PMUX_FUNC_SDMMC1,
356 	PMUX_FUNC_SDMMC2,
357 	PMUX_FUNC_SDMMC3,
358 	PMUX_FUNC_SDMMC4,
359 	PMUX_FUNC_SPDIF,
360 	PMUX_FUNC_SPI1,
361 	PMUX_FUNC_SPI2,
362 	PMUX_FUNC_SPI2_ALT,
363 	PMUX_FUNC_SPI3,
364 	PMUX_FUNC_SPI4,
365 	PMUX_FUNC_SPI5,
366 	PMUX_FUNC_SPI6,
367 	PMUX_FUNC_SYSCLK,
368 	PMUX_FUNC_TEST,
369 	PMUX_FUNC_TRACE,
370 	PMUX_FUNC_UARTA,
371 	PMUX_FUNC_UARTB,
372 	PMUX_FUNC_UARTC,
373 	PMUX_FUNC_UARTD,
374 	PMUX_FUNC_UARTE,
375 	PMUX_FUNC_ULPI,
376 	PMUX_FUNC_VGP1,
377 	PMUX_FUNC_VGP2,
378 	PMUX_FUNC_VGP3,
379 	PMUX_FUNC_VGP4,
380 	PMUX_FUNC_VGP5,
381 	PMUX_FUNC_VGP6,
382 	PMUX_FUNC_VI,
383 	PMUX_FUNC_VI_ALT1,
384 	PMUX_FUNC_VI_ALT2,
385 	PMUX_FUNC_VI_ALT3,
386 	PMUX_FUNC_RSVD1,
387 	PMUX_FUNC_RSVD2,
388 	PMUX_FUNC_RSVD3,
389 	PMUX_FUNC_RSVD4,
390 	PMUX_FUNC_COUNT,
391 };
392 
393 #define TEGRA_PMX_SOC_DRV_GROUP_BASE_REG 0x868
394 #define TEGRA_PMX_SOC_HAS_DRVGRPS
395 #define TEGRA_PMX_GRPS_HAVE_LPMD
396 #define TEGRA_PMX_GRPS_HAVE_SCHMT
397 #define TEGRA_PMX_GRPS_HAVE_HSM
398 #define TEGRA_PMX_PINS_HAVE_E_INPUT
399 #define TEGRA_PMX_PINS_HAVE_LOCK
400 #define TEGRA_PMX_PINS_HAVE_OD
401 #define TEGRA_PMX_PINS_HAVE_IO_RESET
402 #include <asm/arch-tegra/pinmux.h>
403 
404 #endif /* _TEGRA30_PINMUX_H_ */
405