1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3 * TC358746 - Parallel <-> CSI-2 Bridge
4 *
5 * Copyright 2022 Marco Felsch <kernel@pengutronix.de>
6 *
7 * Notes:
8 * - Currently only 'Parallel-in -> CSI-out' mode is supported!
9 */
10
11 #include <linux/bitfield.h>
12 #include <linux/clk.h>
13 #include <linux/clk-provider.h>
14 #include <linux/delay.h>
15 #include <linux/i2c.h>
16 #include <linux/interrupt.h>
17 #include <linux/kernel.h>
18 #include <linux/module.h>
19 #include <linux/phy/phy-mipi-dphy.h>
20 #include <linux/property.h>
21 #include <linux/pm_runtime.h>
22 #include <linux/regmap.h>
23 #include <linux/units.h>
24 #include <media/v4l2-ctrls.h>
25 #include <media/v4l2-device.h>
26 #include <media/v4l2-fwnode.h>
27 #include <media/v4l2-mc.h>
28
29 /* 16-bit registers */
30 #define CHIPID_REG 0x0000
31 #define CHIPID GENMASK(15, 8)
32
33 #define SYSCTL_REG 0x0002
34 #define SRESET BIT(0)
35
36 #define CONFCTL_REG 0x0004
37 #define PDATAF_MASK GENMASK(9, 8)
38 #define PDATAF_MODE0 0
39 #define PDATAF_MODE1 1
40 #define PDATAF_MODE2 2
41 #define PDATAF(val) FIELD_PREP(PDATAF_MASK, (val))
42 #define PPEN BIT(6)
43 #define DATALANE_MASK GENMASK(1, 0)
44
45 #define FIFOCTL_REG 0x0006
46 #define DATAFMT_REG 0x0008
47 #define PDFMT(val) FIELD_PREP(GENMASK(7, 4), (val))
48
49 #define MCLKCTL_REG 0x000c
50 #define MCLK_HIGH_MASK GENMASK(15, 8)
51 #define MCLK_LOW_MASK GENMASK(7, 0)
52 #define MCLK_HIGH(val) FIELD_PREP(MCLK_HIGH_MASK, (val))
53 #define MCLK_LOW(val) FIELD_PREP(MCLK_LOW_MASK, (val))
54
55 #define PLLCTL0_REG 0x0016
56 #define PLL_PRD_MASK GENMASK(15, 12)
57 #define PLL_PRD(val) FIELD_PREP(PLL_PRD_MASK, (val))
58 #define PLL_FBD_MASK GENMASK(8, 0)
59 #define PLL_FBD(val) FIELD_PREP(PLL_FBD_MASK, (val))
60
61 #define PLLCTL1_REG 0x0018
62 #define PLL_FRS_MASK GENMASK(11, 10)
63 #define PLL_FRS(val) FIELD_PREP(PLL_FRS_MASK, (val))
64 #define CKEN BIT(4)
65 #define RESETB BIT(1)
66 #define PLL_EN BIT(0)
67
68 #define CLKCTL_REG 0x0020
69 #define MCLKDIV_MASK GENMASK(3, 2)
70 #define MCLKDIV(val) FIELD_PREP(MCLKDIV_MASK, (val))
71 #define MCLKDIV_8 0
72 #define MCLKDIV_4 1
73 #define MCLKDIV_2 2
74
75 #define WORDCNT_REG 0x0022
76 #define PP_MISC_REG 0x0032
77 #define FRMSTOP BIT(15)
78 #define RSTPTR BIT(14)
79
80 /* 32-bit registers */
81 #define CLW_DPHYCONTTX_REG 0x0100
82 #define CLW_CNTRL_REG 0x0140
83 #define D0W_CNTRL_REG 0x0144
84 #define LANEDISABLE BIT(0)
85
86 #define STARTCNTRL_REG 0x0204
87 #define START BIT(0)
88
89 #define LINEINITCNT_REG 0x0210
90 #define LPTXTIMECNT_REG 0x0214
91 #define TCLK_HEADERCNT_REG 0x0218
92 #define TCLK_ZEROCNT(val) FIELD_PREP(GENMASK(15, 8), (val))
93 #define TCLK_PREPARECNT(val) FIELD_PREP(GENMASK(6, 0), (val))
94
95 #define TCLK_TRAILCNT_REG 0x021C
96 #define THS_HEADERCNT_REG 0x0220
97 #define THS_ZEROCNT(val) FIELD_PREP(GENMASK(14, 8), (val))
98 #define THS_PREPARECNT(val) FIELD_PREP(GENMASK(6, 0), (val))
99
100 #define TWAKEUP_REG 0x0224
101 #define TCLK_POSTCNT_REG 0x0228
102 #define THS_TRAILCNT_REG 0x022C
103 #define HSTXVREGEN_REG 0x0234
104 #define TXOPTIONCNTRL_REG 0x0238
105 #define CSI_CONTROL_REG 0x040C
106 #define CSI_MODE BIT(15)
107 #define TXHSMD BIT(7)
108 #define NOL(val) FIELD_PREP(GENMASK(2, 1), (val))
109
110 #define CSI_CONFW_REG 0x0500
111 #define MODE(val) FIELD_PREP(GENMASK(31, 29), (val))
112 #define MODE_SET 0x5
113 #define ADDRESS(val) FIELD_PREP(GENMASK(28, 24), (val))
114 #define CSI_CONTROL_ADDRESS 0x3
115 #define DATA(val) FIELD_PREP(GENMASK(15, 0), (val))
116
117 #define CSI_START_REG 0x0518
118 #define STRT BIT(0)
119
120 static const struct v4l2_mbus_framefmt tc358746_def_fmt = {
121 .width = 640,
122 .height = 480,
123 .code = MEDIA_BUS_FMT_UYVY8_2X8,
124 .field = V4L2_FIELD_NONE,
125 .colorspace = V4L2_COLORSPACE_DEFAULT,
126 .ycbcr_enc = V4L2_YCBCR_ENC_DEFAULT,
127 .quantization = V4L2_QUANTIZATION_DEFAULT,
128 .xfer_func = V4L2_XFER_FUNC_DEFAULT,
129 };
130
131 static const char * const tc358746_supplies[] = {
132 "vddc", "vddio", "vddmipi"
133 };
134
135 enum {
136 TC358746_SINK,
137 TC358746_SOURCE,
138 TC358746_NR_PADS
139 };
140
141 struct tc358746 {
142 struct v4l2_subdev sd;
143 struct media_pad pads[TC358746_NR_PADS];
144 struct v4l2_async_notifier notifier;
145 struct v4l2_fwnode_endpoint csi_vep;
146
147 struct v4l2_ctrl_handler ctrl_hdl;
148
149 struct regmap *regmap;
150 struct clk *refclk;
151 struct gpio_desc *reset_gpio;
152 struct regulator_bulk_data supplies[ARRAY_SIZE(tc358746_supplies)];
153
154 struct clk_hw mclk_hw;
155 unsigned long mclk_rate;
156 u8 mclk_prediv;
157 u16 mclk_postdiv;
158
159 unsigned long pll_rate;
160 u8 pll_post_div;
161 u16 pll_pre_div;
162 u16 pll_mul;
163
164 #define TC358746_VB_MAX_SIZE (511 * 32)
165 #define TC358746_VB_DEFAULT_SIZE (1 * 32)
166 unsigned int vb_size; /* Video buffer size in bits */
167
168 struct phy_configure_opts_mipi_dphy dphy_cfg;
169 };
170
to_tc358746(struct v4l2_subdev * sd)171 static inline struct tc358746 *to_tc358746(struct v4l2_subdev *sd)
172 {
173 return container_of(sd, struct tc358746, sd);
174 }
175
clk_hw_to_tc358746(struct clk_hw * hw)176 static inline struct tc358746 *clk_hw_to_tc358746(struct clk_hw *hw)
177 {
178 return container_of(hw, struct tc358746, mclk_hw);
179 }
180
181 struct tc358746_format {
182 u32 code;
183 bool csi_format;
184 unsigned char bus_width;
185 unsigned char bpp;
186 /* Register values */
187 u8 pdformat; /* Peripheral Data Format */
188 u8 pdataf; /* Parallel Data Format Option */
189 };
190
191 enum {
192 PDFORMAT_RAW8 = 0,
193 PDFORMAT_RAW10,
194 PDFORMAT_RAW12,
195 PDFORMAT_RGB888,
196 PDFORMAT_RGB666,
197 PDFORMAT_RGB565,
198 PDFORMAT_YUV422_8BIT,
199 /* RESERVED = 7 */
200 PDFORMAT_RAW14 = 8,
201 PDFORMAT_YUV422_10BIT,
202 PDFORMAT_YUV444,
203 };
204
205 /* Check tc358746_src_mbus_code() if you add new formats */
206 static const struct tc358746_format tc358746_formats[] = {
207 {
208 .code = MEDIA_BUS_FMT_UYVY8_2X8,
209 .bus_width = 8,
210 .bpp = 16,
211 .pdformat = PDFORMAT_YUV422_8BIT,
212 .pdataf = PDATAF_MODE0,
213 }, {
214 .code = MEDIA_BUS_FMT_UYVY8_1X16,
215 .csi_format = true,
216 .bus_width = 16,
217 .bpp = 16,
218 .pdformat = PDFORMAT_YUV422_8BIT,
219 .pdataf = PDATAF_MODE1,
220 }, {
221 .code = MEDIA_BUS_FMT_YUYV8_1X16,
222 .csi_format = true,
223 .bus_width = 16,
224 .bpp = 16,
225 .pdformat = PDFORMAT_YUV422_8BIT,
226 .pdataf = PDATAF_MODE2,
227 }, {
228 .code = MEDIA_BUS_FMT_UYVY10_2X10,
229 .bus_width = 10,
230 .bpp = 20,
231 .pdformat = PDFORMAT_YUV422_10BIT,
232 .pdataf = PDATAF_MODE0, /* don't care */
233 }
234 };
235
236 /* Get n-th format for pad */
237 static const struct tc358746_format *
tc358746_get_format_by_idx(unsigned int pad,unsigned int index)238 tc358746_get_format_by_idx(unsigned int pad, unsigned int index)
239 {
240 unsigned int idx = 0;
241 unsigned int i;
242
243 for (i = 0; i < ARRAY_SIZE(tc358746_formats); i++) {
244 const struct tc358746_format *fmt = &tc358746_formats[i];
245
246 if ((pad == TC358746_SOURCE && fmt->csi_format) ||
247 (pad == TC358746_SINK)) {
248 if (idx == index)
249 return fmt;
250 idx++;
251 }
252 }
253
254 return ERR_PTR(-EINVAL);
255 }
256
257 static const struct tc358746_format *
tc358746_get_format_by_code(unsigned int pad,u32 code)258 tc358746_get_format_by_code(unsigned int pad, u32 code)
259 {
260 unsigned int i;
261
262 for (i = 0; i < ARRAY_SIZE(tc358746_formats); i++) {
263 const struct tc358746_format *fmt = &tc358746_formats[i];
264
265 if (pad == TC358746_SINK && fmt->code == code)
266 return fmt;
267
268 if (pad == TC358746_SOURCE && !fmt->csi_format)
269 continue;
270
271 if (fmt->code == code)
272 return fmt;
273 }
274
275 return ERR_PTR(-EINVAL);
276 }
277
tc358746_src_mbus_code(u32 code)278 static u32 tc358746_src_mbus_code(u32 code)
279 {
280 switch (code) {
281 case MEDIA_BUS_FMT_UYVY8_2X8:
282 return MEDIA_BUS_FMT_UYVY8_1X16;
283 case MEDIA_BUS_FMT_UYVY10_2X10:
284 return MEDIA_BUS_FMT_UYVY10_1X20;
285 default:
286 return code;
287 }
288 }
289
tc358746_valid_reg(struct device * dev,unsigned int reg)290 static bool tc358746_valid_reg(struct device *dev, unsigned int reg)
291 {
292 switch (reg) {
293 case CHIPID_REG ... CSI_START_REG:
294 return true;
295 default:
296 return false;
297 }
298 }
299
300 static const struct regmap_config tc358746_regmap_config = {
301 .name = "tc358746",
302 .reg_bits = 16,
303 .val_bits = 16,
304 .max_register = CSI_START_REG,
305 .writeable_reg = tc358746_valid_reg,
306 .readable_reg = tc358746_valid_reg,
307 .reg_format_endian = REGMAP_ENDIAN_BIG,
308 .val_format_endian = REGMAP_ENDIAN_BIG,
309 };
310
tc358746_write(struct tc358746 * tc358746,u32 reg,u32 val)311 static int tc358746_write(struct tc358746 *tc358746, u32 reg, u32 val)
312 {
313 size_t count;
314 int err;
315
316 /* 32-bit registers starting from CLW_DPHYCONTTX */
317 count = reg < CLW_DPHYCONTTX_REG ? 1 : 2;
318
319 err = regmap_bulk_write(tc358746->regmap, reg, &val, count);
320 if (err)
321 dev_err(tc358746->sd.dev,
322 "Failed to write reg:0x%04x err:%d\n", reg, err);
323
324 return err;
325 }
326
tc358746_read(struct tc358746 * tc358746,u32 reg,u32 * val)327 static int tc358746_read(struct tc358746 *tc358746, u32 reg, u32 *val)
328 {
329 size_t count;
330 int err;
331
332 /* 32-bit registers starting from CLW_DPHYCONTTX */
333 count = reg < CLW_DPHYCONTTX_REG ? 1 : 2;
334 *val = 0;
335
336 err = regmap_bulk_read(tc358746->regmap, reg, val, count);
337 if (err)
338 dev_err(tc358746->sd.dev,
339 "Failed to read reg:0x%04x err:%d\n", reg, err);
340
341 return err;
342 }
343
344 static int
tc358746_update_bits(struct tc358746 * tc358746,u32 reg,u32 mask,u32 val)345 tc358746_update_bits(struct tc358746 *tc358746, u32 reg, u32 mask, u32 val)
346 {
347 u32 tmp, orig;
348 int err;
349
350 err = tc358746_read(tc358746, reg, &orig);
351 if (err)
352 return err;
353
354 tmp = orig & ~mask;
355 tmp |= val & mask;
356
357 return tc358746_write(tc358746, reg, tmp);
358 }
359
tc358746_set_bits(struct tc358746 * tc358746,u32 reg,u32 bits)360 static int tc358746_set_bits(struct tc358746 *tc358746, u32 reg, u32 bits)
361 {
362 return tc358746_update_bits(tc358746, reg, bits, bits);
363 }
364
tc358746_clear_bits(struct tc358746 * tc358746,u32 reg,u32 bits)365 static int tc358746_clear_bits(struct tc358746 *tc358746, u32 reg, u32 bits)
366 {
367 return tc358746_update_bits(tc358746, reg, bits, 0);
368 }
369
tc358746_sw_reset(struct tc358746 * tc358746)370 static int tc358746_sw_reset(struct tc358746 *tc358746)
371 {
372 int err;
373
374 err = tc358746_set_bits(tc358746, SYSCTL_REG, SRESET);
375 if (err)
376 return err;
377
378 fsleep(10);
379
380 return tc358746_clear_bits(tc358746, SYSCTL_REG, SRESET);
381 }
382
383 static int
tc358746_apply_pll_config(struct tc358746 * tc358746)384 tc358746_apply_pll_config(struct tc358746 *tc358746)
385 {
386 u8 post = tc358746->pll_post_div;
387 u16 pre = tc358746->pll_pre_div;
388 u16 mul = tc358746->pll_mul;
389 u32 val, mask;
390 int err;
391
392 err = tc358746_read(tc358746, PLLCTL1_REG, &val);
393 if (err)
394 return err;
395
396 /* Don't touch the PLL if running */
397 if (FIELD_GET(PLL_EN, val) == 1)
398 return 0;
399
400 /* Pre-div and Multiplicator have a internal +1 logic */
401 val = PLL_PRD(pre - 1) | PLL_FBD(mul - 1);
402 mask = PLL_PRD_MASK | PLL_FBD_MASK;
403 err = tc358746_update_bits(tc358746, PLLCTL0_REG, mask, val);
404 if (err)
405 return err;
406
407 val = PLL_FRS(ilog2(post)) | RESETB | PLL_EN;
408 mask = PLL_FRS_MASK | RESETB | PLL_EN;
409 err = tc358746_update_bits(tc358746, PLLCTL1_REG, mask, val);
410 if (err)
411 return err;
412
413 fsleep(1000);
414
415 return tc358746_set_bits(tc358746, PLLCTL1_REG, CKEN);
416 }
417
tc358746_apply_misc_config(struct tc358746 * tc358746)418 static int tc358746_apply_misc_config(struct tc358746 *tc358746)
419 {
420 const struct v4l2_mbus_framefmt *mbusfmt;
421 struct v4l2_subdev *sd = &tc358746->sd;
422 struct v4l2_subdev_state *sink_state;
423 const struct tc358746_format *fmt;
424 struct device *dev = sd->dev;
425 u32 val;
426 int err;
427
428 sink_state = v4l2_subdev_lock_and_get_active_state(sd);
429
430 mbusfmt = v4l2_subdev_get_pad_format(sd, sink_state, TC358746_SINK);
431 fmt = tc358746_get_format_by_code(TC358746_SINK, mbusfmt->code);
432
433 /* Self defined CSI user data type id's are not supported yet */
434 val = PDFMT(fmt->pdformat);
435 dev_dbg(dev, "DATAFMT: 0x%x\n", val);
436 err = tc358746_write(tc358746, DATAFMT_REG, val);
437 if (err)
438 goto out;
439
440 val = PDATAF(fmt->pdataf);
441 dev_dbg(dev, "CONFCTL[PDATAF]: 0x%x\n", fmt->pdataf);
442 err = tc358746_update_bits(tc358746, CONFCTL_REG, PDATAF_MASK, val);
443 if (err)
444 goto out;
445
446 val = tc358746->vb_size / 32;
447 dev_dbg(dev, "FIFOCTL: %u (0x%x)\n", val, val);
448 err = tc358746_write(tc358746, FIFOCTL_REG, val);
449 if (err)
450 goto out;
451
452 /* Total number of bytes for each line/width */
453 val = mbusfmt->width * fmt->bpp / 8;
454 dev_dbg(dev, "WORDCNT: %u (0x%x)\n", val, val);
455 err = tc358746_write(tc358746, WORDCNT_REG, val);
456
457 out:
458 v4l2_subdev_unlock_state(sink_state);
459
460 return err;
461 }
462
tc358746_cfg_to_cnt(unsigned long cfg_val,unsigned long clk_hz,unsigned long long time_base)463 static u32 tc358746_cfg_to_cnt(unsigned long cfg_val, unsigned long clk_hz,
464 unsigned long long time_base)
465 {
466 return div64_u64((u64)cfg_val * clk_hz + time_base - 1, time_base);
467 }
468
tc358746_ps_to_cnt(unsigned long cfg_val,unsigned long clk_hz)469 static u32 tc358746_ps_to_cnt(unsigned long cfg_val, unsigned long clk_hz)
470 {
471 return tc358746_cfg_to_cnt(cfg_val, clk_hz, PSEC_PER_SEC);
472 }
473
tc358746_us_to_cnt(unsigned long cfg_val,unsigned long clk_hz)474 static u32 tc358746_us_to_cnt(unsigned long cfg_val, unsigned long clk_hz)
475 {
476 return tc358746_cfg_to_cnt(cfg_val, clk_hz, USEC_PER_SEC);
477 }
478
tc358746_apply_dphy_config(struct tc358746 * tc358746)479 static int tc358746_apply_dphy_config(struct tc358746 *tc358746)
480 {
481 struct phy_configure_opts_mipi_dphy *cfg = &tc358746->dphy_cfg;
482 bool non_cont_clk = !!(tc358746->csi_vep.bus.mipi_csi2.flags &
483 V4L2_MBUS_CSI2_NONCONTINUOUS_CLOCK);
484 struct device *dev = tc358746->sd.dev;
485 unsigned long hs_byte_clk, hf_clk;
486 u32 val, val2, lptxcnt;
487 int err;
488
489 /* The hs_byte_clk is also called SYSCLK in the excel sheet */
490 hs_byte_clk = cfg->hs_clk_rate / 8;
491 hf_clk = hs_byte_clk / 2;
492
493 val = tc358746_us_to_cnt(cfg->init, hf_clk) - 1;
494 dev_dbg(dev, "LINEINITCNT: %u (0x%x)\n", val, val);
495 err = tc358746_write(tc358746, LINEINITCNT_REG, val);
496 if (err)
497 return err;
498
499 val = tc358746_ps_to_cnt(cfg->lpx, hs_byte_clk) - 1;
500 lptxcnt = val;
501 dev_dbg(dev, "LPTXTIMECNT: %u (0x%x)\n", val, val);
502 err = tc358746_write(tc358746, LPTXTIMECNT_REG, val);
503 if (err)
504 return err;
505
506 val = tc358746_ps_to_cnt(cfg->clk_prepare, hs_byte_clk) - 1;
507 val2 = tc358746_ps_to_cnt(cfg->clk_zero, hs_byte_clk) - 1;
508 dev_dbg(dev, "TCLK_PREPARECNT: %u (0x%x)\n", val, val);
509 dev_dbg(dev, "TCLK_ZEROCNT: %u (0x%x)\n", val2, val2);
510 dev_dbg(dev, "TCLK_HEADERCNT: 0x%x\n",
511 (u32)(TCLK_PREPARECNT(val) | TCLK_ZEROCNT(val2)));
512 err = tc358746_write(tc358746, TCLK_HEADERCNT_REG,
513 TCLK_PREPARECNT(val) | TCLK_ZEROCNT(val2));
514 if (err)
515 return err;
516
517 val = tc358746_ps_to_cnt(cfg->clk_trail, hs_byte_clk);
518 dev_dbg(dev, "TCLK_TRAILCNT: %u (0x%x)\n", val, val);
519 err = tc358746_write(tc358746, TCLK_TRAILCNT_REG, val);
520 if (err)
521 return err;
522
523 val = tc358746_ps_to_cnt(cfg->hs_prepare, hs_byte_clk) - 1;
524 val2 = tc358746_ps_to_cnt(cfg->hs_zero, hs_byte_clk) - 1;
525 dev_dbg(dev, "THS_PREPARECNT: %u (0x%x)\n", val, val);
526 dev_dbg(dev, "THS_ZEROCNT: %u (0x%x)\n", val2, val2);
527 dev_dbg(dev, "THS_HEADERCNT: 0x%x\n",
528 (u32)(THS_PREPARECNT(val) | THS_ZEROCNT(val2)));
529 err = tc358746_write(tc358746, THS_HEADERCNT_REG,
530 THS_PREPARECNT(val) | THS_ZEROCNT(val2));
531 if (err)
532 return err;
533
534 /* TWAKEUP > 1ms in lptxcnt steps */
535 val = tc358746_us_to_cnt(cfg->wakeup, hs_byte_clk);
536 val = val / (lptxcnt + 1) - 1;
537 dev_dbg(dev, "TWAKEUP: %u (0x%x)\n", val, val);
538 err = tc358746_write(tc358746, TWAKEUP_REG, val);
539 if (err)
540 return err;
541
542 val = tc358746_ps_to_cnt(cfg->clk_post, hs_byte_clk);
543 dev_dbg(dev, "TCLK_POSTCNT: %u (0x%x)\n", val, val);
544 err = tc358746_write(tc358746, TCLK_POSTCNT_REG, val);
545 if (err)
546 return err;
547
548 val = tc358746_ps_to_cnt(cfg->hs_trail, hs_byte_clk);
549 dev_dbg(dev, "THS_TRAILCNT: %u (0x%x)\n", val, val);
550 err = tc358746_write(tc358746, THS_TRAILCNT_REG, val);
551 if (err)
552 return err;
553
554 dev_dbg(dev, "CONTCLKMODE: %u", non_cont_clk ? 0 : 1);
555
556 return tc358746_write(tc358746, TXOPTIONCNTRL_REG, non_cont_clk ? 0 : 1);
557 }
558
559 #define MAX_DATA_LANES 4
560
tc358746_enable_csi_lanes(struct tc358746 * tc358746,int enable)561 static int tc358746_enable_csi_lanes(struct tc358746 *tc358746, int enable)
562 {
563 unsigned int lanes = tc358746->dphy_cfg.lanes;
564 unsigned int lane;
565 u32 reg, val;
566 int err;
567
568 err = tc358746_update_bits(tc358746, CONFCTL_REG, DATALANE_MASK,
569 lanes - 1);
570 if (err)
571 return err;
572
573 /* Clock lane */
574 val = enable ? 0 : LANEDISABLE;
575 dev_dbg(tc358746->sd.dev, "CLW_CNTRL: 0x%x\n", val);
576 err = tc358746_write(tc358746, CLW_CNTRL_REG, val);
577 if (err)
578 return err;
579
580 for (lane = 0; lane < MAX_DATA_LANES; lane++) {
581 /* Data lanes */
582 reg = D0W_CNTRL_REG + lane * 0x4;
583 val = (enable && lane < lanes) ? 0 : LANEDISABLE;
584
585 dev_dbg(tc358746->sd.dev, "D%uW_CNTRL: 0x%x\n", lane, val);
586 err = tc358746_write(tc358746, reg, val);
587 if (err)
588 return err;
589 }
590
591 val = 0;
592 if (enable) {
593 /* Clock lane */
594 val |= BIT(0);
595
596 /* Data lanes */
597 for (lane = 1; lane <= lanes; lane++)
598 val |= BIT(lane);
599 }
600
601 dev_dbg(tc358746->sd.dev, "HSTXVREGEN: 0x%x\n", val);
602
603 return tc358746_write(tc358746, HSTXVREGEN_REG, val);
604 }
605
tc358746_enable_csi_module(struct tc358746 * tc358746,int enable)606 static int tc358746_enable_csi_module(struct tc358746 *tc358746, int enable)
607 {
608 unsigned int lanes = tc358746->dphy_cfg.lanes;
609 int err;
610
611 /*
612 * START and STRT are only reseted/disabled by sw reset. This is
613 * required to put the lane state back into LP-11 state. The sw reset
614 * don't reset register values.
615 */
616 if (!enable)
617 return tc358746_sw_reset(tc358746);
618
619 err = tc358746_write(tc358746, STARTCNTRL_REG, START);
620 if (err)
621 return err;
622
623 err = tc358746_write(tc358746, CSI_START_REG, STRT);
624 if (err)
625 return err;
626
627 /* CSI_CONTROL_REG is only indirect accessible */
628 return tc358746_write(tc358746, CSI_CONFW_REG,
629 MODE(MODE_SET) |
630 ADDRESS(CSI_CONTROL_ADDRESS) |
631 DATA(CSI_MODE | TXHSMD | NOL(lanes - 1)));
632 }
633
tc358746_enable_parallel_port(struct tc358746 * tc358746,int enable)634 static int tc358746_enable_parallel_port(struct tc358746 *tc358746, int enable)
635 {
636 int err;
637
638 if (enable) {
639 err = tc358746_write(tc358746, PP_MISC_REG, 0);
640 if (err)
641 return err;
642
643 return tc358746_set_bits(tc358746, CONFCTL_REG, PPEN);
644 }
645
646 err = tc358746_set_bits(tc358746, PP_MISC_REG, FRMSTOP);
647 if (err)
648 return err;
649
650 err = tc358746_clear_bits(tc358746, CONFCTL_REG, PPEN);
651 if (err)
652 return err;
653
654 return tc358746_set_bits(tc358746, PP_MISC_REG, RSTPTR);
655 }
656
tc358746_get_remote_sd(struct media_pad * pad)657 static inline struct v4l2_subdev *tc358746_get_remote_sd(struct media_pad *pad)
658 {
659 pad = media_pad_remote_pad_first(pad);
660 if (!pad)
661 return NULL;
662
663 return media_entity_to_v4l2_subdev(pad->entity);
664 }
665
tc358746_s_stream(struct v4l2_subdev * sd,int enable)666 static int tc358746_s_stream(struct v4l2_subdev *sd, int enable)
667 {
668 struct tc358746 *tc358746 = to_tc358746(sd);
669 struct v4l2_subdev *src;
670 int err;
671
672 dev_dbg(sd->dev, "%sable\n", enable ? "en" : "dis");
673
674 src = tc358746_get_remote_sd(&tc358746->pads[TC358746_SINK]);
675 if (!src)
676 return -EPIPE;
677
678 if (enable) {
679 err = pm_runtime_resume_and_get(sd->dev);
680 if (err)
681 return err;
682
683 err = tc358746_apply_dphy_config(tc358746);
684 if (err)
685 goto err_out;
686
687 err = tc358746_apply_misc_config(tc358746);
688 if (err)
689 goto err_out;
690
691 err = tc358746_enable_csi_lanes(tc358746, 1);
692 if (err)
693 goto err_out;
694
695 err = tc358746_enable_csi_module(tc358746, 1);
696 if (err)
697 goto err_out;
698
699 err = tc358746_enable_parallel_port(tc358746, 1);
700 if (err)
701 goto err_out;
702
703 err = v4l2_subdev_call(src, video, s_stream, 1);
704 if (err)
705 goto err_out;
706
707 return 0;
708
709 err_out:
710 pm_runtime_mark_last_busy(sd->dev);
711 pm_runtime_put_sync_autosuspend(sd->dev);
712
713 return err;
714 }
715
716 /*
717 * The lanes must be disabled first (before the csi module) so the
718 * LP-11 state is entered correctly.
719 */
720 err = tc358746_enable_csi_lanes(tc358746, 0);
721 if (err)
722 return err;
723
724 err = tc358746_enable_csi_module(tc358746, 0);
725 if (err)
726 return err;
727
728 err = tc358746_enable_parallel_port(tc358746, 0);
729 if (err)
730 return err;
731
732 pm_runtime_mark_last_busy(sd->dev);
733 pm_runtime_put_sync_autosuspend(sd->dev);
734
735 return v4l2_subdev_call(src, video, s_stream, 0);
736 }
737
tc358746_init_cfg(struct v4l2_subdev * sd,struct v4l2_subdev_state * state)738 static int tc358746_init_cfg(struct v4l2_subdev *sd,
739 struct v4l2_subdev_state *state)
740 {
741 struct v4l2_mbus_framefmt *fmt;
742
743 fmt = v4l2_subdev_get_pad_format(sd, state, TC358746_SINK);
744 *fmt = tc358746_def_fmt;
745
746 fmt = v4l2_subdev_get_pad_format(sd, state, TC358746_SOURCE);
747 *fmt = tc358746_def_fmt;
748 fmt->code = tc358746_src_mbus_code(tc358746_def_fmt.code);
749
750 return 0;
751 }
752
tc358746_enum_mbus_code(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_mbus_code_enum * code)753 static int tc358746_enum_mbus_code(struct v4l2_subdev *sd,
754 struct v4l2_subdev_state *sd_state,
755 struct v4l2_subdev_mbus_code_enum *code)
756 {
757 const struct tc358746_format *fmt;
758
759 fmt = tc358746_get_format_by_idx(code->pad, code->index);
760 if (IS_ERR(fmt))
761 return PTR_ERR(fmt);
762
763 code->code = fmt->code;
764
765 return 0;
766 }
767
tc358746_set_fmt(struct v4l2_subdev * sd,struct v4l2_subdev_state * sd_state,struct v4l2_subdev_format * format)768 static int tc358746_set_fmt(struct v4l2_subdev *sd,
769 struct v4l2_subdev_state *sd_state,
770 struct v4l2_subdev_format *format)
771 {
772 struct v4l2_mbus_framefmt *src_fmt, *sink_fmt;
773 const struct tc358746_format *fmt;
774
775 /* Source follows the sink */
776 if (format->pad == TC358746_SOURCE)
777 return v4l2_subdev_get_fmt(sd, sd_state, format);
778
779 sink_fmt = v4l2_subdev_get_pad_format(sd, sd_state, TC358746_SINK);
780
781 fmt = tc358746_get_format_by_code(format->pad, format->format.code);
782 if (IS_ERR(fmt))
783 fmt = tc358746_get_format_by_code(format->pad, tc358746_def_fmt.code);
784
785 format->format.code = fmt->code;
786 format->format.field = V4L2_FIELD_NONE;
787
788 dev_dbg(sd->dev, "Update format: %ux%u code:0x%x -> %ux%u code:0x%x",
789 sink_fmt->width, sink_fmt->height, sink_fmt->code,
790 format->format.width, format->format.height, format->format.code);
791
792 *sink_fmt = format->format;
793
794 src_fmt = v4l2_subdev_get_pad_format(sd, sd_state, TC358746_SOURCE);
795 *src_fmt = *sink_fmt;
796 src_fmt->code = tc358746_src_mbus_code(sink_fmt->code);
797
798 return 0;
799 }
800
tc358746_find_pll_settings(struct tc358746 * tc358746,unsigned long refclk,unsigned long fout)801 static unsigned long tc358746_find_pll_settings(struct tc358746 *tc358746,
802 unsigned long refclk,
803 unsigned long fout)
804
805 {
806 struct device *dev = tc358746->sd.dev;
807 unsigned long best_freq = 0;
808 u32 min_delta = 0xffffffff;
809 u16 prediv_max = 17;
810 u16 prediv_min = 1;
811 u16 m_best = 0, mul;
812 u16 p_best = 1, p;
813 u8 postdiv;
814
815 if (fout > 1000 * HZ_PER_MHZ) {
816 dev_err(dev, "HS-Clock above 1 Ghz are not supported\n");
817 return 0;
818 }
819
820 if (fout >= 500 * HZ_PER_MHZ)
821 postdiv = 1;
822 else if (fout >= 250 * HZ_PER_MHZ)
823 postdiv = 2;
824 else if (fout >= 125 * HZ_PER_MHZ)
825 postdiv = 4;
826 else
827 postdiv = 8;
828
829 for (p = prediv_min; p <= prediv_max; p++) {
830 unsigned long delta, fin;
831 u64 tmp;
832
833 fin = DIV_ROUND_CLOSEST(refclk, p);
834 if (fin < 4 * HZ_PER_MHZ || fin > 40 * HZ_PER_MHZ)
835 continue;
836
837 tmp = fout * p * postdiv;
838 do_div(tmp, fin);
839 mul = tmp;
840 if (mul > 511)
841 continue;
842
843 tmp = mul * fin;
844 do_div(tmp, p * postdiv);
845
846 delta = abs(fout - tmp);
847 if (delta < min_delta) {
848 p_best = p;
849 m_best = mul;
850 min_delta = delta;
851 best_freq = tmp;
852 }
853
854 if (delta == 0)
855 break;
856 }
857
858 if (!best_freq) {
859 dev_err(dev, "Failed find PLL frequency\n");
860 return 0;
861 }
862
863 tc358746->pll_post_div = postdiv;
864 tc358746->pll_pre_div = p_best;
865 tc358746->pll_mul = m_best;
866
867 if (best_freq != fout)
868 dev_warn(dev, "Request PLL freq:%lu, found PLL freq:%lu\n",
869 fout, best_freq);
870
871 dev_dbg(dev, "Found PLL settings: freq:%lu prediv:%u multi:%u postdiv:%u\n",
872 best_freq, p_best, m_best, postdiv);
873
874 return best_freq;
875 }
876
877 #define TC358746_PRECISION 10
878
879 static int
tc358746_link_validate(struct v4l2_subdev * sd,struct media_link * link,struct v4l2_subdev_format * source_fmt,struct v4l2_subdev_format * sink_fmt)880 tc358746_link_validate(struct v4l2_subdev *sd, struct media_link *link,
881 struct v4l2_subdev_format *source_fmt,
882 struct v4l2_subdev_format *sink_fmt)
883 {
884 struct tc358746 *tc358746 = to_tc358746(sd);
885 unsigned long csi_bitrate, source_bitrate;
886 struct v4l2_subdev_state *sink_state;
887 struct v4l2_mbus_framefmt *mbusfmt;
888 const struct tc358746_format *fmt;
889 unsigned int fifo_sz, tmp, n;
890 struct v4l2_subdev *source;
891 s64 source_link_freq;
892 int err;
893
894 err = v4l2_subdev_link_validate_default(sd, link, source_fmt, sink_fmt);
895 if (err)
896 return err;
897
898 sink_state = v4l2_subdev_lock_and_get_active_state(sd);
899 mbusfmt = v4l2_subdev_get_pad_format(sd, sink_state, TC358746_SINK);
900
901 /* Check the FIFO settings */
902 fmt = tc358746_get_format_by_code(TC358746_SINK, mbusfmt->code);
903
904 source = media_entity_to_v4l2_subdev(link->source->entity);
905 source_link_freq = v4l2_get_link_freq(source->ctrl_handler, 0, 0);
906 if (source_link_freq <= 0) {
907 dev_err(tc358746->sd.dev,
908 "Failed to query or invalid source link frequency\n");
909 v4l2_subdev_unlock_state(sink_state);
910 /* Return -EINVAL in case of source_link_freq is 0 */
911 return source_link_freq ? : -EINVAL;
912 }
913 source_bitrate = source_link_freq * fmt->bus_width;
914
915 csi_bitrate = tc358746->dphy_cfg.lanes * tc358746->pll_rate;
916
917 dev_dbg(tc358746->sd.dev,
918 "Fifo settings params: source-bitrate:%lu csi-bitrate:%lu",
919 source_bitrate, csi_bitrate);
920
921 /* Avoid possible FIFO overflows */
922 if (csi_bitrate < source_bitrate) {
923 v4l2_subdev_unlock_state(sink_state);
924 return -EINVAL;
925 }
926
927 /* Best case */
928 if (csi_bitrate == source_bitrate) {
929 fifo_sz = TC358746_VB_DEFAULT_SIZE;
930 tc358746->vb_size = TC358746_VB_DEFAULT_SIZE;
931 goto out;
932 }
933
934 /*
935 * Avoid possible FIFO underflow in case of
936 * csi_bitrate > source_bitrate. For such case the chip has a internal
937 * fifo which can be used to delay the line output.
938 *
939 * Fifo size calculation (excluding precision):
940 *
941 * fifo-sz, image-width - in bits
942 * sbr - source_bitrate in bits/s
943 * csir - csi_bitrate in bits/s
944 *
945 * image-width / csir >= (image-width - fifo-sz) / sbr
946 * image-width * sbr / csir >= image-width - fifo-sz
947 * fifo-sz >= image-width - image-width * sbr / csir; with n = csir/sbr
948 * fifo-sz >= image-width - image-width / n
949 */
950
951 source_bitrate /= TC358746_PRECISION;
952 n = csi_bitrate / source_bitrate;
953 tmp = (mbusfmt->width * TC358746_PRECISION) / n;
954 fifo_sz = mbusfmt->width - tmp;
955 fifo_sz *= fmt->bpp;
956 tc358746->vb_size = round_up(fifo_sz, 32);
957
958 out:
959 dev_dbg(tc358746->sd.dev,
960 "Found FIFO size[bits]:%u -> aligned to size[bits]:%u\n",
961 fifo_sz, tc358746->vb_size);
962
963 v4l2_subdev_unlock_state(sink_state);
964
965 return tc358746->vb_size > TC358746_VB_MAX_SIZE ? -EINVAL : 0;
966 }
967
tc358746_get_mbus_config(struct v4l2_subdev * sd,unsigned int pad,struct v4l2_mbus_config * config)968 static int tc358746_get_mbus_config(struct v4l2_subdev *sd, unsigned int pad,
969 struct v4l2_mbus_config *config)
970 {
971 struct tc358746 *tc358746 = to_tc358746(sd);
972
973 if (pad != TC358746_SOURCE)
974 return -EINVAL;
975
976 config->type = V4L2_MBUS_CSI2_DPHY;
977 config->bus.mipi_csi2 = tc358746->csi_vep.bus.mipi_csi2;
978
979 return 0;
980 }
981
982 static int __maybe_unused
tc358746_g_register(struct v4l2_subdev * sd,struct v4l2_dbg_register * reg)983 tc358746_g_register(struct v4l2_subdev *sd, struct v4l2_dbg_register *reg)
984 {
985 struct tc358746 *tc358746 = to_tc358746(sd);
986 u32 val;
987 int err;
988
989 /* 32-bit registers starting from CLW_DPHYCONTTX */
990 reg->size = reg->reg < CLW_DPHYCONTTX_REG ? 2 : 4;
991
992 if (!pm_runtime_get_if_in_use(sd->dev))
993 return 0;
994
995 err = tc358746_read(tc358746, reg->reg, &val);
996 reg->val = val;
997
998 pm_runtime_mark_last_busy(sd->dev);
999 pm_runtime_put_sync_autosuspend(sd->dev);
1000
1001 return err;
1002 }
1003
1004 static int __maybe_unused
tc358746_s_register(struct v4l2_subdev * sd,const struct v4l2_dbg_register * reg)1005 tc358746_s_register(struct v4l2_subdev *sd, const struct v4l2_dbg_register *reg)
1006 {
1007 struct tc358746 *tc358746 = to_tc358746(sd);
1008
1009 if (!pm_runtime_get_if_in_use(sd->dev))
1010 return 0;
1011
1012 tc358746_write(tc358746, (u32)reg->reg, (u32)reg->val);
1013
1014 pm_runtime_mark_last_busy(sd->dev);
1015 pm_runtime_put_sync_autosuspend(sd->dev);
1016
1017 return 0;
1018 }
1019
1020 static const struct v4l2_subdev_core_ops tc358746_core_ops = {
1021 #ifdef CONFIG_VIDEO_ADV_DEBUG
1022 .g_register = tc358746_g_register,
1023 .s_register = tc358746_s_register,
1024 #endif
1025 };
1026
1027 static const struct v4l2_subdev_video_ops tc358746_video_ops = {
1028 .s_stream = tc358746_s_stream,
1029 };
1030
1031 static const struct v4l2_subdev_pad_ops tc358746_pad_ops = {
1032 .init_cfg = tc358746_init_cfg,
1033 .enum_mbus_code = tc358746_enum_mbus_code,
1034 .set_fmt = tc358746_set_fmt,
1035 .get_fmt = v4l2_subdev_get_fmt,
1036 .link_validate = tc358746_link_validate,
1037 .get_mbus_config = tc358746_get_mbus_config,
1038 };
1039
1040 static const struct v4l2_subdev_ops tc358746_ops = {
1041 .core = &tc358746_core_ops,
1042 .video = &tc358746_video_ops,
1043 .pad = &tc358746_pad_ops,
1044 };
1045
1046 static const struct media_entity_operations tc358746_entity_ops = {
1047 .get_fwnode_pad = v4l2_subdev_get_fwnode_pad_1_to_1,
1048 .link_validate = v4l2_subdev_link_validate,
1049 };
1050
tc358746_mclk_enable(struct clk_hw * hw)1051 static int tc358746_mclk_enable(struct clk_hw *hw)
1052 {
1053 struct tc358746 *tc358746 = clk_hw_to_tc358746(hw);
1054 unsigned int div;
1055 u32 val;
1056 int err;
1057
1058 div = tc358746->mclk_postdiv / 2;
1059 val = MCLK_HIGH(div - 1) | MCLK_LOW(div - 1);
1060 dev_dbg(tc358746->sd.dev, "MCLKCTL: %u (0x%x)\n", val, val);
1061 err = tc358746_write(tc358746, MCLKCTL_REG, val);
1062 if (err)
1063 return err;
1064
1065 if (tc358746->mclk_prediv == 8)
1066 val = MCLKDIV(MCLKDIV_8);
1067 else if (tc358746->mclk_prediv == 4)
1068 val = MCLKDIV(MCLKDIV_4);
1069 else
1070 val = MCLKDIV(MCLKDIV_2);
1071
1072 dev_dbg(tc358746->sd.dev, "CLKCTL[MCLKDIV]: %u (0x%x)\n", val, val);
1073
1074 return tc358746_update_bits(tc358746, CLKCTL_REG, MCLKDIV_MASK, val);
1075 }
1076
tc358746_mclk_disable(struct clk_hw * hw)1077 static void tc358746_mclk_disable(struct clk_hw *hw)
1078 {
1079 struct tc358746 *tc358746 = clk_hw_to_tc358746(hw);
1080
1081 tc358746_write(tc358746, MCLKCTL_REG, 0);
1082 }
1083
1084 static long
tc358746_find_mclk_settings(struct tc358746 * tc358746,unsigned long mclk_rate)1085 tc358746_find_mclk_settings(struct tc358746 *tc358746, unsigned long mclk_rate)
1086 {
1087 unsigned long pll_rate = tc358746->pll_rate;
1088 const unsigned char prediv[] = { 2, 4, 8 };
1089 unsigned int mclk_prediv, mclk_postdiv;
1090 struct device *dev = tc358746->sd.dev;
1091 unsigned int postdiv, mclkdiv;
1092 unsigned long best_mclk_rate;
1093 unsigned int i;
1094
1095 /*
1096 * MCLK-Div
1097 * -------------------´`---------------------
1098 * ´ `
1099 * +-------------+ +------------------------+
1100 * | MCLK-PreDiv | | MCLK-PostDiv |
1101 * PLL --> | (2/4/8) | --> | (mclk_low + mclk_high) | --> MCLK
1102 * +-------------+ +------------------------+
1103 *
1104 * The register value of mclk_low/high is mclk_low/high+1, i.e.:
1105 * mclk_low/high = 1 --> 2 MCLK-Ref Counts
1106 * mclk_low/high = 255 --> 256 MCLK-Ref Counts == max.
1107 * If mclk_low and mclk_high are 0 then MCLK is disabled.
1108 *
1109 * Keep it simple and support 50/50 duty cycles only for now,
1110 * so the calc will be:
1111 *
1112 * MCLK = PLL / (MCLK-PreDiv * 2 * MCLK-PostDiv)
1113 */
1114
1115 if (mclk_rate == tc358746->mclk_rate)
1116 return mclk_rate;
1117
1118 /* Highest possible rate */
1119 mclkdiv = pll_rate / mclk_rate;
1120 if (mclkdiv <= 8) {
1121 mclk_prediv = 2;
1122 mclk_postdiv = 4;
1123 best_mclk_rate = pll_rate / (2 * 4);
1124 goto out;
1125 }
1126
1127 /* First check the prediv */
1128 for (i = 0; i < ARRAY_SIZE(prediv); i++) {
1129 postdiv = mclkdiv / prediv[i];
1130
1131 if (postdiv % 2)
1132 continue;
1133
1134 if (postdiv >= 4 && postdiv <= 512) {
1135 mclk_prediv = prediv[i];
1136 mclk_postdiv = postdiv;
1137 best_mclk_rate = pll_rate / (prediv[i] * postdiv);
1138 goto out;
1139 }
1140 }
1141
1142 /* No suitable prediv found, so try to adjust the postdiv */
1143 for (postdiv = 4; postdiv <= 512; postdiv += 2) {
1144 unsigned int pre;
1145
1146 pre = mclkdiv / postdiv;
1147 if (pre == 2 || pre == 4 || pre == 8) {
1148 mclk_prediv = pre;
1149 mclk_postdiv = postdiv;
1150 best_mclk_rate = pll_rate / (pre * postdiv);
1151 goto out;
1152 }
1153 }
1154
1155 /* The MCLK <-> PLL gap is to high -> use largest possible div */
1156 mclk_prediv = 8;
1157 mclk_postdiv = 512;
1158 best_mclk_rate = pll_rate / (8 * 512);
1159
1160 out:
1161 tc358746->mclk_prediv = mclk_prediv;
1162 tc358746->mclk_postdiv = mclk_postdiv;
1163 tc358746->mclk_rate = best_mclk_rate;
1164
1165 if (best_mclk_rate != mclk_rate)
1166 dev_warn(dev, "Request MCLK freq:%lu, found MCLK freq:%lu\n",
1167 mclk_rate, best_mclk_rate);
1168
1169 dev_dbg(dev, "Found MCLK settings: freq:%lu prediv:%u postdiv:%u\n",
1170 best_mclk_rate, mclk_prediv, mclk_postdiv);
1171
1172 return best_mclk_rate;
1173 }
1174
1175 static unsigned long
tc358746_recalc_rate(struct clk_hw * hw,unsigned long parent_rate)1176 tc358746_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
1177 {
1178 struct tc358746 *tc358746 = clk_hw_to_tc358746(hw);
1179 unsigned int prediv, postdiv;
1180 u32 val;
1181 int err;
1182
1183 err = tc358746_read(tc358746, MCLKCTL_REG, &val);
1184 if (err)
1185 return 0;
1186
1187 postdiv = FIELD_GET(MCLK_LOW_MASK, val) + 1;
1188 postdiv += FIELD_GET(MCLK_HIGH_MASK, val) + 1;
1189
1190 err = tc358746_read(tc358746, CLKCTL_REG, &val);
1191 if (err)
1192 return 0;
1193
1194 prediv = FIELD_GET(MCLKDIV_MASK, val);
1195 if (prediv == MCLKDIV_8)
1196 prediv = 8;
1197 else if (prediv == MCLKDIV_4)
1198 prediv = 4;
1199 else
1200 prediv = 2;
1201
1202 return tc358746->pll_rate / (prediv * postdiv);
1203 }
1204
tc358746_mclk_round_rate(struct clk_hw * hw,unsigned long rate,unsigned long * parent_rate)1205 static long tc358746_mclk_round_rate(struct clk_hw *hw, unsigned long rate,
1206 unsigned long *parent_rate)
1207 {
1208 struct tc358746 *tc358746 = clk_hw_to_tc358746(hw);
1209
1210 *parent_rate = tc358746->pll_rate;
1211
1212 return tc358746_find_mclk_settings(tc358746, rate);
1213 }
1214
tc358746_mclk_set_rate(struct clk_hw * hw,unsigned long rate,unsigned long parent_rate)1215 static int tc358746_mclk_set_rate(struct clk_hw *hw, unsigned long rate,
1216 unsigned long parent_rate)
1217 {
1218 struct tc358746 *tc358746 = clk_hw_to_tc358746(hw);
1219
1220 tc358746_find_mclk_settings(tc358746, rate);
1221
1222 return tc358746_mclk_enable(hw);
1223 }
1224
1225 static const struct clk_ops tc358746_mclk_ops = {
1226 .enable = tc358746_mclk_enable,
1227 .disable = tc358746_mclk_disable,
1228 .recalc_rate = tc358746_recalc_rate,
1229 .round_rate = tc358746_mclk_round_rate,
1230 .set_rate = tc358746_mclk_set_rate,
1231 };
1232
tc358746_setup_mclk_provider(struct tc358746 * tc358746)1233 static int tc358746_setup_mclk_provider(struct tc358746 *tc358746)
1234 {
1235 struct clk_init_data mclk_initdata = { };
1236 struct device *dev = tc358746->sd.dev;
1237 const char *mclk_name;
1238 int err;
1239
1240 /* MCLK clk provider support is optional */
1241 if (!device_property_present(dev, "#clock-cells"))
1242 return 0;
1243
1244 /* Init to highest possibel MCLK */
1245 tc358746->mclk_postdiv = 512;
1246 tc358746->mclk_prediv = 8;
1247
1248 mclk_name = "tc358746-mclk";
1249 device_property_read_string(dev, "clock-output-names", &mclk_name);
1250
1251 mclk_initdata.name = mclk_name;
1252 mclk_initdata.ops = &tc358746_mclk_ops;
1253 tc358746->mclk_hw.init = &mclk_initdata;
1254
1255 err = devm_clk_hw_register(dev, &tc358746->mclk_hw);
1256 if (err) {
1257 dev_err(dev, "Failed to register mclk provider\n");
1258 return err;
1259 }
1260
1261 err = devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get,
1262 &tc358746->mclk_hw);
1263 if (err)
1264 dev_err(dev, "Failed to add mclk provider\n");
1265
1266 return err;
1267 }
1268
1269 static int
tc358746_init_subdev(struct tc358746 * tc358746,struct i2c_client * client)1270 tc358746_init_subdev(struct tc358746 *tc358746, struct i2c_client *client)
1271 {
1272 struct v4l2_subdev *sd = &tc358746->sd;
1273 int err;
1274
1275 v4l2_i2c_subdev_init(sd, client, &tc358746_ops);
1276 sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
1277 sd->entity.function = MEDIA_ENT_F_VID_IF_BRIDGE;
1278 sd->entity.ops = &tc358746_entity_ops;
1279
1280 tc358746->pads[TC358746_SINK].flags = MEDIA_PAD_FL_SINK;
1281 tc358746->pads[TC358746_SOURCE].flags = MEDIA_PAD_FL_SOURCE;
1282 err = media_entity_pads_init(&sd->entity, TC358746_NR_PADS,
1283 tc358746->pads);
1284 if (err)
1285 return err;
1286
1287 err = v4l2_subdev_init_finalize(sd);
1288 if (err)
1289 media_entity_cleanup(&sd->entity);
1290
1291 return err;
1292 }
1293
1294 static int
tc358746_init_output_port(struct tc358746 * tc358746,unsigned long refclk)1295 tc358746_init_output_port(struct tc358746 *tc358746, unsigned long refclk)
1296 {
1297 struct device *dev = tc358746->sd.dev;
1298 struct v4l2_fwnode_endpoint *vep;
1299 unsigned long csi_link_rate;
1300 struct fwnode_handle *ep;
1301 unsigned char csi_lanes;
1302 int err;
1303
1304 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(dev), TC358746_SOURCE,
1305 0, 0);
1306 if (!ep) {
1307 dev_err(dev, "Missing endpoint node\n");
1308 return -EINVAL;
1309 }
1310
1311 /* Currently we only support 'parallel in' -> 'csi out' */
1312 vep = &tc358746->csi_vep;
1313 vep->bus_type = V4L2_MBUS_CSI2_DPHY;
1314 err = v4l2_fwnode_endpoint_alloc_parse(ep, vep);
1315 fwnode_handle_put(ep);
1316 if (err) {
1317 dev_err(dev, "Failed to parse source endpoint\n");
1318 return err;
1319 }
1320
1321 csi_lanes = vep->bus.mipi_csi2.num_data_lanes;
1322 if (csi_lanes == 0 || csi_lanes > 4 ||
1323 vep->nr_of_link_frequencies == 0) {
1324 dev_err(dev, "error: Invalid CSI-2 settings\n");
1325 err = -EINVAL;
1326 goto err;
1327 }
1328
1329 /* TODO: Add support to handle multiple link frequencies */
1330 csi_link_rate = (unsigned long)vep->link_frequencies[0];
1331 tc358746->pll_rate = tc358746_find_pll_settings(tc358746, refclk,
1332 csi_link_rate * 2);
1333 if (!tc358746->pll_rate) {
1334 err = -EINVAL;
1335 goto err;
1336 }
1337
1338 err = phy_mipi_dphy_get_default_config_for_hsclk(tc358746->pll_rate,
1339 csi_lanes, &tc358746->dphy_cfg);
1340 if (err)
1341 goto err;
1342
1343 tc358746->vb_size = TC358746_VB_DEFAULT_SIZE;
1344
1345 return 0;
1346
1347 err:
1348 v4l2_fwnode_endpoint_free(vep);
1349
1350 return err;
1351 }
1352
tc358746_init_hw(struct tc358746 * tc358746)1353 static int tc358746_init_hw(struct tc358746 *tc358746)
1354 {
1355 struct device *dev = tc358746->sd.dev;
1356 unsigned int chipid;
1357 u32 val;
1358 int err;
1359
1360 err = pm_runtime_resume_and_get(dev);
1361 if (err < 0) {
1362 dev_err(dev, "Failed to resume the device\n");
1363 return err;
1364 }
1365
1366 /* Ensure that CSI interface is put into LP-11 state */
1367 err = tc358746_sw_reset(tc358746);
1368 if (err) {
1369 pm_runtime_put_sync(dev);
1370 dev_err(dev, "Failed to reset the device\n");
1371 return err;
1372 }
1373
1374 err = tc358746_read(tc358746, CHIPID_REG, &val);
1375 pm_runtime_mark_last_busy(dev);
1376 pm_runtime_put_sync_autosuspend(dev);
1377 if (err)
1378 return -ENODEV;
1379
1380 chipid = FIELD_GET(CHIPID, val);
1381 if (chipid != 0x44) {
1382 dev_err(dev, "Invalid chipid 0x%02x\n", chipid);
1383 return -ENODEV;
1384 }
1385
1386 return 0;
1387 }
1388
tc358746_init_controls(struct tc358746 * tc358746)1389 static int tc358746_init_controls(struct tc358746 *tc358746)
1390 {
1391 u64 *link_frequencies = tc358746->csi_vep.link_frequencies;
1392 struct v4l2_ctrl *ctrl;
1393 int err;
1394
1395 err = v4l2_ctrl_handler_init(&tc358746->ctrl_hdl, 1);
1396 if (err)
1397 return err;
1398
1399 /*
1400 * The driver currently supports only one link-frequency, regardless of
1401 * the input from the firmware, see: tc358746_init_output_port(). So
1402 * report only the first frequency from the array of possible given
1403 * frequencies.
1404 */
1405 ctrl = v4l2_ctrl_new_int_menu(&tc358746->ctrl_hdl, NULL,
1406 V4L2_CID_LINK_FREQ, 0, 0,
1407 link_frequencies);
1408 if (ctrl)
1409 ctrl->flags |= V4L2_CTRL_FLAG_READ_ONLY;
1410
1411 err = tc358746->ctrl_hdl.error;
1412 if (err) {
1413 v4l2_ctrl_handler_free(&tc358746->ctrl_hdl);
1414 return err;
1415 }
1416
1417 tc358746->sd.ctrl_handler = &tc358746->ctrl_hdl;
1418
1419 return 0;
1420 }
1421
tc358746_notify_bound(struct v4l2_async_notifier * notifier,struct v4l2_subdev * sd,struct v4l2_async_connection * asd)1422 static int tc358746_notify_bound(struct v4l2_async_notifier *notifier,
1423 struct v4l2_subdev *sd,
1424 struct v4l2_async_connection *asd)
1425 {
1426 struct tc358746 *tc358746 =
1427 container_of(notifier, struct tc358746, notifier);
1428 u32 flags = MEDIA_LNK_FL_ENABLED | MEDIA_LNK_FL_IMMUTABLE;
1429 struct media_pad *sink = &tc358746->pads[TC358746_SINK];
1430
1431 return v4l2_create_fwnode_links_to_pad(sd, sink, flags);
1432 }
1433
1434 static const struct v4l2_async_notifier_operations tc358746_notify_ops = {
1435 .bound = tc358746_notify_bound,
1436 };
1437
tc358746_async_register(struct tc358746 * tc358746)1438 static int tc358746_async_register(struct tc358746 *tc358746)
1439 {
1440 struct v4l2_fwnode_endpoint vep = {
1441 .bus_type = V4L2_MBUS_PARALLEL,
1442 };
1443 struct v4l2_async_connection *asd;
1444 struct fwnode_handle *ep;
1445 int err;
1446
1447 ep = fwnode_graph_get_endpoint_by_id(dev_fwnode(tc358746->sd.dev),
1448 TC358746_SINK, 0, 0);
1449 if (!ep)
1450 return -ENOTCONN;
1451
1452 err = v4l2_fwnode_endpoint_parse(ep, &vep);
1453 if (err) {
1454 fwnode_handle_put(ep);
1455 return err;
1456 }
1457
1458 v4l2_async_subdev_nf_init(&tc358746->notifier, &tc358746->sd);
1459 asd = v4l2_async_nf_add_fwnode_remote(&tc358746->notifier, ep,
1460 struct v4l2_async_connection);
1461 fwnode_handle_put(ep);
1462
1463 if (IS_ERR(asd)) {
1464 err = PTR_ERR(asd);
1465 goto err_cleanup;
1466 }
1467
1468 tc358746->notifier.ops = &tc358746_notify_ops;
1469
1470 err = v4l2_async_nf_register(&tc358746->notifier);
1471 if (err)
1472 goto err_cleanup;
1473
1474 err = v4l2_async_register_subdev(&tc358746->sd);
1475 if (err)
1476 goto err_unregister;
1477
1478 return 0;
1479
1480 err_unregister:
1481 v4l2_async_nf_unregister(&tc358746->notifier);
1482 err_cleanup:
1483 v4l2_async_nf_cleanup(&tc358746->notifier);
1484
1485 return err;
1486 }
1487
tc358746_probe(struct i2c_client * client)1488 static int tc358746_probe(struct i2c_client *client)
1489 {
1490 struct device *dev = &client->dev;
1491 struct tc358746 *tc358746;
1492 unsigned long refclk;
1493 unsigned int i;
1494 int err;
1495
1496 tc358746 = devm_kzalloc(&client->dev, sizeof(*tc358746), GFP_KERNEL);
1497 if (!tc358746)
1498 return -ENOMEM;
1499
1500 tc358746->regmap = devm_regmap_init_i2c(client, &tc358746_regmap_config);
1501 if (IS_ERR(tc358746->regmap))
1502 return dev_err_probe(dev, PTR_ERR(tc358746->regmap),
1503 "Failed to init regmap\n");
1504
1505 tc358746->refclk = devm_clk_get(dev, "refclk");
1506 if (IS_ERR(tc358746->refclk))
1507 return dev_err_probe(dev, PTR_ERR(tc358746->refclk),
1508 "Failed to get refclk\n");
1509
1510 err = clk_prepare_enable(tc358746->refclk);
1511 if (err)
1512 return dev_err_probe(dev, err,
1513 "Failed to enable refclk\n");
1514
1515 refclk = clk_get_rate(tc358746->refclk);
1516 clk_disable_unprepare(tc358746->refclk);
1517
1518 if (refclk < 6 * HZ_PER_MHZ || refclk > 40 * HZ_PER_MHZ)
1519 return dev_err_probe(dev, -EINVAL, "Invalid refclk range\n");
1520
1521 for (i = 0; i < ARRAY_SIZE(tc358746_supplies); i++)
1522 tc358746->supplies[i].supply = tc358746_supplies[i];
1523
1524 err = devm_regulator_bulk_get(dev, ARRAY_SIZE(tc358746_supplies),
1525 tc358746->supplies);
1526 if (err)
1527 return dev_err_probe(dev, err, "Failed to get supplies\n");
1528
1529 tc358746->reset_gpio = devm_gpiod_get_optional(dev, "reset",
1530 GPIOD_OUT_HIGH);
1531 if (IS_ERR(tc358746->reset_gpio))
1532 return dev_err_probe(dev, PTR_ERR(tc358746->reset_gpio),
1533 "Failed to get reset-gpios\n");
1534
1535 err = tc358746_init_subdev(tc358746, client);
1536 if (err)
1537 return dev_err_probe(dev, err, "Failed to init subdev\n");
1538
1539 err = tc358746_init_output_port(tc358746, refclk);
1540 if (err)
1541 goto err_subdev;
1542
1543 /*
1544 * Keep this order since we need the output port link-frequencies
1545 * information.
1546 */
1547 err = tc358746_init_controls(tc358746);
1548 if (err)
1549 goto err_fwnode;
1550
1551 dev_set_drvdata(dev, tc358746);
1552
1553 /* Set to 1sec to give the stream reconfiguration enough time */
1554 pm_runtime_set_autosuspend_delay(dev, 1000);
1555 pm_runtime_use_autosuspend(dev);
1556 pm_runtime_enable(dev);
1557
1558 err = tc358746_init_hw(tc358746);
1559 if (err)
1560 goto err_pm;
1561
1562 err = tc358746_setup_mclk_provider(tc358746);
1563 if (err)
1564 goto err_pm;
1565
1566 err = tc358746_async_register(tc358746);
1567 if (err < 0)
1568 goto err_pm;
1569
1570 dev_dbg(dev, "%s found @ 0x%x (%s)\n", client->name,
1571 client->addr, client->adapter->name);
1572
1573 return 0;
1574
1575 err_pm:
1576 pm_runtime_disable(dev);
1577 pm_runtime_set_suspended(dev);
1578 pm_runtime_dont_use_autosuspend(dev);
1579 v4l2_ctrl_handler_free(&tc358746->ctrl_hdl);
1580 err_fwnode:
1581 v4l2_fwnode_endpoint_free(&tc358746->csi_vep);
1582 err_subdev:
1583 v4l2_subdev_cleanup(&tc358746->sd);
1584 media_entity_cleanup(&tc358746->sd.entity);
1585
1586 return err;
1587 }
1588
tc358746_remove(struct i2c_client * client)1589 static void tc358746_remove(struct i2c_client *client)
1590 {
1591 struct v4l2_subdev *sd = i2c_get_clientdata(client);
1592 struct tc358746 *tc358746 = to_tc358746(sd);
1593
1594 v4l2_subdev_cleanup(sd);
1595 v4l2_ctrl_handler_free(&tc358746->ctrl_hdl);
1596 v4l2_fwnode_endpoint_free(&tc358746->csi_vep);
1597 v4l2_async_nf_unregister(&tc358746->notifier);
1598 v4l2_async_nf_cleanup(&tc358746->notifier);
1599 v4l2_async_unregister_subdev(sd);
1600 media_entity_cleanup(&sd->entity);
1601
1602 pm_runtime_disable(sd->dev);
1603 pm_runtime_set_suspended(sd->dev);
1604 pm_runtime_dont_use_autosuspend(sd->dev);
1605 }
1606
tc358746_suspend(struct device * dev)1607 static int tc358746_suspend(struct device *dev)
1608 {
1609 struct tc358746 *tc358746 = dev_get_drvdata(dev);
1610 int err;
1611
1612 clk_disable_unprepare(tc358746->refclk);
1613
1614 err = regulator_bulk_disable(ARRAY_SIZE(tc358746_supplies),
1615 tc358746->supplies);
1616 if (err)
1617 clk_prepare_enable(tc358746->refclk);
1618
1619 return err;
1620 }
1621
tc358746_resume(struct device * dev)1622 static int tc358746_resume(struct device *dev)
1623 {
1624 struct tc358746 *tc358746 = dev_get_drvdata(dev);
1625 int err;
1626
1627 gpiod_set_value(tc358746->reset_gpio, 1);
1628
1629 err = regulator_bulk_enable(ARRAY_SIZE(tc358746_supplies),
1630 tc358746->supplies);
1631 if (err)
1632 return err;
1633
1634 /* min. 200ns */
1635 usleep_range(10, 20);
1636
1637 gpiod_set_value(tc358746->reset_gpio, 0);
1638
1639 err = clk_prepare_enable(tc358746->refclk);
1640 if (err)
1641 goto err;
1642
1643 /* min. 700us ... 1ms */
1644 usleep_range(1000, 1500);
1645
1646 /*
1647 * Enable the PLL here since it can be called by the clk-framework or by
1648 * the .s_stream() callback. So this is the common place for both.
1649 */
1650 err = tc358746_apply_pll_config(tc358746);
1651 if (err)
1652 goto err_clk;
1653
1654 return 0;
1655
1656 err_clk:
1657 clk_disable_unprepare(tc358746->refclk);
1658 err:
1659 regulator_bulk_disable(ARRAY_SIZE(tc358746_supplies),
1660 tc358746->supplies);
1661 return err;
1662 }
1663
1664 static DEFINE_RUNTIME_DEV_PM_OPS(tc358746_pm_ops, tc358746_suspend,
1665 tc358746_resume, NULL);
1666
1667 static const struct of_device_id __maybe_unused tc358746_of_match[] = {
1668 { .compatible = "toshiba,tc358746" },
1669 { },
1670 };
1671 MODULE_DEVICE_TABLE(of, tc358746_of_match);
1672
1673 static struct i2c_driver tc358746_driver = {
1674 .driver = {
1675 .name = "tc358746",
1676 .pm = pm_ptr(&tc358746_pm_ops),
1677 .of_match_table = tc358746_of_match,
1678 },
1679 .probe = tc358746_probe,
1680 .remove = tc358746_remove,
1681 };
1682
1683 module_i2c_driver(tc358746_driver);
1684
1685 MODULE_DESCRIPTION("Toshiba TC358746 Parallel to CSI-2 bridge driver");
1686 MODULE_AUTHOR("Marco Felsch <kernel@pengutronix.de>");
1687 MODULE_LICENSE("GPL");
1688