1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2017, STMicroelectronics - All Rights Reserved 4 * Author(s): Patrice Chotard, <patrice.chotard@st.com> for STMicroelectronics. 5 */ 6 7 #include <common.h> 8 #include <clk-uclass.h> 9 #include <dm.h> 10 #include <regmap.h> 11 #include <syscon.h> 12 #include <asm/io.h> 13 #include <dm/root.h> 14 15 #include <dt-bindings/clock/stm32h7-clks.h> 16 17 /* RCC CR specific definitions */ 18 #define RCC_CR_HSION BIT(0) 19 #define RCC_CR_HSIRDY BIT(2) 20 21 #define RCC_CR_HSEON BIT(16) 22 #define RCC_CR_HSERDY BIT(17) 23 #define RCC_CR_HSEBYP BIT(18) 24 #define RCC_CR_PLL1ON BIT(24) 25 #define RCC_CR_PLL1RDY BIT(25) 26 27 #define RCC_CR_HSIDIV_MASK GENMASK(4, 3) 28 #define RCC_CR_HSIDIV_SHIFT 3 29 30 #define RCC_CFGR_SW_MASK GENMASK(2, 0) 31 #define RCC_CFGR_SW_HSI 0 32 #define RCC_CFGR_SW_CSI 1 33 #define RCC_CFGR_SW_HSE 2 34 #define RCC_CFGR_SW_PLL1 3 35 #define RCC_CFGR_TIMPRE BIT(15) 36 37 #define RCC_PLLCKSELR_PLLSRC_HSI 0 38 #define RCC_PLLCKSELR_PLLSRC_CSI 1 39 #define RCC_PLLCKSELR_PLLSRC_HSE 2 40 #define RCC_PLLCKSELR_PLLSRC_NO_CLK 3 41 42 #define RCC_PLLCKSELR_PLLSRC_MASK GENMASK(1, 0) 43 44 #define RCC_PLLCKSELR_DIVM1_SHIFT 4 45 #define RCC_PLLCKSELR_DIVM1_MASK GENMASK(9, 4) 46 47 #define RCC_PLL1DIVR_DIVN1_MASK GENMASK(8, 0) 48 49 #define RCC_PLL1DIVR_DIVP1_SHIFT 9 50 #define RCC_PLL1DIVR_DIVP1_MASK GENMASK(15, 9) 51 52 #define RCC_PLL1DIVR_DIVQ1_SHIFT 16 53 #define RCC_PLL1DIVR_DIVQ1_MASK GENMASK(22, 16) 54 55 #define RCC_PLL1DIVR_DIVR1_SHIFT 24 56 #define RCC_PLL1DIVR_DIVR1_MASK GENMASK(30, 24) 57 58 #define RCC_PLL1FRACR_FRACN1_SHIFT 3 59 #define RCC_PLL1FRACR_FRACN1_MASK GENMASK(15, 3) 60 61 #define RCC_PLLCFGR_PLL1RGE_SHIFT 2 62 #define PLL1RGE_1_2_MHZ 0 63 #define PLL1RGE_2_4_MHZ 1 64 #define PLL1RGE_4_8_MHZ 2 65 #define PLL1RGE_8_16_MHZ 3 66 #define RCC_PLLCFGR_DIVP1EN BIT(16) 67 #define RCC_PLLCFGR_DIVQ1EN BIT(17) 68 #define RCC_PLLCFGR_DIVR1EN BIT(18) 69 70 #define RCC_D1CFGR_HPRE_MASK GENMASK(3, 0) 71 #define RCC_D1CFGR_HPRE_DIVIDED BIT(3) 72 #define RCC_D1CFGR_HPRE_DIVIDER GENMASK(2, 0) 73 74 #define RCC_D1CFGR_HPRE_DIV2 8 75 76 #define RCC_D1CFGR_D1PPRE_SHIFT 4 77 #define RCC_D1CFGR_D1PPRE_DIVIDED BIT(6) 78 #define RCC_D1CFGR_D1PPRE_DIVIDER GENMASK(5, 4) 79 80 #define RCC_D1CFGR_D1CPRE_SHIFT 8 81 #define RCC_D1CFGR_D1CPRE_DIVIDER GENMASK(10, 8) 82 #define RCC_D1CFGR_D1CPRE_DIVIDED BIT(11) 83 84 #define RCC_D2CFGR_D2PPRE1_SHIFT 4 85 #define RCC_D2CFGR_D2PPRE1_DIVIDED BIT(6) 86 #define RCC_D2CFGR_D2PPRE1_DIVIDER GENMASK(5, 4) 87 88 #define RCC_D2CFGR_D2PPRE2_SHIFT 8 89 #define RCC_D2CFGR_D2PPRE2_DIVIDED BIT(10) 90 #define RCC_D2CFGR_D2PPRE2_DIVIDER GENMASK(9, 8) 91 92 #define RCC_D3CFGR_D3PPRE_SHIFT 4 93 #define RCC_D3CFGR_D3PPRE_DIVIDED BIT(6) 94 #define RCC_D3CFGR_D3PPRE_DIVIDER GENMASK(5, 4) 95 96 #define RCC_D1CCIPR_FMCSRC_MASK GENMASK(1, 0) 97 #define FMCSRC_HCLKD1 0 98 #define FMCSRC_PLL1_Q_CK 1 99 #define FMCSRC_PLL2_R_CK 2 100 #define FMCSRC_PER_CK 3 101 102 #define RCC_D1CCIPR_QSPISRC_MASK GENMASK(5, 4) 103 #define RCC_D1CCIPR_QSPISRC_SHIFT 4 104 #define QSPISRC_HCLKD1 0 105 #define QSPISRC_PLL1_Q_CK 1 106 #define QSPISRC_PLL2_R_CK 2 107 #define QSPISRC_PER_CK 3 108 109 #define PWR_CR3 0x0c 110 #define PWR_CR3_SCUEN BIT(2) 111 #define PWR_D3CR 0x18 112 #define PWR_D3CR_VOS_MASK GENMASK(15, 14) 113 #define PWR_D3CR_VOS_SHIFT 14 114 #define VOS_SCALE_3 1 115 #define VOS_SCALE_2 2 116 #define VOS_SCALE_1 3 117 #define PWR_D3CR_VOSREADY BIT(13) 118 119 struct stm32_rcc_regs { 120 u32 cr; /* 0x00 Source Control Register */ 121 u32 icscr; /* 0x04 Internal Clock Source Calibration Register */ 122 u32 crrcr; /* 0x08 Clock Recovery RC Register */ 123 u32 reserved1; /* 0x0c reserved */ 124 u32 cfgr; /* 0x10 Clock Configuration Register */ 125 u32 reserved2; /* 0x14 reserved */ 126 u32 d1cfgr; /* 0x18 Domain 1 Clock Configuration Register */ 127 u32 d2cfgr; /* 0x1c Domain 2 Clock Configuration Register */ 128 u32 d3cfgr; /* 0x20 Domain 3 Clock Configuration Register */ 129 u32 reserved3; /* 0x24 reserved */ 130 u32 pllckselr; /* 0x28 PLLs Clock Source Selection Register */ 131 u32 pllcfgr; /* 0x2c PLLs Configuration Register */ 132 u32 pll1divr; /* 0x30 PLL1 Dividers Configuration Register */ 133 u32 pll1fracr; /* 0x34 PLL1 Fractional Divider Register */ 134 u32 pll2divr; /* 0x38 PLL2 Dividers Configuration Register */ 135 u32 pll2fracr; /* 0x3c PLL2 Fractional Divider Register */ 136 u32 pll3divr; /* 0x40 PLL3 Dividers Configuration Register */ 137 u32 pll3fracr; /* 0x44 PLL3 Fractional Divider Register */ 138 u32 reserved4; /* 0x48 reserved */ 139 u32 d1ccipr; /* 0x4c Domain 1 Kernel Clock Configuration Register */ 140 u32 d2ccip1r; /* 0x50 Domain 2 Kernel Clock Configuration Register */ 141 u32 d2ccip2r; /* 0x54 Domain 2 Kernel Clock Configuration Register */ 142 u32 d3ccipr; /* 0x58 Domain 3 Kernel Clock Configuration Register */ 143 u32 reserved5; /* 0x5c reserved */ 144 u32 cier; /* 0x60 Clock Source Interrupt Enable Register */ 145 u32 cifr; /* 0x64 Clock Source Interrupt Flag Register */ 146 u32 cicr; /* 0x68 Clock Source Interrupt Clear Register */ 147 u32 reserved6; /* 0x6c reserved */ 148 u32 bdcr; /* 0x70 Backup Domain Control Register */ 149 u32 csr; /* 0x74 Clock Control and Status Register */ 150 u32 reserved7; /* 0x78 reserved */ 151 152 u32 ahb3rstr; /* 0x7c AHB3 Peripheral Reset Register */ 153 u32 ahb1rstr; /* 0x80 AHB1 Peripheral Reset Register */ 154 u32 ahb2rstr; /* 0x84 AHB2 Peripheral Reset Register */ 155 u32 ahb4rstr; /* 0x88 AHB4 Peripheral Reset Register */ 156 157 u32 apb3rstr; /* 0x8c APB3 Peripheral Reset Register */ 158 u32 apb1lrstr; /* 0x90 APB1 low Peripheral Reset Register */ 159 u32 apb1hrstr; /* 0x94 APB1 high Peripheral Reset Register */ 160 u32 apb2rstr; /* 0x98 APB2 Clock Register */ 161 u32 apb4rstr; /* 0x9c APB4 Clock Register */ 162 163 u32 gcr; /* 0xa0 Global Control Register */ 164 u32 reserved8; /* 0xa4 reserved */ 165 u32 d3amr; /* 0xa8 D3 Autonomous mode Register */ 166 u32 reserved9[9];/* 0xac to 0xcc reserved */ 167 u32 rsr; /* 0xd0 Reset Status Register */ 168 u32 ahb3enr; /* 0xd4 AHB3 Clock Register */ 169 u32 ahb1enr; /* 0xd8 AHB1 Clock Register */ 170 u32 ahb2enr; /* 0xdc AHB2 Clock Register */ 171 u32 ahb4enr; /* 0xe0 AHB4 Clock Register */ 172 173 u32 apb3enr; /* 0xe4 APB3 Clock Register */ 174 u32 apb1lenr; /* 0xe8 APB1 low Clock Register */ 175 u32 apb1henr; /* 0xec APB1 high Clock Register */ 176 u32 apb2enr; /* 0xf0 APB2 Clock Register */ 177 u32 apb4enr; /* 0xf4 APB4 Clock Register */ 178 }; 179 180 #define RCC_AHB3ENR offsetof(struct stm32_rcc_regs, ahb3enr) 181 #define RCC_AHB1ENR offsetof(struct stm32_rcc_regs, ahb1enr) 182 #define RCC_AHB2ENR offsetof(struct stm32_rcc_regs, ahb2enr) 183 #define RCC_AHB4ENR offsetof(struct stm32_rcc_regs, ahb4enr) 184 #define RCC_APB3ENR offsetof(struct stm32_rcc_regs, apb3enr) 185 #define RCC_APB1LENR offsetof(struct stm32_rcc_regs, apb1lenr) 186 #define RCC_APB1HENR offsetof(struct stm32_rcc_regs, apb1henr) 187 #define RCC_APB2ENR offsetof(struct stm32_rcc_regs, apb2enr) 188 #define RCC_APB4ENR offsetof(struct stm32_rcc_regs, apb4enr) 189 190 struct clk_cfg { 191 u32 gate_offset; 192 u8 gate_bit_idx; 193 const char *name; 194 }; 195 196 /* 197 * the way all these entries are sorted in this array could seem 198 * unlogical, but we are dependant of kernel DT_bindings, 199 * where clocks are separate in 2 banks, peripheral clocks and 200 * kernel clocks. 201 */ 202 203 static const struct clk_cfg clk_map[] = { 204 {RCC_AHB3ENR, 31, "d1sram1"}, /* peripheral clocks */ 205 {RCC_AHB3ENR, 30, "itcm"}, 206 {RCC_AHB3ENR, 29, "dtcm2"}, 207 {RCC_AHB3ENR, 28, "dtcm1"}, 208 {RCC_AHB3ENR, 8, "flitf"}, 209 {RCC_AHB3ENR, 5, "jpgdec"}, 210 {RCC_AHB3ENR, 4, "dma2d"}, 211 {RCC_AHB3ENR, 0, "mdma"}, 212 {RCC_AHB1ENR, 28, "usb2ulpi"}, 213 {RCC_AHB1ENR, 17, "eth1rx"}, 214 {RCC_AHB1ENR, 16, "eth1tx"}, 215 {RCC_AHB1ENR, 15, "eth1mac"}, 216 {RCC_AHB1ENR, 14, "art"}, 217 {RCC_AHB1ENR, 26, "usb1ulpi"}, 218 {RCC_AHB1ENR, 1, "dma2"}, 219 {RCC_AHB1ENR, 0, "dma1"}, 220 {RCC_AHB2ENR, 31, "d2sram3"}, 221 {RCC_AHB2ENR, 30, "d2sram2"}, 222 {RCC_AHB2ENR, 29, "d2sram1"}, 223 {RCC_AHB2ENR, 5, "hash"}, 224 {RCC_AHB2ENR, 4, "crypt"}, 225 {RCC_AHB2ENR, 0, "camitf"}, 226 {RCC_AHB4ENR, 28, "bkpram"}, 227 {RCC_AHB4ENR, 25, "hsem"}, 228 {RCC_AHB4ENR, 21, "bdma"}, 229 {RCC_AHB4ENR, 19, "crc"}, 230 {RCC_AHB4ENR, 10, "gpiok"}, 231 {RCC_AHB4ENR, 9, "gpioj"}, 232 {RCC_AHB4ENR, 8, "gpioi"}, 233 {RCC_AHB4ENR, 7, "gpioh"}, 234 {RCC_AHB4ENR, 6, "gpiog"}, 235 {RCC_AHB4ENR, 5, "gpiof"}, 236 {RCC_AHB4ENR, 4, "gpioe"}, 237 {RCC_AHB4ENR, 3, "gpiod"}, 238 {RCC_AHB4ENR, 2, "gpioc"}, 239 {RCC_AHB4ENR, 1, "gpiob"}, 240 {RCC_AHB4ENR, 0, "gpioa"}, 241 {RCC_APB3ENR, 6, "wwdg1"}, 242 {RCC_APB1LENR, 29, "dac12"}, 243 {RCC_APB1LENR, 11, "wwdg2"}, 244 {RCC_APB1LENR, 8, "tim14"}, 245 {RCC_APB1LENR, 7, "tim13"}, 246 {RCC_APB1LENR, 6, "tim12"}, 247 {RCC_APB1LENR, 5, "tim7"}, 248 {RCC_APB1LENR, 4, "tim6"}, 249 {RCC_APB1LENR, 3, "tim5"}, 250 {RCC_APB1LENR, 2, "tim4"}, 251 {RCC_APB1LENR, 1, "tim3"}, 252 {RCC_APB1LENR, 0, "tim2"}, 253 {RCC_APB1HENR, 5, "mdios"}, 254 {RCC_APB1HENR, 4, "opamp"}, 255 {RCC_APB1HENR, 1, "crs"}, 256 {RCC_APB2ENR, 18, "tim17"}, 257 {RCC_APB2ENR, 17, "tim16"}, 258 {RCC_APB2ENR, 16, "tim15"}, 259 {RCC_APB2ENR, 1, "tim8"}, 260 {RCC_APB2ENR, 0, "tim1"}, 261 {RCC_APB4ENR, 26, "tmpsens"}, 262 {RCC_APB4ENR, 16, "rtcapb"}, 263 {RCC_APB4ENR, 15, "vref"}, 264 {RCC_APB4ENR, 14, "comp12"}, 265 {RCC_APB4ENR, 1, "syscfg"}, 266 {RCC_AHB3ENR, 16, "sdmmc1"}, /* kernel clocks */ 267 {RCC_AHB3ENR, 14, "quadspi"}, 268 {RCC_AHB3ENR, 12, "fmc"}, 269 {RCC_AHB1ENR, 27, "usb2otg"}, 270 {RCC_AHB1ENR, 25, "usb1otg"}, 271 {RCC_AHB1ENR, 5, "adc12"}, 272 {RCC_AHB2ENR, 9, "sdmmc2"}, 273 {RCC_AHB2ENR, 6, "rng"}, 274 {RCC_AHB4ENR, 24, "adc3"}, 275 {RCC_APB3ENR, 4, "dsi"}, 276 {RCC_APB3ENR, 3, "ltdc"}, 277 {RCC_APB1LENR, 31, "usart8"}, 278 {RCC_APB1LENR, 30, "usart7"}, 279 {RCC_APB1LENR, 27, "hdmicec"}, 280 {RCC_APB1LENR, 23, "i2c3"}, 281 {RCC_APB1LENR, 22, "i2c2"}, 282 {RCC_APB1LENR, 21, "i2c1"}, 283 {RCC_APB1LENR, 20, "uart5"}, 284 {RCC_APB1LENR, 19, "uart4"}, 285 {RCC_APB1LENR, 18, "usart3"}, 286 {RCC_APB1LENR, 17, "usart2"}, 287 {RCC_APB1LENR, 16, "spdifrx"}, 288 {RCC_APB1LENR, 15, "spi3"}, 289 {RCC_APB1LENR, 14, "spi2"}, 290 {RCC_APB1LENR, 9, "lptim1"}, 291 {RCC_APB1HENR, 8, "fdcan"}, 292 {RCC_APB1HENR, 2, "swp"}, 293 {RCC_APB2ENR, 29, "hrtim"}, 294 {RCC_APB2ENR, 28, "dfsdm1"}, 295 {RCC_APB2ENR, 24, "sai3"}, 296 {RCC_APB2ENR, 23, "sai2"}, 297 {RCC_APB2ENR, 22, "sai1"}, 298 {RCC_APB2ENR, 20, "spi5"}, 299 {RCC_APB2ENR, 13, "spi4"}, 300 {RCC_APB2ENR, 12, "spi1"}, 301 {RCC_APB2ENR, 5, "usart6"}, 302 {RCC_APB2ENR, 4, "usart1"}, 303 {RCC_APB4ENR, 21, "sai4a"}, 304 {RCC_APB4ENR, 21, "sai4b"}, 305 {RCC_APB4ENR, 12, "lptim5"}, 306 {RCC_APB4ENR, 11, "lptim4"}, 307 {RCC_APB4ENR, 10, "lptim3"}, 308 {RCC_APB4ENR, 9, "lptim2"}, 309 {RCC_APB4ENR, 7, "i2c4"}, 310 {RCC_APB4ENR, 5, "spi6"}, 311 {RCC_APB4ENR, 3, "lpuart1"}, 312 }; 313 314 struct stm32_clk { 315 struct stm32_rcc_regs *rcc_base; 316 struct regmap *pwr_regmap; 317 }; 318 319 struct pll_psc { 320 u8 divm; 321 u16 divn; 322 u8 divp; 323 u8 divq; 324 u8 divr; 325 }; 326 327 /* 328 * OSC_HSE = 25 MHz 329 * VCO = 500MHz 330 * pll1_p = 250MHz / pll1_q = 250MHz pll1_r = 250Mhz 331 */ 332 struct pll_psc sys_pll_psc = { 333 .divm = 4, 334 .divn = 80, 335 .divp = 2, 336 .divq = 2, 337 .divr = 2, 338 }; 339 340 enum apb { 341 APB1, 342 APB2, 343 }; 344 configure_clocks(struct udevice * dev)345 int configure_clocks(struct udevice *dev) 346 { 347 struct stm32_clk *priv = dev_get_priv(dev); 348 struct stm32_rcc_regs *regs = priv->rcc_base; 349 uint8_t *pwr_base = (uint8_t *)regmap_get_range(priv->pwr_regmap, 0); 350 uint32_t pllckselr = 0; 351 uint32_t pll1divr = 0; 352 uint32_t pllcfgr = 0; 353 354 /* Switch on HSI */ 355 setbits_le32(®s->cr, RCC_CR_HSION); 356 while (!(readl(®s->cr) & RCC_CR_HSIRDY)) 357 ; 358 359 /* Reset CFGR, now HSI is the default system clock */ 360 writel(0, ®s->cfgr); 361 362 /* Set all kernel domain clock registers to reset value*/ 363 writel(0x0, ®s->d1ccipr); 364 writel(0x0, ®s->d2ccip1r); 365 writel(0x0, ®s->d2ccip2r); 366 367 /* Set voltage scaling at scale 1 (1,15 - 1,26 Volts) */ 368 clrsetbits_le32(pwr_base + PWR_D3CR, PWR_D3CR_VOS_MASK, 369 VOS_SCALE_1 << PWR_D3CR_VOS_SHIFT); 370 /* Lock supply configuration update */ 371 clrbits_le32(pwr_base + PWR_CR3, PWR_CR3_SCUEN); 372 while (!(readl(pwr_base + PWR_D3CR) & PWR_D3CR_VOSREADY)) 373 ; 374 375 /* disable HSE to configure it */ 376 clrbits_le32(®s->cr, RCC_CR_HSEON); 377 while ((readl(®s->cr) & RCC_CR_HSERDY)) 378 ; 379 380 /* clear HSE bypass and set it ON */ 381 clrbits_le32(®s->cr, RCC_CR_HSEBYP); 382 /* Switch on HSE */ 383 setbits_le32(®s->cr, RCC_CR_HSEON); 384 while (!(readl(®s->cr) & RCC_CR_HSERDY)) 385 ; 386 387 /* pll setup, disable it */ 388 clrbits_le32(®s->cr, RCC_CR_PLL1ON); 389 while ((readl(®s->cr) & RCC_CR_PLL1RDY)) 390 ; 391 392 /* Select HSE as PLL clock source */ 393 pllckselr |= RCC_PLLCKSELR_PLLSRC_HSE; 394 pllckselr |= sys_pll_psc.divm << RCC_PLLCKSELR_DIVM1_SHIFT; 395 writel(pllckselr, ®s->pllckselr); 396 397 pll1divr |= (sys_pll_psc.divr - 1) << RCC_PLL1DIVR_DIVR1_SHIFT; 398 pll1divr |= (sys_pll_psc.divq - 1) << RCC_PLL1DIVR_DIVQ1_SHIFT; 399 pll1divr |= (sys_pll_psc.divp - 1) << RCC_PLL1DIVR_DIVP1_SHIFT; 400 pll1divr |= (sys_pll_psc.divn - 1); 401 writel(pll1divr, ®s->pll1divr); 402 403 pllcfgr |= PLL1RGE_4_8_MHZ << RCC_PLLCFGR_PLL1RGE_SHIFT; 404 pllcfgr |= RCC_PLLCFGR_DIVP1EN; 405 pllcfgr |= RCC_PLLCFGR_DIVQ1EN; 406 pllcfgr |= RCC_PLLCFGR_DIVR1EN; 407 writel(pllcfgr, ®s->pllcfgr); 408 409 /* pll setup, enable it */ 410 setbits_le32(®s->cr, RCC_CR_PLL1ON); 411 412 /* set HPRE (/2) DI clk --> 125MHz */ 413 clrsetbits_le32(®s->d1cfgr, RCC_D1CFGR_HPRE_MASK, 414 RCC_D1CFGR_HPRE_DIV2); 415 416 /* select PLL1 as system clock source (sys_ck)*/ 417 clrsetbits_le32(®s->cfgr, RCC_CFGR_SW_MASK, RCC_CFGR_SW_PLL1); 418 while ((readl(®s->cfgr) & RCC_CFGR_SW_MASK) != RCC_CFGR_SW_PLL1) 419 ; 420 421 /* sdram: use pll1_q as fmc_k clk */ 422 clrsetbits_le32(®s->d1ccipr, RCC_D1CCIPR_FMCSRC_MASK, 423 FMCSRC_PLL1_Q_CK); 424 425 return 0; 426 } 427 stm32_get_HSI_divider(struct stm32_rcc_regs * regs)428 static u32 stm32_get_HSI_divider(struct stm32_rcc_regs *regs) 429 { 430 u32 divider; 431 432 /* get HSI divider value */ 433 divider = readl(®s->cr) & RCC_CR_HSIDIV_MASK; 434 divider = divider >> RCC_CR_HSIDIV_SHIFT; 435 436 return divider; 437 }; 438 439 enum pllsrc { 440 HSE, 441 LSE, 442 HSI, 443 CSI, 444 I2S, 445 TIMER, 446 PLLSRC_NB, 447 }; 448 449 static const char * const pllsrc_name[PLLSRC_NB] = { 450 [HSE] = "clk-hse", 451 [LSE] = "clk-lse", 452 [HSI] = "clk-hsi", 453 [CSI] = "clk-csi", 454 [I2S] = "clk-i2s", 455 [TIMER] = "timer-clk" 456 }; 457 stm32_get_rate(struct stm32_rcc_regs * regs,enum pllsrc pllsrc)458 static ulong stm32_get_rate(struct stm32_rcc_regs *regs, enum pllsrc pllsrc) 459 { 460 struct clk clk; 461 struct udevice *fixed_clock_dev = NULL; 462 u32 divider; 463 int ret; 464 const char *name = pllsrc_name[pllsrc]; 465 466 debug("%s name %s\n", __func__, name); 467 468 clk.id = 0; 469 ret = uclass_get_device_by_name(UCLASS_CLK, name, &fixed_clock_dev); 470 if (ret) { 471 pr_err("Can't find clk %s (%d)", name, ret); 472 return 0; 473 } 474 475 ret = clk_request(fixed_clock_dev, &clk); 476 if (ret) { 477 pr_err("Can't request %s clk (%d)", name, ret); 478 return 0; 479 } 480 481 divider = 0; 482 if (pllsrc == HSI) 483 divider = stm32_get_HSI_divider(regs); 484 485 debug("%s divider %d rate %ld\n", __func__, 486 divider, clk_get_rate(&clk)); 487 488 return clk_get_rate(&clk) >> divider; 489 }; 490 491 enum pll1_output { 492 PLL1_P_CK, 493 PLL1_Q_CK, 494 PLL1_R_CK, 495 }; 496 stm32_get_PLL1_rate(struct stm32_rcc_regs * regs,enum pll1_output output)497 static u32 stm32_get_PLL1_rate(struct stm32_rcc_regs *regs, 498 enum pll1_output output) 499 { 500 ulong pllsrc = 0; 501 u32 divm1, divn1, divp1, divq1, divr1, fracn1; 502 ulong vco, rate; 503 504 /* get the PLLSRC */ 505 switch (readl(®s->pllckselr) & RCC_PLLCKSELR_PLLSRC_MASK) { 506 case RCC_PLLCKSELR_PLLSRC_HSI: 507 pllsrc = stm32_get_rate(regs, HSI); 508 break; 509 case RCC_PLLCKSELR_PLLSRC_CSI: 510 pllsrc = stm32_get_rate(regs, CSI); 511 break; 512 case RCC_PLLCKSELR_PLLSRC_HSE: 513 pllsrc = stm32_get_rate(regs, HSE); 514 break; 515 case RCC_PLLCKSELR_PLLSRC_NO_CLK: 516 /* shouldn't happen */ 517 pr_err("wrong value for RCC_PLLCKSELR register\n"); 518 pllsrc = 0; 519 break; 520 } 521 522 /* pllsrc = 0 ? no need to go ahead */ 523 if (!pllsrc) 524 return pllsrc; 525 526 /* get divm1, divp1, divn1 and divr1 */ 527 divm1 = readl(®s->pllckselr) & RCC_PLLCKSELR_DIVM1_MASK; 528 divm1 = divm1 >> RCC_PLLCKSELR_DIVM1_SHIFT; 529 530 divn1 = (readl(®s->pll1divr) & RCC_PLL1DIVR_DIVN1_MASK) + 1; 531 532 divp1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVP1_MASK; 533 divp1 = (divp1 >> RCC_PLL1DIVR_DIVP1_SHIFT) + 1; 534 535 divq1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVQ1_MASK; 536 divq1 = (divq1 >> RCC_PLL1DIVR_DIVQ1_SHIFT) + 1; 537 538 divr1 = readl(®s->pll1divr) & RCC_PLL1DIVR_DIVR1_MASK; 539 divr1 = (divr1 >> RCC_PLL1DIVR_DIVR1_SHIFT) + 1; 540 541 fracn1 = readl(®s->pll1fracr) & RCC_PLL1DIVR_DIVR1_MASK; 542 fracn1 = fracn1 & RCC_PLL1DIVR_DIVR1_SHIFT; 543 544 vco = (pllsrc / divm1) * divn1; 545 rate = (pllsrc * fracn1) / (divm1 * 8192); 546 547 debug("%s divm1 = %d divn1 = %d divp1 = %d divq1 = %d divr1 = %d\n", 548 __func__, divm1, divn1, divp1, divq1, divr1); 549 debug("%s fracn1 = %d vco = %ld rate = %ld\n", 550 __func__, fracn1, vco, rate); 551 552 switch (output) { 553 case PLL1_P_CK: 554 return (vco + rate) / divp1; 555 break; 556 case PLL1_Q_CK: 557 return (vco + rate) / divq1; 558 break; 559 560 case PLL1_R_CK: 561 return (vco + rate) / divr1; 562 break; 563 } 564 565 return -EINVAL; 566 } 567 stm32_get_apb_psc(struct stm32_rcc_regs * regs,enum apb apb)568 static u32 stm32_get_apb_psc(struct stm32_rcc_regs *regs, enum apb apb) 569 { 570 u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512}; 571 u32 d2cfgr = readl(®s->d2cfgr); 572 573 if (apb == APB1) { 574 if (d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDED) 575 /* get D2 domain APB1 prescaler */ 576 return prescaler_table[ 577 ((d2cfgr & RCC_D2CFGR_D2PPRE1_DIVIDER) 578 >> RCC_D2CFGR_D2PPRE1_SHIFT)]; 579 } else { /* APB2 */ 580 if (d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDED) 581 /* get D2 domain APB2 prescaler */ 582 return prescaler_table[ 583 ((d2cfgr & RCC_D2CFGR_D2PPRE2_DIVIDER) 584 >> RCC_D2CFGR_D2PPRE2_SHIFT)]; 585 } 586 587 return 1; 588 }; 589 stm32_get_timer_rate(struct stm32_clk * priv,u32 sysclk,enum apb apb)590 static u32 stm32_get_timer_rate(struct stm32_clk *priv, u32 sysclk, 591 enum apb apb) 592 { 593 struct stm32_rcc_regs *regs = priv->rcc_base; 594 u32 psc = stm32_get_apb_psc(regs, apb); 595 596 if (readl(®s->cfgr) & RCC_CFGR_TIMPRE) 597 /* 598 * if APB prescaler is configured to a 599 * division factor of 1, 2 or 4 600 */ 601 switch (psc) { 602 case 1: 603 case 2: 604 case 4: 605 return sysclk; 606 case 8: 607 return sysclk / 2; 608 case 16: 609 return sysclk / 4; 610 default: 611 pr_err("unexpected prescaler value (%d)\n", psc); 612 return 0; 613 } 614 else 615 switch (psc) { 616 case 1: 617 return sysclk; 618 case 2: 619 case 4: 620 case 8: 621 case 16: 622 return sysclk / psc; 623 default: 624 pr_err("unexpected prescaler value (%d)\n", psc); 625 return 0; 626 } 627 }; 628 stm32_clk_get_rate(struct clk * clk)629 static ulong stm32_clk_get_rate(struct clk *clk) 630 { 631 struct stm32_clk *priv = dev_get_priv(clk->dev); 632 struct stm32_rcc_regs *regs = priv->rcc_base; 633 ulong sysclk = 0; 634 u32 gate_offset; 635 u32 d1cfgr, d3cfgr; 636 /* prescaler table lookups for clock computation */ 637 u16 prescaler_table[8] = {2, 4, 8, 16, 64, 128, 256, 512}; 638 u8 source, idx; 639 640 /* 641 * get system clock (sys_ck) source 642 * can be HSI_CK, CSI_CK, HSE_CK or pll1_p_ck 643 */ 644 source = readl(®s->cfgr) & RCC_CFGR_SW_MASK; 645 switch (source) { 646 case RCC_CFGR_SW_PLL1: 647 sysclk = stm32_get_PLL1_rate(regs, PLL1_P_CK); 648 break; 649 case RCC_CFGR_SW_HSE: 650 sysclk = stm32_get_rate(regs, HSE); 651 break; 652 653 case RCC_CFGR_SW_CSI: 654 sysclk = stm32_get_rate(regs, CSI); 655 break; 656 657 case RCC_CFGR_SW_HSI: 658 sysclk = stm32_get_rate(regs, HSI); 659 break; 660 } 661 662 /* sysclk = 0 ? no need to go ahead */ 663 if (!sysclk) 664 return sysclk; 665 666 debug("%s system clock: source = %d freq = %ld\n", 667 __func__, source, sysclk); 668 669 d1cfgr = readl(®s->d1cfgr); 670 671 if (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDED) { 672 /* get D1 domain Core prescaler */ 673 idx = (d1cfgr & RCC_D1CFGR_D1CPRE_DIVIDER) >> 674 RCC_D1CFGR_D1CPRE_SHIFT; 675 sysclk = sysclk / prescaler_table[idx]; 676 } 677 678 if (d1cfgr & RCC_D1CFGR_HPRE_DIVIDED) { 679 /* get D1 domain AHB prescaler */ 680 idx = d1cfgr & RCC_D1CFGR_HPRE_DIVIDER; 681 sysclk = sysclk / prescaler_table[idx]; 682 } 683 684 gate_offset = clk_map[clk->id].gate_offset; 685 686 debug("%s clk->id=%ld gate_offset=0x%x sysclk=%ld\n", 687 __func__, clk->id, gate_offset, sysclk); 688 689 switch (gate_offset) { 690 case RCC_AHB3ENR: 691 case RCC_AHB1ENR: 692 case RCC_AHB2ENR: 693 case RCC_AHB4ENR: 694 return sysclk; 695 break; 696 697 case RCC_APB3ENR: 698 if (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDED) { 699 /* get D1 domain APB3 prescaler */ 700 idx = (d1cfgr & RCC_D1CFGR_D1PPRE_DIVIDER) >> 701 RCC_D1CFGR_D1PPRE_SHIFT; 702 sysclk = sysclk / prescaler_table[idx]; 703 } 704 705 debug("%s system clock: freq after APB3 prescaler = %ld\n", 706 __func__, sysclk); 707 708 return sysclk; 709 break; 710 711 case RCC_APB4ENR: 712 d3cfgr = readl(®s->d3cfgr); 713 if (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDED) { 714 /* get D3 domain APB4 prescaler */ 715 idx = (d3cfgr & RCC_D3CFGR_D3PPRE_DIVIDER) >> 716 RCC_D3CFGR_D3PPRE_SHIFT; 717 sysclk = sysclk / prescaler_table[idx]; 718 } 719 720 debug("%s system clock: freq after APB4 prescaler = %ld\n", 721 __func__, sysclk); 722 723 return sysclk; 724 break; 725 726 case RCC_APB1LENR: 727 case RCC_APB1HENR: 728 /* special case for GPT timers */ 729 switch (clk->id) { 730 case TIM14_CK: 731 case TIM13_CK: 732 case TIM12_CK: 733 case TIM7_CK: 734 case TIM6_CK: 735 case TIM5_CK: 736 case TIM4_CK: 737 case TIM3_CK: 738 case TIM2_CK: 739 return stm32_get_timer_rate(priv, sysclk, APB1); 740 } 741 742 debug("%s system clock: freq after APB1 prescaler = %ld\n", 743 __func__, sysclk); 744 745 return (sysclk / stm32_get_apb_psc(regs, APB1)); 746 break; 747 748 case RCC_APB2ENR: 749 /* special case for timers */ 750 switch (clk->id) { 751 case TIM17_CK: 752 case TIM16_CK: 753 case TIM15_CK: 754 case TIM8_CK: 755 case TIM1_CK: 756 return stm32_get_timer_rate(priv, sysclk, APB2); 757 } 758 759 debug("%s system clock: freq after APB2 prescaler = %ld\n", 760 __func__, sysclk); 761 762 return (sysclk / stm32_get_apb_psc(regs, APB2)); 763 764 break; 765 766 default: 767 pr_err("unexpected gate_offset value (0x%x)\n", gate_offset); 768 return -EINVAL; 769 break; 770 } 771 } 772 stm32_clk_enable(struct clk * clk)773 static int stm32_clk_enable(struct clk *clk) 774 { 775 struct stm32_clk *priv = dev_get_priv(clk->dev); 776 struct stm32_rcc_regs *regs = priv->rcc_base; 777 u32 gate_offset; 778 u32 gate_bit_index; 779 unsigned long clk_id = clk->id; 780 781 gate_offset = clk_map[clk_id].gate_offset; 782 gate_bit_index = clk_map[clk_id].gate_bit_idx; 783 784 debug("%s: clkid=%ld gate offset=0x%x bit_index=%d name=%s\n", 785 __func__, clk->id, gate_offset, gate_bit_index, 786 clk_map[clk_id].name); 787 788 setbits_le32(®s->cr + (gate_offset / 4), BIT(gate_bit_index)); 789 790 return 0; 791 } 792 stm32_clk_probe(struct udevice * dev)793 static int stm32_clk_probe(struct udevice *dev) 794 { 795 struct stm32_clk *priv = dev_get_priv(dev); 796 struct udevice *syscon; 797 fdt_addr_t addr; 798 int err; 799 800 addr = dev_read_addr(dev); 801 if (addr == FDT_ADDR_T_NONE) 802 return -EINVAL; 803 804 priv->rcc_base = (struct stm32_rcc_regs *)addr; 805 806 /* get corresponding syscon phandle */ 807 err = uclass_get_device_by_phandle(UCLASS_SYSCON, dev, 808 "st,syscfg", &syscon); 809 810 if (err) { 811 pr_err("unable to find syscon device\n"); 812 return err; 813 } 814 815 priv->pwr_regmap = syscon_get_regmap(syscon); 816 if (!priv->pwr_regmap) { 817 pr_err("unable to find regmap\n"); 818 return -ENODEV; 819 } 820 821 configure_clocks(dev); 822 823 return 0; 824 } 825 stm32_clk_of_xlate(struct clk * clk,struct ofnode_phandle_args * args)826 static int stm32_clk_of_xlate(struct clk *clk, 827 struct ofnode_phandle_args *args) 828 { 829 if (args->args_count != 1) { 830 debug("Invaild args_count: %d\n", args->args_count); 831 return -EINVAL; 832 } 833 834 if (args->args_count) { 835 clk->id = args->args[0]; 836 /* 837 * this computation convert DT clock index which is used to 838 * point into 2 separate clock arrays (peripheral and kernel 839 * clocks bank) (see include/dt-bindings/clock/stm32h7-clks.h) 840 * into index to point into only one array where peripheral 841 * and kernel clocks are consecutive 842 */ 843 if (clk->id >= KERN_BANK) { 844 clk->id -= KERN_BANK; 845 clk->id += LAST_PERIF_BANK - PERIF_BANK + 1; 846 } else { 847 clk->id -= PERIF_BANK; 848 } 849 } else { 850 clk->id = 0; 851 } 852 853 debug("%s clk->id %ld\n", __func__, clk->id); 854 855 return 0; 856 } 857 858 static struct clk_ops stm32_clk_ops = { 859 .of_xlate = stm32_clk_of_xlate, 860 .enable = stm32_clk_enable, 861 .get_rate = stm32_clk_get_rate, 862 }; 863 864 U_BOOT_DRIVER(stm32h7_clk) = { 865 .name = "stm32h7_rcc_clock", 866 .id = UCLASS_CLK, 867 .ops = &stm32_clk_ops, 868 .probe = stm32_clk_probe, 869 .priv_auto_alloc_size = sizeof(struct stm32_clk), 870 .flags = DM_FLAG_PRE_RELOC, 871 }; 872