1/* SPDX-License-Identifier: GPL-2.0+ */ 2/* 3 * Copyright (C) 2011 Renesas Electronics Europe Ltd. 4 * Copyright (C) 2008 Renesas Solutions Corp. 5 * Copyright (C) 2008 Nobuhiro Iwamatsu 6 * 7 * Based on board/renesas/rsk7203/lowlevel_init.S 8 */ 9#include <config.h> 10 11#include <asm/processor.h> 12#include <asm/macro.h> 13 14 .global lowlevel_init 15 16 .text 17 .align 2 18 19lowlevel_init: 20 /* Cache setting */ 21 write32 CCR1_A ,CCR1_D 22 23 /* io_set_cpg */ 24 write8 STBCR3_A, STBCR3_D 25 write8 STBCR4_A, STBCR4_D 26 write8 STBCR5_A, STBCR5_D 27 write8 STBCR6_A, STBCR6_D 28 write8 STBCR7_A, STBCR7_D 29 write8 STBCR8_A, STBCR8_D 30 31 /* ConfigurePortPins */ 32 33 /* Leaving LED1 ON for sanity test */ 34 write16 PJCR1_A, PJCR1_D1 35 write16 PJCR2_A, PJCR2_D 36 write16 PJIOR0_A, PJIOR0_D1 37 write16 PJDR0_A, PJDR0_D 38 write16 PJPR0_A, PJPR0_D 39 40 /* Configure EN_PIN & RS_PIN */ 41 write16 PGCR2_A, PGCR2_D 42 write16 PGIOR0_A, PGIOR0_D 43 44 /* Configure the port pins connected to UART */ 45 write16 PJCR1_A, PJCR1_D2 46 write16 PJIOR0_A, PJIOR0_D2 47 48 /* Configure Operating Frequency */ 49 write16 WTCSR_A, WTCSR_D0 50 write16 WTCSR_A, WTCSR_D1 51 write16 WTCNT_A, WTCNT_D 52 53 /* Control of RESBANK */ 54 write16 IBNR_A, IBNR_D 55 /* Enable SCIF3 module */ 56 write16 STBCR4_A, STBCR4_D 57 58 /* Set clock mode*/ 59 write16 FRQCR_A, FRQCR_D 60 61 /* Configure Bus And Memory */ 62init_bsc_cs0: 63 64pfc_settings: 65 write16 PCCR2_A, PCCR2_D 66 write16 PCCR1_A, PCCR1_D 67 write16 PCCR0_A, PCCR0_D 68 69 write16 PBCR0_A, PBCR0_D 70 write16 PBCR1_A, PBCR1_D 71 write16 PBCR2_A, PBCR2_D 72 write16 PBCR3_A, PBCR3_D 73 write16 PBCR4_A, PBCR4_D 74 write16 PBCR5_A, PBCR5_D 75 76 write16 PDCR0_A, PDCR0_D 77 write16 PDCR1_A, PDCR1_D 78 write16 PDCR2_A, PDCR2_D 79 write16 PDCR3_A, PDCR3_D 80 81 write32 CS0WCR_A, CS0WCR_D 82 write32 CS0BCR_A, CS0BCR_D 83 84init_bsc_cs2: 85 write16 PJCR0_A, PJCR0_D 86 write32 CS2WCR_A, CS2WCR_D 87 88init_sdram: 89 write32 CS3BCR_A, CS3BCR_D 90 write32 CS3WCR_A, CS3WCR_D 91 write32 SDCR_A, SDCR_D 92 write32 RTCOR_A, RTCOR_D 93 write32 RTCSR_A, RTCSR_D 94 95 /* wait 200us */ 96 mov.l REPEAT_D, r3 97 mov #0, r2 98repeat0: 99 add #1, r2 100 cmp/hs r3, r2 101 bf repeat0 102 nop 103 104 mov.l SDRAM_MODE, r1 105 mov #0, r0 106 mov.l r0, @r1 107 108 nop 109 rts 110 111 .align 4 112 113CCR1_A: .long CCR1 114CCR1_D: .long 0x0000090B 115FRQCR_A: .long 0xFFFE0010 116FRQCR_D: .word 0x1003 117.align 2 118STBCR3_A: .long 0xFFFE0408 119STBCR3_D: .long 0x00000002 120STBCR4_A: .long 0xFFFE040C 121STBCR4_D: .word 0x0000 122.align 2 123STBCR5_A: .long 0xFFFE0410 124STBCR5_D: .long 0x00000010 125STBCR6_A: .long 0xFFFE0414 126STBCR6_D: .long 0x00000002 127STBCR7_A: .long 0xFFFE0418 128STBCR7_D: .long 0x0000002A 129STBCR8_A: .long 0xFFFE041C 130STBCR8_D: .long 0x0000007E 131PJCR1_A: .long 0xFFFE390C 132PJCR1_D1: .word 0x0000 133PJCR1_D2: .word 0x0022 134PJCR2_A: .long 0xFFFE390A 135PJCR2_D: .word 0x0000 136.align 2 137PJIOR0_A: .long 0xFFFE3912 138PJIOR0_D1: .word 0x0FC0 139PJIOR0_D2: .word 0x0FE0 140PJDR0_A: .long 0xFFFE3916 141PJDR0_D: .word 0x0FBF 142.align 2 143PJPR0_A: .long 0xFFFE391A 144PJPR0_D: .long 0x00000FBF 145PGCR2_A: .long 0xFFFE38CA 146PGCR2_D: .word 0x0000 147.align 2 148PGIOR0_A: .long 0xFFFE38D2 149PGIOR0_D: .word 0x03F0 150.align 2 151WTCSR_A: .long 0xFFFE0000 152WTCSR_D0: .word 0x0000 153WTCSR_D1: .word 0x0000 154WTCNT_A: .long 0xFFFE0002 155WTCNT_D: .word 0x0000 156.align 2 157PCCR0_A: .long 0xFFFE384E 158PDCR0_A: .long 0xFFFE386E 159PDCR1_A: .long 0xFFFE386C 160PDCR2_A: .long 0xFFFE386A 161PDCR3_A: .long 0xFFFE3868 162PBCR0_A: .long 0xFFFE382E 163PBCR1_A: .long 0xFFFE382C 164PBCR2_A: .long 0xFFFE382A 165PBCR3_A: .long 0xFFFE3828 166PBCR4_A: .long 0xFFFE3826 167PBCR5_A: .long 0xFFFE3824 168PCCR0_D: .word 0x1111 169PDCR0_D: .word 0x1111 170PDCR1_D: .word 0x1111 171PDCR2_D: .word 0x1111 172PDCR3_D: .word 0x1111 173PBCR0_D: .word 0x1110 174PBCR1_D: .word 0x1111 175PBCR2_D: .word 0x1111 176PBCR3_D: .word 0x1111 177PBCR4_D: .word 0x1111 178PBCR5_D: .word 0x0111 179.align 2 180CS0WCR_A: .long 0xFFFC0028 181CS0WCR_D: .long 0x00000B41 182CS0BCR_A: .long 0xFFFC0004 183CS0BCR_D: .long 0x10000400 184PJCR0_A: .long 0xFFFE390E 185PJCR0_D: .word 0x3300 186.align 2 187CS2WCR_A: .long 0xFFFC0030 188CS2WCR_D: .long 0x00000B01 189PCCR2_A: .long 0xFFFE384A 190PCCR2_D: .word 0x0001 191.align 2 192PCCR1_A: .long 0xFFFE384C 193PCCR1_D: .word 0x1111 194.align 2 195CS3BCR_A: .long 0xFFFC0010 196CS3BCR_D: .long 0x00004400 197CS3WCR_A: .long 0xFFFC0034 198CS3WCR_D: .long 0x0000288A 199SDCR_A: .long 0xFFFC004C 200SDCR_D: .long 0x00000812 201RTCOR_A: .long 0xFFFC0058 202RTCOR_D: .long 0xA55A0046 203RTCSR_A: .long 0xFFFC0050 204RTCSR_D: .long 0xA55A0010 205IBNR_A: .long 0xFFFE080E 206IBNR_D: .word 0x0000 207.align 2 208SDRAM_MODE: .long 0xFFFC5040 209REPEAT_D: .long 0x00000085 210