1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2012 Renesas Electronics Europe Ltd. 4 * Copyright (C) 2012 Phil Edworthy 5 * Copyright (C) 2008 Renesas Solutions Corp. 6 * Copyright (C) 2008 Nobuhiro Iwamatsu 7 * 8 * Based on board/renesas/rsk7264/lowlevel_init.S 9 */ 10 #include <config.h> 11 12 #include <asm/processor.h> 13 #include <asm/macro.h> 14 15 .global lowlevel_init 16 17 .text 18 .align 2 19 20 lowlevel_init: 21 /* Flush and enable caches (data cache in write-through mode) */ 22 write32 CCR1_A ,CCR1_D 23 24 /* Disable WDT */ 25 write16 WTCSR_A, WTCSR_D 26 write16 WTCNT_A, WTCNT_D 27 28 /* Disable Register Bank interrupts */ 29 write16 IBNR_A, IBNR_D 30 31 /* Set clocks based on 13.225MHz xtal */ 32 write16 FRQCR_A, FRQCR_D /* CPU=266MHz, I=133MHz, P=66MHz */ 33 34 /* Enable all peripherals */ 35 write8 STBCR3_A, STBCR3_D 36 write8 STBCR4_A, STBCR4_D 37 write8 STBCR5_A, STBCR5_D 38 write8 STBCR6_A, STBCR6_D 39 write8 STBCR7_A, STBCR7_D 40 write8 STBCR8_A, STBCR8_D 41 write8 STBCR9_A, STBCR9_D 42 write8 STBCR10_A, STBCR10_D 43 44 /* SCIF7 and IIC2 */ 45 write16 PJCR3_A, PJCR3_D /* TXD7 */ 46 write16 PECR1_A, PECR1_D /* RXD7, SDA2, SCL2 */ 47 48 /* Configure bus (CS0) */ 49 write16 PFCR3_A, PFCR3_D /* A24 */ 50 write16 PFCR2_A, PFCR2_D /* A23 and CS1# */ 51 write16 PBCR5_A, PBCR5_D /* A22, A21, A20 */ 52 write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */ 53 write32 CS0WCR_A, CS0WCR_D 54 write32 CS0BCR_A, CS0BCR_D 55 56 /* Configure SDRAM (CS3) */ 57 write16 PCCR2_A, PCCR2_D /* CS3# */ 58 write16 PCCR1_A, PCCR1_D /* CKE, CAS#, RAS#, DQMLU# */ 59 write16 PCCR0_A, PCCR0_D /* DQMLL#, RD/WR# */ 60 write32 CS3BCR_A, CS3BCR_D 61 write32 CS3WCR_A, CS3WCR_D 62 write32 SDCR_A, SDCR_D 63 write32 RTCOR_A, RTCOR_D 64 write32 RTCSR_A, RTCSR_D 65 66 /* Configure ethernet (CS1) */ 67 write16 PHCR1_A, PHCR1_D /* PINT5 on PH5 */ 68 write16 PHCR0_A, PHCR0_D 69 write16 PFCR2_A, PFCR2_D /* CS1# */ 70 write32 CS1BCR_A, CS1BCR_D /* Big endian */ 71 write32 CS1WCR_A, CS1WCR_D /* 1 cycle */ 72 write16 PJDR1_A, PJDR1_D /* FIFO-SEL = 1 */ 73 write16 PJIOR1_A, PJIOR1_D 74 75 /* wait 200us */ 76 mov.l REPEAT_D, r3 77 mov #0, r2 78 repeat0: 79 add #1, r2 80 cmp/hs r3, r2 81 bf repeat0 82 nop 83 84 mov.l SDRAM_MODE, r1 85 mov #0, r0 86 mov.l r0, @r1 87 88 nop 89 rts 90 91 .align 4 92 93 CCR1_A: .long CCR1 94 CCR1_D: .long 0x0000090B 95 96 STBCR3_A: .long 0xFFFE0408 97 STBCR4_A: .long 0xFFFE040C 98 STBCR5_A: .long 0xFFFE0410 99 STBCR6_A: .long 0xFFFE0414 100 STBCR7_A: .long 0xFFFE0418 101 STBCR8_A: .long 0xFFFE041C 102 STBCR9_A: .long 0xFFFE0440 103 STBCR10_A: .long 0xFFFE0444 104 STBCR3_D: .long 0x0000001A 105 STBCR4_D: .long 0x00000000 106 STBCR5_D: .long 0x00000000 107 STBCR6_D: .long 0x00000000 108 STBCR7_D: .long 0x00000012 109 STBCR8_D: .long 0x00000009 110 STBCR9_D: .long 0x00000000 111 STBCR10_D: .long 0x00000010 112 113 WTCSR_A: .long 0xFFFE0000 114 WTCNT_A: .long 0xFFFE0002 115 WTCSR_D: .word 0xA518 116 WTCNT_D: .word 0x5A00 117 118 IBNR_A: .long 0xFFFE080E 119 IBNR_D: .word 0x0000 120 .align 2 121 FRQCR_A: .long 0xFFFE0010 122 FRQCR_D: .word 0x0015 123 .align 2 124 125 PJCR3_A: .long 0xFFFE3908 126 PJCR3_D: .word 0x5000 127 .align 2 128 PECR1_A: .long 0xFFFE388C 129 PECR1_D: .word 0x2011 130 .align 2 131 132 PFCR3_A: .long 0xFFFE38A8 133 PFCR2_A: .long 0xFFFE38AA 134 PBCR5_A: .long 0xFFFE3824 135 PFCR3_D: .word 0x0010 136 PFCR2_D: .word 0x0101 137 PBCR5_D: .word 0x0111 138 .align 2 139 CS0WCR_A: .long 0xFFFC0028 140 CS0WCR_D: .long 0x00000341 141 CS0BCR_A: .long 0xFFFC0004 142 CS0BCR_D: .long 0x00000400 143 144 PCCR2_A: .long 0xFFFE384A 145 PCCR1_A: .long 0xFFFE384C 146 PCCR0_A: .long 0xFFFE384E 147 PCCR2_D: .word 0x0001 148 PCCR1_D: .word 0x1111 149 PCCR0_D: .word 0x1111 150 .align 2 151 CS3BCR_A: .long 0xFFFC0010 152 CS3BCR_D: .long 0x00004400 153 CS3WCR_A: .long 0xFFFC0034 154 CS3WCR_D: .long 0x00004912 155 SDCR_A: .long 0xFFFC004C 156 SDCR_D: .long 0x00000811 157 RTCOR_A: .long 0xFFFC0058 158 RTCOR_D: .long 0xA55A0035 159 RTCSR_A: .long 0xFFFC0050 160 RTCSR_D: .long 0xA55A0010 161 .align 2 162 SDRAM_MODE: .long 0xFFFC5460 163 REPEAT_D: .long 0x000033F1 164 165 PHCR1_A: .long 0xFFFE38EC 166 PHCR0_A: .long 0xFFFE38EE 167 PHCR1_D: .word 0x2222 168 PHCR0_D: .word 0x2222 169 .align 2 170 CS1BCR_A: .long 0xFFFC0008 171 CS1BCR_D: .long 0x00000400 172 CS1WCR_A: .long 0xFFFC002C 173 CS1WCR_D: .long 0x00000080 174 PJDR1_A: .long 0xFFFE3914 175 PJDR1_D: .word 0x0000 176 .align 2 177 PJIOR1_A: .long 0xFFFE3910 178 PJIOR1_D: .word 0x8000 179 .align 2 180