xref: /openbmc/u-boot/drivers/usb/musb-new/pic32.c (revision a376702f)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * Microchip PIC32 MUSB "glue layer"
4  *
5  * Copyright (C) 2015, Microchip Technology Inc.
6  *  Cristian Birsan <cristian.birsan@microchip.com>
7  *  Purna Chandra Mandal <purna.mandal@microchip.com>
8  *
9  * Based on the dsps "glue layer" code.
10  */
11 
12 #include <common.h>
13 #include <linux/usb/musb.h>
14 #include "linux-compat.h"
15 #include "musb_core.h"
16 #include "musb_uboot.h"
17 
18 DECLARE_GLOBAL_DATA_PTR;
19 
20 #define PIC32_TX_EP_MASK	0x0f		/* EP0 + 7 Tx EPs */
21 #define PIC32_RX_EP_MASK	0x0e		/* 7 Rx EPs */
22 
23 #define MUSB_SOFTRST		0x7f
24 #define  MUSB_SOFTRST_NRST	BIT(0)
25 #define  MUSB_SOFTRST_NRSTX	BIT(1)
26 
27 #define USBCRCON		0
28 #define  USBCRCON_USBWKUPEN	BIT(0)  /* Enable Wakeup Interrupt */
29 #define  USBCRCON_USBRIE	BIT(1)  /* Enable Remote resume Interrupt */
30 #define  USBCRCON_USBIE		BIT(2)  /* Enable USB General interrupt */
31 #define  USBCRCON_SENDMONEN	BIT(3)  /* Enable Session End VBUS monitoring */
32 #define  USBCRCON_BSVALMONEN	BIT(4)  /* Enable B-Device VBUS monitoring */
33 #define  USBCRCON_ASVALMONEN	BIT(5)  /* Enable A-Device VBUS monitoring */
34 #define  USBCRCON_VBUSMONEN	BIT(6)  /* Enable VBUS monitoring */
35 #define  USBCRCON_PHYIDEN	BIT(7)  /* PHY ID monitoring enable */
36 #define  USBCRCON_USBIDVAL	BIT(8)  /* USB ID value */
37 #define  USBCRCON_USBIDOVEN	BIT(9)  /* USB ID override enable */
38 #define  USBCRCON_USBWK		BIT(24) /* USB Wakeup Status */
39 #define  USBCRCON_USBRF		BIT(25) /* USB Resume Status */
40 #define  USBCRCON_USBIF		BIT(26) /* USB General Interrupt Status */
41 
42 /* PIC32 controller data */
43 struct pic32_musb_data {
44 	struct musb_host_data mdata;
45 	struct device dev;
46 	void __iomem *musb_glue;
47 };
48 
49 #define to_pic32_musb_data(d)	\
50 	container_of(d, struct pic32_musb_data, dev)
51 
pic32_musb_disable(struct musb * musb)52 static void pic32_musb_disable(struct musb *musb)
53 {
54 	/* no way to shut the controller */
55 }
56 
pic32_musb_enable(struct musb * musb)57 static int pic32_musb_enable(struct musb *musb)
58 {
59 	/* soft reset by NRSTx */
60 	musb_writeb(musb->mregs, MUSB_SOFTRST, MUSB_SOFTRST_NRSTX);
61 	/* set mode */
62 	musb_platform_set_mode(musb, musb->board_mode);
63 
64 	return 0;
65 }
66 
pic32_interrupt(int irq,void * hci)67 static irqreturn_t pic32_interrupt(int irq, void *hci)
68 {
69 	struct musb  *musb = hci;
70 	irqreturn_t ret = IRQ_NONE;
71 	u32 epintr, usbintr;
72 
73 	/* ack usb core interrupts */
74 	musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
75 	if (musb->int_usb)
76 		musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
77 
78 	/* ack endpoint interrupts */
79 	musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX) & PIC32_RX_EP_MASK;
80 	if (musb->int_rx)
81 		musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
82 
83 	musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX) & PIC32_TX_EP_MASK;
84 	if (musb->int_tx)
85 		musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
86 
87 	/* drop spurious RX and TX if device is disconnected */
88 	if (musb->int_usb & MUSB_INTR_DISCONNECT) {
89 		musb->int_tx = 0;
90 		musb->int_rx = 0;
91 	}
92 
93 	if (musb->int_tx || musb->int_rx || musb->int_usb)
94 		ret = musb_interrupt(musb);
95 
96 	return ret;
97 }
98 
pic32_musb_set_mode(struct musb * musb,u8 mode)99 static int pic32_musb_set_mode(struct musb *musb, u8 mode)
100 {
101 	struct device *dev = musb->controller;
102 	struct pic32_musb_data *pdata = to_pic32_musb_data(dev);
103 
104 	switch (mode) {
105 	case MUSB_HOST:
106 		clrsetbits_le32(pdata->musb_glue + USBCRCON,
107 				USBCRCON_USBIDVAL, USBCRCON_USBIDOVEN);
108 		break;
109 	case MUSB_PERIPHERAL:
110 		setbits_le32(pdata->musb_glue + USBCRCON,
111 			     USBCRCON_USBIDVAL | USBCRCON_USBIDOVEN);
112 		break;
113 	case MUSB_OTG:
114 		dev_err(dev, "support for OTG is unimplemented\n");
115 		break;
116 	default:
117 		dev_err(dev, "unsupported mode %d\n", mode);
118 		return -EINVAL;
119 	}
120 
121 	return 0;
122 }
123 
pic32_musb_init(struct musb * musb)124 static int pic32_musb_init(struct musb *musb)
125 {
126 	struct pic32_musb_data *pdata = to_pic32_musb_data(musb->controller);
127 	u32 ctrl, hwvers;
128 	u8 power;
129 
130 	/* Returns zero if not clocked */
131 	hwvers = musb_read_hwvers(musb->mregs);
132 	if (!hwvers)
133 		return -ENODEV;
134 
135 	/* Reset the musb */
136 	power = musb_readb(musb->mregs, MUSB_POWER);
137 	power = power | MUSB_POWER_RESET;
138 	musb_writeb(musb->mregs, MUSB_POWER, power);
139 	mdelay(100);
140 
141 	/* Start the on-chip PHY and its PLL. */
142 	power = power & ~MUSB_POWER_RESET;
143 	musb_writeb(musb->mregs, MUSB_POWER, power);
144 
145 	musb->isr = pic32_interrupt;
146 
147 	ctrl =  USBCRCON_USBIF | USBCRCON_USBRF |
148 		USBCRCON_USBWK | USBCRCON_USBIDOVEN |
149 		USBCRCON_PHYIDEN | USBCRCON_USBIE |
150 		USBCRCON_USBRIE | USBCRCON_USBWKUPEN |
151 		USBCRCON_VBUSMONEN;
152 	writel(ctrl, pdata->musb_glue + USBCRCON);
153 
154 	return 0;
155 }
156 
157 /* PIC32 supports only 32bit read operation */
musb_read_fifo(struct musb_hw_ep * hw_ep,u16 len,u8 * dst)158 void musb_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
159 {
160 	void __iomem *fifo = hw_ep->fifo;
161 	u32 val, rem = len % 4;
162 
163 	/* USB stack ensures dst is always 32bit aligned. */
164 	readsl(fifo, dst, len / 4);
165 	if (rem) {
166 		dst += len & ~0x03;
167 		val = musb_readl(fifo, 0);
168 		memcpy(dst, &val, rem);
169 	}
170 }
171 
172 const struct musb_platform_ops pic32_musb_ops = {
173 	.init		= pic32_musb_init,
174 	.set_mode	= pic32_musb_set_mode,
175 	.disable	= pic32_musb_disable,
176 	.enable		= pic32_musb_enable,
177 };
178 
179 /* PIC32 default FIFO config - fits in 8KB */
180 static struct musb_fifo_cfg pic32_musb_fifo_config[] = {
181 	{ .hw_ep_num = 1, .style = FIFO_TX, .maxpacket = 512, },
182 	{ .hw_ep_num = 1, .style = FIFO_RX, .maxpacket = 512, },
183 	{ .hw_ep_num = 2, .style = FIFO_TX, .maxpacket = 512, },
184 	{ .hw_ep_num = 2, .style = FIFO_RX, .maxpacket = 512, },
185 	{ .hw_ep_num = 3, .style = FIFO_TX, .maxpacket = 512, },
186 	{ .hw_ep_num = 3, .style = FIFO_RX, .maxpacket = 512, },
187 	{ .hw_ep_num = 4, .style = FIFO_TX, .maxpacket = 512, },
188 	{ .hw_ep_num = 4, .style = FIFO_RX, .maxpacket = 512, },
189 	{ .hw_ep_num = 5, .style = FIFO_TX, .maxpacket = 512, },
190 	{ .hw_ep_num = 5, .style = FIFO_RX, .maxpacket = 512, },
191 	{ .hw_ep_num = 6, .style = FIFO_TX, .maxpacket = 512, },
192 	{ .hw_ep_num = 6, .style = FIFO_RX, .maxpacket = 512, },
193 	{ .hw_ep_num = 7, .style = FIFO_TX, .maxpacket = 512, },
194 	{ .hw_ep_num = 7, .style = FIFO_RX, .maxpacket = 512, },
195 };
196 
197 static struct musb_hdrc_config pic32_musb_config = {
198 	.fifo_cfg	= pic32_musb_fifo_config,
199 	.fifo_cfg_size	= ARRAY_SIZE(pic32_musb_fifo_config),
200 	.multipoint     = 1,
201 	.dyn_fifo       = 1,
202 	.num_eps        = 8,
203 	.ram_bits       = 11,
204 };
205 
206 /* PIC32 has one MUSB controller which can be host or gadget */
207 static struct musb_hdrc_platform_data pic32_musb_plat = {
208 	.mode           = MUSB_HOST,
209 	.config         = &pic32_musb_config,
210 	.power          = 250,		/* 500mA */
211 	.platform_ops	= &pic32_musb_ops,
212 };
213 
musb_usb_probe(struct udevice * dev)214 static int musb_usb_probe(struct udevice *dev)
215 {
216 	struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
217 	struct pic32_musb_data *pdata = dev_get_priv(dev);
218 	struct musb_host_data *mdata = &pdata->mdata;
219 	struct fdt_resource mc, glue;
220 	void *fdt = (void *)gd->fdt_blob;
221 	int node = dev_of_offset(dev);
222 	void __iomem *mregs;
223 	int ret;
224 
225 	priv->desc_before_addr = true;
226 
227 	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
228 				     "mc", &mc);
229 	if (ret < 0) {
230 		printf("pic32-musb: resource \"mc\" not found\n");
231 		return ret;
232 	}
233 
234 	ret = fdt_get_named_resource(fdt, node, "reg", "reg-names",
235 				     "control", &glue);
236 	if (ret < 0) {
237 		printf("pic32-musb: resource \"control\" not found\n");
238 		return ret;
239 	}
240 
241 	mregs = ioremap(mc.start, fdt_resource_size(&mc));
242 	pdata->musb_glue = ioremap(glue.start, fdt_resource_size(&glue));
243 
244 	/* init controller */
245 #ifdef CONFIG_USB_MUSB_HOST
246 	mdata->host = musb_init_controller(&pic32_musb_plat,
247 					   &pdata->dev, mregs);
248 	if (!mdata->host)
249 		return -EIO;
250 
251 	ret = musb_lowlevel_init(mdata);
252 #else
253 	pic32_musb_plat.mode = MUSB_PERIPHERAL;
254 	mdata->host = musb_register(&pic32_musb_plat, &pdata->dev, mregs);
255 	if (!mdata->host)
256 		return -EIO;
257 #endif
258 	if ((ret == 0) && mdata->host)
259 		printf("PIC32 MUSB OTG\n");
260 
261 	return ret;
262 }
263 
musb_usb_remove(struct udevice * dev)264 static int musb_usb_remove(struct udevice *dev)
265 {
266 	struct pic32_musb_data *pdata = dev_get_priv(dev);
267 
268 	musb_stop(pdata->mdata.host);
269 
270 	return 0;
271 }
272 
273 static const struct udevice_id pic32_musb_ids[] = {
274 	{ .compatible = "microchip,pic32mzda-usb" },
275 	{ }
276 };
277 
278 U_BOOT_DRIVER(usb_musb) = {
279 	.name		= "pic32-musb",
280 	.id		= UCLASS_USB,
281 	.of_match	= pic32_musb_ids,
282 	.probe		= musb_usb_probe,
283 	.remove		= musb_usb_remove,
284 #ifdef CONFIG_USB_MUSB_HOST
285 	.ops		= &musb_usb_ops,
286 #endif
287 	.platdata_auto_alloc_size = sizeof(struct usb_platdata),
288 	.priv_auto_alloc_size = sizeof(struct pic32_musb_data),
289 };
290