1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Copyright 2014 Bart Tanghe <bart.tanghe@thomasmore.be>
4 */
5
6 #include <linux/clk.h>
7 #include <linux/err.h>
8 #include <linux/io.h>
9 #include <linux/module.h>
10 #include <linux/of.h>
11 #include <linux/platform_device.h>
12 #include <linux/pwm.h>
13
14 #define PWM_CONTROL 0x000
15 #define PWM_CONTROL_SHIFT(x) ((x) * 8)
16 #define PWM_CONTROL_MASK 0xff
17 #define PWM_MODE 0x80 /* set timer in PWM mode */
18 #define PWM_ENABLE (1 << 0)
19 #define PWM_POLARITY (1 << 4)
20
21 #define PERIOD(x) (((x) * 0x10) + 0x10)
22 #define DUTY(x) (((x) * 0x10) + 0x14)
23
24 #define PERIOD_MIN 0x2
25
26 struct bcm2835_pwm {
27 struct pwm_chip chip;
28 struct device *dev;
29 void __iomem *base;
30 struct clk *clk;
31 };
32
to_bcm2835_pwm(struct pwm_chip * chip)33 static inline struct bcm2835_pwm *to_bcm2835_pwm(struct pwm_chip *chip)
34 {
35 return container_of(chip, struct bcm2835_pwm, chip);
36 }
37
bcm2835_pwm_request(struct pwm_chip * chip,struct pwm_device * pwm)38 static int bcm2835_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
39 {
40 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
41 u32 value;
42
43 value = readl(pc->base + PWM_CONTROL);
44 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
45 value |= (PWM_MODE << PWM_CONTROL_SHIFT(pwm->hwpwm));
46 writel(value, pc->base + PWM_CONTROL);
47
48 return 0;
49 }
50
bcm2835_pwm_free(struct pwm_chip * chip,struct pwm_device * pwm)51 static void bcm2835_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
52 {
53 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
54 u32 value;
55
56 value = readl(pc->base + PWM_CONTROL);
57 value &= ~(PWM_CONTROL_MASK << PWM_CONTROL_SHIFT(pwm->hwpwm));
58 writel(value, pc->base + PWM_CONTROL);
59 }
60
bcm2835_pwm_apply(struct pwm_chip * chip,struct pwm_device * pwm,const struct pwm_state * state)61 static int bcm2835_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
62 const struct pwm_state *state)
63 {
64
65 struct bcm2835_pwm *pc = to_bcm2835_pwm(chip);
66 unsigned long rate = clk_get_rate(pc->clk);
67 unsigned long long period_cycles;
68 u64 max_period;
69
70 u32 val;
71
72 if (!rate) {
73 dev_err(pc->dev, "failed to get clock rate\n");
74 return -EINVAL;
75 }
76
77 /*
78 * period_cycles must be a 32 bit value, so period * rate / NSEC_PER_SEC
79 * must be <= U32_MAX. As U32_MAX * NSEC_PER_SEC < U64_MAX the
80 * multiplication period * rate doesn't overflow.
81 * To calculate the maximal possible period that guarantees the
82 * above inequality:
83 *
84 * round(period * rate / NSEC_PER_SEC) <= U32_MAX
85 * <=> period * rate / NSEC_PER_SEC < U32_MAX + 0.5
86 * <=> period * rate < (U32_MAX + 0.5) * NSEC_PER_SEC
87 * <=> period < ((U32_MAX + 0.5) * NSEC_PER_SEC) / rate
88 * <=> period < ((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate
89 * <=> period <= ceil((U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC/2) / rate) - 1
90 */
91 max_period = DIV_ROUND_UP_ULL((u64)U32_MAX * NSEC_PER_SEC + NSEC_PER_SEC / 2, rate) - 1;
92
93 if (state->period > max_period)
94 return -EINVAL;
95
96 /* set period */
97 period_cycles = DIV_ROUND_CLOSEST_ULL(state->period * rate, NSEC_PER_SEC);
98
99 /* don't accept a period that is too small */
100 if (period_cycles < PERIOD_MIN)
101 return -EINVAL;
102
103 writel(period_cycles, pc->base + PERIOD(pwm->hwpwm));
104
105 /* set duty cycle */
106 val = DIV_ROUND_CLOSEST_ULL(state->duty_cycle * rate, NSEC_PER_SEC);
107 writel(val, pc->base + DUTY(pwm->hwpwm));
108
109 /* set polarity */
110 val = readl(pc->base + PWM_CONTROL);
111
112 if (state->polarity == PWM_POLARITY_NORMAL)
113 val &= ~(PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm));
114 else
115 val |= PWM_POLARITY << PWM_CONTROL_SHIFT(pwm->hwpwm);
116
117 /* enable/disable */
118 if (state->enabled)
119 val |= PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm);
120 else
121 val &= ~(PWM_ENABLE << PWM_CONTROL_SHIFT(pwm->hwpwm));
122
123 writel(val, pc->base + PWM_CONTROL);
124
125 return 0;
126 }
127
128 static const struct pwm_ops bcm2835_pwm_ops = {
129 .request = bcm2835_pwm_request,
130 .free = bcm2835_pwm_free,
131 .apply = bcm2835_pwm_apply,
132 .owner = THIS_MODULE,
133 };
134
bcm2835_pwm_probe(struct platform_device * pdev)135 static int bcm2835_pwm_probe(struct platform_device *pdev)
136 {
137 struct bcm2835_pwm *pc;
138 int ret;
139
140 pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
141 if (!pc)
142 return -ENOMEM;
143
144 pc->dev = &pdev->dev;
145
146 pc->base = devm_platform_ioremap_resource(pdev, 0);
147 if (IS_ERR(pc->base))
148 return PTR_ERR(pc->base);
149
150 pc->clk = devm_clk_get(&pdev->dev, NULL);
151 if (IS_ERR(pc->clk))
152 return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
153 "clock not found\n");
154
155 ret = clk_prepare_enable(pc->clk);
156 if (ret)
157 return ret;
158
159 pc->chip.dev = &pdev->dev;
160 pc->chip.ops = &bcm2835_pwm_ops;
161 pc->chip.npwm = 2;
162
163 platform_set_drvdata(pdev, pc);
164
165 ret = pwmchip_add(&pc->chip);
166 if (ret < 0)
167 goto add_fail;
168
169 return 0;
170
171 add_fail:
172 clk_disable_unprepare(pc->clk);
173 return ret;
174 }
175
bcm2835_pwm_remove(struct platform_device * pdev)176 static void bcm2835_pwm_remove(struct platform_device *pdev)
177 {
178 struct bcm2835_pwm *pc = platform_get_drvdata(pdev);
179
180 pwmchip_remove(&pc->chip);
181
182 clk_disable_unprepare(pc->clk);
183 }
184
185 static const struct of_device_id bcm2835_pwm_of_match[] = {
186 { .compatible = "brcm,bcm2835-pwm", },
187 { /* sentinel */ }
188 };
189 MODULE_DEVICE_TABLE(of, bcm2835_pwm_of_match);
190
191 static struct platform_driver bcm2835_pwm_driver = {
192 .driver = {
193 .name = "bcm2835-pwm",
194 .of_match_table = bcm2835_pwm_of_match,
195 },
196 .probe = bcm2835_pwm_probe,
197 .remove_new = bcm2835_pwm_remove,
198 };
199 module_platform_driver(bcm2835_pwm_driver);
200
201 MODULE_AUTHOR("Bart Tanghe <bart.tanghe@thomasmore.be>");
202 MODULE_DESCRIPTION("Broadcom BCM2835 PWM driver");
203 MODULE_LICENSE("GPL v2");
204