1 /* SPDX-License-Identifier: GPL-2.0 2 * 3 * Copyright 2016-2020 HabanaLabs, Ltd. 4 * All Rights Reserved. 5 * 6 */ 7 8 /************************************ 9 ** This is an auto-generated file ** 10 ** DO NOT EDIT BELOW ** 11 ************************************/ 12 13 #ifndef ASIC_REG_PDMA0_CORE_SPECIAL_MASKS_H_ 14 #define ASIC_REG_PDMA0_CORE_SPECIAL_MASKS_H_ 15 16 /* 17 ***************************************** 18 * PDMA0_CORE_SPECIAL 19 * (Prototype: SPECIAL_REGS) 20 ***************************************** 21 */ 22 23 /* PDMA0_CORE_SPECIAL_GLBL_PRIV */ 24 #define PDMA0_CORE_SPECIAL_GLBL_PRIV_VAL_SHIFT 0 25 #define PDMA0_CORE_SPECIAL_GLBL_PRIV_VAL_MASK 0xFFFFFFFF 26 27 /* PDMA0_CORE_SPECIAL_MEM_GW_DATA */ 28 #define PDMA0_CORE_SPECIAL_MEM_GW_DATA_VAL_SHIFT 0 29 #define PDMA0_CORE_SPECIAL_MEM_GW_DATA_VAL_MASK 0xFFFFFFFF 30 31 /* PDMA0_CORE_SPECIAL_MEM_GW_REQ */ 32 #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_ADDR_SHIFT 0 33 #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_ADDR_MASK 0x3FFFFF 34 #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_MID_SHIFT 22 35 #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_MID_MASK 0x3FC00000 36 #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_WNR_SHIFT 30 37 #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_WNR_MASK 0x40000000 38 #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_VLD_SHIFT 31 39 #define PDMA0_CORE_SPECIAL_MEM_GW_REQ_VLD_MASK 0x80000000 40 41 /* PDMA0_CORE_SPECIAL_MEM_NUMOF */ 42 #define PDMA0_CORE_SPECIAL_MEM_NUMOF_VAL_SHIFT 0 43 #define PDMA0_CORE_SPECIAL_MEM_NUMOF_VAL_MASK 0xFF 44 45 /* PDMA0_CORE_SPECIAL_MEM_ECC_SEL */ 46 #define PDMA0_CORE_SPECIAL_MEM_ECC_SEL_VAL_SHIFT 0 47 #define PDMA0_CORE_SPECIAL_MEM_ECC_SEL_VAL_MASK 0xFF 48 49 /* PDMA0_CORE_SPECIAL_MEM_ECC_CTL */ 50 #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_INJ_SHIFT 0 51 #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_INJ_MASK 0x1 52 #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_INJ_SHIFT 1 53 #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_INJ_MASK 0x2 54 #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_CLR_SHIFT 2 55 #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_SERR_CLR_MASK 0x4 56 #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_CLR_SHIFT 3 57 #define PDMA0_CORE_SPECIAL_MEM_ECC_CTL_DERR_CLR_MASK 0x8 58 59 /* PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK */ 60 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_SERR_SHIFT 0 61 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_SERR_MASK 0x1 62 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_DERR_SHIFT 1 63 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_MASK_DERR_MASK 0x2 64 65 /* PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK */ 66 #define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_SERR_SHIFT 0 67 #define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_SERR_MASK 0x1 68 #define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_DERR_SHIFT 1 69 #define PDMA0_CORE_SPECIAL_MEM_ECC_GLBL_ERR_MASK_DERR_MASK 0x2 70 71 /* PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS */ 72 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SYND_SHIFT 0 73 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SYND_MASK 0xFFFF 74 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SERR_SHIFT 16 75 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_SERR_MASK 0x10000 76 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_DERR_SHIFT 17 77 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_STS_DERR_MASK 0x20000 78 79 /* PDMA0_CORE_SPECIAL_MEM_ECC_ERR_ADDR */ 80 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_ADDR_VAL_SHIFT 0 81 #define PDMA0_CORE_SPECIAL_MEM_ECC_ERR_ADDR_VAL_MASK 0xFFFF 82 83 /* PDMA0_CORE_SPECIAL_MEM_RM */ 84 #define PDMA0_CORE_SPECIAL_MEM_RM_VAL_SHIFT 0 85 #define PDMA0_CORE_SPECIAL_MEM_RM_VAL_MASK 0x3FFFFFFF 86 87 /* PDMA0_CORE_SPECIAL_GLBL_ERR_MASK */ 88 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_RD_SHIFT 0 89 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_RD_MASK 0x1 90 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_RD_SHIFT 1 91 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_RD_MASK 0x2 92 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_RD_SHIFT 2 93 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_RD_MASK 0x4 94 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_WR_SHIFT 3 95 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_PRIV_WR_MASK 0x8 96 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_WR_SHIFT 4 97 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_SEC_WR_MASK 0x10 98 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_WR_SHIFT 5 99 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_APB_UNMAPPED_WR_MASK 0x20 100 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_SEC_WR_SHIFT 16 101 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_SEC_WR_MASK 0x10000 102 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_UNMAPPED_WR_SHIFT 17 103 #define PDMA0_CORE_SPECIAL_GLBL_ERR_MASK_EXT_UNMAPPED_WR_MASK 0x20000 104 105 /* PDMA0_CORE_SPECIAL_GLBL_ERR_ADDR */ 106 #define PDMA0_CORE_SPECIAL_GLBL_ERR_ADDR_VAL_SHIFT 0 107 #define PDMA0_CORE_SPECIAL_GLBL_ERR_ADDR_VAL_MASK 0xFFFFFFFF 108 109 /* PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE */ 110 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_SHIFT 0 111 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_RD_MASK 0x1 112 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_SHIFT 1 113 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_RD_MASK 0x2 114 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_SHIFT 2 115 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_RD_MASK 0x4 116 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_SHIFT 3 117 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_PRIV_WR_MASK 0x8 118 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_SHIFT 4 119 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_SEC_WR_MASK 0x10 120 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_SHIFT 5 121 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_APB_UNMAPPED_WR_MASK 0x20 122 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_SHIFT 16 123 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_SEC_WR_MASK 0x10000 124 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_SHIFT 17 125 #define PDMA0_CORE_SPECIAL_GLBL_ERR_CAUSE_EXT_UNMAPPED_WR_MASK 0x20000 126 127 /* PDMA0_CORE_SPECIAL_GLBL_SPARE */ 128 #define PDMA0_CORE_SPECIAL_GLBL_SPARE_R_SHIFT 0 129 #define PDMA0_CORE_SPECIAL_GLBL_SPARE_R_MASK 0xFFFFFFFF 130 131 /* PDMA0_CORE_SPECIAL_GLBL_SEC */ 132 #define PDMA0_CORE_SPECIAL_GLBL_SEC_VAL_SHIFT 0 133 #define PDMA0_CORE_SPECIAL_GLBL_SEC_VAL_MASK 0xFFFFFFFF 134 135 #endif /* ASIC_REG_PDMA0_CORE_SPECIAL_MASKS_H_ */ 136