1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  *  Probe module for 8250/16550-type MCHP PCI serial ports.
4  *
5  *  Based on drivers/tty/serial/8250/8250_pci.c,
6  *
7  *  Copyright (C) 2022 Microchip Technology Inc., All Rights Reserved.
8  */
9 
10 #include <linux/bitfield.h>
11 #include <linux/bitops.h>
12 #include <linux/io.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/pci.h>
16 #include <linux/serial_core.h>
17 #include <linux/slab.h>
18 #include <linux/string.h>
19 #include <linux/units.h>
20 #include <linux/tty.h>
21 
22 #include <asm/byteorder.h>
23 
24 #include "8250.h"
25 #include "8250_pcilib.h"
26 
27 #define PCI_DEVICE_ID_EFAR_PCI12000		0xa002
28 #define PCI_DEVICE_ID_EFAR_PCI11010		0xa012
29 #define PCI_DEVICE_ID_EFAR_PCI11101		0xa022
30 #define PCI_DEVICE_ID_EFAR_PCI11400		0xa032
31 #define PCI_DEVICE_ID_EFAR_PCI11414		0xa042
32 
33 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p	0x0001
34 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012	0x0002
35 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013	0x0003
36 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023	0x0004
37 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123	0x0005
38 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01	0x0006
39 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02	0x0007
40 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03	0x0008
41 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12	0x0009
42 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13	0x000a
43 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23	0x000b
44 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0	0x000c
45 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1	0x000d
46 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2	0x000e
47 #define PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3	0x000f
48 
49 #define PCI_SUBDEVICE_ID_EFAR_PCI12000		PCI_DEVICE_ID_EFAR_PCI12000
50 #define PCI_SUBDEVICE_ID_EFAR_PCI11010		PCI_DEVICE_ID_EFAR_PCI11010
51 #define PCI_SUBDEVICE_ID_EFAR_PCI11101		PCI_DEVICE_ID_EFAR_PCI11101
52 #define PCI_SUBDEVICE_ID_EFAR_PCI11400		PCI_DEVICE_ID_EFAR_PCI11400
53 #define PCI_SUBDEVICE_ID_EFAR_PCI11414		PCI_DEVICE_ID_EFAR_PCI11414
54 
55 #define UART_ACTV_REG				0x11
56 #define UART_BLOCK_SET_ACTIVE			BIT(0)
57 
58 #define UART_PCI_CTRL_REG			0x80
59 #define UART_PCI_CTRL_SET_MULTIPLE_MSI		BIT(4)
60 #define UART_PCI_CTRL_D3_CLK_ENABLE		BIT(0)
61 
62 #define ADCL_CFG_REG				0x40
63 #define ADCL_CFG_POL_SEL			BIT(2)
64 #define ADCL_CFG_PIN_SEL			BIT(1)
65 #define ADCL_CFG_EN				BIT(0)
66 
67 #define UART_BIT_SAMPLE_CNT			16
68 #define BAUD_CLOCK_DIV_INT_MSK			GENMASK(31, 8)
69 #define ADCL_CFG_RTS_DELAY_MASK			GENMASK(11, 8)
70 #define UART_CLOCK_DEFAULT			(62500 * HZ_PER_KHZ)
71 
72 #define UART_WAKE_REG				0x8C
73 #define UART_WAKE_MASK_REG			0x90
74 #define UART_WAKE_N_PIN				BIT(2)
75 #define UART_WAKE_NCTS				BIT(1)
76 #define UART_WAKE_INT				BIT(0)
77 #define UART_WAKE_SRCS	\
78 	(UART_WAKE_N_PIN | UART_WAKE_NCTS | UART_WAKE_INT)
79 
80 #define UART_BAUD_CLK_DIVISOR_REG		0x54
81 
82 #define UART_RESET_REG				0x94
83 #define UART_RESET_D3_RESET_DISABLE		BIT(16)
84 
85 #define MAX_PORTS				4
86 #define PORT_OFFSET				0x100
87 
88 static const int logical_to_physical_port_idx[][MAX_PORTS] = {
89 	{0,  1,  2,  3}, /* PCI12000, PCI11010, PCI11101, PCI11400, PCI11414 */
90 	{0,  1,  2,  3}, /* PCI4p */
91 	{0,  1,  2, -1}, /* PCI3p012 */
92 	{0,  1,  3, -1}, /* PCI3p013 */
93 	{0,  2,  3, -1}, /* PCI3p023 */
94 	{1,  2,  3, -1}, /* PCI3p123 */
95 	{0,  1, -1, -1}, /* PCI2p01 */
96 	{0,  2, -1, -1}, /* PCI2p02 */
97 	{0,  3, -1, -1}, /* PCI2p03 */
98 	{1,  2, -1, -1}, /* PCI2p12 */
99 	{1,  3, -1, -1}, /* PCI2p13 */
100 	{2,  3, -1, -1}, /* PCI2p23 */
101 	{0, -1, -1, -1}, /* PCI1p0 */
102 	{1, -1, -1, -1}, /* PCI1p1 */
103 	{2, -1, -1, -1}, /* PCI1p2 */
104 	{3, -1, -1, -1}, /* PCI1p3 */
105 };
106 
107 struct pci1xxxx_8250 {
108 	unsigned int nr;
109 	void __iomem *membase;
110 	int line[];
111 };
112 
pci1xxxx_get_num_ports(struct pci_dev * dev)113 static int pci1xxxx_get_num_ports(struct pci_dev *dev)
114 {
115 	switch (dev->subsystem_device) {
116 	case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p0:
117 	case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p1:
118 	case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p2:
119 	case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3:
120 	case PCI_SUBDEVICE_ID_EFAR_PCI12000:
121 	case PCI_SUBDEVICE_ID_EFAR_PCI11010:
122 	case PCI_SUBDEVICE_ID_EFAR_PCI11101:
123 	case PCI_SUBDEVICE_ID_EFAR_PCI11400:
124 	default:
125 		return 1;
126 	case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p01:
127 	case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p02:
128 	case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p03:
129 	case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p12:
130 	case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p13:
131 	case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_2p23:
132 		return 2;
133 	case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p012:
134 	case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p123:
135 	case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p013:
136 	case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_3p023:
137 		return 3;
138 	case PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_4p:
139 	case PCI_SUBDEVICE_ID_EFAR_PCI11414:
140 		return 4;
141 	}
142 }
143 
pci1xxxx_get_divisor(struct uart_port * port,unsigned int baud,unsigned int * frac)144 static unsigned int pci1xxxx_get_divisor(struct uart_port *port,
145 					 unsigned int baud, unsigned int *frac)
146 {
147 	unsigned int quot;
148 
149 	/*
150 	 * Calculate baud rate sampling period in nanoseconds.
151 	 * Fractional part x denotes x/255 parts of a nanosecond.
152 	 */
153 	quot = NSEC_PER_SEC / (baud * UART_BIT_SAMPLE_CNT);
154 	*frac = (NSEC_PER_SEC - quot * baud * UART_BIT_SAMPLE_CNT) *
155 		  255 / UART_BIT_SAMPLE_CNT / baud;
156 
157 	return quot;
158 }
159 
pci1xxxx_set_divisor(struct uart_port * port,unsigned int baud,unsigned int quot,unsigned int frac)160 static void pci1xxxx_set_divisor(struct uart_port *port, unsigned int baud,
161 				 unsigned int quot, unsigned int frac)
162 {
163 	writel(FIELD_PREP(BAUD_CLOCK_DIV_INT_MSK, quot) | frac,
164 	       port->membase + UART_BAUD_CLK_DIVISOR_REG);
165 }
166 
pci1xxxx_rs485_config(struct uart_port * port,struct ktermios * termios,struct serial_rs485 * rs485)167 static int pci1xxxx_rs485_config(struct uart_port *port,
168 				 struct ktermios *termios,
169 				 struct serial_rs485 *rs485)
170 {
171 	u32 delay_in_baud_periods;
172 	u32 baud_period_in_ns;
173 	u32 mode_cfg = 0;
174 	u32 clock_div;
175 
176 	/*
177 	 * pci1xxxx's uart hardware supports only RTS delay after
178 	 * Tx and in units of bit times to a maximum of 15
179 	 */
180 	if (rs485->flags & SER_RS485_ENABLED) {
181 		mode_cfg = ADCL_CFG_EN | ADCL_CFG_PIN_SEL;
182 
183 		if (!(rs485->flags & SER_RS485_RTS_ON_SEND))
184 			mode_cfg |= ADCL_CFG_POL_SEL;
185 
186 		if (rs485->delay_rts_after_send) {
187 			clock_div = readl(port->membase + UART_BAUD_CLK_DIVISOR_REG);
188 			baud_period_in_ns =
189 				FIELD_GET(BAUD_CLOCK_DIV_INT_MSK, clock_div) *
190 				UART_BIT_SAMPLE_CNT;
191 			delay_in_baud_periods =
192 				rs485->delay_rts_after_send * NSEC_PER_MSEC /
193 				baud_period_in_ns;
194 			delay_in_baud_periods =
195 				min_t(u32, delay_in_baud_periods,
196 				      FIELD_MAX(ADCL_CFG_RTS_DELAY_MASK));
197 			mode_cfg |= FIELD_PREP(ADCL_CFG_RTS_DELAY_MASK,
198 					   delay_in_baud_periods);
199 			rs485->delay_rts_after_send =
200 				baud_period_in_ns * delay_in_baud_periods /
201 				NSEC_PER_MSEC;
202 		}
203 	}
204 	writel(mode_cfg, port->membase + ADCL_CFG_REG);
205 	return 0;
206 }
207 
208 static const struct serial_rs485 pci1xxxx_rs485_supported = {
209 	.flags = SER_RS485_ENABLED | SER_RS485_RTS_ON_SEND |
210 		 SER_RS485_RTS_AFTER_SEND,
211 	.delay_rts_after_send = 1,
212 	/* Delay RTS before send is not supported */
213 };
214 
pci1xxxx_port_suspend(int line)215 static bool pci1xxxx_port_suspend(int line)
216 {
217 	struct uart_8250_port *up = serial8250_get_port(line);
218 	struct uart_port *port = &up->port;
219 	struct tty_port *tport = &port->state->port;
220 	unsigned long flags;
221 	bool ret = false;
222 	u8 wakeup_mask;
223 
224 	mutex_lock(&tport->mutex);
225 	if (port->suspended == 0 && port->dev) {
226 		wakeup_mask = readb(up->port.membase + UART_WAKE_MASK_REG);
227 
228 		spin_lock_irqsave(&port->lock, flags);
229 		port->mctrl &= ~TIOCM_OUT2;
230 		port->ops->set_mctrl(port, port->mctrl);
231 		spin_unlock_irqrestore(&port->lock, flags);
232 
233 		ret = (wakeup_mask & UART_WAKE_SRCS) != UART_WAKE_SRCS;
234 	}
235 
236 	writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG);
237 	mutex_unlock(&tport->mutex);
238 
239 	return ret;
240 }
241 
pci1xxxx_port_resume(int line)242 static void pci1xxxx_port_resume(int line)
243 {
244 	struct uart_8250_port *up = serial8250_get_port(line);
245 	struct uart_port *port = &up->port;
246 	struct tty_port *tport = &port->state->port;
247 	unsigned long flags;
248 
249 	mutex_lock(&tport->mutex);
250 	writeb(UART_BLOCK_SET_ACTIVE, port->membase + UART_ACTV_REG);
251 	writeb(UART_WAKE_SRCS, port->membase + UART_WAKE_REG);
252 
253 	if (port->suspended == 0) {
254 		spin_lock_irqsave(&port->lock, flags);
255 		port->mctrl |= TIOCM_OUT2;
256 		port->ops->set_mctrl(port, port->mctrl);
257 		spin_unlock_irqrestore(&port->lock, flags);
258 	}
259 	mutex_unlock(&tport->mutex);
260 }
261 
pci1xxxx_suspend(struct device * dev)262 static int pci1xxxx_suspend(struct device *dev)
263 {
264 	struct pci1xxxx_8250 *priv = dev_get_drvdata(dev);
265 	struct pci_dev *pcidev = to_pci_dev(dev);
266 	bool wakeup = false;
267 	unsigned int data;
268 	void __iomem *p;
269 	int i;
270 
271 	for (i = 0; i < priv->nr; i++) {
272 		if (priv->line[i] >= 0) {
273 			serial8250_suspend_port(priv->line[i]);
274 			wakeup |= pci1xxxx_port_suspend(priv->line[i]);
275 		}
276 	}
277 
278 	p = pci_ioremap_bar(pcidev, 0);
279 	if (!p) {
280 		dev_err(dev, "remapping of bar 0 memory failed");
281 		return -ENOMEM;
282 	}
283 
284 	data = readl(p + UART_RESET_REG);
285 	writel(data | UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG);
286 
287 	if (wakeup)
288 		writeb(UART_PCI_CTRL_D3_CLK_ENABLE, p + UART_PCI_CTRL_REG);
289 
290 	iounmap(p);
291 	device_set_wakeup_enable(dev, true);
292 	pci_wake_from_d3(pcidev, true);
293 
294 	return 0;
295 }
296 
pci1xxxx_resume(struct device * dev)297 static int pci1xxxx_resume(struct device *dev)
298 {
299 	struct pci1xxxx_8250 *priv = dev_get_drvdata(dev);
300 	struct pci_dev *pcidev = to_pci_dev(dev);
301 	unsigned int data;
302 	void __iomem *p;
303 	int i;
304 
305 	p = pci_ioremap_bar(pcidev, 0);
306 	if (!p) {
307 		dev_err(dev, "remapping of bar 0 memory failed");
308 		return -ENOMEM;
309 	}
310 
311 	data = readl(p + UART_RESET_REG);
312 	writel(data & ~UART_RESET_D3_RESET_DISABLE, p + UART_RESET_REG);
313 	iounmap(p);
314 
315 	for (i = 0; i < priv->nr; i++) {
316 		if (priv->line[i] >= 0) {
317 			pci1xxxx_port_resume(priv->line[i]);
318 			serial8250_resume_port(priv->line[i]);
319 		}
320 	}
321 
322 	return 0;
323 }
324 
pci1xxxx_setup(struct pci_dev * pdev,struct uart_8250_port * port,int port_idx)325 static int pci1xxxx_setup(struct pci_dev *pdev,
326 			  struct uart_8250_port *port, int port_idx)
327 {
328 	int ret;
329 
330 	port->port.flags |= UPF_FIXED_TYPE | UPF_SKIP_TEST;
331 	port->port.type = PORT_MCHP16550A;
332 	port->port.set_termios = serial8250_do_set_termios;
333 	port->port.get_divisor = pci1xxxx_get_divisor;
334 	port->port.set_divisor = pci1xxxx_set_divisor;
335 	port->port.rs485_config = pci1xxxx_rs485_config;
336 	port->port.rs485_supported = pci1xxxx_rs485_supported;
337 
338 	ret = serial8250_pci_setup_port(pdev, port, 0, PORT_OFFSET * port_idx, 0);
339 	if (ret < 0)
340 		return ret;
341 
342 	writeb(UART_BLOCK_SET_ACTIVE, port->port.membase + UART_ACTV_REG);
343 	writeb(UART_WAKE_SRCS, port->port.membase + UART_WAKE_REG);
344 	writeb(UART_WAKE_N_PIN, port->port.membase + UART_WAKE_MASK_REG);
345 
346 	return 0;
347 }
348 
pci1xxxx_get_max_port(int subsys_dev)349 static unsigned int pci1xxxx_get_max_port(int subsys_dev)
350 {
351 	unsigned int i = MAX_PORTS;
352 
353 	if (subsys_dev < ARRAY_SIZE(logical_to_physical_port_idx))
354 		while (i--) {
355 			if (logical_to_physical_port_idx[subsys_dev][i] != -1)
356 				return logical_to_physical_port_idx[subsys_dev][i] + 1;
357 		}
358 
359 	if (subsys_dev == PCI_SUBDEVICE_ID_EFAR_PCI11414)
360 		return 4;
361 
362 	return 1;
363 }
364 
pci1xxxx_logical_to_physical_port_translate(int subsys_dev,int port)365 static int pci1xxxx_logical_to_physical_port_translate(int subsys_dev, int port)
366 {
367 	if (subsys_dev < ARRAY_SIZE(logical_to_physical_port_idx))
368 		return logical_to_physical_port_idx[subsys_dev][port];
369 
370 	return logical_to_physical_port_idx[0][port];
371 }
372 
pci1xxxx_serial_probe(struct pci_dev * pdev,const struct pci_device_id * id)373 static int pci1xxxx_serial_probe(struct pci_dev *pdev,
374 				 const struct pci_device_id *id)
375 {
376 	struct device *dev = &pdev->dev;
377 	struct pci1xxxx_8250 *priv;
378 	struct uart_8250_port uart;
379 	unsigned int max_vec_reqd;
380 	unsigned int nr_ports, i;
381 	int num_vectors;
382 	int subsys_dev;
383 	int port_idx;
384 	int rc;
385 
386 	rc = pcim_enable_device(pdev);
387 	if (rc)
388 		return rc;
389 
390 	nr_ports = pci1xxxx_get_num_ports(pdev);
391 
392 	priv = devm_kzalloc(dev, struct_size(priv, line, nr_ports), GFP_KERNEL);
393 	if (!priv)
394 		return -ENOMEM;
395 
396 	priv->membase = pci_ioremap_bar(pdev, 0);
397 	if (!priv->membase)
398 		return -ENOMEM;
399 
400 	pci_set_master(pdev);
401 
402 	priv->nr = nr_ports;
403 
404 	subsys_dev = pdev->subsystem_device;
405 	max_vec_reqd = pci1xxxx_get_max_port(subsys_dev);
406 
407 	num_vectors = pci_alloc_irq_vectors(pdev, 1, max_vec_reqd, PCI_IRQ_ALL_TYPES);
408 	if (num_vectors < 0) {
409 		pci_iounmap(pdev, priv->membase);
410 		return num_vectors;
411 	}
412 
413 	memset(&uart, 0, sizeof(uart));
414 	uart.port.flags = UPF_SHARE_IRQ | UPF_FIXED_PORT;
415 	uart.port.uartclk = UART_CLOCK_DEFAULT;
416 	uart.port.dev = dev;
417 
418 	if (num_vectors == max_vec_reqd)
419 		writeb(UART_PCI_CTRL_SET_MULTIPLE_MSI, priv->membase + UART_PCI_CTRL_REG);
420 
421 	for (i = 0; i < nr_ports; i++) {
422 		priv->line[i] = -ENODEV;
423 
424 		port_idx = pci1xxxx_logical_to_physical_port_translate(subsys_dev, i);
425 
426 		if (num_vectors == max_vec_reqd)
427 			uart.port.irq = pci_irq_vector(pdev, port_idx);
428 		else
429 			uart.port.irq = pci_irq_vector(pdev, 0);
430 
431 		rc = pci1xxxx_setup(pdev, &uart, port_idx);
432 		if (rc) {
433 			dev_warn(dev, "Failed to setup port %u\n", i);
434 			continue;
435 		}
436 
437 		priv->line[i] = serial8250_register_8250_port(&uart);
438 		if (priv->line[i] < 0) {
439 			dev_warn(dev,
440 				"Couldn't register serial port %lx, irq %d, type %d, error %d\n",
441 				uart.port.iobase, uart.port.irq, uart.port.iotype,
442 				priv->line[i]);
443 		}
444 	}
445 
446 	pci_set_drvdata(pdev, priv);
447 
448 	return 0;
449 }
450 
pci1xxxx_serial_remove(struct pci_dev * dev)451 static void pci1xxxx_serial_remove(struct pci_dev *dev)
452 {
453 	struct pci1xxxx_8250 *priv = pci_get_drvdata(dev);
454 	unsigned int i;
455 
456 	for (i = 0; i < priv->nr; i++) {
457 		if (priv->line[i] >= 0)
458 			serial8250_unregister_port(priv->line[i]);
459 	}
460 
461 	pci_free_irq_vectors(dev);
462 	pci_iounmap(dev, priv->membase);
463 }
464 
465 static DEFINE_SIMPLE_DEV_PM_OPS(pci1xxxx_pm_ops, pci1xxxx_suspend, pci1xxxx_resume);
466 
467 static const struct pci_device_id pci1xxxx_pci_tbl[] = {
468 	{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11010) },
469 	{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11101) },
470 	{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11400) },
471 	{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI11414) },
472 	{ PCI_VDEVICE(EFAR, PCI_DEVICE_ID_EFAR_PCI12000) },
473 	{}
474 };
475 MODULE_DEVICE_TABLE(pci, pci1xxxx_pci_tbl);
476 
477 static struct pci_driver pci1xxxx_pci_driver = {
478 	.name = "pci1xxxx serial",
479 	.probe = pci1xxxx_serial_probe,
480 	.remove = pci1xxxx_serial_remove,
481 	.driver = {
482 		.pm     = pm_sleep_ptr(&pci1xxxx_pm_ops),
483 	},
484 	.id_table = pci1xxxx_pci_tbl,
485 };
486 module_pci_driver(pci1xxxx_pci_driver);
487 
488 static_assert((ARRAY_SIZE(logical_to_physical_port_idx) == PCI_SUBDEVICE_ID_EFAR_PCI1XXXX_1p3 + 1));
489 
490 MODULE_IMPORT_NS(SERIAL_8250_PCI);
491 MODULE_DESCRIPTION("Microchip Technology Inc. PCIe to UART module");
492 MODULE_AUTHOR("Kumaravel Thiagarajan <kumaravel.thiagarajan@microchip.com>");
493 MODULE_AUTHOR("Tharun Kumar P <tharunkumar.pasumarthi@microchip.com>");
494 MODULE_LICENSE("GPL");
495