1 // SPDX-License-Identifier: GPL-2.0
2 /*
3 * Intel MID PCI support
4 * Copyright (c) 2008 Intel Corporation
5 * Jesse Barnes <jesse.barnes@intel.com>
6 *
7 * Moorestown has an interesting PCI implementation:
8 * - configuration space is memory mapped (as defined by MCFG)
9 * - Lincroft devices also have a real, type 1 configuration space
10 * - Early Lincroft silicon has a type 1 access bug that will cause
11 * a hang if non-existent devices are accessed
12 * - some devices have the "fixed BAR" capability, which means
13 * they can't be relocated or modified; check for that during
14 * BAR sizing
15 *
16 * So, we use the MCFG space for all reads and writes, but also send
17 * Lincroft writes to type 1 space. But only read/write if the device
18 * actually exists, otherwise return all 1s for reads and bit bucket
19 * the writes.
20 */
21
22 #include <linux/sched.h>
23 #include <linux/pci.h>
24 #include <linux/ioport.h>
25 #include <linux/init.h>
26 #include <linux/dmi.h>
27 #include <linux/acpi.h>
28 #include <linux/io.h>
29 #include <linux/smp.h>
30
31 #include <asm/cpu_device_id.h>
32 #include <asm/segment.h>
33 #include <asm/pci_x86.h>
34 #include <asm/hw_irq.h>
35 #include <asm/io_apic.h>
36 #include <asm/intel-family.h>
37 #include <asm/intel-mid.h>
38 #include <asm/acpi.h>
39
40 #define PCIE_CAP_OFFSET 0x100
41
42 /* Quirks for the listed devices */
43 #define PCI_DEVICE_ID_INTEL_MRFLD_MMC 0x1190
44 #define PCI_DEVICE_ID_INTEL_MRFLD_HSU 0x1191
45
46 /* Fixed BAR fields */
47 #define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00 /* Fixed BAR (TBD) */
48 #define PCI_FIXED_BAR_0_SIZE 0x04
49 #define PCI_FIXED_BAR_1_SIZE 0x08
50 #define PCI_FIXED_BAR_2_SIZE 0x0c
51 #define PCI_FIXED_BAR_3_SIZE 0x10
52 #define PCI_FIXED_BAR_4_SIZE 0x14
53 #define PCI_FIXED_BAR_5_SIZE 0x1c
54
55 static int pci_soc_mode;
56
57 /**
58 * fixed_bar_cap - return the offset of the fixed BAR cap if found
59 * @bus: PCI bus
60 * @devfn: device in question
61 *
62 * Look for the fixed BAR cap on @bus and @devfn, returning its offset
63 * if found or 0 otherwise.
64 */
fixed_bar_cap(struct pci_bus * bus,unsigned int devfn)65 static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn)
66 {
67 int pos;
68 u32 pcie_cap = 0, cap_data;
69
70 pos = PCIE_CAP_OFFSET;
71
72 if (!raw_pci_ext_ops)
73 return 0;
74
75 while (pos) {
76 if (raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
77 devfn, pos, 4, &pcie_cap))
78 return 0;
79
80 if (PCI_EXT_CAP_ID(pcie_cap) == 0x0000 ||
81 PCI_EXT_CAP_ID(pcie_cap) == 0xffff)
82 break;
83
84 if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) {
85 raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
86 devfn, pos + 4, 4, &cap_data);
87 if ((cap_data & 0xffff) == PCIE_VNDR_CAP_ID_FIXED_BAR)
88 return pos;
89 }
90
91 pos = PCI_EXT_CAP_NEXT(pcie_cap);
92 }
93
94 return 0;
95 }
96
pci_device_update_fixed(struct pci_bus * bus,unsigned int devfn,int reg,int len,u32 val,int offset)97 static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
98 int reg, int len, u32 val, int offset)
99 {
100 u32 size;
101 unsigned int domain, busnum;
102 int bar = (reg - PCI_BASE_ADDRESS_0) >> 2;
103
104 domain = pci_domain_nr(bus);
105 busnum = bus->number;
106
107 if (val == ~0 && len == 4) {
108 unsigned long decode;
109
110 raw_pci_ext_ops->read(domain, busnum, devfn,
111 offset + 8 + (bar * 4), 4, &size);
112
113 /* Turn the size into a decode pattern for the sizing code */
114 if (size) {
115 decode = size - 1;
116 decode |= decode >> 1;
117 decode |= decode >> 2;
118 decode |= decode >> 4;
119 decode |= decode >> 8;
120 decode |= decode >> 16;
121 decode++;
122 decode = ~(decode - 1);
123 } else {
124 decode = 0;
125 }
126
127 /*
128 * If val is all ones, the core code is trying to size the reg,
129 * so update the mmconfig space with the real size.
130 *
131 * Note: this assumes the fixed size we got is a power of two.
132 */
133 return raw_pci_ext_ops->write(domain, busnum, devfn, reg, 4,
134 decode);
135 }
136
137 /* This is some other kind of BAR write, so just do it. */
138 return raw_pci_ext_ops->write(domain, busnum, devfn, reg, len, val);
139 }
140
141 /**
142 * type1_access_ok - check whether to use type 1
143 * @bus: bus number
144 * @devfn: device & function in question
145 * @reg: configuration register offset
146 *
147 * If the bus is on a Lincroft chip and it exists, or is not on a Lincroft at
148 * all, the we can go ahead with any reads & writes. If it's on a Lincroft,
149 * but doesn't exist, avoid the access altogether to keep the chip from
150 * hanging.
151 */
type1_access_ok(unsigned int bus,unsigned int devfn,int reg)152 static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
153 {
154 /*
155 * This is a workaround for A0 LNC bug where PCI status register does
156 * not have new CAP bit set. can not be written by SW either.
157 *
158 * PCI header type in real LNC indicates a single function device, this
159 * will prevent probing other devices under the same function in PCI
160 * shim. Therefore, use the header type in shim instead.
161 */
162 if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE)
163 return false;
164 if (bus == 0 && (devfn == PCI_DEVFN(2, 0)
165 || devfn == PCI_DEVFN(0, 0)
166 || devfn == PCI_DEVFN(3, 0)))
167 return true;
168 return false; /* Langwell on others */
169 }
170
pci_read(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 * value)171 static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
172 int size, u32 *value)
173 {
174 if (type1_access_ok(bus->number, devfn, where))
175 return pci_direct_conf1.read(pci_domain_nr(bus), bus->number,
176 devfn, where, size, value);
177 return raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
178 devfn, where, size, value);
179 }
180
pci_write(struct pci_bus * bus,unsigned int devfn,int where,int size,u32 value)181 static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
182 int size, u32 value)
183 {
184 int offset;
185
186 /*
187 * On MRST, there is no PCI ROM BAR, this will cause a subsequent read
188 * to ROM BAR return 0 then being ignored.
189 */
190 if (where == PCI_ROM_ADDRESS)
191 return 0;
192
193 /*
194 * Devices with fixed BARs need special handling:
195 * - BAR sizing code will save, write ~0, read size, restore
196 * - so writes to fixed BARs need special handling
197 * - other writes to fixed BAR devices should go through mmconfig
198 */
199 offset = fixed_bar_cap(bus, devfn);
200 if (offset &&
201 (where >= PCI_BASE_ADDRESS_0 && where <= PCI_BASE_ADDRESS_5)) {
202 return pci_device_update_fixed(bus, devfn, where, size, value,
203 offset);
204 }
205
206 /*
207 * On Moorestown update both real & mmconfig space
208 * Note: early Lincroft silicon can't handle type 1 accesses to
209 * non-existent devices, so just eat the write in that case.
210 */
211 if (type1_access_ok(bus->number, devfn, where))
212 return pci_direct_conf1.write(pci_domain_nr(bus), bus->number,
213 devfn, where, size, value);
214 return raw_pci_ext_ops->write(pci_domain_nr(bus), bus->number, devfn,
215 where, size, value);
216 }
217
218 static const struct x86_cpu_id intel_mid_cpu_ids[] = {
219 X86_MATCH_INTEL_FAM6_MODEL(ATOM_SILVERMONT_MID, NULL),
220 {}
221 };
222
intel_mid_pci_irq_enable(struct pci_dev * dev)223 static int intel_mid_pci_irq_enable(struct pci_dev *dev)
224 {
225 const struct x86_cpu_id *id;
226 struct irq_alloc_info info;
227 bool polarity_low;
228 u16 model = 0;
229 int ret;
230 u8 gsi;
231
232 if (dev->irq_managed && dev->irq > 0)
233 return 0;
234
235 ret = pci_read_config_byte(dev, PCI_INTERRUPT_LINE, &gsi);
236 if (ret) {
237 dev_warn(&dev->dev, "Failed to read interrupt line: %d\n", ret);
238 return pcibios_err_to_errno(ret);
239 }
240
241 id = x86_match_cpu(intel_mid_cpu_ids);
242 if (id)
243 model = id->model;
244
245 switch (model) {
246 case INTEL_FAM6_ATOM_SILVERMONT_MID:
247 polarity_low = false;
248
249 /* Special treatment for IRQ0 */
250 if (gsi == 0) {
251 /*
252 * Skip HS UART common registers device since it has
253 * IRQ0 assigned and not used by the kernel.
254 */
255 if (dev->device == PCI_DEVICE_ID_INTEL_MRFLD_HSU)
256 return -EBUSY;
257 /*
258 * TNG has IRQ0 assigned to eMMC controller. But there
259 * are also other devices with bogus PCI configuration
260 * that have IRQ0 assigned. This check ensures that
261 * eMMC gets it. The rest of devices still could be
262 * enabled without interrupt line being allocated.
263 */
264 if (dev->device != PCI_DEVICE_ID_INTEL_MRFLD_MMC)
265 return 0;
266 }
267 break;
268 default:
269 polarity_low = true;
270 break;
271 }
272
273 ioapic_set_alloc_attr(&info, dev_to_node(&dev->dev), 1, polarity_low);
274
275 /*
276 * MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
277 * IOAPIC RTE entries, so we just enable RTE for the device.
278 */
279 ret = mp_map_gsi_to_irq(gsi, IOAPIC_MAP_ALLOC, &info);
280 if (ret < 0)
281 return ret;
282
283 dev->irq = ret;
284 dev->irq_managed = 1;
285
286 return 0;
287 }
288
intel_mid_pci_irq_disable(struct pci_dev * dev)289 static void intel_mid_pci_irq_disable(struct pci_dev *dev)
290 {
291 if (!mp_should_keep_irq(&dev->dev) && dev->irq_managed &&
292 dev->irq > 0) {
293 mp_unmap_irq(dev->irq);
294 dev->irq_managed = 0;
295 }
296 }
297
298 static const struct pci_ops intel_mid_pci_ops __initconst = {
299 .read = pci_read,
300 .write = pci_write,
301 };
302
303 /**
304 * intel_mid_pci_init - installs intel_mid_pci_ops
305 *
306 * Moorestown has an interesting PCI implementation (see above).
307 * Called when the early platform detection installs it.
308 */
intel_mid_pci_init(void)309 int __init intel_mid_pci_init(void)
310 {
311 pr_info("Intel MID platform detected, using MID PCI ops\n");
312 pci_mmcfg_late_init();
313 pcibios_enable_irq = intel_mid_pci_irq_enable;
314 pcibios_disable_irq = intel_mid_pci_irq_disable;
315 pci_root_ops = intel_mid_pci_ops;
316 pci_soc_mode = 1;
317 /* Continue with standard init */
318 acpi_noirq_set();
319 return 1;
320 }
321
322 /*
323 * Langwell devices are not true PCI devices; they are not subject to 10 ms
324 * d3 to d0 delay required by PCI spec.
325 */
pci_d3delay_fixup(struct pci_dev * dev)326 static void pci_d3delay_fixup(struct pci_dev *dev)
327 {
328 /*
329 * PCI fixups are effectively decided compile time. If we have a dual
330 * SoC/non-SoC kernel we don't want to mangle d3 on non-SoC devices.
331 */
332 if (!pci_soc_mode)
333 return;
334 /*
335 * True PCI devices in Lincroft should allow type 1 access, the rest
336 * are Langwell fake PCI devices.
337 */
338 if (type1_access_ok(dev->bus->number, dev->devfn, PCI_DEVICE_ID))
339 return;
340 dev->d3hot_delay = 0;
341 }
342 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_d3delay_fixup);
343
mid_power_off_one_device(struct pci_dev * dev)344 static void mid_power_off_one_device(struct pci_dev *dev)
345 {
346 u16 pmcsr;
347
348 /*
349 * Update current state first, otherwise PCI core enforces PCI_D0 in
350 * pci_set_power_state() for devices which status was PCI_UNKNOWN.
351 */
352 pci_read_config_word(dev, dev->pm_cap + PCI_PM_CTRL, &pmcsr);
353 dev->current_state = (pci_power_t __force)(pmcsr & PCI_PM_CTRL_STATE_MASK);
354
355 pci_set_power_state(dev, PCI_D3hot);
356 }
357
mid_power_off_devices(struct pci_dev * dev)358 static void mid_power_off_devices(struct pci_dev *dev)
359 {
360 int id;
361
362 if (!pci_soc_mode)
363 return;
364
365 id = intel_mid_pwr_get_lss_id(dev);
366 if (id < 0)
367 return;
368
369 /*
370 * This sets only PMCSR bits. The actual power off will happen in
371 * arch/x86/platform/intel-mid/pwr.c.
372 */
373 mid_power_off_one_device(dev);
374 }
375
376 DECLARE_PCI_FIXUP_FINAL(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, mid_power_off_devices);
377
378 /*
379 * Langwell devices reside at fixed offsets, don't try to move them.
380 */
pci_fixed_bar_fixup(struct pci_dev * dev)381 static void pci_fixed_bar_fixup(struct pci_dev *dev)
382 {
383 unsigned long offset;
384 u32 size;
385 int i;
386
387 if (!pci_soc_mode)
388 return;
389
390 /* Must have extended configuration space */
391 if (dev->cfg_size < PCIE_CAP_OFFSET + 4)
392 return;
393
394 /* Fixup the BAR sizes for fixed BAR devices and make them unmoveable */
395 offset = fixed_bar_cap(dev->bus, dev->devfn);
396 if (!offset || PCI_DEVFN(2, 0) == dev->devfn ||
397 PCI_DEVFN(2, 2) == dev->devfn)
398 return;
399
400 for (i = 0; i < PCI_STD_NUM_BARS; i++) {
401 pci_read_config_dword(dev, offset + 8 + (i * 4), &size);
402 dev->resource[i].end = dev->resource[i].start + size - 1;
403 dev->resource[i].flags |= IORESOURCE_PCI_FIXED;
404 }
405 }
406 DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixed_bar_fixup);
407