1 #ifndef QEMU_PCI_H
2 #define QEMU_PCI_H
3
4 #include "exec/memory.h"
5 #include "sysemu/dma.h"
6 #include "sysemu/host_iommu_device.h"
7
8 /* PCI includes legacy ISA access. */
9 #include "hw/isa/isa.h"
10
11 extern bool pci_available;
12
13 /* PCI bus */
14
15 #define PCI_DEVFN(slot, func) ((((slot) & 0x1f) << 3) | ((func) & 0x07))
16 #define PCI_BUS_NUM(x) (((x) >> 8) & 0xff)
17 #define PCI_SLOT(devfn) (((devfn) >> 3) & 0x1f)
18 #define PCI_FUNC(devfn) ((devfn) & 0x07)
19 #define PCI_BUILD_BDF(bus, devfn) ((bus << 8) | (devfn))
20 #define PCI_BDF_TO_DEVFN(x) ((x) & 0xff)
21 #define PCI_BUS_MAX 256
22 #define PCI_DEVFN_MAX 256
23 #define PCI_SLOT_MAX 32
24 #define PCI_FUNC_MAX 8
25
26 /* Class, Vendor and Device IDs from Linux's pci_ids.h */
27 #include "hw/pci/pci_ids.h"
28
29 /* QEMU-specific Vendor and Device ID definitions */
30
31 /* IBM (0x1014) */
32 #define PCI_DEVICE_ID_IBM_440GX 0x027f
33 #define PCI_DEVICE_ID_IBM_OPENPIC2 0xffff
34
35 /* Hitachi (0x1054) */
36 #define PCI_VENDOR_ID_HITACHI 0x1054
37 #define PCI_DEVICE_ID_HITACHI_SH7751R 0x350e
38
39 /* Apple (0x106b) */
40 #define PCI_DEVICE_ID_APPLE_343S1201 0x0010
41 #define PCI_DEVICE_ID_APPLE_UNI_N_I_PCI 0x001e
42 #define PCI_DEVICE_ID_APPLE_UNI_N_PCI 0x001f
43 #define PCI_DEVICE_ID_APPLE_UNI_N_KEYL 0x0022
44 #define PCI_DEVICE_ID_APPLE_IPID_USB 0x003f
45
46 /* Realtek (0x10ec) */
47 #define PCI_DEVICE_ID_REALTEK_8029 0x8029
48
49 /* Xilinx (0x10ee) */
50 #define PCI_DEVICE_ID_XILINX_XC2VP30 0x0300
51
52 /* Marvell (0x11ab) */
53 #define PCI_DEVICE_ID_MARVELL_GT6412X 0x4620
54
55 /* QEMU/Bochs VGA (0x1234) */
56 #define PCI_VENDOR_ID_QEMU 0x1234
57 #define PCI_DEVICE_ID_QEMU_VGA 0x1111
58 #define PCI_DEVICE_ID_QEMU_IPMI 0x1112
59
60 /* VMWare (0x15ad) */
61 #define PCI_VENDOR_ID_VMWARE 0x15ad
62 #define PCI_DEVICE_ID_VMWARE_SVGA2 0x0405
63 #define PCI_DEVICE_ID_VMWARE_SVGA 0x0710
64 #define PCI_DEVICE_ID_VMWARE_NET 0x0720
65 #define PCI_DEVICE_ID_VMWARE_SCSI 0x0730
66 #define PCI_DEVICE_ID_VMWARE_PVSCSI 0x07C0
67 #define PCI_DEVICE_ID_VMWARE_IDE 0x1729
68 #define PCI_DEVICE_ID_VMWARE_VMXNET3 0x07B0
69
70 /* Intel (0x8086) */
71 #define PCI_DEVICE_ID_INTEL_82551IT 0x1209
72 #define PCI_DEVICE_ID_INTEL_82557 0x1229
73 #define PCI_DEVICE_ID_INTEL_82801IR 0x2922
74
75 /* Red Hat / Qumranet (for QEMU) -- see pci-ids.txt */
76 #define PCI_VENDOR_ID_REDHAT_QUMRANET 0x1af4
77 #define PCI_SUBVENDOR_ID_REDHAT_QUMRANET 0x1af4
78 #define PCI_SUBDEVICE_ID_QEMU 0x1100
79
80 /* legacy virtio-pci devices */
81 #define PCI_DEVICE_ID_VIRTIO_NET 0x1000
82 #define PCI_DEVICE_ID_VIRTIO_BLOCK 0x1001
83 #define PCI_DEVICE_ID_VIRTIO_BALLOON 0x1002
84 #define PCI_DEVICE_ID_VIRTIO_CONSOLE 0x1003
85 #define PCI_DEVICE_ID_VIRTIO_SCSI 0x1004
86 #define PCI_DEVICE_ID_VIRTIO_RNG 0x1005
87 #define PCI_DEVICE_ID_VIRTIO_9P 0x1009
88 #define PCI_DEVICE_ID_VIRTIO_VSOCK 0x1012
89
90 /*
91 * modern virtio-pci devices get their id assigned automatically,
92 * there is no need to add #defines here. It gets calculated as
93 *
94 * PCI_DEVICE_ID = PCI_DEVICE_ID_VIRTIO_10_BASE +
95 * virtio_bus_get_vdev_id(bus)
96 */
97 #define PCI_DEVICE_ID_VIRTIO_10_BASE 0x1040
98
99 #define PCI_VENDOR_ID_REDHAT 0x1b36
100 #define PCI_DEVICE_ID_REDHAT_BRIDGE 0x0001
101 #define PCI_DEVICE_ID_REDHAT_SERIAL 0x0002
102 #define PCI_DEVICE_ID_REDHAT_SERIAL2 0x0003
103 #define PCI_DEVICE_ID_REDHAT_SERIAL4 0x0004
104 #define PCI_DEVICE_ID_REDHAT_TEST 0x0005
105 #define PCI_DEVICE_ID_REDHAT_ROCKER 0x0006
106 #define PCI_DEVICE_ID_REDHAT_SDHCI 0x0007
107 #define PCI_DEVICE_ID_REDHAT_PCIE_HOST 0x0008
108 #define PCI_DEVICE_ID_REDHAT_PXB 0x0009
109 #define PCI_DEVICE_ID_REDHAT_BRIDGE_SEAT 0x000a
110 #define PCI_DEVICE_ID_REDHAT_PXB_PCIE 0x000b
111 #define PCI_DEVICE_ID_REDHAT_PCIE_RP 0x000c
112 #define PCI_DEVICE_ID_REDHAT_XHCI 0x000d
113 #define PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE 0x000e
114 #define PCI_DEVICE_ID_REDHAT_MDPY 0x000f
115 #define PCI_DEVICE_ID_REDHAT_NVME 0x0010
116 #define PCI_DEVICE_ID_REDHAT_PVPANIC 0x0011
117 #define PCI_DEVICE_ID_REDHAT_ACPI_ERST 0x0012
118 #define PCI_DEVICE_ID_REDHAT_UFS 0x0013
119 #define PCI_DEVICE_ID_REDHAT_QXL 0x0100
120
121 #define FMT_PCIBUS PRIx64
122
123 typedef uint64_t pcibus_t;
124
125 struct PCIHostDeviceAddress {
126 unsigned int domain;
127 unsigned int bus;
128 unsigned int slot;
129 unsigned int function;
130 };
131
132 typedef void PCIConfigWriteFunc(PCIDevice *pci_dev,
133 uint32_t address, uint32_t data, int len);
134 typedef uint32_t PCIConfigReadFunc(PCIDevice *pci_dev,
135 uint32_t address, int len);
136 typedef void PCIMapIORegionFunc(PCIDevice *pci_dev, int region_num,
137 pcibus_t addr, pcibus_t size, int type);
138 typedef void PCIUnregisterFunc(PCIDevice *pci_dev);
139
140 typedef void MSITriggerFunc(PCIDevice *dev, MSIMessage msg);
141 typedef MSIMessage MSIPrepareMessageFunc(PCIDevice *dev, unsigned vector);
142 typedef MSIMessage MSIxPrepareMessageFunc(PCIDevice *dev, unsigned vector);
143
144 typedef struct PCIIORegion {
145 pcibus_t addr; /* current PCI mapping address. -1 means not mapped */
146 #define PCI_BAR_UNMAPPED (~(pcibus_t)0)
147 pcibus_t size;
148 uint8_t type;
149 MemoryRegion *memory;
150 MemoryRegion *address_space;
151 } PCIIORegion;
152
153 #define PCI_ROM_SLOT 6
154 #define PCI_NUM_REGIONS 7
155
156 enum {
157 QEMU_PCI_VGA_MEM,
158 QEMU_PCI_VGA_IO_LO,
159 QEMU_PCI_VGA_IO_HI,
160 QEMU_PCI_VGA_NUM_REGIONS,
161 };
162
163 #define QEMU_PCI_VGA_MEM_BASE 0xa0000
164 #define QEMU_PCI_VGA_MEM_SIZE 0x20000
165 #define QEMU_PCI_VGA_IO_LO_BASE 0x3b0
166 #define QEMU_PCI_VGA_IO_LO_SIZE 0xc
167 #define QEMU_PCI_VGA_IO_HI_BASE 0x3c0
168 #define QEMU_PCI_VGA_IO_HI_SIZE 0x20
169
170 #include "hw/pci/pci_regs.h"
171
172 /* PCI HEADER_TYPE */
173 #define PCI_HEADER_TYPE_MULTI_FUNCTION 0x80
174
175 /* Size of the standard PCI config header */
176 #define PCI_CONFIG_HEADER_SIZE 0x40
177 /* Size of the standard PCI config space */
178 #define PCI_CONFIG_SPACE_SIZE 0x100
179 /* Size of the standard PCIe config space: 4KB */
180 #define PCIE_CONFIG_SPACE_SIZE 0x1000
181
182 #define PCI_NUM_PINS 4 /* A-D */
183
184 /* Bits in cap_present field. */
185 enum {
186 QEMU_PCI_CAP_MSI = 0x1,
187 QEMU_PCI_CAP_MSIX = 0x2,
188 QEMU_PCI_CAP_EXPRESS = 0x4,
189
190 /* multifunction capable device */
191 #define QEMU_PCI_CAP_MULTIFUNCTION_BITNR 3
192 QEMU_PCI_CAP_MULTIFUNCTION = (1 << QEMU_PCI_CAP_MULTIFUNCTION_BITNR),
193
194 /* command register SERR bit enabled - unused since QEMU v5.0 */
195 #define QEMU_PCI_CAP_SERR_BITNR 4
196 QEMU_PCI_CAP_SERR = (1 << QEMU_PCI_CAP_SERR_BITNR),
197 /* Standard hot plug controller. */
198 #define QEMU_PCI_SHPC_BITNR 5
199 QEMU_PCI_CAP_SHPC = (1 << QEMU_PCI_SHPC_BITNR),
200 #define QEMU_PCI_SLOTID_BITNR 6
201 QEMU_PCI_CAP_SLOTID = (1 << QEMU_PCI_SLOTID_BITNR),
202 /* PCI Express capability - Power Controller Present */
203 #define QEMU_PCIE_SLTCAP_PCP_BITNR 7
204 QEMU_PCIE_SLTCAP_PCP = (1 << QEMU_PCIE_SLTCAP_PCP_BITNR),
205 /* Link active status in endpoint capability is always set */
206 #define QEMU_PCIE_LNKSTA_DLLLA_BITNR 8
207 QEMU_PCIE_LNKSTA_DLLLA = (1 << QEMU_PCIE_LNKSTA_DLLLA_BITNR),
208 #define QEMU_PCIE_EXTCAP_INIT_BITNR 9
209 QEMU_PCIE_EXTCAP_INIT = (1 << QEMU_PCIE_EXTCAP_INIT_BITNR),
210 #define QEMU_PCIE_CXL_BITNR 10
211 QEMU_PCIE_CAP_CXL = (1 << QEMU_PCIE_CXL_BITNR),
212 #define QEMU_PCIE_ERR_UNC_MASK_BITNR 11
213 QEMU_PCIE_ERR_UNC_MASK = (1 << QEMU_PCIE_ERR_UNC_MASK_BITNR),
214 #define QEMU_PCIE_ARI_NEXTFN_1_BITNR 12
215 QEMU_PCIE_ARI_NEXTFN_1 = (1 << QEMU_PCIE_ARI_NEXTFN_1_BITNR),
216 };
217
218 typedef struct PCIINTxRoute {
219 enum {
220 PCI_INTX_ENABLED,
221 PCI_INTX_INVERTED,
222 PCI_INTX_DISABLED,
223 } mode;
224 int irq;
225 } PCIINTxRoute;
226
227 typedef void (*PCIINTxRoutingNotifier)(PCIDevice *dev);
228 typedef int (*MSIVectorUseNotifier)(PCIDevice *dev, unsigned int vector,
229 MSIMessage msg);
230 typedef void (*MSIVectorReleaseNotifier)(PCIDevice *dev, unsigned int vector);
231 typedef void (*MSIVectorPollNotifier)(PCIDevice *dev,
232 unsigned int vector_start,
233 unsigned int vector_end);
234
235 void pci_register_bar(PCIDevice *pci_dev, int region_num,
236 uint8_t attr, MemoryRegion *memory);
237 void pci_register_vga(PCIDevice *pci_dev, MemoryRegion *mem,
238 MemoryRegion *io_lo, MemoryRegion *io_hi);
239 void pci_unregister_vga(PCIDevice *pci_dev);
240 pcibus_t pci_get_bar_addr(PCIDevice *pci_dev, int region_num);
241
242 int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
243 uint8_t offset, uint8_t size,
244 Error **errp);
245
246 void pci_del_capability(PCIDevice *pci_dev, uint8_t cap_id, uint8_t cap_size);
247
248 uint8_t pci_find_capability(PCIDevice *pci_dev, uint8_t cap_id);
249
250
251 uint32_t pci_default_read_config(PCIDevice *d,
252 uint32_t address, int len);
253 void pci_default_write_config(PCIDevice *d,
254 uint32_t address, uint32_t val, int len);
255 void pci_device_save(PCIDevice *s, QEMUFile *f);
256 int pci_device_load(PCIDevice *s, QEMUFile *f);
257 MemoryRegion *pci_address_space(PCIDevice *dev);
258 MemoryRegion *pci_address_space_io(PCIDevice *dev);
259
260 /*
261 * Should not normally be used by devices. For use by sPAPR target
262 * where QEMU emulates firmware.
263 */
264 int pci_bar(PCIDevice *d, int reg);
265
266 typedef void (*pci_set_irq_fn)(void *opaque, int irq_num, int level);
267 typedef int (*pci_map_irq_fn)(PCIDevice *pci_dev, int irq_num);
268 typedef PCIINTxRoute (*pci_route_irq_fn)(void *opaque, int pin);
269
270 #define TYPE_PCI_BUS "PCI"
271 OBJECT_DECLARE_TYPE(PCIBus, PCIBusClass, PCI_BUS)
272 #define TYPE_PCIE_BUS "PCIE"
273 #define TYPE_CXL_BUS "CXL"
274
275 typedef void (*pci_bus_dev_fn)(PCIBus *b, PCIDevice *d, void *opaque);
276 typedef void (*pci_bus_fn)(PCIBus *b, void *opaque);
277 typedef void *(*pci_bus_ret_fn)(PCIBus *b, void *opaque);
278
279 bool pci_bus_is_express(const PCIBus *bus);
280
281 void pci_root_bus_init(PCIBus *bus, size_t bus_size, DeviceState *parent,
282 const char *name,
283 MemoryRegion *mem, MemoryRegion *io,
284 uint8_t devfn_min, const char *typename);
285 PCIBus *pci_root_bus_new(DeviceState *parent, const char *name,
286 MemoryRegion *mem, MemoryRegion *io,
287 uint8_t devfn_min, const char *typename);
288 void pci_root_bus_cleanup(PCIBus *bus);
289 void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq,
290 void *irq_opaque, int nirq);
291 void pci_bus_map_irqs(PCIBus *bus, pci_map_irq_fn map_irq);
292 void pci_bus_irqs_cleanup(PCIBus *bus);
293 int pci_bus_get_irq_level(PCIBus *bus, int irq_num);
294 uint32_t pci_bus_get_slot_reserved_mask(PCIBus *bus);
295 void pci_bus_set_slot_reserved_mask(PCIBus *bus, uint32_t mask);
296 void pci_bus_clear_slot_reserved_mask(PCIBus *bus, uint32_t mask);
297 /* 0 <= pin <= 3 0 = INTA, 1 = INTB, 2 = INTC, 3 = INTD */
pci_swizzle(int slot,int pin)298 static inline int pci_swizzle(int slot, int pin)
299 {
300 return (slot + pin) % PCI_NUM_PINS;
301 }
302 int pci_swizzle_map_irq_fn(PCIDevice *pci_dev, int pin);
303 PCIBus *pci_register_root_bus(DeviceState *parent, const char *name,
304 pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
305 void *irq_opaque,
306 MemoryRegion *mem, MemoryRegion *io,
307 uint8_t devfn_min, int nirq,
308 const char *typename);
309 void pci_unregister_root_bus(PCIBus *bus);
310 void pci_bus_set_route_irq_fn(PCIBus *, pci_route_irq_fn);
311 PCIINTxRoute pci_device_route_intx_to_irq(PCIDevice *dev, int pin);
312 bool pci_intx_route_changed(PCIINTxRoute *old, PCIINTxRoute *new);
313 void pci_bus_fire_intx_routing_notifier(PCIBus *bus);
314 void pci_device_set_intx_routing_notifier(PCIDevice *dev,
315 PCIINTxRoutingNotifier notifier);
316 void pci_device_reset(PCIDevice *dev);
317
318 void pci_init_nic_devices(PCIBus *bus, const char *default_model);
319 bool pci_init_nic_in_slot(PCIBus *rootbus, const char *default_model,
320 const char *alias, const char *devaddr);
321 PCIDevice *pci_vga_init(PCIBus *bus);
322
pci_get_bus(const PCIDevice * dev)323 static inline PCIBus *pci_get_bus(const PCIDevice *dev)
324 {
325 return PCI_BUS(qdev_get_parent_bus(DEVICE(dev)));
326 }
327 int pci_bus_num(PCIBus *s);
328 void pci_bus_range(PCIBus *bus, int *min_bus, int *max_bus);
pci_dev_bus_num(const PCIDevice * dev)329 static inline int pci_dev_bus_num(const PCIDevice *dev)
330 {
331 return pci_bus_num(pci_get_bus(dev));
332 }
333
334 int pci_bus_numa_node(PCIBus *bus);
335 void pci_for_each_device(PCIBus *bus, int bus_num,
336 pci_bus_dev_fn fn,
337 void *opaque);
338 void pci_for_each_device_reverse(PCIBus *bus, int bus_num,
339 pci_bus_dev_fn fn,
340 void *opaque);
341 void pci_for_each_device_under_bus(PCIBus *bus,
342 pci_bus_dev_fn fn, void *opaque);
343 void pci_for_each_device_under_bus_reverse(PCIBus *bus,
344 pci_bus_dev_fn fn,
345 void *opaque);
346 void pci_for_each_bus_depth_first(PCIBus *bus, pci_bus_ret_fn begin,
347 pci_bus_fn end, void *parent_state);
348 PCIDevice *pci_get_function_0(PCIDevice *pci_dev);
349
350 /* Use this wrapper when specific scan order is not required. */
351 static inline
pci_for_each_bus(PCIBus * bus,pci_bus_fn fn,void * opaque)352 void pci_for_each_bus(PCIBus *bus, pci_bus_fn fn, void *opaque)
353 {
354 pci_for_each_bus_depth_first(bus, NULL, fn, opaque);
355 }
356
357 PCIBus *pci_device_root_bus(const PCIDevice *d);
358 const char *pci_root_bus_path(PCIDevice *dev);
359 bool pci_bus_bypass_iommu(PCIBus *bus);
360 PCIDevice *pci_find_device(PCIBus *bus, int bus_num, uint8_t devfn);
361 int pci_qdev_find_device(const char *id, PCIDevice **pdev);
362 void pci_bus_get_w64_range(PCIBus *bus, Range *range);
363
364 void pci_device_deassert_intx(PCIDevice *dev);
365
366
367 /**
368 * struct PCIIOMMUOps: callbacks structure for specific IOMMU handlers
369 * of a PCIBus
370 *
371 * Allows to modify the behavior of some IOMMU operations of the PCI
372 * framework for a set of devices on a PCI bus.
373 */
374 typedef struct PCIIOMMUOps {
375 /**
376 * @get_address_space: get the address space for a set of devices
377 * on a PCI bus.
378 *
379 * Mandatory callback which returns a pointer to an #AddressSpace
380 *
381 * @bus: the #PCIBus being accessed.
382 *
383 * @opaque: the data passed to pci_setup_iommu().
384 *
385 * @devfn: device and function number
386 */
387 AddressSpace * (*get_address_space)(PCIBus *bus, void *opaque, int devfn);
388 /**
389 * @set_iommu_device: attach a HostIOMMUDevice to a vIOMMU
390 *
391 * Optional callback, if not implemented in vIOMMU, then vIOMMU can't
392 * retrieve host information from the associated HostIOMMUDevice.
393 *
394 * @bus: the #PCIBus of the PCI device.
395 *
396 * @opaque: the data passed to pci_setup_iommu().
397 *
398 * @devfn: device and function number of the PCI device.
399 *
400 * @dev: the #HostIOMMUDevice to attach.
401 *
402 * @errp: pass an Error out only when return false
403 *
404 * Returns: true if HostIOMMUDevice is attached or else false with errp set.
405 */
406 bool (*set_iommu_device)(PCIBus *bus, void *opaque, int devfn,
407 HostIOMMUDevice *dev, Error **errp);
408 /**
409 * @unset_iommu_device: detach a HostIOMMUDevice from a vIOMMU
410 *
411 * Optional callback.
412 *
413 * @bus: the #PCIBus of the PCI device.
414 *
415 * @opaque: the data passed to pci_setup_iommu().
416 *
417 * @devfn: device and function number of the PCI device.
418 */
419 void (*unset_iommu_device)(PCIBus *bus, void *opaque, int devfn);
420 } PCIIOMMUOps;
421
422 AddressSpace *pci_device_iommu_address_space(PCIDevice *dev);
423 bool pci_device_set_iommu_device(PCIDevice *dev, HostIOMMUDevice *hiod,
424 Error **errp);
425 void pci_device_unset_iommu_device(PCIDevice *dev);
426
427 /**
428 * pci_setup_iommu: Initialize specific IOMMU handlers for a PCIBus
429 *
430 * Let PCI host bridges define specific operations.
431 *
432 * @bus: the #PCIBus being updated.
433 * @ops: the #PCIIOMMUOps
434 * @opaque: passed to callbacks of the @ops structure.
435 */
436 void pci_setup_iommu(PCIBus *bus, const PCIIOMMUOps *ops, void *opaque);
437
438 pcibus_t pci_bar_address(PCIDevice *d,
439 int reg, uint8_t type, pcibus_t size);
440
441 static inline void
pci_set_byte(uint8_t * config,uint8_t val)442 pci_set_byte(uint8_t *config, uint8_t val)
443 {
444 *config = val;
445 }
446
447 static inline uint8_t
pci_get_byte(const uint8_t * config)448 pci_get_byte(const uint8_t *config)
449 {
450 return *config;
451 }
452
453 static inline void
pci_set_word(uint8_t * config,uint16_t val)454 pci_set_word(uint8_t *config, uint16_t val)
455 {
456 stw_le_p(config, val);
457 }
458
459 static inline uint16_t
pci_get_word(const uint8_t * config)460 pci_get_word(const uint8_t *config)
461 {
462 return lduw_le_p(config);
463 }
464
465 static inline void
pci_set_long(uint8_t * config,uint32_t val)466 pci_set_long(uint8_t *config, uint32_t val)
467 {
468 stl_le_p(config, val);
469 }
470
471 static inline uint32_t
pci_get_long(const uint8_t * config)472 pci_get_long(const uint8_t *config)
473 {
474 return ldl_le_p(config);
475 }
476
477 /*
478 * PCI capabilities and/or their fields
479 * are generally DWORD aligned only so
480 * mechanism used by pci_set/get_quad()
481 * must be tolerant to unaligned pointers
482 *
483 */
484 static inline void
pci_set_quad(uint8_t * config,uint64_t val)485 pci_set_quad(uint8_t *config, uint64_t val)
486 {
487 stq_le_p(config, val);
488 }
489
490 static inline uint64_t
pci_get_quad(const uint8_t * config)491 pci_get_quad(const uint8_t *config)
492 {
493 return ldq_le_p(config);
494 }
495
496 static inline void
pci_config_set_vendor_id(uint8_t * pci_config,uint16_t val)497 pci_config_set_vendor_id(uint8_t *pci_config, uint16_t val)
498 {
499 pci_set_word(&pci_config[PCI_VENDOR_ID], val);
500 }
501
502 static inline void
pci_config_set_device_id(uint8_t * pci_config,uint16_t val)503 pci_config_set_device_id(uint8_t *pci_config, uint16_t val)
504 {
505 pci_set_word(&pci_config[PCI_DEVICE_ID], val);
506 }
507
508 static inline void
pci_config_set_revision(uint8_t * pci_config,uint8_t val)509 pci_config_set_revision(uint8_t *pci_config, uint8_t val)
510 {
511 pci_set_byte(&pci_config[PCI_REVISION_ID], val);
512 }
513
514 static inline void
pci_config_set_class(uint8_t * pci_config,uint16_t val)515 pci_config_set_class(uint8_t *pci_config, uint16_t val)
516 {
517 pci_set_word(&pci_config[PCI_CLASS_DEVICE], val);
518 }
519
520 static inline void
pci_config_set_prog_interface(uint8_t * pci_config,uint8_t val)521 pci_config_set_prog_interface(uint8_t *pci_config, uint8_t val)
522 {
523 pci_set_byte(&pci_config[PCI_CLASS_PROG], val);
524 }
525
526 static inline void
pci_config_set_interrupt_pin(uint8_t * pci_config,uint8_t val)527 pci_config_set_interrupt_pin(uint8_t *pci_config, uint8_t val)
528 {
529 pci_set_byte(&pci_config[PCI_INTERRUPT_PIN], val);
530 }
531
532 /*
533 * helper functions to do bit mask operation on configuration space.
534 * Just to set bit, use test-and-set and discard returned value.
535 * Just to clear bit, use test-and-clear and discard returned value.
536 * NOTE: They aren't atomic.
537 */
538 static inline uint8_t
pci_byte_test_and_clear_mask(uint8_t * config,uint8_t mask)539 pci_byte_test_and_clear_mask(uint8_t *config, uint8_t mask)
540 {
541 uint8_t val = pci_get_byte(config);
542 pci_set_byte(config, val & ~mask);
543 return val & mask;
544 }
545
546 static inline uint8_t
pci_byte_test_and_set_mask(uint8_t * config,uint8_t mask)547 pci_byte_test_and_set_mask(uint8_t *config, uint8_t mask)
548 {
549 uint8_t val = pci_get_byte(config);
550 pci_set_byte(config, val | mask);
551 return val & mask;
552 }
553
554 static inline uint16_t
pci_word_test_and_clear_mask(uint8_t * config,uint16_t mask)555 pci_word_test_and_clear_mask(uint8_t *config, uint16_t mask)
556 {
557 uint16_t val = pci_get_word(config);
558 pci_set_word(config, val & ~mask);
559 return val & mask;
560 }
561
562 static inline uint16_t
pci_word_test_and_set_mask(uint8_t * config,uint16_t mask)563 pci_word_test_and_set_mask(uint8_t *config, uint16_t mask)
564 {
565 uint16_t val = pci_get_word(config);
566 pci_set_word(config, val | mask);
567 return val & mask;
568 }
569
570 static inline uint32_t
pci_long_test_and_clear_mask(uint8_t * config,uint32_t mask)571 pci_long_test_and_clear_mask(uint8_t *config, uint32_t mask)
572 {
573 uint32_t val = pci_get_long(config);
574 pci_set_long(config, val & ~mask);
575 return val & mask;
576 }
577
578 static inline uint32_t
pci_long_test_and_set_mask(uint8_t * config,uint32_t mask)579 pci_long_test_and_set_mask(uint8_t *config, uint32_t mask)
580 {
581 uint32_t val = pci_get_long(config);
582 pci_set_long(config, val | mask);
583 return val & mask;
584 }
585
586 static inline uint64_t
pci_quad_test_and_clear_mask(uint8_t * config,uint64_t mask)587 pci_quad_test_and_clear_mask(uint8_t *config, uint64_t mask)
588 {
589 uint64_t val = pci_get_quad(config);
590 pci_set_quad(config, val & ~mask);
591 return val & mask;
592 }
593
594 static inline uint64_t
pci_quad_test_and_set_mask(uint8_t * config,uint64_t mask)595 pci_quad_test_and_set_mask(uint8_t *config, uint64_t mask)
596 {
597 uint64_t val = pci_get_quad(config);
598 pci_set_quad(config, val | mask);
599 return val & mask;
600 }
601
602 /* Access a register specified by a mask */
603 static inline void
pci_set_byte_by_mask(uint8_t * config,uint8_t mask,uint8_t reg)604 pci_set_byte_by_mask(uint8_t *config, uint8_t mask, uint8_t reg)
605 {
606 uint8_t val = pci_get_byte(config);
607 uint8_t rval;
608
609 assert(mask);
610 rval = reg << ctz32(mask);
611 pci_set_byte(config, (~mask & val) | (mask & rval));
612 }
613
614 static inline void
pci_set_word_by_mask(uint8_t * config,uint16_t mask,uint16_t reg)615 pci_set_word_by_mask(uint8_t *config, uint16_t mask, uint16_t reg)
616 {
617 uint16_t val = pci_get_word(config);
618 uint16_t rval;
619
620 assert(mask);
621 rval = reg << ctz32(mask);
622 pci_set_word(config, (~mask & val) | (mask & rval));
623 }
624
625 static inline void
pci_set_long_by_mask(uint8_t * config,uint32_t mask,uint32_t reg)626 pci_set_long_by_mask(uint8_t *config, uint32_t mask, uint32_t reg)
627 {
628 uint32_t val = pci_get_long(config);
629 uint32_t rval;
630
631 assert(mask);
632 rval = reg << ctz32(mask);
633 pci_set_long(config, (~mask & val) | (mask & rval));
634 }
635
636 static inline void
pci_set_quad_by_mask(uint8_t * config,uint64_t mask,uint64_t reg)637 pci_set_quad_by_mask(uint8_t *config, uint64_t mask, uint64_t reg)
638 {
639 uint64_t val = pci_get_quad(config);
640 uint64_t rval;
641
642 assert(mask);
643 rval = reg << ctz32(mask);
644 pci_set_quad(config, (~mask & val) | (mask & rval));
645 }
646
647 PCIDevice *pci_new_multifunction(int devfn, const char *name);
648 PCIDevice *pci_new(int devfn, const char *name);
649 bool pci_realize_and_unref(PCIDevice *dev, PCIBus *bus, Error **errp);
650
651 PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
652 const char *name);
653 PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name);
654
655 void lsi53c8xx_handle_legacy_cmdline(DeviceState *lsi_dev);
656
657 qemu_irq pci_allocate_irq(PCIDevice *pci_dev);
658 void pci_set_irq(PCIDevice *pci_dev, int level);
659
pci_irq_assert(PCIDevice * pci_dev)660 static inline void pci_irq_assert(PCIDevice *pci_dev)
661 {
662 pci_set_irq(pci_dev, 1);
663 }
664
pci_irq_deassert(PCIDevice * pci_dev)665 static inline void pci_irq_deassert(PCIDevice *pci_dev)
666 {
667 pci_set_irq(pci_dev, 0);
668 }
669
670 /*
671 * FIXME: PCI does not work this way.
672 * All the callers to this method should be fixed.
673 */
pci_irq_pulse(PCIDevice * pci_dev)674 static inline void pci_irq_pulse(PCIDevice *pci_dev)
675 {
676 pci_irq_assert(pci_dev);
677 pci_irq_deassert(pci_dev);
678 }
679
680 MSIMessage pci_get_msi_message(PCIDevice *dev, int vector);
681 void pci_set_power(PCIDevice *pci_dev, bool state);
682
683 #endif
684