xref: /openbmc/u-boot/drivers/pci/pci-aardvark.c (revision b25f8e21)
1 /*
2  * ***************************************************************************
3  * Copyright (C) 2015 Marvell International Ltd.
4  * ***************************************************************************
5  * This program is free software: you can redistribute it and/or modify it
6  * under the terms of the GNU General Public License as published by the Free
7  * Software Foundation, either version 2 of the License, or any later version.
8  *
9  * This program is distributed in the hope that it will be useful,
10  * but WITHOUT ANY WARRANTY; without even the implied warranty of
11  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
12  * GNU General Public License for more details.
13  *
14  * You should have received a copy of the GNU General Public License
15  * along with this program.  If not, see <http://www.gnu.org/licenses/>.
16  * ***************************************************************************
17  */
18 /* pcie_advk.c
19  *
20  * Ported from Linux driver - driver/pci/host/pci-aardvark.c
21  *
22  * Author: Victor Gu <xigu@marvell.com>
23  *         Hezi Shahmoon <hezi.shahmoon@marvell.com>
24  *
25  */
26 
27 #include <common.h>
28 #include <dm.h>
29 #include <pci.h>
30 #include <asm/io.h>
31 #include <asm-generic/gpio.h>
32 #include <linux/ioport.h>
33 
34 /* PCIe core registers */
35 #define PCIE_CORE_CMD_STATUS_REG				0x4
36 #define     PCIE_CORE_CMD_IO_ACCESS_EN				BIT(0)
37 #define     PCIE_CORE_CMD_MEM_ACCESS_EN				BIT(1)
38 #define     PCIE_CORE_CMD_MEM_IO_REQ_EN				BIT(2)
39 #define PCIE_CORE_DEV_CTRL_STATS_REG				0xc8
40 #define     PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE	(0 << 4)
41 #define     PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE		(0 << 11)
42 #define PCIE_CORE_LINK_CTRL_STAT_REG				0xd0
43 #define     PCIE_CORE_LINK_TRAINING				BIT(5)
44 #define PCIE_CORE_ERR_CAPCTL_REG				0x118
45 #define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX			BIT(5)
46 #define     PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN			BIT(6)
47 #define     PCIE_CORE_ERR_CAPCTL_ECRC_CHECK			BIT(7)
48 #define     PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV			BIT(8)
49 
50 /* PIO registers base address and register offsets */
51 #define PIO_BASE_ADDR				0x4000
52 #define PIO_CTRL				(PIO_BASE_ADDR + 0x0)
53 #define   PIO_CTRL_TYPE_MASK			GENMASK(3, 0)
54 #define   PIO_CTRL_ADDR_WIN_DISABLE		BIT(24)
55 #define PIO_STAT				(PIO_BASE_ADDR + 0x4)
56 #define   PIO_COMPLETION_STATUS_SHIFT		7
57 #define   PIO_COMPLETION_STATUS_MASK		GENMASK(9, 7)
58 #define   PIO_COMPLETION_STATUS_OK		0
59 #define   PIO_COMPLETION_STATUS_UR		1
60 #define   PIO_COMPLETION_STATUS_CRS		2
61 #define   PIO_COMPLETION_STATUS_CA		4
62 #define   PIO_NON_POSTED_REQ			BIT(10)
63 #define   PIO_ERR_STATUS			BIT(11)
64 #define PIO_ADDR_LS				(PIO_BASE_ADDR + 0x8)
65 #define PIO_ADDR_MS				(PIO_BASE_ADDR + 0xc)
66 #define PIO_WR_DATA				(PIO_BASE_ADDR + 0x10)
67 #define PIO_WR_DATA_STRB			(PIO_BASE_ADDR + 0x14)
68 #define PIO_RD_DATA				(PIO_BASE_ADDR + 0x18)
69 #define PIO_START				(PIO_BASE_ADDR + 0x1c)
70 #define PIO_ISR					(PIO_BASE_ADDR + 0x20)
71 
72 /* Aardvark Control registers */
73 #define CONTROL_BASE_ADDR			0x4800
74 #define PCIE_CORE_CTRL0_REG			(CONTROL_BASE_ADDR + 0x0)
75 #define     PCIE_GEN_SEL_MSK			0x3
76 #define     PCIE_GEN_SEL_SHIFT			0x0
77 #define     SPEED_GEN_1				0
78 #define     SPEED_GEN_2				1
79 #define     SPEED_GEN_3				2
80 #define     IS_RC_MSK				1
81 #define     IS_RC_SHIFT				2
82 #define     LANE_CNT_MSK			0x18
83 #define     LANE_CNT_SHIFT			0x3
84 #define     LANE_COUNT_1			(0 << LANE_CNT_SHIFT)
85 #define     LANE_COUNT_2			(1 << LANE_CNT_SHIFT)
86 #define     LANE_COUNT_4			(2 << LANE_CNT_SHIFT)
87 #define     LANE_COUNT_8			(3 << LANE_CNT_SHIFT)
88 #define     LINK_TRAINING_EN			BIT(6)
89 #define PCIE_CORE_CTRL2_REG			(CONTROL_BASE_ADDR + 0x8)
90 #define     PCIE_CORE_CTRL2_RESERVED		0x7
91 #define     PCIE_CORE_CTRL2_TD_ENABLE		BIT(4)
92 #define     PCIE_CORE_CTRL2_STRICT_ORDER_ENABLE	BIT(5)
93 #define     PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE	BIT(6)
94 
95 /* LMI registers base address and register offsets */
96 #define LMI_BASE_ADDR				0x6000
97 #define CFG_REG					(LMI_BASE_ADDR + 0x0)
98 #define     LTSSM_SHIFT				24
99 #define     LTSSM_MASK				0x3f
100 #define     LTSSM_L0				0x10
101 
102 /* PCIe core controller registers */
103 #define CTRL_CORE_BASE_ADDR			0x18000
104 #define CTRL_CONFIG_REG				(CTRL_CORE_BASE_ADDR + 0x0)
105 #define     CTRL_MODE_SHIFT			0x0
106 #define     CTRL_MODE_MASK			0x1
107 #define     PCIE_CORE_MODE_DIRECT		0x0
108 #define     PCIE_CORE_MODE_COMMAND		0x1
109 
110 /* Transaction types */
111 #define PCIE_CONFIG_RD_TYPE0			0x8
112 #define PCIE_CONFIG_RD_TYPE1			0x9
113 #define PCIE_CONFIG_WR_TYPE0			0xa
114 #define PCIE_CONFIG_WR_TYPE1			0xb
115 
116 /* PCI_BDF shifts 8bit, so we need extra 4bit shift */
117 #define PCIE_BDF(dev)				(dev << 4)
118 #define PCIE_CONF_BUS(bus)			(((bus) & 0xff) << 20)
119 #define PCIE_CONF_DEV(dev)			(((dev) & 0x1f) << 15)
120 #define PCIE_CONF_FUNC(fun)			(((fun) & 0x7)	<< 12)
121 #define PCIE_CONF_REG(reg)			((reg) & 0xffc)
122 #define PCIE_CONF_ADDR(bus, devfn, where)	\
123 	(PCIE_CONF_BUS(bus) | PCIE_CONF_DEV(PCI_SLOT(devfn))	| \
124 	 PCIE_CONF_FUNC(PCI_FUNC(devfn)) | PCIE_CONF_REG(where))
125 
126 /* PCIe Retries & Timeout definitions */
127 #define MAX_RETRIES				10
128 #define PIO_WAIT_TIMEOUT			100
129 #define LINK_WAIT_TIMEOUT			100000
130 
131 #define CFG_RD_UR_VAL			0xFFFFFFFF
132 #define CFG_RD_CRS_VAL			0xFFFF0001
133 
134 /**
135  * struct pcie_advk - Advk PCIe controller state
136  *
137  * @reg_base:    The base address of the register space.
138  * @first_busno: This driver supports multiple PCIe controllers.
139  *               first_busno stores the bus number of the PCIe root-port
140  *               number which may vary depending on the PCIe setup
141  *               (PEX switches etc).
142  * @device:      The pointer to PCI uclass device.
143  */
144 struct pcie_advk {
145 	void           *base;
146 	int            first_busno;
147 	struct udevice *dev;
148 };
149 
advk_writel(struct pcie_advk * pcie,uint val,uint reg)150 static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg)
151 {
152 	writel(val, pcie->base + reg);
153 }
154 
advk_readl(struct pcie_advk * pcie,uint reg)155 static inline uint advk_readl(struct pcie_advk *pcie, uint reg)
156 {
157 	return readl(pcie->base + reg);
158 }
159 
160 /**
161  * pcie_advk_addr_valid() - Check for valid bus address
162  *
163  * @bdf: The PCI device to access
164  * @first_busno: Bus number of the PCIe controller root complex
165  *
166  * Return: 1 on valid, 0 on invalid
167  */
pcie_advk_addr_valid(pci_dev_t bdf,int first_busno)168 static int pcie_advk_addr_valid(pci_dev_t bdf, int first_busno)
169 {
170 	/*
171 	 * In PCIE-E only a single device (0) can exist
172 	 * on the local bus. Beyound the local bus, there might be
173 	 * a Switch and everything is possible.
174 	 */
175 	if ((PCI_BUS(bdf) == first_busno) && (PCI_DEV(bdf) > 0))
176 		return 0;
177 
178 	return 1;
179 }
180 
181 /**
182  * pcie_advk_wait_pio() - Wait for PIO access to be accomplished
183  *
184  * @pcie: The PCI device to access
185  *
186  * Wait up to 1 micro second for PIO access to be accomplished.
187  *
188  * Return 1 (true) if PIO access is accomplished.
189  * Return 0 (false) if PIO access is timed out.
190  */
pcie_advk_wait_pio(struct pcie_advk * pcie)191 static int pcie_advk_wait_pio(struct pcie_advk *pcie)
192 {
193 	uint start, isr;
194 	uint count;
195 
196 	for (count = 0; count < MAX_RETRIES; count++) {
197 		start = advk_readl(pcie, PIO_START);
198 		isr = advk_readl(pcie, PIO_ISR);
199 		if (!start && isr)
200 			return 1;
201 		/*
202 		 * Do not check the PIO state too frequently,
203 		 * 100us delay is appropriate.
204 		 */
205 		udelay(PIO_WAIT_TIMEOUT);
206 	}
207 
208 	dev_err(pcie->dev, "config read/write timed out\n");
209 	return 0;
210 }
211 
212 /**
213  * pcie_advk_check_pio_status() - Validate PIO status and get the read result
214  *
215  * @pcie: Pointer to the PCI bus
216  * @read: Read from or write to configuration space - true(read) false(write)
217  * @read_val: Pointer to the read result, only valid when read is true
218  *
219  */
pcie_advk_check_pio_status(struct pcie_advk * pcie,bool read,uint * read_val)220 static int pcie_advk_check_pio_status(struct pcie_advk *pcie,
221 				      bool read,
222 				      uint *read_val)
223 {
224 	uint reg;
225 	unsigned int status;
226 	char *strcomp_status, *str_posted;
227 
228 	reg = advk_readl(pcie, PIO_STAT);
229 	status = (reg & PIO_COMPLETION_STATUS_MASK) >>
230 		PIO_COMPLETION_STATUS_SHIFT;
231 
232 	switch (status) {
233 	case PIO_COMPLETION_STATUS_OK:
234 		if (reg & PIO_ERR_STATUS) {
235 			strcomp_status = "COMP_ERR";
236 			break;
237 		}
238 		/* Get the read result */
239 		if (read)
240 			*read_val = advk_readl(pcie, PIO_RD_DATA);
241 		/* No error */
242 		strcomp_status = NULL;
243 		break;
244 	case PIO_COMPLETION_STATUS_UR:
245 		if (read) {
246 			/* For reading, UR is not an error status. */
247 			*read_val = CFG_RD_UR_VAL;
248 			strcomp_status = NULL;
249 		} else {
250 			strcomp_status = "UR";
251 		}
252 		break;
253 	case PIO_COMPLETION_STATUS_CRS:
254 		if (read) {
255 			/* For reading, CRS is not an error status. */
256 			*read_val = CFG_RD_CRS_VAL;
257 			strcomp_status = NULL;
258 		} else {
259 			strcomp_status = "CRS";
260 		}
261 		break;
262 	case PIO_COMPLETION_STATUS_CA:
263 		strcomp_status = "CA";
264 		break;
265 	default:
266 		strcomp_status = "Unknown";
267 		break;
268 	}
269 
270 	if (!strcomp_status)
271 		return 0;
272 
273 	if (reg & PIO_NON_POSTED_REQ)
274 		str_posted = "Non-posted";
275 	else
276 		str_posted = "Posted";
277 
278 	dev_err(pcie->dev, "%s PIO Response Status: %s, %#x @ %#x\n",
279 		str_posted, strcomp_status, reg,
280 		advk_readl(pcie, PIO_ADDR_LS));
281 
282 	return -EFAULT;
283 }
284 
285 /**
286  * pcie_advk_read_config() - Read from configuration space
287  *
288  * @bus: Pointer to the PCI bus
289  * @bdf: Identifies the PCIe device to access
290  * @offset: The offset into the device's configuration space
291  * @valuep: A pointer at which to store the read value
292  * @size: Indicates the size of access to perform
293  *
294  * Read a value of size @size from offset @offset within the configuration
295  * space of the device identified by the bus, device & function numbers in @bdf
296  * on the PCI bus @bus.
297  *
298  * Return: 0 on success
299  */
pcie_advk_read_config(struct udevice * bus,pci_dev_t bdf,uint offset,ulong * valuep,enum pci_size_t size)300 static int pcie_advk_read_config(struct udevice *bus, pci_dev_t bdf,
301 				 uint offset, ulong *valuep,
302 				 enum pci_size_t size)
303 {
304 	struct pcie_advk *pcie = dev_get_priv(bus);
305 	uint reg;
306 	int ret;
307 
308 	dev_dbg(pcie->dev, "PCIE CFG read:  (b,d,f)=(%2d,%2d,%2d) ",
309 		PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
310 
311 	if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
312 		dev_dbg(pcie->dev, "- out of range\n");
313 		*valuep = pci_get_ff(size);
314 		return 0;
315 	}
316 
317 	/* Start PIO */
318 	advk_writel(pcie, 0, PIO_START);
319 	advk_writel(pcie, 1, PIO_ISR);
320 
321 	/* Program the control register */
322 	reg = advk_readl(pcie, PIO_CTRL);
323 	reg &= ~PIO_CTRL_TYPE_MASK;
324 	if (PCI_BUS(bdf) == pcie->first_busno)
325 		reg |= PCIE_CONFIG_RD_TYPE0;
326 	else
327 		reg |= PCIE_CONFIG_RD_TYPE1;
328 	advk_writel(pcie, reg, PIO_CTRL);
329 
330 	/* Program the address registers */
331 	reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
332 	advk_writel(pcie, reg, PIO_ADDR_LS);
333 	advk_writel(pcie, 0, PIO_ADDR_MS);
334 
335 	/* Start the transfer */
336 	advk_writel(pcie, 1, PIO_START);
337 
338 	if (!pcie_advk_wait_pio(pcie))
339 		return -EINVAL;
340 
341 	/* Check PIO status and get the read result */
342 	ret = pcie_advk_check_pio_status(pcie, true, &reg);
343 	if (ret)
344 		return ret;
345 
346 	dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08x)\n",
347 		offset, size, reg);
348 	*valuep = pci_conv_32_to_size(reg, offset, size);
349 
350 	return 0;
351 }
352 
353 /**
354  * pcie_calc_datastrobe() - Calculate data strobe
355  *
356  * @offset: The offset into the device's configuration space
357  * @size: Indicates the size of access to perform
358  *
359  * Calculate data strobe according to offset and size
360  *
361  */
pcie_calc_datastrobe(uint offset,enum pci_size_t size)362 static uint pcie_calc_datastrobe(uint offset, enum pci_size_t size)
363 {
364 	uint bytes, data_strobe;
365 
366 	switch (size) {
367 	case PCI_SIZE_8:
368 		bytes = 1;
369 		break;
370 	case PCI_SIZE_16:
371 		bytes = 2;
372 		break;
373 	default:
374 		bytes = 4;
375 	}
376 
377 	data_strobe = GENMASK(bytes - 1, 0) << (offset & 0x3);
378 
379 	return data_strobe;
380 }
381 
382 /**
383  * pcie_advk_write_config() - Write to configuration space
384  *
385  * @bus: Pointer to the PCI bus
386  * @bdf: Identifies the PCIe device to access
387  * @offset: The offset into the device's configuration space
388  * @value: The value to write
389  * @size: Indicates the size of access to perform
390  *
391  * Write the value @value of size @size from offset @offset within the
392  * configuration space of the device identified by the bus, device & function
393  * numbers in @bdf on the PCI bus @bus.
394  *
395  * Return: 0 on success
396  */
pcie_advk_write_config(struct udevice * bus,pci_dev_t bdf,uint offset,ulong value,enum pci_size_t size)397 static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf,
398 				  uint offset, ulong value,
399 				  enum pci_size_t size)
400 {
401 	struct pcie_advk *pcie = dev_get_priv(bus);
402 	uint reg;
403 
404 	dev_dbg(pcie->dev, "PCIE CFG write: (b,d,f)=(%2d,%2d,%2d) ",
405 		PCI_BUS(bdf), PCI_DEV(bdf), PCI_FUNC(bdf));
406 	dev_dbg(pcie->dev, "(addr,size,val)=(0x%04x, %d, 0x%08lx)\n",
407 		offset, size, value);
408 
409 	if (!pcie_advk_addr_valid(bdf, pcie->first_busno)) {
410 		dev_dbg(pcie->dev, "- out of range\n");
411 		return 0;
412 	}
413 
414 	/* Start PIO */
415 	advk_writel(pcie, 0, PIO_START);
416 	advk_writel(pcie, 1, PIO_ISR);
417 
418 	/* Program the control register */
419 	reg = advk_readl(pcie, PIO_CTRL);
420 	reg &= ~PIO_CTRL_TYPE_MASK;
421 	if (PCI_BUS(bdf) == pcie->first_busno)
422 		reg |= PCIE_CONFIG_WR_TYPE0;
423 	else
424 		reg |= PCIE_CONFIG_WR_TYPE1;
425 	advk_writel(pcie, reg, PIO_CTRL);
426 
427 	/* Program the address registers */
428 	reg = PCIE_BDF(bdf) | PCIE_CONF_REG(offset);
429 	advk_writel(pcie, reg, PIO_ADDR_LS);
430 	advk_writel(pcie, 0, PIO_ADDR_MS);
431 	dev_dbg(pcie->dev, "\tPIO req. - addr = 0x%08x\n", reg);
432 
433 	/* Program the data register */
434 	reg = pci_conv_size_to_32(0, value, offset, size);
435 	advk_writel(pcie, reg, PIO_WR_DATA);
436 	dev_dbg(pcie->dev, "\tPIO req. - val  = 0x%08x\n", reg);
437 
438 	/* Program the data strobe */
439 	reg = pcie_calc_datastrobe(offset, size);
440 	advk_writel(pcie, reg, PIO_WR_DATA_STRB);
441 	dev_dbg(pcie->dev, "\tPIO req. - strb = 0x%02x\n", reg);
442 
443 	/* Start the transfer */
444 	advk_writel(pcie, 1, PIO_START);
445 
446 	if (!pcie_advk_wait_pio(pcie)) {
447 		dev_dbg(pcie->dev, "- wait pio timeout\n");
448 		return -EINVAL;
449 	}
450 
451 	/* Check PIO status */
452 	pcie_advk_check_pio_status(pcie, false, &reg);
453 
454 	return 0;
455 }
456 
457 /**
458  * pcie_advk_link_up() - Check if PCIe link is up or not
459  *
460  * @pcie: The PCI device to access
461  *
462  * Return 1 (true) on link up.
463  * Return 0 (false) on link down.
464  */
pcie_advk_link_up(struct pcie_advk * pcie)465 static int pcie_advk_link_up(struct pcie_advk *pcie)
466 {
467 	u32 val, ltssm_state;
468 
469 	val = advk_readl(pcie, CFG_REG);
470 	ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
471 	return ltssm_state >= LTSSM_L0;
472 }
473 
474 /**
475  * pcie_advk_wait_for_link() - Wait for link training to be accomplished
476  *
477  * @pcie: The PCI device to access
478  *
479  * Wait up to 1 second for link training to be accomplished.
480  *
481  * Return 1 (true) if link training ends up with link up success.
482  * Return 0 (false) if link training ends up with link up failure.
483  */
pcie_advk_wait_for_link(struct pcie_advk * pcie)484 static int pcie_advk_wait_for_link(struct pcie_advk *pcie)
485 {
486 	int retries;
487 
488 	/* check if the link is up or not */
489 	for (retries = 0; retries < MAX_RETRIES; retries++) {
490 		if (pcie_advk_link_up(pcie)) {
491 			printf("PCIE-%d: Link up\n", pcie->first_busno);
492 			return 0;
493 		}
494 
495 		udelay(LINK_WAIT_TIMEOUT);
496 	}
497 
498 	printf("PCIE-%d: Link down\n", pcie->first_busno);
499 
500 	return -ETIMEDOUT;
501 }
502 
503 /**
504  * pcie_advk_setup_hw() - PCIe initailzation
505  *
506  * @pcie: The PCI device to access
507  *
508  * Return: 0 on success
509  */
pcie_advk_setup_hw(struct pcie_advk * pcie)510 static int pcie_advk_setup_hw(struct pcie_advk *pcie)
511 {
512 	u32 reg;
513 
514 	/* Set to Direct mode */
515 	reg = advk_readl(pcie, CTRL_CONFIG_REG);
516 	reg &= ~(CTRL_MODE_MASK << CTRL_MODE_SHIFT);
517 	reg |= ((PCIE_CORE_MODE_DIRECT & CTRL_MODE_MASK) << CTRL_MODE_SHIFT);
518 	advk_writel(pcie, reg, CTRL_CONFIG_REG);
519 
520 	/* Set PCI global control register to RC mode */
521 	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
522 	reg |= (IS_RC_MSK << IS_RC_SHIFT);
523 	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
524 
525 	/* Set Advanced Error Capabilities and Control PF0 register */
526 	reg = PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX |
527 		PCIE_CORE_ERR_CAPCTL_ECRC_CHK_TX_EN |
528 		PCIE_CORE_ERR_CAPCTL_ECRC_CHECK |
529 		PCIE_CORE_ERR_CAPCTL_ECRC_CHECK_RCV;
530 	advk_writel(pcie, reg, PCIE_CORE_ERR_CAPCTL_REG);
531 
532 	/* Set PCIe Device Control and Status 1 PF0 register */
533 	reg = PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE |
534 		PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE;
535 	advk_writel(pcie, reg, PCIE_CORE_DEV_CTRL_STATS_REG);
536 
537 	/* Program PCIe Control 2 to disable strict ordering */
538 	reg = PCIE_CORE_CTRL2_RESERVED |
539 		PCIE_CORE_CTRL2_TD_ENABLE;
540 	advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
541 
542 	/* Set GEN2 */
543 	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
544 	reg &= ~PCIE_GEN_SEL_MSK;
545 	reg |= SPEED_GEN_2;
546 	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
547 
548 	/* Set lane X1 */
549 	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
550 	reg &= ~LANE_CNT_MSK;
551 	reg |= LANE_COUNT_1;
552 	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
553 
554 	/* Enable link training */
555 	reg = advk_readl(pcie, PCIE_CORE_CTRL0_REG);
556 	reg |= LINK_TRAINING_EN;
557 	advk_writel(pcie, reg, PCIE_CORE_CTRL0_REG);
558 
559 	/*
560 	 * Enable AXI address window location generation:
561 	 * When it is enabled, the default outbound window
562 	 * configurations (Default User Field: 0xD0074CFC)
563 	 * are used to transparent address translation for
564 	 * the outbound transactions. Thus, PCIe address
565 	 * windows are not required.
566 	 */
567 	reg = advk_readl(pcie, PCIE_CORE_CTRL2_REG);
568 	reg |= PCIE_CORE_CTRL2_ADDRWIN_MAP_ENABLE;
569 	advk_writel(pcie, reg, PCIE_CORE_CTRL2_REG);
570 
571 	/*
572 	 * Bypass the address window mapping for PIO:
573 	 * Since PIO access already contains all required
574 	 * info over AXI interface by PIO registers, the
575 	 * address window is not required.
576 	 */
577 	reg = advk_readl(pcie, PIO_CTRL);
578 	reg |= PIO_CTRL_ADDR_WIN_DISABLE;
579 	advk_writel(pcie, reg, PIO_CTRL);
580 
581 	/* Start link training */
582 	reg = advk_readl(pcie, PCIE_CORE_LINK_CTRL_STAT_REG);
583 	reg |= PCIE_CORE_LINK_TRAINING;
584 	advk_writel(pcie, reg, PCIE_CORE_LINK_CTRL_STAT_REG);
585 
586 	/* Wait for PCIe link up */
587 	if (pcie_advk_wait_for_link(pcie))
588 		return -ENXIO;
589 
590 	reg = advk_readl(pcie, PCIE_CORE_CMD_STATUS_REG);
591 	reg |= PCIE_CORE_CMD_MEM_ACCESS_EN |
592 		PCIE_CORE_CMD_IO_ACCESS_EN |
593 		PCIE_CORE_CMD_MEM_IO_REQ_EN;
594 	advk_writel(pcie, reg, PCIE_CORE_CMD_STATUS_REG);
595 
596 	return 0;
597 }
598 
599 /**
600  * pcie_advk_probe() - Probe the PCIe bus for active link
601  *
602  * @dev: A pointer to the device being operated on
603  *
604  * Probe for an active link on the PCIe bus and configure the controller
605  * to enable this port.
606  *
607  * Return: 0 on success, else -ENODEV
608  */
pcie_advk_probe(struct udevice * dev)609 static int pcie_advk_probe(struct udevice *dev)
610 {
611 	struct pcie_advk *pcie = dev_get_priv(dev);
612 
613 #ifdef CONFIG_DM_GPIO
614 	struct gpio_desc reset_gpio;
615 
616 	gpio_request_by_name(dev, "reset-gpio", 0, &reset_gpio,
617 			     GPIOD_IS_OUT);
618 	/*
619 	 * Issue reset to add-in card through the dedicated GPIO.
620 	 * Some boards are connecting the card reset pin to common system
621 	 * reset wire and others are using separate GPIO port.
622 	 * In the last case we have to release a reset of the addon card
623 	 * using this GPIO.
624 	 *
625 	 * FIX-ME:
626 	 *     The PCIe RESET signal is not supposed to be released along
627 	 *     with the SOC RESET signal. It should be lowered as early as
628 	 *     possible before PCIe PHY initialization. Moreover, the PCIe
629 	 *     clock should be gated as well.
630 	 */
631 	if (dm_gpio_is_valid(&reset_gpio)) {
632 		dev_dbg(pcie->dev, "Toggle PCIE Reset GPIO ...\n");
633 		dm_gpio_set_value(&reset_gpio, 0);
634 		mdelay(200);
635 		dm_gpio_set_value(&reset_gpio, 1);
636 	}
637 #else
638 	dev_dbg(pcie->dev, "PCIE Reset on GPIO support is missing\n");
639 #endif /* CONFIG_DM_GPIO */
640 
641 	pcie->first_busno = dev->seq;
642 	pcie->dev = pci_get_controller(dev);
643 
644 	return pcie_advk_setup_hw(pcie);
645 }
646 
647 /**
648  * pcie_advk_ofdata_to_platdata() - Translate from DT to device state
649  *
650  * @dev: A pointer to the device being operated on
651  *
652  * Translate relevant data from the device tree pertaining to device @dev into
653  * state that the driver will later make use of. This state is stored in the
654  * device's private data structure.
655  *
656  * Return: 0 on success, else -EINVAL
657  */
pcie_advk_ofdata_to_platdata(struct udevice * dev)658 static int pcie_advk_ofdata_to_platdata(struct udevice *dev)
659 {
660 	struct pcie_advk *pcie = dev_get_priv(dev);
661 
662 	/* Get the register base address */
663 	pcie->base = (void *)dev_read_addr_index(dev, 0);
664 	if ((fdt_addr_t)pcie->base == FDT_ADDR_T_NONE)
665 		return -EINVAL;
666 
667 	return 0;
668 }
669 
670 static const struct dm_pci_ops pcie_advk_ops = {
671 	.read_config	= pcie_advk_read_config,
672 	.write_config	= pcie_advk_write_config,
673 };
674 
675 static const struct udevice_id pcie_advk_ids[] = {
676 	{ .compatible = "marvell,armada-37xx-pcie" },
677 	{ }
678 };
679 
680 U_BOOT_DRIVER(pcie_advk) = {
681 	.name			= "pcie_advk",
682 	.id			= UCLASS_PCI,
683 	.of_match		= pcie_advk_ids,
684 	.ops			= &pcie_advk_ops,
685 	.ofdata_to_platdata	= pcie_advk_ofdata_to_platdata,
686 	.probe			= pcie_advk_probe,
687 	.priv_auto_alloc_size	= sizeof(struct pcie_advk),
688 };
689