1 // SPDX-License-Identifier: MIT 2 #ifndef YELLOW_CARP_OFFSET_H 3 #define YELLOW_CARP_OFFSET_H 4 5 6 #define MAX_INSTANCE 7 7 #define MAX_SEGMENT 6 8 9 10 struct IP_BASE_INSTANCE { 11 unsigned int segment[MAX_SEGMENT]; 12 } __maybe_unused; 13 14 struct IP_BASE { 15 struct IP_BASE_INSTANCE instance[MAX_INSTANCE]; 16 } __maybe_unused; 17 18 19 static const struct IP_BASE ACP_BASE = { { { { 0x02403800, 0x00480000, 0, 0, 0, 0 } }, 20 { { 0, 0, 0, 0, 0, 0 } }, 21 { { 0, 0, 0, 0, 0, 0 } }, 22 { { 0, 0, 0, 0, 0, 0 } }, 23 { { 0, 0, 0, 0, 0, 0 } }, 24 { { 0, 0, 0, 0, 0, 0 } }, 25 { { 0, 0, 0, 0, 0, 0 } } } }; 26 static const struct IP_BASE ATHUB_BASE = { { { { 0x00000C00, 0x00013300, 0x02408C00, 0, 0, 0 } }, 27 { { 0, 0, 0, 0, 0, 0 } }, 28 { { 0, 0, 0, 0, 0, 0 } }, 29 { { 0, 0, 0, 0, 0, 0 } }, 30 { { 0, 0, 0, 0, 0, 0 } }, 31 { { 0, 0, 0, 0, 0, 0 } }, 32 { { 0, 0, 0, 0, 0, 0 } } } }; 33 static const struct IP_BASE CLK_BASE = { { { { 0x00016C00, 0x02401800, 0, 0, 0, 0 } }, 34 { { 0x00016E00, 0x02401C00, 0, 0, 0, 0 } }, 35 { { 0x00017000, 0x02402000, 0, 0, 0, 0 } }, 36 { { 0x00017200, 0x02402400, 0, 0, 0, 0 } }, 37 { { 0x0001B000, 0x0242D800, 0, 0, 0, 0 } }, 38 { { 0x0001B200, 0x0242DC00, 0, 0, 0, 0 } }, 39 { { 0x0001B400, 0x0242E000, 0, 0, 0, 0 } } } }; 40 static const struct IP_BASE DBGU_IO_BASE = { { { { 0x000001E0, 0x00000260, 0x00000280, 0x0240B400, 0x02413C00, 0x02416000 } }, 41 { { 0, 0, 0, 0, 0, 0 } }, 42 { { 0, 0, 0, 0, 0, 0 } }, 43 { { 0, 0, 0, 0, 0, 0 } }, 44 { { 0, 0, 0, 0, 0, 0 } }, 45 { { 0, 0, 0, 0, 0, 0 } }, 46 { { 0, 0, 0, 0, 0, 0 } } } }; 47 static const struct IP_BASE DCN_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, 48 { { 0, 0, 0, 0, 0, 0 } }, 49 { { 0, 0, 0, 0, 0, 0 } }, 50 { { 0, 0, 0, 0, 0, 0 } }, 51 { { 0, 0, 0, 0, 0, 0 } }, 52 { { 0, 0, 0, 0, 0, 0 } }, 53 { { 0, 0, 0, 0, 0, 0 } } } }; 54 static const struct IP_BASE DPCS_BASE = { { { { 0x00000012, 0x000000C0, 0x000034C0, 0x00009000, 0x02403C00, 0 } }, 55 { { 0, 0, 0, 0, 0, 0 } }, 56 { { 0, 0, 0, 0, 0, 0 } }, 57 { { 0, 0, 0, 0, 0, 0 } }, 58 { { 0, 0, 0, 0, 0, 0 } }, 59 { { 0, 0, 0, 0, 0, 0 } }, 60 { { 0, 0, 0, 0, 0, 0 } } } }; 61 static const struct IP_BASE DF_BASE = { { { { 0x00007000, 0x0240B800, 0x02447800, 0x00C00000, 0x03640000, 0 } }, 62 { { 0, 0, 0, 0, 0, 0 } }, 63 { { 0, 0, 0, 0, 0, 0 } }, 64 { { 0, 0, 0, 0, 0, 0 } }, 65 { { 0, 0, 0, 0, 0, 0 } }, 66 { { 0, 0, 0, 0, 0, 0 } }, 67 { { 0, 0, 0, 0, 0, 0 } } } }; 68 static const struct IP_BASE FCH_BASE = { { { { 0x0240C000, 0x00B40000, 0x11000000, 0, 0, 0 } }, 69 { { 0, 0, 0, 0, 0, 0 } }, 70 { { 0, 0, 0, 0, 0, 0 } }, 71 { { 0, 0, 0, 0, 0, 0 } }, 72 { { 0, 0, 0, 0, 0, 0 } }, 73 { { 0, 0, 0, 0, 0, 0 } }, 74 { { 0, 0, 0, 0, 0, 0 } } } }; 75 static const struct IP_BASE FUSE_BASE = { { { { 0x00017400, 0x02401400, 0, 0, 0, 0 } }, 76 { { 0, 0, 0, 0, 0, 0 } }, 77 { { 0, 0, 0, 0, 0, 0 } }, 78 { { 0, 0, 0, 0, 0, 0 } }, 79 { { 0, 0, 0, 0, 0, 0 } }, 80 { { 0, 0, 0, 0, 0, 0 } }, 81 { { 0, 0, 0, 0, 0, 0 } } } }; 82 static const struct IP_BASE GC_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } }, 83 { { 0, 0, 0, 0, 0, 0 } }, 84 { { 0, 0, 0, 0, 0, 0 } }, 85 { { 0, 0, 0, 0, 0, 0 } }, 86 { { 0, 0, 0, 0, 0, 0 } }, 87 { { 0, 0, 0, 0, 0, 0 } }, 88 { { 0, 0, 0, 0, 0, 0 } } } }; 89 static const struct IP_BASE HDP_BASE = { { { { 0x00000F20, 0x0240A400, 0, 0, 0, 0 } }, 90 { { 0, 0, 0, 0, 0, 0 } }, 91 { { 0, 0, 0, 0, 0, 0 } }, 92 { { 0, 0, 0, 0, 0, 0 } }, 93 { { 0, 0, 0, 0, 0, 0 } }, 94 { { 0, 0, 0, 0, 0, 0 } }, 95 { { 0, 0, 0, 0, 0, 0 } } } }; 96 static const struct IP_BASE IOHC0_BASE = { { { { 0x00010000, 0x02406000, 0x04EC0000, 0, 0, 0 } }, 97 { { 0, 0, 0, 0, 0, 0 } }, 98 { { 0, 0, 0, 0, 0, 0 } }, 99 { { 0, 0, 0, 0, 0, 0 } }, 100 { { 0, 0, 0, 0, 0, 0 } }, 101 { { 0, 0, 0, 0, 0, 0 } }, 102 { { 0, 0, 0, 0, 0, 0 } } } }; 103 static const struct IP_BASE MMHUB_BASE = { { { { 0x00013200, 0x0001A000, 0x02408800, 0, 0, 0 } }, 104 { { 0, 0, 0, 0, 0, 0 } }, 105 { { 0, 0, 0, 0, 0, 0 } }, 106 { { 0, 0, 0, 0, 0, 0 } }, 107 { { 0, 0, 0, 0, 0, 0 } }, 108 { { 0, 0, 0, 0, 0, 0 } }, 109 { { 0, 0, 0, 0, 0, 0 } } } }; 110 static const struct IP_BASE MP0_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } }, 111 { { 0, 0, 0, 0, 0, 0 } }, 112 { { 0, 0, 0, 0, 0, 0 } }, 113 { { 0, 0, 0, 0, 0, 0 } }, 114 { { 0, 0, 0, 0, 0, 0 } }, 115 { { 0, 0, 0, 0, 0, 0 } }, 116 { { 0, 0, 0, 0, 0, 0 } } } }; 117 static const struct IP_BASE MP1_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } }, 118 { { 0, 0, 0, 0, 0, 0 } }, 119 { { 0, 0, 0, 0, 0, 0 } }, 120 { { 0, 0, 0, 0, 0, 0 } }, 121 { { 0, 0, 0, 0, 0, 0 } }, 122 { { 0, 0, 0, 0, 0, 0 } }, 123 { { 0, 0, 0, 0, 0, 0 } } } }; 124 static const struct IP_BASE MP2_BASE = { { { { 0x00016000, 0x0243FC00, 0x00DC0000, 0x00E00000, 0x00E40000, 0 } }, 125 { { 0, 0, 0, 0, 0, 0 } }, 126 { { 0, 0, 0, 0, 0, 0 } }, 127 { { 0, 0, 0, 0, 0, 0 } }, 128 { { 0, 0, 0, 0, 0, 0 } }, 129 { { 0, 0, 0, 0, 0, 0 } }, 130 { { 0, 0, 0, 0, 0, 0 } } } }; 131 static const struct IP_BASE NBIO_BASE = { { { { 0x00000000, 0x00000014, 0x00000D20, 0x00010400, 0x0241B000, 0x04040000 } }, 132 { { 0, 0, 0, 0, 0, 0 } }, 133 { { 0, 0, 0, 0, 0, 0 } }, 134 { { 0, 0, 0, 0, 0, 0 } }, 135 { { 0, 0, 0, 0, 0, 0 } }, 136 { { 0, 0, 0, 0, 0, 0 } }, 137 { { 0, 0, 0, 0, 0, 0 } } } }; 138 static const struct IP_BASE OSSSYS_BASE = { { { { 0x000010A0, 0x0240A000, 0, 0, 0, 0 } }, 139 { { 0, 0, 0, 0, 0, 0 } }, 140 { { 0, 0, 0, 0, 0, 0 } }, 141 { { 0, 0, 0, 0, 0, 0 } }, 142 { { 0, 0, 0, 0, 0, 0 } }, 143 { { 0, 0, 0, 0, 0, 0 } }, 144 { { 0, 0, 0, 0, 0, 0 } } } }; 145 static const struct IP_BASE PCIE_BASE = { { { { 0x02411800, 0x04440000, 0, 0, 0, 0 } }, 146 { { 0x02411C00, 0x04480000, 0, 0, 0, 0 } }, 147 { { 0x02412000, 0x044C0000, 0, 0, 0, 0 } }, 148 { { 0x02412400, 0x04500000, 0, 0, 0, 0 } }, 149 { { 0, 0, 0, 0, 0, 0 } }, 150 { { 0, 0, 0, 0, 0, 0 } }, 151 { { 0, 0, 0, 0, 0, 0 } } } }; 152 static const struct IP_BASE SDMA0_BASE = { { { { 0x00001260, 0x0000A000, 0x02402C00, 0, 0, 0 } }, 153 { { 0, 0, 0, 0, 0, 0 } }, 154 { { 0, 0, 0, 0, 0, 0 } }, 155 { { 0, 0, 0, 0, 0, 0 } }, 156 { { 0, 0, 0, 0, 0, 0 } }, 157 { { 0, 0, 0, 0, 0, 0 } }, 158 { { 0, 0, 0, 0, 0, 0 } } } }; 159 static const struct IP_BASE SMUIO_BASE = { { { { 0x00016800, 0x00016A00, 0x02401000, 0x00440000, 0, 0 } }, 160 { { 0x0001BC00, 0x0242D400, 0, 0, 0, 0 } }, 161 { { 0, 0, 0, 0, 0, 0 } }, 162 { { 0, 0, 0, 0, 0, 0 } }, 163 { { 0, 0, 0, 0, 0, 0 } }, 164 { { 0, 0, 0, 0, 0, 0 } }, 165 { { 0, 0, 0, 0, 0, 0 } } } }; 166 static const struct IP_BASE THM_BASE = { { { { 0x00016600, 0x02400C00, 0, 0, 0, 0 } }, 167 { { 0, 0, 0, 0, 0, 0 } }, 168 { { 0, 0, 0, 0, 0, 0 } }, 169 { { 0, 0, 0, 0, 0, 0 } }, 170 { { 0, 0, 0, 0, 0, 0 } }, 171 { { 0, 0, 0, 0, 0, 0 } }, 172 { { 0, 0, 0, 0, 0, 0 } } } }; 173 static const struct IP_BASE UMC_BASE = { { { { 0x00014000, 0x00054000, 0x02425800, 0x02425C00, 0, 0 } }, 174 { { 0x00094000, 0x000D4000, 0x02426000, 0x02426400, 0, 0 } }, 175 { { 0, 0, 0, 0, 0, 0 } }, 176 { { 0, 0, 0, 0, 0, 0 } }, 177 { { 0, 0, 0, 0, 0, 0 } }, 178 { { 0, 0, 0, 0, 0, 0 } }, 179 { { 0, 0, 0, 0, 0, 0 } } } }; 180 static const struct IP_BASE VCN_BASE = { { { { 0x00007800, 0x00007E00, 0x02403000, 0, 0, 0 } }, 181 { { 0, 0, 0, 0, 0, 0 } }, 182 { { 0, 0, 0, 0, 0, 0 } }, 183 { { 0, 0, 0, 0, 0, 0 } }, 184 { { 0, 0, 0, 0, 0, 0 } }, 185 { { 0, 0, 0, 0, 0, 0 } }, 186 { { 0, 0, 0, 0, 0, 0 } } } }; 187 188 189 #define ACP_BASE__INST0_SEG0 0x02403800 190 #define ACP_BASE__INST0_SEG1 0x00480000 191 #define ACP_BASE__INST0_SEG2 0 192 #define ACP_BASE__INST0_SEG3 0 193 #define ACP_BASE__INST0_SEG4 0 194 #define ACP_BASE__INST0_SEG5 0 195 196 #define ACP_BASE__INST1_SEG0 0 197 #define ACP_BASE__INST1_SEG1 0 198 #define ACP_BASE__INST1_SEG2 0 199 #define ACP_BASE__INST1_SEG3 0 200 #define ACP_BASE__INST1_SEG4 0 201 #define ACP_BASE__INST1_SEG5 0 202 203 #define ACP_BASE__INST2_SEG0 0 204 #define ACP_BASE__INST2_SEG1 0 205 #define ACP_BASE__INST2_SEG2 0 206 #define ACP_BASE__INST2_SEG3 0 207 #define ACP_BASE__INST2_SEG4 0 208 #define ACP_BASE__INST2_SEG5 0 209 210 #define ACP_BASE__INST3_SEG0 0 211 #define ACP_BASE__INST3_SEG1 0 212 #define ACP_BASE__INST3_SEG2 0 213 #define ACP_BASE__INST3_SEG3 0 214 #define ACP_BASE__INST3_SEG4 0 215 #define ACP_BASE__INST3_SEG5 0 216 217 #define ACP_BASE__INST4_SEG0 0 218 #define ACP_BASE__INST4_SEG1 0 219 #define ACP_BASE__INST4_SEG2 0 220 #define ACP_BASE__INST4_SEG3 0 221 #define ACP_BASE__INST4_SEG4 0 222 #define ACP_BASE__INST4_SEG5 0 223 224 #define ACP_BASE__INST5_SEG0 0 225 #define ACP_BASE__INST5_SEG1 0 226 #define ACP_BASE__INST5_SEG2 0 227 #define ACP_BASE__INST5_SEG3 0 228 #define ACP_BASE__INST5_SEG4 0 229 #define ACP_BASE__INST5_SEG5 0 230 231 #define ACP_BASE__INST6_SEG0 0 232 #define ACP_BASE__INST6_SEG1 0 233 #define ACP_BASE__INST6_SEG2 0 234 #define ACP_BASE__INST6_SEG3 0 235 #define ACP_BASE__INST6_SEG4 0 236 #define ACP_BASE__INST6_SEG5 0 237 238 #define ATHUB_BASE__INST0_SEG0 0x00000C00 239 #define ATHUB_BASE__INST0_SEG1 0x00013300 240 #define ATHUB_BASE__INST0_SEG2 0x02408C00 241 #define ATHUB_BASE__INST0_SEG3 0 242 #define ATHUB_BASE__INST0_SEG4 0 243 #define ATHUB_BASE__INST0_SEG5 0 244 245 #define ATHUB_BASE__INST1_SEG0 0 246 #define ATHUB_BASE__INST1_SEG1 0 247 #define ATHUB_BASE__INST1_SEG2 0 248 #define ATHUB_BASE__INST1_SEG3 0 249 #define ATHUB_BASE__INST1_SEG4 0 250 #define ATHUB_BASE__INST1_SEG5 0 251 252 #define ATHUB_BASE__INST2_SEG0 0 253 #define ATHUB_BASE__INST2_SEG1 0 254 #define ATHUB_BASE__INST2_SEG2 0 255 #define ATHUB_BASE__INST2_SEG3 0 256 #define ATHUB_BASE__INST2_SEG4 0 257 #define ATHUB_BASE__INST2_SEG5 0 258 259 #define ATHUB_BASE__INST3_SEG0 0 260 #define ATHUB_BASE__INST3_SEG1 0 261 #define ATHUB_BASE__INST3_SEG2 0 262 #define ATHUB_BASE__INST3_SEG3 0 263 #define ATHUB_BASE__INST3_SEG4 0 264 #define ATHUB_BASE__INST3_SEG5 0 265 266 #define ATHUB_BASE__INST4_SEG0 0 267 #define ATHUB_BASE__INST4_SEG1 0 268 #define ATHUB_BASE__INST4_SEG2 0 269 #define ATHUB_BASE__INST4_SEG3 0 270 #define ATHUB_BASE__INST4_SEG4 0 271 #define ATHUB_BASE__INST4_SEG5 0 272 273 #define ATHUB_BASE__INST5_SEG0 0 274 #define ATHUB_BASE__INST5_SEG1 0 275 #define ATHUB_BASE__INST5_SEG2 0 276 #define ATHUB_BASE__INST5_SEG3 0 277 #define ATHUB_BASE__INST5_SEG4 0 278 #define ATHUB_BASE__INST5_SEG5 0 279 280 #define ATHUB_BASE__INST6_SEG0 0 281 #define ATHUB_BASE__INST6_SEG1 0 282 #define ATHUB_BASE__INST6_SEG2 0 283 #define ATHUB_BASE__INST6_SEG3 0 284 #define ATHUB_BASE__INST6_SEG4 0 285 #define ATHUB_BASE__INST6_SEG5 0 286 287 #define CLK_BASE__INST0_SEG0 0x00016C00 288 #define CLK_BASE__INST0_SEG1 0x02401800 289 #define CLK_BASE__INST0_SEG2 0 290 #define CLK_BASE__INST0_SEG3 0 291 #define CLK_BASE__INST0_SEG4 0 292 #define CLK_BASE__INST0_SEG5 0 293 294 #define CLK_BASE__INST1_SEG0 0x00016E00 295 #define CLK_BASE__INST1_SEG1 0x02401C00 296 #define CLK_BASE__INST1_SEG2 0 297 #define CLK_BASE__INST1_SEG3 0 298 #define CLK_BASE__INST1_SEG4 0 299 #define CLK_BASE__INST1_SEG5 0 300 301 #define CLK_BASE__INST2_SEG0 0x00017000 302 #define CLK_BASE__INST2_SEG1 0x02402000 303 #define CLK_BASE__INST2_SEG2 0 304 #define CLK_BASE__INST2_SEG3 0 305 #define CLK_BASE__INST2_SEG4 0 306 #define CLK_BASE__INST2_SEG5 0 307 308 #define CLK_BASE__INST3_SEG0 0x00017200 309 #define CLK_BASE__INST3_SEG1 0x02402400 310 #define CLK_BASE__INST3_SEG2 0 311 #define CLK_BASE__INST3_SEG3 0 312 #define CLK_BASE__INST3_SEG4 0 313 #define CLK_BASE__INST3_SEG5 0 314 315 #define CLK_BASE__INST4_SEG0 0x0001B000 316 #define CLK_BASE__INST4_SEG1 0x0242D800 317 #define CLK_BASE__INST4_SEG2 0 318 #define CLK_BASE__INST4_SEG3 0 319 #define CLK_BASE__INST4_SEG4 0 320 #define CLK_BASE__INST4_SEG5 0 321 322 #define CLK_BASE__INST5_SEG0 0x0001B200 323 #define CLK_BASE__INST5_SEG1 0x0242DC00 324 #define CLK_BASE__INST5_SEG2 0 325 #define CLK_BASE__INST5_SEG3 0 326 #define CLK_BASE__INST5_SEG4 0 327 #define CLK_BASE__INST5_SEG5 0 328 329 #define CLK_BASE__INST6_SEG0 0x0001B400 330 #define CLK_BASE__INST6_SEG1 0x0242E000 331 #define CLK_BASE__INST6_SEG2 0 332 #define CLK_BASE__INST6_SEG3 0 333 #define CLK_BASE__INST6_SEG4 0 334 #define CLK_BASE__INST6_SEG5 0 335 336 #define DBGU_IO_BASE__INST0_SEG0 0x000001E0 337 #define DBGU_IO_BASE__INST0_SEG1 0x00000260 338 #define DBGU_IO_BASE__INST0_SEG2 0x00000280 339 #define DBGU_IO_BASE__INST0_SEG3 0x0240B400 340 #define DBGU_IO_BASE__INST0_SEG4 0x02413C00 341 #define DBGU_IO_BASE__INST0_SEG5 0x02416000 342 343 #define DBGU_IO_BASE__INST1_SEG0 0 344 #define DBGU_IO_BASE__INST1_SEG1 0 345 #define DBGU_IO_BASE__INST1_SEG2 0 346 #define DBGU_IO_BASE__INST1_SEG3 0 347 #define DBGU_IO_BASE__INST1_SEG4 0 348 #define DBGU_IO_BASE__INST1_SEG5 0 349 350 #define DBGU_IO_BASE__INST2_SEG0 0 351 #define DBGU_IO_BASE__INST2_SEG1 0 352 #define DBGU_IO_BASE__INST2_SEG2 0 353 #define DBGU_IO_BASE__INST2_SEG3 0 354 #define DBGU_IO_BASE__INST2_SEG4 0 355 #define DBGU_IO_BASE__INST2_SEG5 0 356 357 #define DBGU_IO_BASE__INST3_SEG0 0 358 #define DBGU_IO_BASE__INST3_SEG1 0 359 #define DBGU_IO_BASE__INST3_SEG2 0 360 #define DBGU_IO_BASE__INST3_SEG3 0 361 #define DBGU_IO_BASE__INST3_SEG4 0 362 #define DBGU_IO_BASE__INST3_SEG5 0 363 364 #define DBGU_IO_BASE__INST4_SEG0 0 365 #define DBGU_IO_BASE__INST4_SEG1 0 366 #define DBGU_IO_BASE__INST4_SEG2 0 367 #define DBGU_IO_BASE__INST4_SEG3 0 368 #define DBGU_IO_BASE__INST4_SEG4 0 369 #define DBGU_IO_BASE__INST4_SEG5 0 370 371 #define DBGU_IO_BASE__INST5_SEG0 0 372 #define DBGU_IO_BASE__INST5_SEG1 0 373 #define DBGU_IO_BASE__INST5_SEG2 0 374 #define DBGU_IO_BASE__INST5_SEG3 0 375 #define DBGU_IO_BASE__INST5_SEG4 0 376 #define DBGU_IO_BASE__INST5_SEG5 0 377 378 #define DBGU_IO_BASE__INST6_SEG0 0 379 #define DBGU_IO_BASE__INST6_SEG1 0 380 #define DBGU_IO_BASE__INST6_SEG2 0 381 #define DBGU_IO_BASE__INST6_SEG3 0 382 #define DBGU_IO_BASE__INST6_SEG4 0 383 #define DBGU_IO_BASE__INST6_SEG5 0 384 385 #define DCN_BASE__INST0_SEG0 0x00000012 386 #define DCN_BASE__INST0_SEG1 0x000000C0 387 #define DCN_BASE__INST0_SEG2 0x000034C0 388 #define DCN_BASE__INST0_SEG3 0x00009000 389 #define DCN_BASE__INST0_SEG4 0x02403C00 390 #define DCN_BASE__INST0_SEG5 0 391 392 #define DCN_BASE__INST1_SEG0 0 393 #define DCN_BASE__INST1_SEG1 0 394 #define DCN_BASE__INST1_SEG2 0 395 #define DCN_BASE__INST1_SEG3 0 396 #define DCN_BASE__INST1_SEG4 0 397 #define DCN_BASE__INST1_SEG5 0 398 399 #define DCN_BASE__INST2_SEG0 0 400 #define DCN_BASE__INST2_SEG1 0 401 #define DCN_BASE__INST2_SEG2 0 402 #define DCN_BASE__INST2_SEG3 0 403 #define DCN_BASE__INST2_SEG4 0 404 #define DCN_BASE__INST2_SEG5 0 405 406 #define DCN_BASE__INST3_SEG0 0 407 #define DCN_BASE__INST3_SEG1 0 408 #define DCN_BASE__INST3_SEG2 0 409 #define DCN_BASE__INST3_SEG3 0 410 #define DCN_BASE__INST3_SEG4 0 411 #define DCN_BASE__INST3_SEG5 0 412 413 #define DCN_BASE__INST4_SEG0 0 414 #define DCN_BASE__INST4_SEG1 0 415 #define DCN_BASE__INST4_SEG2 0 416 #define DCN_BASE__INST4_SEG3 0 417 #define DCN_BASE__INST4_SEG4 0 418 #define DCN_BASE__INST4_SEG5 0 419 420 #define DCN_BASE__INST5_SEG0 0 421 #define DCN_BASE__INST5_SEG1 0 422 #define DCN_BASE__INST5_SEG2 0 423 #define DCN_BASE__INST5_SEG3 0 424 #define DCN_BASE__INST5_SEG4 0 425 #define DCN_BASE__INST5_SEG5 0 426 427 #define DCN_BASE__INST6_SEG0 0 428 #define DCN_BASE__INST6_SEG1 0 429 #define DCN_BASE__INST6_SEG2 0 430 #define DCN_BASE__INST6_SEG3 0 431 #define DCN_BASE__INST6_SEG4 0 432 #define DCN_BASE__INST6_SEG5 0 433 434 #define DPCS_BASE__INST0_SEG0 0x00000012 435 #define DPCS_BASE__INST0_SEG1 0x000000C0 436 #define DPCS_BASE__INST0_SEG2 0x000034C0 437 #define DPCS_BASE__INST0_SEG3 0x00009000 438 #define DPCS_BASE__INST0_SEG4 0x02403C00 439 #define DPCS_BASE__INST0_SEG5 0 440 441 #define DPCS_BASE__INST1_SEG0 0 442 #define DPCS_BASE__INST1_SEG1 0 443 #define DPCS_BASE__INST1_SEG2 0 444 #define DPCS_BASE__INST1_SEG3 0 445 #define DPCS_BASE__INST1_SEG4 0 446 #define DPCS_BASE__INST1_SEG5 0 447 448 #define DPCS_BASE__INST2_SEG0 0 449 #define DPCS_BASE__INST2_SEG1 0 450 #define DPCS_BASE__INST2_SEG2 0 451 #define DPCS_BASE__INST2_SEG3 0 452 #define DPCS_BASE__INST2_SEG4 0 453 #define DPCS_BASE__INST2_SEG5 0 454 455 #define DPCS_BASE__INST3_SEG0 0 456 #define DPCS_BASE__INST3_SEG1 0 457 #define DPCS_BASE__INST3_SEG2 0 458 #define DPCS_BASE__INST3_SEG3 0 459 #define DPCS_BASE__INST3_SEG4 0 460 #define DPCS_BASE__INST3_SEG5 0 461 462 #define DPCS_BASE__INST4_SEG0 0 463 #define DPCS_BASE__INST4_SEG1 0 464 #define DPCS_BASE__INST4_SEG2 0 465 #define DPCS_BASE__INST4_SEG3 0 466 #define DPCS_BASE__INST4_SEG4 0 467 #define DPCS_BASE__INST4_SEG5 0 468 469 #define DPCS_BASE__INST5_SEG0 0 470 #define DPCS_BASE__INST5_SEG1 0 471 #define DPCS_BASE__INST5_SEG2 0 472 #define DPCS_BASE__INST5_SEG3 0 473 #define DPCS_BASE__INST5_SEG4 0 474 #define DPCS_BASE__INST5_SEG5 0 475 476 #define DPCS_BASE__INST6_SEG0 0 477 #define DPCS_BASE__INST6_SEG1 0 478 #define DPCS_BASE__INST6_SEG2 0 479 #define DPCS_BASE__INST6_SEG3 0 480 #define DPCS_BASE__INST6_SEG4 0 481 #define DPCS_BASE__INST6_SEG5 0 482 483 #define DF_BASE__INST0_SEG0 0x00007000 484 #define DF_BASE__INST0_SEG1 0x0240B800 485 #define DF_BASE__INST0_SEG2 0x02447800 486 #define DF_BASE__INST0_SEG3 0x00C00000 487 #define DF_BASE__INST0_SEG4 0x03640000 488 #define DF_BASE__INST0_SEG5 0 489 490 #define DF_BASE__INST1_SEG0 0 491 #define DF_BASE__INST1_SEG1 0 492 #define DF_BASE__INST1_SEG2 0 493 #define DF_BASE__INST1_SEG3 0 494 #define DF_BASE__INST1_SEG4 0 495 #define DF_BASE__INST1_SEG5 0 496 497 #define DF_BASE__INST2_SEG0 0 498 #define DF_BASE__INST2_SEG1 0 499 #define DF_BASE__INST2_SEG2 0 500 #define DF_BASE__INST2_SEG3 0 501 #define DF_BASE__INST2_SEG4 0 502 #define DF_BASE__INST2_SEG5 0 503 504 #define DF_BASE__INST3_SEG0 0 505 #define DF_BASE__INST3_SEG1 0 506 #define DF_BASE__INST3_SEG2 0 507 #define DF_BASE__INST3_SEG3 0 508 #define DF_BASE__INST3_SEG4 0 509 #define DF_BASE__INST3_SEG5 0 510 511 #define DF_BASE__INST4_SEG0 0 512 #define DF_BASE__INST4_SEG1 0 513 #define DF_BASE__INST4_SEG2 0 514 #define DF_BASE__INST4_SEG3 0 515 #define DF_BASE__INST4_SEG4 0 516 #define DF_BASE__INST4_SEG5 0 517 518 #define DF_BASE__INST5_SEG0 0 519 #define DF_BASE__INST5_SEG1 0 520 #define DF_BASE__INST5_SEG2 0 521 #define DF_BASE__INST5_SEG3 0 522 #define DF_BASE__INST5_SEG4 0 523 #define DF_BASE__INST5_SEG5 0 524 525 #define DF_BASE__INST6_SEG0 0 526 #define DF_BASE__INST6_SEG1 0 527 #define DF_BASE__INST6_SEG2 0 528 #define DF_BASE__INST6_SEG3 0 529 #define DF_BASE__INST6_SEG4 0 530 #define DF_BASE__INST6_SEG5 0 531 532 #define FCH_BASE__INST0_SEG0 0x0240C000 533 #define FCH_BASE__INST0_SEG1 0x00B40000 534 #define FCH_BASE__INST0_SEG2 0x11000000 535 #define FCH_BASE__INST0_SEG3 0 536 #define FCH_BASE__INST0_SEG4 0 537 #define FCH_BASE__INST0_SEG5 0 538 539 #define FCH_BASE__INST1_SEG0 0 540 #define FCH_BASE__INST1_SEG1 0 541 #define FCH_BASE__INST1_SEG2 0 542 #define FCH_BASE__INST1_SEG3 0 543 #define FCH_BASE__INST1_SEG4 0 544 #define FCH_BASE__INST1_SEG5 0 545 546 #define FCH_BASE__INST2_SEG0 0 547 #define FCH_BASE__INST2_SEG1 0 548 #define FCH_BASE__INST2_SEG2 0 549 #define FCH_BASE__INST2_SEG3 0 550 #define FCH_BASE__INST2_SEG4 0 551 #define FCH_BASE__INST2_SEG5 0 552 553 #define FCH_BASE__INST3_SEG0 0 554 #define FCH_BASE__INST3_SEG1 0 555 #define FCH_BASE__INST3_SEG2 0 556 #define FCH_BASE__INST3_SEG3 0 557 #define FCH_BASE__INST3_SEG4 0 558 #define FCH_BASE__INST3_SEG5 0 559 560 #define FCH_BASE__INST4_SEG0 0 561 #define FCH_BASE__INST4_SEG1 0 562 #define FCH_BASE__INST4_SEG2 0 563 #define FCH_BASE__INST4_SEG3 0 564 #define FCH_BASE__INST4_SEG4 0 565 #define FCH_BASE__INST4_SEG5 0 566 567 #define FCH_BASE__INST5_SEG0 0 568 #define FCH_BASE__INST5_SEG1 0 569 #define FCH_BASE__INST5_SEG2 0 570 #define FCH_BASE__INST5_SEG3 0 571 #define FCH_BASE__INST5_SEG4 0 572 #define FCH_BASE__INST5_SEG5 0 573 574 #define FCH_BASE__INST6_SEG0 0 575 #define FCH_BASE__INST6_SEG1 0 576 #define FCH_BASE__INST6_SEG2 0 577 #define FCH_BASE__INST6_SEG3 0 578 #define FCH_BASE__INST6_SEG4 0 579 #define FCH_BASE__INST6_SEG5 0 580 581 #define FUSE_BASE__INST0_SEG0 0x00017400 582 #define FUSE_BASE__INST0_SEG1 0x02401400 583 #define FUSE_BASE__INST0_SEG2 0 584 #define FUSE_BASE__INST0_SEG3 0 585 #define FUSE_BASE__INST0_SEG4 0 586 #define FUSE_BASE__INST0_SEG5 0 587 588 #define FUSE_BASE__INST1_SEG0 0 589 #define FUSE_BASE__INST1_SEG1 0 590 #define FUSE_BASE__INST1_SEG2 0 591 #define FUSE_BASE__INST1_SEG3 0 592 #define FUSE_BASE__INST1_SEG4 0 593 #define FUSE_BASE__INST1_SEG5 0 594 595 #define FUSE_BASE__INST2_SEG0 0 596 #define FUSE_BASE__INST2_SEG1 0 597 #define FUSE_BASE__INST2_SEG2 0 598 #define FUSE_BASE__INST2_SEG3 0 599 #define FUSE_BASE__INST2_SEG4 0 600 #define FUSE_BASE__INST2_SEG5 0 601 602 #define FUSE_BASE__INST3_SEG0 0 603 #define FUSE_BASE__INST3_SEG1 0 604 #define FUSE_BASE__INST3_SEG2 0 605 #define FUSE_BASE__INST3_SEG3 0 606 #define FUSE_BASE__INST3_SEG4 0 607 #define FUSE_BASE__INST3_SEG5 0 608 609 #define FUSE_BASE__INST4_SEG0 0 610 #define FUSE_BASE__INST4_SEG1 0 611 #define FUSE_BASE__INST4_SEG2 0 612 #define FUSE_BASE__INST4_SEG3 0 613 #define FUSE_BASE__INST4_SEG4 0 614 #define FUSE_BASE__INST4_SEG5 0 615 616 #define FUSE_BASE__INST5_SEG0 0 617 #define FUSE_BASE__INST5_SEG1 0 618 #define FUSE_BASE__INST5_SEG2 0 619 #define FUSE_BASE__INST5_SEG3 0 620 #define FUSE_BASE__INST5_SEG4 0 621 #define FUSE_BASE__INST5_SEG5 0 622 623 #define FUSE_BASE__INST6_SEG0 0 624 #define FUSE_BASE__INST6_SEG1 0 625 #define FUSE_BASE__INST6_SEG2 0 626 #define FUSE_BASE__INST6_SEG3 0 627 #define FUSE_BASE__INST6_SEG4 0 628 #define FUSE_BASE__INST6_SEG5 0 629 630 #define GC_BASE__INST0_SEG0 0x00001260 631 #define GC_BASE__INST0_SEG1 0x0000A000 632 #define GC_BASE__INST0_SEG2 0x02402C00 633 #define GC_BASE__INST0_SEG3 0 634 #define GC_BASE__INST0_SEG4 0 635 #define GC_BASE__INST0_SEG5 0 636 637 #define GC_BASE__INST1_SEG0 0 638 #define GC_BASE__INST1_SEG1 0 639 #define GC_BASE__INST1_SEG2 0 640 #define GC_BASE__INST1_SEG3 0 641 #define GC_BASE__INST1_SEG4 0 642 #define GC_BASE__INST1_SEG5 0 643 644 #define GC_BASE__INST2_SEG0 0 645 #define GC_BASE__INST2_SEG1 0 646 #define GC_BASE__INST2_SEG2 0 647 #define GC_BASE__INST2_SEG3 0 648 #define GC_BASE__INST2_SEG4 0 649 #define GC_BASE__INST2_SEG5 0 650 651 #define GC_BASE__INST3_SEG0 0 652 #define GC_BASE__INST3_SEG1 0 653 #define GC_BASE__INST3_SEG2 0 654 #define GC_BASE__INST3_SEG3 0 655 #define GC_BASE__INST3_SEG4 0 656 #define GC_BASE__INST3_SEG5 0 657 658 #define GC_BASE__INST4_SEG0 0 659 #define GC_BASE__INST4_SEG1 0 660 #define GC_BASE__INST4_SEG2 0 661 #define GC_BASE__INST4_SEG3 0 662 #define GC_BASE__INST4_SEG4 0 663 #define GC_BASE__INST4_SEG5 0 664 665 #define GC_BASE__INST5_SEG0 0 666 #define GC_BASE__INST5_SEG1 0 667 #define GC_BASE__INST5_SEG2 0 668 #define GC_BASE__INST5_SEG3 0 669 #define GC_BASE__INST5_SEG4 0 670 #define GC_BASE__INST5_SEG5 0 671 672 #define GC_BASE__INST6_SEG0 0 673 #define GC_BASE__INST6_SEG1 0 674 #define GC_BASE__INST6_SEG2 0 675 #define GC_BASE__INST6_SEG3 0 676 #define GC_BASE__INST6_SEG4 0 677 #define GC_BASE__INST6_SEG5 0 678 679 #define HDP_BASE__INST0_SEG0 0x00000F20 680 #define HDP_BASE__INST0_SEG1 0x0240A400 681 #define HDP_BASE__INST0_SEG2 0 682 #define HDP_BASE__INST0_SEG3 0 683 #define HDP_BASE__INST0_SEG4 0 684 #define HDP_BASE__INST0_SEG5 0 685 686 #define HDP_BASE__INST1_SEG0 0 687 #define HDP_BASE__INST1_SEG1 0 688 #define HDP_BASE__INST1_SEG2 0 689 #define HDP_BASE__INST1_SEG3 0 690 #define HDP_BASE__INST1_SEG4 0 691 #define HDP_BASE__INST1_SEG5 0 692 693 #define HDP_BASE__INST2_SEG0 0 694 #define HDP_BASE__INST2_SEG1 0 695 #define HDP_BASE__INST2_SEG2 0 696 #define HDP_BASE__INST2_SEG3 0 697 #define HDP_BASE__INST2_SEG4 0 698 #define HDP_BASE__INST2_SEG5 0 699 700 #define HDP_BASE__INST3_SEG0 0 701 #define HDP_BASE__INST3_SEG1 0 702 #define HDP_BASE__INST3_SEG2 0 703 #define HDP_BASE__INST3_SEG3 0 704 #define HDP_BASE__INST3_SEG4 0 705 #define HDP_BASE__INST3_SEG5 0 706 707 #define HDP_BASE__INST4_SEG0 0 708 #define HDP_BASE__INST4_SEG1 0 709 #define HDP_BASE__INST4_SEG2 0 710 #define HDP_BASE__INST4_SEG3 0 711 #define HDP_BASE__INST4_SEG4 0 712 #define HDP_BASE__INST4_SEG5 0 713 714 #define HDP_BASE__INST5_SEG0 0 715 #define HDP_BASE__INST5_SEG1 0 716 #define HDP_BASE__INST5_SEG2 0 717 #define HDP_BASE__INST5_SEG3 0 718 #define HDP_BASE__INST5_SEG4 0 719 #define HDP_BASE__INST5_SEG5 0 720 721 #define HDP_BASE__INST6_SEG0 0 722 #define HDP_BASE__INST6_SEG1 0 723 #define HDP_BASE__INST6_SEG2 0 724 #define HDP_BASE__INST6_SEG3 0 725 #define HDP_BASE__INST6_SEG4 0 726 #define HDP_BASE__INST6_SEG5 0 727 728 #define IOHC0_BASE__INST0_SEG0 0x00010000 729 #define IOHC0_BASE__INST0_SEG1 0x02406000 730 #define IOHC0_BASE__INST0_SEG2 0x04EC0000 731 #define IOHC0_BASE__INST0_SEG3 0 732 #define IOHC0_BASE__INST0_SEG4 0 733 #define IOHC0_BASE__INST0_SEG5 0 734 735 #define IOHC0_BASE__INST1_SEG0 0 736 #define IOHC0_BASE__INST1_SEG1 0 737 #define IOHC0_BASE__INST1_SEG2 0 738 #define IOHC0_BASE__INST1_SEG3 0 739 #define IOHC0_BASE__INST1_SEG4 0 740 #define IOHC0_BASE__INST1_SEG5 0 741 742 #define IOHC0_BASE__INST2_SEG0 0 743 #define IOHC0_BASE__INST2_SEG1 0 744 #define IOHC0_BASE__INST2_SEG2 0 745 #define IOHC0_BASE__INST2_SEG3 0 746 #define IOHC0_BASE__INST2_SEG4 0 747 #define IOHC0_BASE__INST2_SEG5 0 748 749 #define IOHC0_BASE__INST3_SEG0 0 750 #define IOHC0_BASE__INST3_SEG1 0 751 #define IOHC0_BASE__INST3_SEG2 0 752 #define IOHC0_BASE__INST3_SEG3 0 753 #define IOHC0_BASE__INST3_SEG4 0 754 #define IOHC0_BASE__INST3_SEG5 0 755 756 #define IOHC0_BASE__INST4_SEG0 0 757 #define IOHC0_BASE__INST4_SEG1 0 758 #define IOHC0_BASE__INST4_SEG2 0 759 #define IOHC0_BASE__INST4_SEG3 0 760 #define IOHC0_BASE__INST4_SEG4 0 761 #define IOHC0_BASE__INST4_SEG5 0 762 763 #define IOHC0_BASE__INST5_SEG0 0 764 #define IOHC0_BASE__INST5_SEG1 0 765 #define IOHC0_BASE__INST5_SEG2 0 766 #define IOHC0_BASE__INST5_SEG3 0 767 #define IOHC0_BASE__INST5_SEG4 0 768 #define IOHC0_BASE__INST5_SEG5 0 769 770 #define IOHC0_BASE__INST6_SEG0 0 771 #define IOHC0_BASE__INST6_SEG1 0 772 #define IOHC0_BASE__INST6_SEG2 0 773 #define IOHC0_BASE__INST6_SEG3 0 774 #define IOHC0_BASE__INST6_SEG4 0 775 #define IOHC0_BASE__INST6_SEG5 0 776 777 #define MMHUB_BASE__INST0_SEG0 0x00013200 778 #define MMHUB_BASE__INST0_SEG1 0x0001A000 779 #define MMHUB_BASE__INST0_SEG2 0x02408800 780 #define MMHUB_BASE__INST0_SEG3 0 781 #define MMHUB_BASE__INST0_SEG4 0 782 #define MMHUB_BASE__INST0_SEG5 0 783 784 #define MMHUB_BASE__INST1_SEG0 0 785 #define MMHUB_BASE__INST1_SEG1 0 786 #define MMHUB_BASE__INST1_SEG2 0 787 #define MMHUB_BASE__INST1_SEG3 0 788 #define MMHUB_BASE__INST1_SEG4 0 789 #define MMHUB_BASE__INST1_SEG5 0 790 791 #define MMHUB_BASE__INST2_SEG0 0 792 #define MMHUB_BASE__INST2_SEG1 0 793 #define MMHUB_BASE__INST2_SEG2 0 794 #define MMHUB_BASE__INST2_SEG3 0 795 #define MMHUB_BASE__INST2_SEG4 0 796 #define MMHUB_BASE__INST2_SEG5 0 797 798 #define MMHUB_BASE__INST3_SEG0 0 799 #define MMHUB_BASE__INST3_SEG1 0 800 #define MMHUB_BASE__INST3_SEG2 0 801 #define MMHUB_BASE__INST3_SEG3 0 802 #define MMHUB_BASE__INST3_SEG4 0 803 #define MMHUB_BASE__INST3_SEG5 0 804 805 #define MMHUB_BASE__INST4_SEG0 0 806 #define MMHUB_BASE__INST4_SEG1 0 807 #define MMHUB_BASE__INST4_SEG2 0 808 #define MMHUB_BASE__INST4_SEG3 0 809 #define MMHUB_BASE__INST4_SEG4 0 810 #define MMHUB_BASE__INST4_SEG5 0 811 812 #define MMHUB_BASE__INST5_SEG0 0 813 #define MMHUB_BASE__INST5_SEG1 0 814 #define MMHUB_BASE__INST5_SEG2 0 815 #define MMHUB_BASE__INST5_SEG3 0 816 #define MMHUB_BASE__INST5_SEG4 0 817 #define MMHUB_BASE__INST5_SEG5 0 818 819 #define MMHUB_BASE__INST6_SEG0 0 820 #define MMHUB_BASE__INST6_SEG1 0 821 #define MMHUB_BASE__INST6_SEG2 0 822 #define MMHUB_BASE__INST6_SEG3 0 823 #define MMHUB_BASE__INST6_SEG4 0 824 #define MMHUB_BASE__INST6_SEG5 0 825 826 #define MP0_BASE__INST0_SEG0 0x00016000 827 #define MP0_BASE__INST0_SEG1 0x0243FC00 828 #define MP0_BASE__INST0_SEG2 0x00DC0000 829 #define MP0_BASE__INST0_SEG3 0x00E00000 830 #define MP0_BASE__INST0_SEG4 0x00E40000 831 #define MP0_BASE__INST0_SEG5 0 832 833 #define MP0_BASE__INST1_SEG0 0 834 #define MP0_BASE__INST1_SEG1 0 835 #define MP0_BASE__INST1_SEG2 0 836 #define MP0_BASE__INST1_SEG3 0 837 #define MP0_BASE__INST1_SEG4 0 838 #define MP0_BASE__INST1_SEG5 0 839 840 #define MP0_BASE__INST2_SEG0 0 841 #define MP0_BASE__INST2_SEG1 0 842 #define MP0_BASE__INST2_SEG2 0 843 #define MP0_BASE__INST2_SEG3 0 844 #define MP0_BASE__INST2_SEG4 0 845 #define MP0_BASE__INST2_SEG5 0 846 847 #define MP0_BASE__INST3_SEG0 0 848 #define MP0_BASE__INST3_SEG1 0 849 #define MP0_BASE__INST3_SEG2 0 850 #define MP0_BASE__INST3_SEG3 0 851 #define MP0_BASE__INST3_SEG4 0 852 #define MP0_BASE__INST3_SEG5 0 853 854 #define MP0_BASE__INST4_SEG0 0 855 #define MP0_BASE__INST4_SEG1 0 856 #define MP0_BASE__INST4_SEG2 0 857 #define MP0_BASE__INST4_SEG3 0 858 #define MP0_BASE__INST4_SEG4 0 859 #define MP0_BASE__INST4_SEG5 0 860 861 #define MP0_BASE__INST5_SEG0 0 862 #define MP0_BASE__INST5_SEG1 0 863 #define MP0_BASE__INST5_SEG2 0 864 #define MP0_BASE__INST5_SEG3 0 865 #define MP0_BASE__INST5_SEG4 0 866 #define MP0_BASE__INST5_SEG5 0 867 868 #define MP0_BASE__INST6_SEG0 0 869 #define MP0_BASE__INST6_SEG1 0 870 #define MP0_BASE__INST6_SEG2 0 871 #define MP0_BASE__INST6_SEG3 0 872 #define MP0_BASE__INST6_SEG4 0 873 #define MP0_BASE__INST6_SEG5 0 874 875 #define MP1_BASE__INST0_SEG0 0x00016000 876 #define MP1_BASE__INST0_SEG1 0x0243FC00 877 #define MP1_BASE__INST0_SEG2 0x00DC0000 878 #define MP1_BASE__INST0_SEG3 0x00E00000 879 #define MP1_BASE__INST0_SEG4 0x00E40000 880 #define MP1_BASE__INST0_SEG5 0 881 882 #define MP1_BASE__INST1_SEG0 0 883 #define MP1_BASE__INST1_SEG1 0 884 #define MP1_BASE__INST1_SEG2 0 885 #define MP1_BASE__INST1_SEG3 0 886 #define MP1_BASE__INST1_SEG4 0 887 #define MP1_BASE__INST1_SEG5 0 888 889 #define MP1_BASE__INST2_SEG0 0 890 #define MP1_BASE__INST2_SEG1 0 891 #define MP1_BASE__INST2_SEG2 0 892 #define MP1_BASE__INST2_SEG3 0 893 #define MP1_BASE__INST2_SEG4 0 894 #define MP1_BASE__INST2_SEG5 0 895 896 #define MP1_BASE__INST3_SEG0 0 897 #define MP1_BASE__INST3_SEG1 0 898 #define MP1_BASE__INST3_SEG2 0 899 #define MP1_BASE__INST3_SEG3 0 900 #define MP1_BASE__INST3_SEG4 0 901 #define MP1_BASE__INST3_SEG5 0 902 903 #define MP1_BASE__INST4_SEG0 0 904 #define MP1_BASE__INST4_SEG1 0 905 #define MP1_BASE__INST4_SEG2 0 906 #define MP1_BASE__INST4_SEG3 0 907 #define MP1_BASE__INST4_SEG4 0 908 #define MP1_BASE__INST4_SEG5 0 909 910 #define MP1_BASE__INST5_SEG0 0 911 #define MP1_BASE__INST5_SEG1 0 912 #define MP1_BASE__INST5_SEG2 0 913 #define MP1_BASE__INST5_SEG3 0 914 #define MP1_BASE__INST5_SEG4 0 915 #define MP1_BASE__INST5_SEG5 0 916 917 #define MP1_BASE__INST6_SEG0 0 918 #define MP1_BASE__INST6_SEG1 0 919 #define MP1_BASE__INST6_SEG2 0 920 #define MP1_BASE__INST6_SEG3 0 921 #define MP1_BASE__INST6_SEG4 0 922 #define MP1_BASE__INST6_SEG5 0 923 924 #define MP2_BASE__INST0_SEG0 0x00016000 925 #define MP2_BASE__INST0_SEG1 0x0243FC00 926 #define MP2_BASE__INST0_SEG2 0x00DC0000 927 #define MP2_BASE__INST0_SEG3 0x00E00000 928 #define MP2_BASE__INST0_SEG4 0x00E40000 929 #define MP2_BASE__INST0_SEG5 0 930 931 #define MP2_BASE__INST1_SEG0 0 932 #define MP2_BASE__INST1_SEG1 0 933 #define MP2_BASE__INST1_SEG2 0 934 #define MP2_BASE__INST1_SEG3 0 935 #define MP2_BASE__INST1_SEG4 0 936 #define MP2_BASE__INST1_SEG5 0 937 938 #define MP2_BASE__INST2_SEG0 0 939 #define MP2_BASE__INST2_SEG1 0 940 #define MP2_BASE__INST2_SEG2 0 941 #define MP2_BASE__INST2_SEG3 0 942 #define MP2_BASE__INST2_SEG4 0 943 #define MP2_BASE__INST2_SEG5 0 944 945 #define MP2_BASE__INST3_SEG0 0 946 #define MP2_BASE__INST3_SEG1 0 947 #define MP2_BASE__INST3_SEG2 0 948 #define MP2_BASE__INST3_SEG3 0 949 #define MP2_BASE__INST3_SEG4 0 950 #define MP2_BASE__INST3_SEG5 0 951 952 #define MP2_BASE__INST4_SEG0 0 953 #define MP2_BASE__INST4_SEG1 0 954 #define MP2_BASE__INST4_SEG2 0 955 #define MP2_BASE__INST4_SEG3 0 956 #define MP2_BASE__INST4_SEG4 0 957 #define MP2_BASE__INST4_SEG5 0 958 959 #define MP2_BASE__INST5_SEG0 0 960 #define MP2_BASE__INST5_SEG1 0 961 #define MP2_BASE__INST5_SEG2 0 962 #define MP2_BASE__INST5_SEG3 0 963 #define MP2_BASE__INST5_SEG4 0 964 #define MP2_BASE__INST5_SEG5 0 965 966 #define MP2_BASE__INST6_SEG0 0 967 #define MP2_BASE__INST6_SEG1 0 968 #define MP2_BASE__INST6_SEG2 0 969 #define MP2_BASE__INST6_SEG3 0 970 #define MP2_BASE__INST6_SEG4 0 971 #define MP2_BASE__INST6_SEG5 0 972 973 #define NBIO_BASE__INST0_SEG0 0x00000000 974 #define NBIO_BASE__INST0_SEG1 0x00000014 975 #define NBIO_BASE__INST0_SEG2 0x00000D20 976 #define NBIO_BASE__INST0_SEG3 0x00010400 977 #define NBIO_BASE__INST0_SEG4 0x0241B000 978 #define NBIO_BASE__INST0_SEG5 0x04040000 979 980 #define NBIO_BASE__INST1_SEG0 0 981 #define NBIO_BASE__INST1_SEG1 0 982 #define NBIO_BASE__INST1_SEG2 0 983 #define NBIO_BASE__INST1_SEG3 0 984 #define NBIO_BASE__INST1_SEG4 0 985 #define NBIO_BASE__INST1_SEG5 0 986 987 #define NBIO_BASE__INST2_SEG0 0 988 #define NBIO_BASE__INST2_SEG1 0 989 #define NBIO_BASE__INST2_SEG2 0 990 #define NBIO_BASE__INST2_SEG3 0 991 #define NBIO_BASE__INST2_SEG4 0 992 #define NBIO_BASE__INST2_SEG5 0 993 994 #define NBIO_BASE__INST3_SEG0 0 995 #define NBIO_BASE__INST3_SEG1 0 996 #define NBIO_BASE__INST3_SEG2 0 997 #define NBIO_BASE__INST3_SEG3 0 998 #define NBIO_BASE__INST3_SEG4 0 999 #define NBIO_BASE__INST3_SEG5 0 1000 1001 #define NBIO_BASE__INST4_SEG0 0 1002 #define NBIO_BASE__INST4_SEG1 0 1003 #define NBIO_BASE__INST4_SEG2 0 1004 #define NBIO_BASE__INST4_SEG3 0 1005 #define NBIO_BASE__INST4_SEG4 0 1006 #define NBIO_BASE__INST4_SEG5 0 1007 1008 #define NBIO_BASE__INST5_SEG0 0 1009 #define NBIO_BASE__INST5_SEG1 0 1010 #define NBIO_BASE__INST5_SEG2 0 1011 #define NBIO_BASE__INST5_SEG3 0 1012 #define NBIO_BASE__INST5_SEG4 0 1013 #define NBIO_BASE__INST5_SEG5 0 1014 1015 #define NBIO_BASE__INST6_SEG0 0 1016 #define NBIO_BASE__INST6_SEG1 0 1017 #define NBIO_BASE__INST6_SEG2 0 1018 #define NBIO_BASE__INST6_SEG3 0 1019 #define NBIO_BASE__INST6_SEG4 0 1020 #define NBIO_BASE__INST6_SEG5 0 1021 1022 #define OSSSYS_BASE__INST0_SEG0 0x000010A0 1023 #define OSSSYS_BASE__INST0_SEG1 0x0240A000 1024 #define OSSSYS_BASE__INST0_SEG2 0 1025 #define OSSSYS_BASE__INST0_SEG3 0 1026 #define OSSSYS_BASE__INST0_SEG4 0 1027 #define OSSSYS_BASE__INST0_SEG5 0 1028 1029 #define OSSSYS_BASE__INST1_SEG0 0 1030 #define OSSSYS_BASE__INST1_SEG1 0 1031 #define OSSSYS_BASE__INST1_SEG2 0 1032 #define OSSSYS_BASE__INST1_SEG3 0 1033 #define OSSSYS_BASE__INST1_SEG4 0 1034 #define OSSSYS_BASE__INST1_SEG5 0 1035 1036 #define OSSSYS_BASE__INST2_SEG0 0 1037 #define OSSSYS_BASE__INST2_SEG1 0 1038 #define OSSSYS_BASE__INST2_SEG2 0 1039 #define OSSSYS_BASE__INST2_SEG3 0 1040 #define OSSSYS_BASE__INST2_SEG4 0 1041 #define OSSSYS_BASE__INST2_SEG5 0 1042 1043 #define OSSSYS_BASE__INST3_SEG0 0 1044 #define OSSSYS_BASE__INST3_SEG1 0 1045 #define OSSSYS_BASE__INST3_SEG2 0 1046 #define OSSSYS_BASE__INST3_SEG3 0 1047 #define OSSSYS_BASE__INST3_SEG4 0 1048 #define OSSSYS_BASE__INST3_SEG5 0 1049 1050 #define OSSSYS_BASE__INST4_SEG0 0 1051 #define OSSSYS_BASE__INST4_SEG1 0 1052 #define OSSSYS_BASE__INST4_SEG2 0 1053 #define OSSSYS_BASE__INST4_SEG3 0 1054 #define OSSSYS_BASE__INST4_SEG4 0 1055 #define OSSSYS_BASE__INST4_SEG5 0 1056 1057 #define OSSSYS_BASE__INST5_SEG0 0 1058 #define OSSSYS_BASE__INST5_SEG1 0 1059 #define OSSSYS_BASE__INST5_SEG2 0 1060 #define OSSSYS_BASE__INST5_SEG3 0 1061 #define OSSSYS_BASE__INST5_SEG4 0 1062 #define OSSSYS_BASE__INST5_SEG5 0 1063 1064 #define OSSSYS_BASE__INST6_SEG0 0 1065 #define OSSSYS_BASE__INST6_SEG1 0 1066 #define OSSSYS_BASE__INST6_SEG2 0 1067 #define OSSSYS_BASE__INST6_SEG3 0 1068 #define OSSSYS_BASE__INST6_SEG4 0 1069 #define OSSSYS_BASE__INST6_SEG5 0 1070 1071 #define PCIE_BASE__INST0_SEG0 0x02411800 1072 #define PCIE_BASE__INST0_SEG1 0x04440000 1073 #define PCIE_BASE__INST0_SEG2 0 1074 #define PCIE_BASE__INST0_SEG3 0 1075 #define PCIE_BASE__INST0_SEG4 0 1076 #define PCIE_BASE__INST0_SEG5 0 1077 1078 #define PCIE_BASE__INST1_SEG0 0x02411C00 1079 #define PCIE_BASE__INST1_SEG1 0x04480000 1080 #define PCIE_BASE__INST1_SEG2 0 1081 #define PCIE_BASE__INST1_SEG3 0 1082 #define PCIE_BASE__INST1_SEG4 0 1083 #define PCIE_BASE__INST1_SEG5 0 1084 1085 #define PCIE_BASE__INST2_SEG0 0x02412000 1086 #define PCIE_BASE__INST2_SEG1 0x044C0000 1087 #define PCIE_BASE__INST2_SEG2 0 1088 #define PCIE_BASE__INST2_SEG3 0 1089 #define PCIE_BASE__INST2_SEG4 0 1090 #define PCIE_BASE__INST2_SEG5 0 1091 1092 #define PCIE_BASE__INST3_SEG0 0x02412400 1093 #define PCIE_BASE__INST3_SEG1 0x04500000 1094 #define PCIE_BASE__INST3_SEG2 0 1095 #define PCIE_BASE__INST3_SEG3 0 1096 #define PCIE_BASE__INST3_SEG4 0 1097 #define PCIE_BASE__INST3_SEG5 0 1098 1099 #define PCIE_BASE__INST4_SEG0 0 1100 #define PCIE_BASE__INST4_SEG1 0 1101 #define PCIE_BASE__INST4_SEG2 0 1102 #define PCIE_BASE__INST4_SEG3 0 1103 #define PCIE_BASE__INST4_SEG4 0 1104 #define PCIE_BASE__INST4_SEG5 0 1105 1106 #define PCIE_BASE__INST5_SEG0 0 1107 #define PCIE_BASE__INST5_SEG1 0 1108 #define PCIE_BASE__INST5_SEG2 0 1109 #define PCIE_BASE__INST5_SEG3 0 1110 #define PCIE_BASE__INST5_SEG4 0 1111 #define PCIE_BASE__INST5_SEG5 0 1112 1113 #define PCIE_BASE__INST6_SEG0 0 1114 #define PCIE_BASE__INST6_SEG1 0 1115 #define PCIE_BASE__INST6_SEG2 0 1116 #define PCIE_BASE__INST6_SEG3 0 1117 #define PCIE_BASE__INST6_SEG4 0 1118 #define PCIE_BASE__INST6_SEG5 0 1119 1120 #define SDMA0_BASE__INST0_SEG0 0x00001260 1121 #define SDMA0_BASE__INST0_SEG1 0x0000A000 1122 #define SDMA0_BASE__INST0_SEG2 0x02402C00 1123 #define SDMA0_BASE__INST0_SEG3 0 1124 #define SDMA0_BASE__INST0_SEG4 0 1125 #define SDMA0_BASE__INST0_SEG5 0 1126 1127 #define SDMA0_BASE__INST1_SEG0 0 1128 #define SDMA0_BASE__INST1_SEG1 0 1129 #define SDMA0_BASE__INST1_SEG2 0 1130 #define SDMA0_BASE__INST1_SEG3 0 1131 #define SDMA0_BASE__INST1_SEG4 0 1132 #define SDMA0_BASE__INST1_SEG5 0 1133 1134 #define SDMA0_BASE__INST2_SEG0 0 1135 #define SDMA0_BASE__INST2_SEG1 0 1136 #define SDMA0_BASE__INST2_SEG2 0 1137 #define SDMA0_BASE__INST2_SEG3 0 1138 #define SDMA0_BASE__INST2_SEG4 0 1139 #define SDMA0_BASE__INST2_SEG5 0 1140 1141 #define SDMA0_BASE__INST3_SEG0 0 1142 #define SDMA0_BASE__INST3_SEG1 0 1143 #define SDMA0_BASE__INST3_SEG2 0 1144 #define SDMA0_BASE__INST3_SEG3 0 1145 #define SDMA0_BASE__INST3_SEG4 0 1146 #define SDMA0_BASE__INST3_SEG5 0 1147 1148 #define SDMA0_BASE__INST4_SEG0 0 1149 #define SDMA0_BASE__INST4_SEG1 0 1150 #define SDMA0_BASE__INST4_SEG2 0 1151 #define SDMA0_BASE__INST4_SEG3 0 1152 #define SDMA0_BASE__INST4_SEG4 0 1153 #define SDMA0_BASE__INST4_SEG5 0 1154 1155 #define SDMA0_BASE__INST5_SEG0 0 1156 #define SDMA0_BASE__INST5_SEG1 0 1157 #define SDMA0_BASE__INST5_SEG2 0 1158 #define SDMA0_BASE__INST5_SEG3 0 1159 #define SDMA0_BASE__INST5_SEG4 0 1160 #define SDMA0_BASE__INST5_SEG5 0 1161 1162 #define SDMA0_BASE__INST6_SEG0 0 1163 #define SDMA0_BASE__INST6_SEG1 0 1164 #define SDMA0_BASE__INST6_SEG2 0 1165 #define SDMA0_BASE__INST6_SEG3 0 1166 #define SDMA0_BASE__INST6_SEG4 0 1167 #define SDMA0_BASE__INST6_SEG5 0 1168 1169 #define SMUIO_BASE__INST0_SEG0 0x00016800 1170 #define SMUIO_BASE__INST0_SEG1 0x00016A00 1171 #define SMUIO_BASE__INST0_SEG2 0x02401000 1172 #define SMUIO_BASE__INST0_SEG3 0x00440000 1173 #define SMUIO_BASE__INST0_SEG4 0 1174 #define SMUIO_BASE__INST0_SEG5 0 1175 1176 #define SMUIO_BASE__INST1_SEG0 0x0001BC00 1177 #define SMUIO_BASE__INST1_SEG1 0x0242D400 1178 #define SMUIO_BASE__INST1_SEG2 0 1179 #define SMUIO_BASE__INST1_SEG3 0 1180 #define SMUIO_BASE__INST1_SEG4 0 1181 #define SMUIO_BASE__INST1_SEG5 0 1182 1183 #define SMUIO_BASE__INST2_SEG0 0 1184 #define SMUIO_BASE__INST2_SEG1 0 1185 #define SMUIO_BASE__INST2_SEG2 0 1186 #define SMUIO_BASE__INST2_SEG3 0 1187 #define SMUIO_BASE__INST2_SEG4 0 1188 #define SMUIO_BASE__INST2_SEG5 0 1189 1190 #define SMUIO_BASE__INST3_SEG0 0 1191 #define SMUIO_BASE__INST3_SEG1 0 1192 #define SMUIO_BASE__INST3_SEG2 0 1193 #define SMUIO_BASE__INST3_SEG3 0 1194 #define SMUIO_BASE__INST3_SEG4 0 1195 #define SMUIO_BASE__INST3_SEG5 0 1196 1197 #define SMUIO_BASE__INST4_SEG0 0 1198 #define SMUIO_BASE__INST4_SEG1 0 1199 #define SMUIO_BASE__INST4_SEG2 0 1200 #define SMUIO_BASE__INST4_SEG3 0 1201 #define SMUIO_BASE__INST4_SEG4 0 1202 #define SMUIO_BASE__INST4_SEG5 0 1203 1204 #define SMUIO_BASE__INST5_SEG0 0 1205 #define SMUIO_BASE__INST5_SEG1 0 1206 #define SMUIO_BASE__INST5_SEG2 0 1207 #define SMUIO_BASE__INST5_SEG3 0 1208 #define SMUIO_BASE__INST5_SEG4 0 1209 #define SMUIO_BASE__INST5_SEG5 0 1210 1211 #define SMUIO_BASE__INST6_SEG0 0 1212 #define SMUIO_BASE__INST6_SEG1 0 1213 #define SMUIO_BASE__INST6_SEG2 0 1214 #define SMUIO_BASE__INST6_SEG3 0 1215 #define SMUIO_BASE__INST6_SEG4 0 1216 #define SMUIO_BASE__INST6_SEG5 0 1217 1218 #define THM_BASE__INST0_SEG0 0x00016600 1219 #define THM_BASE__INST0_SEG1 0x02400C00 1220 #define THM_BASE__INST0_SEG2 0 1221 #define THM_BASE__INST0_SEG3 0 1222 #define THM_BASE__INST0_SEG4 0 1223 #define THM_BASE__INST0_SEG5 0 1224 1225 #define THM_BASE__INST1_SEG0 0 1226 #define THM_BASE__INST1_SEG1 0 1227 #define THM_BASE__INST1_SEG2 0 1228 #define THM_BASE__INST1_SEG3 0 1229 #define THM_BASE__INST1_SEG4 0 1230 #define THM_BASE__INST1_SEG5 0 1231 1232 #define THM_BASE__INST2_SEG0 0 1233 #define THM_BASE__INST2_SEG1 0 1234 #define THM_BASE__INST2_SEG2 0 1235 #define THM_BASE__INST2_SEG3 0 1236 #define THM_BASE__INST2_SEG4 0 1237 #define THM_BASE__INST2_SEG5 0 1238 1239 #define THM_BASE__INST3_SEG0 0 1240 #define THM_BASE__INST3_SEG1 0 1241 #define THM_BASE__INST3_SEG2 0 1242 #define THM_BASE__INST3_SEG3 0 1243 #define THM_BASE__INST3_SEG4 0 1244 #define THM_BASE__INST3_SEG5 0 1245 1246 #define THM_BASE__INST4_SEG0 0 1247 #define THM_BASE__INST4_SEG1 0 1248 #define THM_BASE__INST4_SEG2 0 1249 #define THM_BASE__INST4_SEG3 0 1250 #define THM_BASE__INST4_SEG4 0 1251 #define THM_BASE__INST4_SEG5 0 1252 1253 #define THM_BASE__INST5_SEG0 0 1254 #define THM_BASE__INST5_SEG1 0 1255 #define THM_BASE__INST5_SEG2 0 1256 #define THM_BASE__INST5_SEG3 0 1257 #define THM_BASE__INST5_SEG4 0 1258 #define THM_BASE__INST5_SEG5 0 1259 1260 #define THM_BASE__INST6_SEG0 0 1261 #define THM_BASE__INST6_SEG1 0 1262 #define THM_BASE__INST6_SEG2 0 1263 #define THM_BASE__INST6_SEG3 0 1264 #define THM_BASE__INST6_SEG4 0 1265 #define THM_BASE__INST6_SEG5 0 1266 1267 #define UMC_BASE__INST0_SEG0 0x00014000 1268 #define UMC_BASE__INST0_SEG1 0x00054000 1269 #define UMC_BASE__INST0_SEG2 0x02425800 1270 #define UMC_BASE__INST0_SEG3 0x02425C00 1271 #define UMC_BASE__INST0_SEG4 0 1272 #define UMC_BASE__INST0_SEG5 0 1273 1274 #define UMC_BASE__INST1_SEG0 0x00094000 1275 #define UMC_BASE__INST1_SEG1 0x000D4000 1276 #define UMC_BASE__INST1_SEG2 0x02426000 1277 #define UMC_BASE__INST1_SEG3 0x02426400 1278 #define UMC_BASE__INST1_SEG4 0 1279 #define UMC_BASE__INST1_SEG5 0 1280 1281 #define UMC_BASE__INST2_SEG0 0 1282 #define UMC_BASE__INST2_SEG1 0 1283 #define UMC_BASE__INST2_SEG2 0 1284 #define UMC_BASE__INST2_SEG3 0 1285 #define UMC_BASE__INST2_SEG4 0 1286 #define UMC_BASE__INST2_SEG5 0 1287 1288 #define UMC_BASE__INST3_SEG0 0 1289 #define UMC_BASE__INST3_SEG1 0 1290 #define UMC_BASE__INST3_SEG2 0 1291 #define UMC_BASE__INST3_SEG3 0 1292 #define UMC_BASE__INST3_SEG4 0 1293 #define UMC_BASE__INST3_SEG5 0 1294 1295 #define UMC_BASE__INST4_SEG0 0 1296 #define UMC_BASE__INST4_SEG1 0 1297 #define UMC_BASE__INST4_SEG2 0 1298 #define UMC_BASE__INST4_SEG3 0 1299 #define UMC_BASE__INST4_SEG4 0 1300 #define UMC_BASE__INST4_SEG5 0 1301 1302 #define UMC_BASE__INST5_SEG0 0 1303 #define UMC_BASE__INST5_SEG1 0 1304 #define UMC_BASE__INST5_SEG2 0 1305 #define UMC_BASE__INST5_SEG3 0 1306 #define UMC_BASE__INST5_SEG4 0 1307 #define UMC_BASE__INST5_SEG5 0 1308 1309 #define UMC_BASE__INST6_SEG0 0 1310 #define UMC_BASE__INST6_SEG1 0 1311 #define UMC_BASE__INST6_SEG2 0 1312 #define UMC_BASE__INST6_SEG3 0 1313 #define UMC_BASE__INST6_SEG4 0 1314 #define UMC_BASE__INST6_SEG5 0 1315 1316 #define VCN_BASE__INST0_SEG0 0x00007800 1317 #define VCN_BASE__INST0_SEG1 0x00007E00 1318 #define VCN_BASE__INST0_SEG2 0x02403000 1319 #define VCN_BASE__INST0_SEG3 0 1320 #define VCN_BASE__INST0_SEG4 0 1321 #define VCN_BASE__INST0_SEG5 0 1322 1323 #define VCN_BASE__INST1_SEG0 0 1324 #define VCN_BASE__INST1_SEG1 0 1325 #define VCN_BASE__INST1_SEG2 0 1326 #define VCN_BASE__INST1_SEG3 0 1327 #define VCN_BASE__INST1_SEG4 0 1328 #define VCN_BASE__INST1_SEG5 0 1329 1330 #define VCN_BASE__INST2_SEG0 0 1331 #define VCN_BASE__INST2_SEG1 0 1332 #define VCN_BASE__INST2_SEG2 0 1333 #define VCN_BASE__INST2_SEG3 0 1334 #define VCN_BASE__INST2_SEG4 0 1335 #define VCN_BASE__INST2_SEG5 0 1336 1337 #define VCN_BASE__INST3_SEG0 0 1338 #define VCN_BASE__INST3_SEG1 0 1339 #define VCN_BASE__INST3_SEG2 0 1340 #define VCN_BASE__INST3_SEG3 0 1341 #define VCN_BASE__INST3_SEG4 0 1342 #define VCN_BASE__INST3_SEG5 0 1343 1344 #define VCN_BASE__INST4_SEG0 0 1345 #define VCN_BASE__INST4_SEG1 0 1346 #define VCN_BASE__INST4_SEG2 0 1347 #define VCN_BASE__INST4_SEG3 0 1348 #define VCN_BASE__INST4_SEG4 0 1349 #define VCN_BASE__INST4_SEG5 0 1350 1351 #define VCN_BASE__INST5_SEG0 0 1352 #define VCN_BASE__INST5_SEG1 0 1353 #define VCN_BASE__INST5_SEG2 0 1354 #define VCN_BASE__INST5_SEG3 0 1355 #define VCN_BASE__INST5_SEG4 0 1356 #define VCN_BASE__INST5_SEG5 0 1357 1358 #define VCN_BASE__INST6_SEG0 0 1359 #define VCN_BASE__INST6_SEG1 0 1360 #define VCN_BASE__INST6_SEG2 0 1361 #define VCN_BASE__INST6_SEG3 0 1362 #define VCN_BASE__INST6_SEG4 0 1363 #define VCN_BASE__INST6_SEG5 0 1364 1365 #endif 1366