xref: /openbmc/u-boot/drivers/video/i915_reg.h (revision e8f80a5a)
1 /* SPDX-License-Identifier: BSD-3-Clause */
2 /*
3  * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
4  * All Rights Reserved.
5  */
6 
7 #ifndef _I915_REG_H_
8 #define _I915_REG_H_
9 
10 /* Hotplug control (945+ only) */
11 #define PORT_HOTPLUG_EN		0x61110
12 #define   HDMIB_HOTPLUG_INT_EN			(1 << 29)
13 #define   DPB_HOTPLUG_INT_EN			(1 << 29)
14 #define   HDMIC_HOTPLUG_INT_EN			(1 << 28)
15 #define   DPC_HOTPLUG_INT_EN			(1 << 28)
16 #define   HDMID_HOTPLUG_INT_EN			(1 << 27)
17 #define   DPD_HOTPLUG_INT_EN			(1 << 27)
18 #define   SDVOB_HOTPLUG_INT_EN			(1 << 26)
19 #define   SDVOC_HOTPLUG_INT_EN			(1 << 25)
20 #define   TV_HOTPLUG_INT_EN			(1 << 18)
21 #define   CRT_HOTPLUG_INT_EN			(1 << 9)
22 #define   CRT_HOTPLUG_FORCE_DETECT		(1 << 3)
23 #define CRT_HOTPLUG_ACTIVATION_PERIOD_32	(0 << 8)
24 /* must use period 64 on GM45 according to docs */
25 #define CRT_HOTPLUG_ACTIVATION_PERIOD_64	(1 << 8)
26 #define CRT_HOTPLUG_DAC_ON_TIME_2M		(0 << 7)
27 #define CRT_HOTPLUG_DAC_ON_TIME_4M		(1 << 7)
28 #define CRT_HOTPLUG_VOLTAGE_COMPARE_40		(0 << 5)
29 #define CRT_HOTPLUG_VOLTAGE_COMPARE_50		(1 << 5)
30 #define CRT_HOTPLUG_VOLTAGE_COMPARE_60		(2 << 5)
31 #define CRT_HOTPLUG_VOLTAGE_COMPARE_70		(3 << 5)
32 #define CRT_HOTPLUG_VOLTAGE_COMPARE_MASK	(3 << 5)
33 #define CRT_HOTPLUG_DETECT_DELAY_1G		(0 << 4)
34 #define CRT_HOTPLUG_DETECT_DELAY_2G		(1 << 4)
35 #define CRT_HOTPLUG_DETECT_VOLTAGE_325MV	(0 << 2)
36 #define CRT_HOTPLUG_DETECT_VOLTAGE_475MV	(1 << 2)
37 
38 /* Backlight control */
39 #define BLC_PWM_CTL2		0x61250 /* 965+ only */
40 #define   BLM_PWM_ENABLE		(1 << 31)
41 #define   BLM_COMBINATION_MODE		(1 << 30) /* gen4 only */
42 #define   BLM_PIPE_SELECT		(1 << 29)
43 #define   BLM_PIPE_SELECT_IVB		(3 << 29)
44 #define   BLM_PIPE_A			(0 << 29)
45 #define   BLM_PIPE_B			(1 << 29)
46 #define   BLM_PIPE_C			(2 << 29) /* ivb + */
47 #define   BLM_PIPE(pipe)		((pipe) << 29)
48 #define   BLM_POLARITY_I965		(1 << 28) /* gen4 only */
49 #define   BLM_PHASE_IN_INTERUPT_STATUS	(1 << 26)
50 #define   BLM_PHASE_IN_ENABLE		(1 << 25)
51 #define   BLM_PHASE_IN_INTERUPT_ENABL	(1 << 24)
52 #define   BLM_PHASE_IN_TIME_BASE_SHIFT	(16)
53 #define   BLM_PHASE_IN_TIME_BASE_MASK	(0xff << 16)
54 #define   BLM_PHASE_IN_COUNT_SHIFT	(8)
55 #define   BLM_PHASE_IN_COUNT_MASK	(0xff << 8)
56 #define   BLM_PHASE_IN_INCR_SHIFT	(0)
57 #define   BLM_PHASE_IN_INCR_MASK	(0xff << 0)
58 #define BLC_PWM_CTL		0x61254
59 /*
60  * This is the most significant 15 bits of the number of backlight cycles in a
61  * complete cycle of the modulated backlight control.
62  *
63  * The actual value is this field multiplied by two.
64  */
65 #define   BACKLIGHT_MODULATION_FREQ_SHIFT	(17)
66 #define   BACKLIGHT_MODULATION_FREQ_MASK	(0x7fff << 17)
67 #define   BLM_LEGACY_MODE			(1 << 16) /* gen2 only */
68 /*
69  * This is the number of cycles out of the backlight modulation cycle for which
70  * the backlight is on.
71  *
72  * This field must be no greater than the number of cycles in the complete
73  * backlight modulation cycle.
74  */
75 #define   BACKLIGHT_DUTY_CYCLE_SHIFT		(0)
76 #define   BACKLIGHT_DUTY_CYCLE_MASK		(0xffff)
77 #define   BACKLIGHT_DUTY_CYCLE_MASK_PNV		(0xfffe)
78 #define   BLM_POLARITY_PNV			(1 << 0) /* pnv only */
79 
80 #define BLC_HIST_CTL		0x61260
81 
82 /*
83  * New registers for PCH-split platforms. Safe where new bits show up, the
84  * register layout machtes with gen4 BLC_PWM_CTL[12]
85  */
86 #define BLC_PWM_CPU_CTL2	0x48250
87 #define  BLC_PWM2_ENABLE        (1<<31)
88 #define BLC_PWM_CPU_CTL		0x48254
89 
90 #define BLM_HIST_CTL			0x48260
91 #define  ENH_HIST_ENABLE		(1<<31)
92 #define  ENH_MODIF_TBL_ENABLE		(1<<30)
93 #define  ENH_PIPE_A_SELECT		(0<<29)
94 #define  ENH_PIPE_B_SELECT		(1<<29)
95 #define  ENH_PIPE(pipe) _PIPE(pipe, ENH_PIPE_A_SELECT, ENH_PIPE_B_SELECT)
96 #define  HIST_MODE_YUV			(0<<24)
97 #define  HIST_MODE_HSV			(1<<24)
98 #define  ENH_MODE_DIRECT		(0<<13)
99 #define  ENH_MODE_ADDITIVE		(1<<13)
100 #define  ENH_MODE_MULTIPLICATIVE	(2<<13)
101 #define  BIN_REGISTER_SET		(1<<11)
102 #define  ENH_NUM_BINS			32
103 
104 #define BLM_HIST_ENH			0x48264
105 
106 #define BLM_HIST_GUARD_BAND		0x48268
107 #define  BLM_HIST_INTR_ENABLE		(1<<31)
108 #define  BLM_HIST_EVENT_STATUS		(1<<30)
109 #define  BLM_HIST_INTR_DELAY_MASK	(0xFF<<22)
110 #define  BLM_HIST_INTR_DELAY_SHIFT	22
111 
112 /*
113  * PCH CTL1 is totally different, all but the below bits are reserved. CTL2 is
114  * like the normal CTL from gen4 and earlier. Hooray for confusing naming.
115  */
116 #define BLC_PWM_PCH_CTL1	0xc8250
117 #define   BLM_PCH_PWM_ENABLE			(1 << 31)
118 #define   BLM_PCH_OVERRIDE_ENABLE		(1 << 30)
119 #define   BLM_PCH_POLARITY			(1 << 29)
120 #define BLC_PWM_PCH_CTL2	0xc8254
121 
122 /* digital port hotplug */
123 #define PCH_PORT_HOTPLUG        0xc4030		/* SHOTPLUG_CTL */
124 #define PORTD_HOTPLUG_ENABLE            (1 << 20)
125 #define PORTD_PULSE_DURATION_2ms        (0)
126 #define PORTD_PULSE_DURATION_4_5ms      (1 << 18)
127 #define PORTD_PULSE_DURATION_6ms        (2 << 18)
128 #define PORTD_PULSE_DURATION_100ms      (3 << 18)
129 #define PORTD_PULSE_DURATION_MASK	(3 << 18)
130 #define PORTD_HOTPLUG_NO_DETECT         (0)
131 #define PORTD_HOTPLUG_SHORT_DETECT      (1 << 16)
132 #define PORTD_HOTPLUG_LONG_DETECT       (1 << 17)
133 #define PORTC_HOTPLUG_ENABLE            (1 << 12)
134 #define PORTC_PULSE_DURATION_2ms        (0)
135 #define PORTC_PULSE_DURATION_4_5ms      (1 << 10)
136 #define PORTC_PULSE_DURATION_6ms        (2 << 10)
137 #define PORTC_PULSE_DURATION_100ms      (3 << 10)
138 #define PORTC_PULSE_DURATION_MASK	(3 << 10)
139 #define PORTC_HOTPLUG_NO_DETECT         (0)
140 #define PORTC_HOTPLUG_SHORT_DETECT      (1 << 8)
141 #define PORTC_HOTPLUG_LONG_DETECT       (1 << 9)
142 #define PORTB_HOTPLUG_ENABLE            (1 << 4)
143 #define PORTB_PULSE_DURATION_2ms        (0)
144 #define PORTB_PULSE_DURATION_4_5ms      (1 << 2)
145 #define PORTB_PULSE_DURATION_6ms        (2 << 2)
146 #define PORTB_PULSE_DURATION_100ms      (3 << 2)
147 #define PORTB_PULSE_DURATION_MASK	(3 << 2)
148 #define PORTB_HOTPLUG_NO_DETECT         (0)
149 #define PORTB_HOTPLUG_SHORT_DETECT      (1 << 0)
150 #define PORTB_HOTPLUG_LONG_DETECT       (1 << 1)
151 
152 #define PCH_GPIOA               0xc5010
153 #define PCH_GPIOB               0xc5014
154 #define PCH_GPIOC               0xc5018
155 #define PCH_GPIOD               0xc501c
156 #define PCH_GPIOE               0xc5020
157 #define PCH_GPIOF               0xc5024
158 
159 #define PCH_GMBUS0		0xc5100
160 #define PCH_GMBUS1		0xc5104
161 #define PCH_GMBUS2		0xc5108
162 #define PCH_GMBUS3		0xc510c
163 #define PCH_GMBUS4		0xc5110
164 #define PCH_GMBUS5		0xc5120
165 
166 #define _PCH_DPLL_A              0xc6014
167 #define _PCH_DPLL_B              0xc6018
168 #define _PCH_DPLL(pll) (pll == 0 ? _PCH_DPLL_A : _PCH_DPLL_B)
169 
170 #define _PCH_FPA0                0xc6040
171 #define  FP_CB_TUNE		(0x3<<22)
172 #define _PCH_FPA1                0xc6044
173 #define _PCH_FPB0                0xc6048
174 #define _PCH_FPB1                0xc604c
175 #define _PCH_FP0(pll) (pll == 0 ? _PCH_FPA0 : _PCH_FPB0)
176 #define _PCH_FP1(pll) (pll == 0 ? _PCH_FPA1 : _PCH_FPB1)
177 
178 #define PCH_DPLL_TEST           0xc606c
179 
180 #define PCH_DREF_CONTROL        0xC6200
181 #define  DREF_CONTROL_MASK      0x7fc3
182 #define  DREF_CPU_SOURCE_OUTPUT_DISABLE         (0<<13)
183 #define  DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD      (2<<13)
184 #define  DREF_CPU_SOURCE_OUTPUT_NONSPREAD       (3<<13)
185 #define  DREF_CPU_SOURCE_OUTPUT_MASK		(3<<13)
186 #define  DREF_SSC_SOURCE_DISABLE                (0<<11)
187 #define  DREF_SSC_SOURCE_ENABLE                 (2<<11)
188 #define  DREF_SSC_SOURCE_MASK			(3<<11)
189 #define  DREF_NONSPREAD_SOURCE_DISABLE          (0<<9)
190 #define  DREF_NONSPREAD_CK505_ENABLE		(1<<9)
191 #define  DREF_NONSPREAD_SOURCE_ENABLE           (2<<9)
192 #define  DREF_NONSPREAD_SOURCE_MASK		(3<<9)
193 #define  DREF_SUPERSPREAD_SOURCE_DISABLE        (0<<7)
194 #define  DREF_SUPERSPREAD_SOURCE_ENABLE         (2<<7)
195 #define  DREF_SUPERSPREAD_SOURCE_MASK		(3<<7)
196 #define  DREF_SSC4_DOWNSPREAD                   (0<<6)
197 #define  DREF_SSC4_CENTERSPREAD                 (1<<6)
198 #define  DREF_SSC1_DISABLE                      (0<<1)
199 #define  DREF_SSC1_ENABLE                       (1<<1)
200 #define  DREF_SSC4_DISABLE                      (0)
201 #define  DREF_SSC4_ENABLE                       (1)
202 
203 #define PCH_RAWCLK_FREQ         0xc6204
204 #define  FDL_TP1_TIMER_SHIFT    12
205 #define  FDL_TP1_TIMER_MASK     (3<<12)
206 #define  FDL_TP2_TIMER_SHIFT    10
207 #define  FDL_TP2_TIMER_MASK     (3<<10)
208 #define  RAWCLK_FREQ_MASK       0x3ff
209 
210 #define PCH_DPLL_TMR_CFG        0xc6208
211 
212 #define PCH_SSC4_PARMS          0xc6210
213 #define PCH_SSC4_AUX_PARMS      0xc6214
214 
215 #define PCH_DPLL_SEL		0xc7000
216 #define  TRANSA_DPLL_ENABLE	(1<<3)
217 #define	 TRANSA_DPLLB_SEL	(1<<0)
218 #define	 TRANSA_DPLLA_SEL	0
219 #define  TRANSB_DPLL_ENABLE	(1<<7)
220 #define	 TRANSB_DPLLB_SEL	(1<<4)
221 #define	 TRANSB_DPLLA_SEL	(0)
222 #define  TRANSC_DPLL_ENABLE	(1<<11)
223 #define	 TRANSC_DPLLB_SEL	(1<<8)
224 #define	 TRANSC_DPLLA_SEL	(0)
225 
226 /* transcoder */
227 
228 #define _TRANS_HTOTAL_A          0xe0000
229 #define  TRANS_HTOTAL_SHIFT     16
230 #define  TRANS_HACTIVE_SHIFT    0
231 #define _TRANS_HBLANK_A          0xe0004
232 #define  TRANS_HBLANK_END_SHIFT 16
233 #define  TRANS_HBLANK_START_SHIFT 0
234 #define _TRANS_HSYNC_A           0xe0008
235 #define  TRANS_HSYNC_END_SHIFT  16
236 #define  TRANS_HSYNC_START_SHIFT 0
237 #define _TRANS_VTOTAL_A          0xe000c
238 #define  TRANS_VTOTAL_SHIFT     16
239 #define  TRANS_VACTIVE_SHIFT    0
240 #define _TRANS_VBLANK_A          0xe0010
241 #define  TRANS_VBLANK_END_SHIFT 16
242 #define  TRANS_VBLANK_START_SHIFT 0
243 #define _TRANS_VSYNC_A           0xe0014
244 #define  TRANS_VSYNC_END_SHIFT  16
245 #define  TRANS_VSYNC_START_SHIFT 0
246 #define _TRANS_VSYNCSHIFT_A	0xe0028
247 
248 #define _TRANSA_DATA_M1          0xe0030
249 #define _TRANSA_DATA_N1          0xe0034
250 #define _TRANSA_DATA_M2          0xe0038
251 #define _TRANSA_DATA_N2          0xe003c
252 #define _TRANSA_DP_LINK_M1       0xe0040
253 #define _TRANSA_DP_LINK_N1       0xe0044
254 #define _TRANSA_DP_LINK_M2       0xe0048
255 #define _TRANSA_DP_LINK_N2       0xe004c
256 
257 /* Per-transcoder DIP controls */
258 
259 #define _VIDEO_DIP_CTL_A         0xe0200
260 #define _VIDEO_DIP_DATA_A        0xe0208
261 #define _VIDEO_DIP_GCP_A         0xe0210
262 
263 #define _VIDEO_DIP_CTL_B         0xe1200
264 #define _VIDEO_DIP_DATA_B        0xe1208
265 #define _VIDEO_DIP_GCP_B         0xe1210
266 
267 #define TVIDEO_DIP_CTL(pipe) _PIPE(pipe, _VIDEO_DIP_CTL_A, _VIDEO_DIP_CTL_B)
268 #define TVIDEO_DIP_DATA(pipe) _PIPE(pipe, _VIDEO_DIP_DATA_A, _VIDEO_DIP_DATA_B)
269 #define TVIDEO_DIP_GCP(pipe) _PIPE(pipe, _VIDEO_DIP_GCP_A, _VIDEO_DIP_GCP_B)
270 
271 #define VLV_VIDEO_DIP_CTL_A		0x60200
272 #define VLV_VIDEO_DIP_DATA_A		0x60208
273 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_A	0x60210
274 
275 #define VLV_VIDEO_DIP_CTL_B		0x61170
276 #define VLV_VIDEO_DIP_DATA_B		0x61174
277 #define VLV_VIDEO_DIP_GDCP_PAYLOAD_B	0x61178
278 
279 #define VLV_TVIDEO_DIP_CTL(pipe) \
280 	 _PIPE(pipe, VLV_VIDEO_DIP_CTL_A, VLV_VIDEO_DIP_CTL_B)
281 #define VLV_TVIDEO_DIP_DATA(pipe) \
282 	 _PIPE(pipe, VLV_VIDEO_DIP_DATA_A, VLV_VIDEO_DIP_DATA_B)
283 #define VLV_TVIDEO_DIP_GCP(pipe) \
284 	_PIPE(pipe, VLV_VIDEO_DIP_GDCP_PAYLOAD_A, VLV_VIDEO_DIP_GDCP_PAYLOAD_B)
285 
286 /* vlv has 2 sets of panel control regs. */
287 #define PIPEA_PP_STATUS         0x61200
288 #define PIPEA_PP_CONTROL        0x61204
289 #define PIPEA_PP_ON_DELAYS      0x61208
290 #define PIPEA_PP_OFF_DELAYS     0x6120c
291 #define PIPEA_PP_DIVISOR        0x61210
292 
293 #define PIPEB_PP_STATUS         0x61300
294 #define PIPEB_PP_CONTROL        0x61304
295 #define PIPEB_PP_ON_DELAYS      0x61308
296 #define PIPEB_PP_OFF_DELAYS     0x6130c
297 #define PIPEB_PP_DIVISOR        0x61310
298 
299 #define PCH_PP_STATUS		0xc7200
300 #define PCH_PP_CONTROL		0xc7204
301 #define  PANEL_UNLOCK_REGS	(0xabcd << 16)
302 #define  PANEL_UNLOCK_MASK	(0xffff << 16)
303 #define  EDP_FORCE_VDD		(1 << 3)
304 #define  EDP_BLC_ENABLE		(1 << 2)
305 #define  PANEL_POWER_RESET	(1 << 1)
306 #define  PANEL_POWER_OFF	(0 << 0)
307 #define  PANEL_POWER_ON		(1 << 0)
308 #define PCH_PP_ON_DELAYS	0xc7208
309 #define  PANEL_PORT_SELECT_MASK	(3 << 30)
310 #define  PANEL_PORT_SELECT_LVDS	(0 << 30)
311 #define  PANEL_PORT_SELECT_DPA	(1 << 30)
312 #define  EDP_PANEL		(1 << 30)
313 #define  PANEL_PORT_SELECT_DPC	(2 << 30)
314 #define  PANEL_PORT_SELECT_DPD	(3 << 30)
315 #define  PANEL_POWER_UP_DELAY_MASK	(0x1fff0000)
316 #define  PANEL_POWER_UP_DELAY_SHIFT	16
317 #define  PANEL_LIGHT_ON_DELAY_MASK	(0x1fff)
318 #define  PANEL_LIGHT_ON_DELAY_SHIFT	0
319 
320 #define PCH_PP_OFF_DELAYS	0xc720c
321 #define  PANEL_POWER_PORT_SELECT_MASK	(0x3 << 30)
322 #define  PANEL_POWER_PORT_LVDS		(0 << 30)
323 #define  PANEL_POWER_PORT_DP_A		(1 << 30)
324 #define  PANEL_POWER_PORT_DP_C		(2 << 30)
325 #define  PANEL_POWER_PORT_DP_D		(3 << 30)
326 #define  PANEL_POWER_DOWN_DELAY_MASK	(0x1fff0000)
327 #define  PANEL_POWER_DOWN_DELAY_SHIFT	16
328 #define  PANEL_LIGHT_OFF_DELAY_MASK	(0x1fff)
329 #define  PANEL_LIGHT_OFF_DELAY_SHIFT	0
330 
331 #define PCH_PP_DIVISOR		0xc7210
332 #define  PP_REFERENCE_DIVIDER_MASK	(0xffffff00)
333 #define  PP_REFERENCE_DIVIDER_SHIFT	8
334 #define  PANEL_POWER_CYCLE_DELAY_MASK	(0x1f)
335 #define  PANEL_POWER_CYCLE_DELAY_SHIFT	0
336 
337 #define PCH_DP_B		0xe4100
338 #define PCH_DPB_AUX_CH_CTL	0xe4110
339 #define PCH_DPB_AUX_CH_DATA1	0xe4114
340 #define PCH_DPB_AUX_CH_DATA2	0xe4118
341 #define PCH_DPB_AUX_CH_DATA3	0xe411c
342 #define PCH_DPB_AUX_CH_DATA4	0xe4120
343 #define PCH_DPB_AUX_CH_DATA5	0xe4124
344 
345 #define PCH_DP_C		0xe4200
346 #define PCH_DPC_AUX_CH_CTL	0xe4210
347 #define PCH_DPC_AUX_CH_DATA1	0xe4214
348 #define PCH_DPC_AUX_CH_DATA2	0xe4218
349 #define PCH_DPC_AUX_CH_DATA3	0xe421c
350 #define PCH_DPC_AUX_CH_DATA4	0xe4220
351 #define PCH_DPC_AUX_CH_DATA5	0xe4224
352 
353 #define PCH_DP_D		0xe4300
354 #define PCH_DPD_AUX_CH_CTL	0xe4310
355 #define PCH_DPD_AUX_CH_DATA1	0xe4314
356 #define PCH_DPD_AUX_CH_DATA2	0xe4318
357 #define PCH_DPD_AUX_CH_DATA3	0xe431c
358 #define PCH_DPD_AUX_CH_DATA4	0xe4320
359 #define PCH_DPD_AUX_CH_DATA5	0xe4324
360 
361 #endif /* _I915_REG_H_ */
362