1/* SPDX-License-Identifier: GPL-2.0+ */
2/*
3 * Copyright (C) 2008 Nobuhiro Iwamatsu
4 * Copyright (C) 2008 Renesas Solutions Corp.
5 */
6#include <config.h>
7
8#include <asm/processor.h>
9#include <asm/macro.h>
10
11	.global	lowlevel_init
12
13	.text
14	.align	2
15
16lowlevel_init:
17	/* Cache setting */
18	write32	CCR1_A ,CCR1_D
19
20	/* ConfigurePortPins */
21	write16	PECRL3_A, PECRL3_D
22
23	write16	PCCRL4_A, PCCRL4_D0
24
25	write16	PECRL4_A, PECRL4_D0
26
27	write16	PEIORL_A, PEIORL_D0
28
29	write16	PCIORL_A, PCIORL_D
30
31	write16	PFCRH2_A, PFCRH2_D
32
33	write16	PFCRH3_A, PFCRH3_D
34
35	write16	PFCRH1_A, PFCRH1_D
36
37	write16	PFIORH_A, PFIORH_D
38
39	write16	PECRL1_A, PECRL1_D0
40
41	write16	PEIORL_A, PEIORL_D1
42
43	/* Configure Operating Frequency */
44	write16	WTCSR_A, WTCSR_D0
45
46	write16	WTCSR_A, WTCSR_D1
47
48	write16	WTCNT_A, WTCNT_D
49
50	/* Set clock mode*/
51	write16	FRQCR_A, FRQCR_D
52
53	/* Configure Bus And Memory */
54init_bsc_cs0:
55	write16	PCCRL4_A, PCCRL4_D1
56
57	write16	PECRL1_A, PECRL1_D1
58
59	write32	CMNCR_A, CMNCR_D
60
61	write32	CS0BCR_A, CS0BCR_D
62
63	write32	CS0WCR_A, CS0WCR_D
64
65init_bsc_cs1:
66	write16	PECRL4_A, PECRL4_D1
67
68	write32	CS1WCR_A, CS1WCR_D
69
70init_sdram:
71	write16	PCCRL2_A, PCCRL2_D
72
73	write16	PCCRL4_A, PCCRL4_D2
74
75	write16	PCCRL1_A, PCCRL1_D
76
77	write16	PCCRL3_A, PCCRL3_D
78
79	write32	CS3BCR_A, CS3BCR_D
80
81	write32	CS3WCR_A, CS3WCR_D
82
83	write32	SDCR_A, SDCR_D
84
85	write32	RTCOR_A, RTCOR_D
86
87	write32	RTCSR_A, RTCSR_D
88
89	/* wait 200us */
90	mov.l	REPEAT_D, r3
91	mov	#0, r2
92repeat0:
93	add	#1, r2
94	cmp/hs	r3, r2
95	bf	repeat0
96	nop
97
98	mov.l	SDRAM_MODE, r1
99	mov	#0, r0
100	mov.l	r0, @r1
101
102	nop
103	rts
104
105	.align 4
106
107CCR1_A:		.long CCR1
108CCR1_D:		.long 0x0000090B
109PCCRL4_A:	.long 0xFFFE3910
110PCCRL4_D0:	.word 0x0000
111.align 2
112PECRL4_A:	.long 0xFFFE3A10
113PECRL4_D0:	.word 0x0000
114.align 2
115PECRL3_A:	.long 0xFFFE3A12
116PECRL3_D:	.word 0x0000
117.align 2
118PEIORL_A:	.long 0xFFFE3A06
119PEIORL_D0:	.word 0x1C00
120PEIORL_D1:	.word 0x1C02
121PCIORL_A:	.long 0xFFFE3906
122PCIORL_D:	.word 0x4000
123.align 2
124PFCRH2_A:	.long 0xFFFE3A8C
125PFCRH2_D:	.word 0x0000
126.align 2
127PFCRH3_A:	.long 0xFFFE3A8A
128PFCRH3_D:	.word 0x0000
129.align 2
130PFCRH1_A:	.long 0xFFFE3A8E
131PFCRH1_D:	.word 0x0000
132.align 2
133PFIORH_A:	.long 0xFFFE3A84
134PFIORH_D:	.word 0x0729
135.align 2
136PECRL1_A:	.long 0xFFFE3A16
137PECRL1_D0:	.word 0x0033
138.align 2
139
140
141WTCSR_A:	.long 0xFFFE0000
142WTCSR_D0:	.word 0xA518
143WTCSR_D1:	.word 0xA51D
144WTCNT_A:	.long 0xFFFE0002
145WTCNT_D:	.word 0x5A84
146.align 2
147FRQCR_A:	.long 0xFFFE0010
148FRQCR_D:	.word 0x0104
149.align 2
150
151PCCRL4_D1:	.word 0x0010
152PECRL1_D1:	.word 0x0133
153
154CMNCR_A:	.long 0xFFFC0000
155CMNCR_D:	.long 0x00001810
156CS0BCR_A:	.long 0xFFFC0004
157CS0BCR_D:	.long 0x10000400
158CS0WCR_A:	.long 0xFFFC0028
159CS0WCR_D:	.long 0x00000B41
160PECRL4_D1:	.word 0x0100
161.align 2
162CS1WCR_A:	.long 0xFFFC002C
163CS1WCR_D:	.long 0x00000B01
164PCCRL4_D2:	.word 0x0011
165.align 2
166PCCRL3_A:	.long 0xFFFE3912
167PCCRL3_D:	.word 0x0011
168.align 2
169PCCRL2_A:	.long 0xFFFE3914
170PCCRL2_D:	.word 0x1111
171.align 2
172PCCRL1_A:	.long 0xFFFE3916
173PCCRL1_D:	.word 0x1010
174.align 2
175PDCRL4_A:	.long 0xFFFE3990
176PDCRL4_D:	.word 0x0011
177.align 2
178PDCRL3_A:	.long 0xFFFE3992
179PDCRL3_D:	.word 0x00011
180.align 2
181PDCRL2_A:	.long 0xFFFE3994
182PDCRL2_D:	.word 0x1111
183.align 2
184PDCRL1_A:	.long 0xFFFE3996
185PDCRL1_D:	.word 0x1000
186.align 2
187CS3BCR_A:	.long 0xFFFC0010
188CS3BCR_D:	.long 0x00004400
189CS3WCR_A:	.long 0xFFFC0034
190CS3WCR_D:	.long 0x00002892
191SDCR_A:		.long 0xFFFC004C
192SDCR_D:		.long 0x00000809
193RTCOR_A:	.long 0xFFFC0058
194RTCOR_D:	.long 0xA55A0041
195RTCSR_A:	.long 0xFFFC0050
196RTCSR_D:	.long 0xa55a0010
197
198SDRAM_MODE:	.long 0xFFFC5040
199REPEAT_D:	.long 0x00009C40
200