1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (C) Marvell International Ltd. and its affiliates
4  */
5 
6 #ifndef _DDR3_TRAINING_IP_DB_H_
7 #define _DDR3_TRAINING_IP_DB_H_
8 
9 enum hws_pattern {
10 	PATTERN_PBS1,
11 	PATTERN_PBS2,
12 	PATTERN_PBS3,
13 	PATTERN_TEST,
14 	PATTERN_RL,
15 	PATTERN_RL2,
16 	PATTERN_STATIC_PBS,
17 	PATTERN_KILLER_DQ0,
18 	PATTERN_KILLER_DQ1,
19 	PATTERN_KILLER_DQ2,
20 	PATTERN_KILLER_DQ3,
21 	PATTERN_KILLER_DQ4,
22 	PATTERN_KILLER_DQ5,
23 	PATTERN_KILLER_DQ6,
24 	PATTERN_KILLER_DQ7,
25 	PATTERN_VREF,
26 	PATTERN_FULL_SSO0,
27 	PATTERN_FULL_SSO1,
28 	PATTERN_FULL_SSO2,
29 	PATTERN_FULL_SSO3,
30 	PATTERN_LAST,
31 	PATTERN_SSO_FULL_XTALK_DQ0,
32 	PATTERN_SSO_FULL_XTALK_DQ1,
33 	PATTERN_SSO_FULL_XTALK_DQ2,
34 	PATTERN_SSO_FULL_XTALK_DQ3,
35 	PATTERN_SSO_FULL_XTALK_DQ4,
36 	PATTERN_SSO_FULL_XTALK_DQ5,
37 	PATTERN_SSO_FULL_XTALK_DQ6,
38 	PATTERN_SSO_FULL_XTALK_DQ7,
39 	PATTERN_SSO_XTALK_FREE_DQ0,
40 	PATTERN_SSO_XTALK_FREE_DQ1,
41 	PATTERN_SSO_XTALK_FREE_DQ2,
42 	PATTERN_SSO_XTALK_FREE_DQ3,
43 	PATTERN_SSO_XTALK_FREE_DQ4,
44 	PATTERN_SSO_XTALK_FREE_DQ5,
45 	PATTERN_SSO_XTALK_FREE_DQ6,
46 	PATTERN_SSO_XTALK_FREE_DQ7,
47 	PATTERN_ISI_XTALK_FREE
48 };
49 
50 enum mv_wl_supp_mode {
51 	WRITE_LEVELING_SUPP_REG_MODE,
52 	WRITE_LEVELING_SUPP_ECC_MODE_DATA_PUPS,
53 	WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP4,
54 	WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP3,
55 	WRITE_LEVELING_SUPP_ECC_MODE_ECC_PUP8
56 };
57 
58 enum mv_ddr_dev_attribute {
59 	MV_ATTR_TIP_REV,
60 	MV_ATTR_PHY_EDGE,
61 	MV_ATTR_OCTET_PER_INTERFACE,
62 	MV_ATTR_PLL_BEFORE_INIT,
63 	MV_ATTR_TUNE_MASK,
64 	MV_ATTR_INIT_FREQ,
65 	MV_ATTR_MID_FREQ,
66 	MV_ATTR_DFS_LOW_FREQ,
67 	MV_ATTR_DFS_LOW_PHY,
68 	MV_ATTR_DELAY_ENABLE,
69 	MV_ATTR_CK_DELAY,
70 	MV_ATTR_CA_DELAY,
71 	MV_ATTR_INTERLEAVE_WA,
72 	MV_ATTR_LAST
73 };
74 
75 enum mv_ddr_tip_revison {
76 	MV_TIP_REV_NA,
77 	MV_TIP_REV_1, /* NP5 */
78 	MV_TIP_REV_2, /* BC2 */
79 	MV_TIP_REV_3, /* AC3 */
80 	MV_TIP_REV_4, /* A-380/A-390 */
81 	MV_TIP_REV_LAST
82 };
83 
84 enum mv_ddr_phy_edge {
85 	MV_DDR_PHY_EDGE_POSITIVE,
86 	MV_DDR_PHY_EDGE_NEGATIVE
87 };
88 
89 /* Device attribute functions */
90 void ddr3_tip_dev_attr_init(u32 dev_num);
91 u32 ddr3_tip_dev_attr_get(u32 dev_num, enum mv_ddr_dev_attribute attr_id);
92 void ddr3_tip_dev_attr_set(u32 dev_num, enum mv_ddr_dev_attribute attr_id, u32 value);
93 
94 #endif /* _DDR3_TRAINING_IP_DB_H_ */
95