1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3 * Copyright (c) 2011 The Chromium OS Authors.
4 * Copyright (c) 2009-2015 NVIDIA Corporation
5 * Copyright (c) 2013 Lucas Stach
6 */
7
8 #include <common.h>
9 #include <dm.h>
10 #include <linux/errno.h>
11 #include <asm/io.h>
12 #include <asm-generic/gpio.h>
13 #include <asm/arch/clock.h>
14 #include <asm/arch-tegra/usb.h>
15 #include <asm/arch-tegra/clk_rst.h>
16 #include <usb.h>
17 #include <usb/ulpi.h>
18 #include <linux/libfdt.h>
19
20 #include "ehci.h"
21
22 #define USB1_ADDR_MASK 0xFFFF0000
23
24 #define HOSTPC1_DEVLC 0x84
25 #define HOSTPC1_PSPD(x) (((x) >> 25) & 0x3)
26
27 #ifdef CONFIG_USB_ULPI
28 #ifndef CONFIG_USB_ULPI_VIEWPORT
29 #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \
30 define CONFIG_USB_ULPI_VIEWPORT"
31 #endif
32 #endif
33
34 /* Parameters we need for USB */
35 enum {
36 PARAM_DIVN, /* PLL FEEDBACK DIVIDer */
37 PARAM_DIVM, /* PLL INPUT DIVIDER */
38 PARAM_DIVP, /* POST DIVIDER (2^N) */
39 PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */
40 PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */
41 PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */
42 PARAM_STABLE_COUNT, /* PLL-U STABLE count */
43 PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */
44 PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */
45 PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */
46 PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */
47
48 PARAM_COUNT
49 };
50
51 /* Possible port types (dual role mode) */
52 enum dr_mode {
53 DR_MODE_NONE = 0,
54 DR_MODE_HOST, /* supports host operation */
55 DR_MODE_DEVICE, /* supports device operation */
56 DR_MODE_OTG, /* supports both */
57 };
58
59 enum usb_ctlr_type {
60 USB_CTLR_T20,
61 USB_CTLR_T30,
62 USB_CTLR_T114,
63 USB_CTLR_T210,
64
65 USB_CTRL_COUNT,
66 };
67
68 /* Information about a USB port */
69 struct fdt_usb {
70 struct ehci_ctrl ehci;
71 struct usb_ctlr *reg; /* address of registers in physical memory */
72 unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */
73 unsigned ulpi:1; /* 1 if port has external ULPI transceiver */
74 unsigned enabled:1; /* 1 to enable, 0 to disable */
75 unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
76 enum usb_ctlr_type type;
77 enum usb_init_type init_type;
78 enum dr_mode dr_mode; /* dual role mode */
79 enum periph_id periph_id;/* peripheral id */
80 struct gpio_desc vbus_gpio; /* GPIO for vbus enable */
81 struct gpio_desc phy_reset_gpio; /* GPIO to reset ULPI phy */
82 };
83
84 /*
85 * This table has USB timing parameters for each Oscillator frequency we
86 * support. There are four sets of values:
87 *
88 * 1. PLLU configuration information (reference clock is osc/clk_m and
89 * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
90 *
91 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
92 * ----------------------------------------------------------------------
93 * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0)
94 * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a)
95 * Filter frequency (MHz) 1 4.8 6 2
96 * CPCON 1100b 0011b 1100b 1100b
97 * LFCON0 0 0 0 0
98 *
99 * 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
100 *
101 * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
102 * ---------------------------------------------------------------------------
103 * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04)
104 * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66)
105 * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09)
106 * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE)
107 *
108 * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
109 * SessEnd. Each of these signals have their own debouncer and for each of
110 * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
111 * BIAS_DEBOUNCE_B).
112 *
113 * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
114 * 0xffff -> No debouncing at all
115 * <n> ms = <n> *1000 / (1/19.2MHz) / 4
116 *
117 * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have:
118 * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0
119 *
120 * We need to use only DebounceA for BOOTROM. We don't need the DebounceB
121 * values, so we can keep those to default.
122 *
123 * 4. The 20 microsecond delay after bias cell operation.
124 */
125 static const unsigned T20_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
126 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
127 { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
128 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
129 { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
130 { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 },
131 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 },
132 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }
133 };
134
135 static const unsigned T30_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
136 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
137 { 0x3C0, 0x0D, 0x00, 0xC, 1, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 5 },
138 { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 7 },
139 { 0x3C0, 0x0C, 0x00, 0xC, 1, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 },
140 { 0x3C0, 0x1A, 0x00, 0xC, 1, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 },
141 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 },
142 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }
143 };
144
145 static const unsigned T114_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
146 /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
147 { 0x3C0, 0x0D, 0x00, 0xC, 2, 0x02, 0x33, 0x09, 0x7F, 0x7EF4, 6 },
148 { 0x0C8, 0x04, 0x00, 0x3, 2, 0x03, 0x4B, 0x0C, 0xBB, 0xBB80, 8 },
149 { 0x3C0, 0x0C, 0x00, 0xC, 2, 0x02, 0x2F, 0x08, 0x76, 0x7530, 5 },
150 { 0x3C0, 0x1A, 0x00, 0xC, 2, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 11 },
151 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 },
152 { 0x000, 0x00, 0x00, 0x0, 0, 0x00, 0x00, 0x00, 0x00, 0x0000, 0 }
153 };
154
155 /* NOTE: 13/26MHz settings are N/A for T210, so dupe 12MHz settings for now */
156 static const unsigned T210_usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
157 /* DivN, DivM, DivP, KCP, KVCO, Delays Debounce, Bias */
158 { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 32500, 5 },
159 { 0x019, 0x01, 0x01, 0x0, 0, 0x03, 0x4B, 0x0C, 0xBB, 48000, 8 },
160 { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 30000, 5 },
161 { 0x028, 0x01, 0x01, 0x0, 0, 0x02, 0x2F, 0x08, 0x76, 65000, 5 },
162 { 0x019, 0x02, 0x01, 0x0, 0, 0x05, 0x96, 0x18, 0x177, 96000, 15 },
163 { 0x028, 0x04, 0x01, 0x0, 0, 0x04, 0x66, 0x09, 0xFE, 120000, 20 }
164 };
165
166 /* UTMIP Idle Wait Delay */
167 static const u8 utmip_idle_wait_delay = 17;
168
169 /* UTMIP Elastic limit */
170 static const u8 utmip_elastic_limit = 16;
171
172 /* UTMIP High Speed Sync Start Delay */
173 static const u8 utmip_hs_sync_start_delay = 9;
174
175 struct fdt_usb_controller {
176 /* flag to determine whether controller supports hostpc register */
177 u32 has_hostpc:1;
178 const unsigned *pll_parameter;
179 };
180
181 static struct fdt_usb_controller fdt_usb_controllers[USB_CTRL_COUNT] = {
182 {
183 .has_hostpc = 0,
184 .pll_parameter = (const unsigned *)T20_usb_pll,
185 },
186 {
187 .has_hostpc = 1,
188 .pll_parameter = (const unsigned *)T30_usb_pll,
189 },
190 {
191 .has_hostpc = 1,
192 .pll_parameter = (const unsigned *)T114_usb_pll,
193 },
194 {
195 .has_hostpc = 1,
196 .pll_parameter = (const unsigned *)T210_usb_pll,
197 },
198 };
199
200 /*
201 * A known hardware issue where Connect Status Change bit of PORTSC register
202 * of USB1 controller will be set after Port Reset.
203 * We have to clear it in order for later device enumeration to proceed.
204 */
tegra_ehci_powerup_fixup(struct ehci_ctrl * ctrl,uint32_t * status_reg,uint32_t * reg)205 static void tegra_ehci_powerup_fixup(struct ehci_ctrl *ctrl,
206 uint32_t *status_reg, uint32_t *reg)
207 {
208 struct fdt_usb *config = ctrl->priv;
209 struct fdt_usb_controller *controller;
210
211 controller = &fdt_usb_controllers[config->type];
212 mdelay(50);
213 /* This is to avoid PORT_ENABLE bit to be cleared in "ehci-hcd.c". */
214 if (controller->has_hostpc)
215 *reg |= EHCI_PS_PE;
216
217 if (!config->has_legacy_mode)
218 return;
219 /* For EHCI_PS_CSC to be cleared in ehci_hcd.c */
220 if (ehci_readl(status_reg) & EHCI_PS_CSC)
221 *reg |= EHCI_PS_CSC;
222 }
223
tegra_ehci_set_usbmode(struct ehci_ctrl * ctrl)224 static void tegra_ehci_set_usbmode(struct ehci_ctrl *ctrl)
225 {
226 struct fdt_usb *config = ctrl->priv;
227 struct usb_ctlr *usbctlr;
228 uint32_t tmp;
229
230 usbctlr = config->reg;
231
232 tmp = ehci_readl(&usbctlr->usb_mode);
233 tmp |= USBMODE_CM_HC;
234 ehci_writel(&usbctlr->usb_mode, tmp);
235 }
236
tegra_ehci_get_port_speed(struct ehci_ctrl * ctrl,uint32_t reg)237 static int tegra_ehci_get_port_speed(struct ehci_ctrl *ctrl, uint32_t reg)
238 {
239 struct fdt_usb *config = ctrl->priv;
240 struct fdt_usb_controller *controller;
241 uint32_t tmp;
242 uint32_t *reg_ptr;
243
244 controller = &fdt_usb_controllers[config->type];
245 if (controller->has_hostpc) {
246 reg_ptr = (uint32_t *)((u8 *)&ctrl->hcor->or_usbcmd +
247 HOSTPC1_DEVLC);
248 tmp = ehci_readl(reg_ptr);
249 return HOSTPC1_PSPD(tmp);
250 } else
251 return PORTSC_PSPD(reg);
252 }
253
254 /* Set up VBUS for host/device mode */
set_up_vbus(struct fdt_usb * config,enum usb_init_type init)255 static void set_up_vbus(struct fdt_usb *config, enum usb_init_type init)
256 {
257 /*
258 * If we are an OTG port initializing in host mode,
259 * check if remote host is driving VBus and bail out in this case.
260 */
261 if (init == USB_INIT_HOST &&
262 config->dr_mode == DR_MODE_OTG &&
263 (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS)) {
264 printf("tegrausb: VBUS input active; not enabling as host\n");
265 return;
266 }
267
268 if (dm_gpio_is_valid(&config->vbus_gpio)) {
269 int vbus_value;
270
271 vbus_value = (init == USB_INIT_HOST);
272 dm_gpio_set_value(&config->vbus_gpio, vbus_value);
273
274 debug("set_up_vbus: GPIO %d %d\n",
275 gpio_get_number(&config->vbus_gpio), vbus_value);
276 }
277 }
278
usbf_reset_controller(struct fdt_usb * config,struct usb_ctlr * usbctlr)279 static void usbf_reset_controller(struct fdt_usb *config,
280 struct usb_ctlr *usbctlr)
281 {
282 /* Reset the USB controller with 2us delay */
283 reset_periph(config->periph_id, 2);
284
285 /*
286 * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under
287 * base address
288 */
289 if (config->has_legacy_mode)
290 setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE);
291
292 /* Put UTMIP1/3 in reset */
293 setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
294
295 /* Enable the UTMIP PHY */
296 if (config->utmi)
297 setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
298 }
299
get_pll_timing(struct fdt_usb_controller * controller)300 static const unsigned *get_pll_timing(struct fdt_usb_controller *controller)
301 {
302 const unsigned *timing;
303
304 timing = controller->pll_parameter +
305 clock_get_osc_freq() * PARAM_COUNT;
306
307 return timing;
308 }
309
310 /* select the PHY to use with a USB controller */
init_phy_mux(struct fdt_usb * config,uint pts,enum usb_init_type init)311 static void init_phy_mux(struct fdt_usb *config, uint pts,
312 enum usb_init_type init)
313 {
314 struct usb_ctlr *usbctlr = config->reg;
315
316 #if defined(CONFIG_TEGRA20)
317 if (config->periph_id == PERIPH_ID_USBD) {
318 clrsetbits_le32(&usbctlr->port_sc1, PTS1_MASK,
319 pts << PTS1_SHIFT);
320 clrbits_le32(&usbctlr->port_sc1, STS1);
321 } else {
322 clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
323 pts << PTS_SHIFT);
324 clrbits_le32(&usbctlr->port_sc1, STS);
325 }
326 #else
327 /* Set to Host mode (if applicable) after Controller Reset was done */
328 clrsetbits_le32(&usbctlr->usb_mode, USBMODE_CM_HC,
329 (init == USB_INIT_HOST) ? USBMODE_CM_HC : 0);
330 /*
331 * Select PHY interface after setting host mode.
332 * For device mode, the ordering requirement is not an issue, since
333 * only the first USB controller supports device mode, and that USB
334 * controller can only talk to a UTMI PHY, so the PHY selection is
335 * already made at reset time, so this write is a no-op.
336 */
337 clrsetbits_le32(&usbctlr->hostpc1_devlc, PTS_MASK,
338 pts << PTS_SHIFT);
339 clrbits_le32(&usbctlr->hostpc1_devlc, STS);
340 #endif
341 }
342
343 /* set up the UTMI USB controller with the parameters provided */
init_utmi_usb_controller(struct fdt_usb * config,enum usb_init_type init)344 static int init_utmi_usb_controller(struct fdt_usb *config,
345 enum usb_init_type init)
346 {
347 struct fdt_usb_controller *controller;
348 u32 b_sess_valid_mask, val;
349 int loop_count;
350 const unsigned *timing;
351 struct usb_ctlr *usbctlr = config->reg;
352 struct clk_rst_ctlr *clkrst;
353 struct usb_ctlr *usb1ctlr;
354
355 clock_enable(config->periph_id);
356
357 /* Reset the usb controller */
358 usbf_reset_controller(config, usbctlr);
359
360 /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
361 clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
362
363 /* Follow the crystal clock disable by >100ns delay */
364 udelay(1);
365
366 b_sess_valid_mask = (VBUS_B_SESS_VLD_SW_VALUE | VBUS_B_SESS_VLD_SW_EN);
367 clrsetbits_le32(&usbctlr->phy_vbus_sensors, b_sess_valid_mask,
368 (init == USB_INIT_DEVICE) ? b_sess_valid_mask : 0);
369
370 /*
371 * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
372 * mux must be switched to actually use a_sess_vld threshold.
373 */
374 if (config->dr_mode == DR_MODE_OTG &&
375 dm_gpio_is_valid(&config->vbus_gpio))
376 clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
377 VBUS_SENSE_CTL_MASK,
378 VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
379
380 controller = &fdt_usb_controllers[config->type];
381 debug("controller=%p, type=%d\n", controller, config->type);
382
383 /*
384 * PLL Delay CONFIGURATION settings. The following parameters control
385 * the bring up of the plls.
386 */
387 timing = get_pll_timing(controller);
388
389 if (!controller->has_hostpc) {
390 val = readl(&usbctlr->utmip_misc_cfg1);
391 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
392 timing[PARAM_STABLE_COUNT] <<
393 UTMIP_PLLU_STABLE_COUNT_SHIFT);
394 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
395 timing[PARAM_ACTIVE_DELAY_COUNT] <<
396 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
397 writel(val, &usbctlr->utmip_misc_cfg1);
398
399 /* Set PLL enable delay count and crystal frequency count */
400 val = readl(&usbctlr->utmip_pll_cfg1);
401 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
402 timing[PARAM_ENABLE_DELAY_COUNT] <<
403 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
404 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
405 timing[PARAM_XTAL_FREQ_COUNT] <<
406 UTMIP_XTAL_FREQ_COUNT_SHIFT);
407 writel(val, &usbctlr->utmip_pll_cfg1);
408 } else {
409 clkrst = (struct clk_rst_ctlr *)NV_PA_CLK_RST_BASE;
410
411 val = readl(&clkrst->crc_utmip_pll_cfg2);
412 clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
413 timing[PARAM_STABLE_COUNT] <<
414 UTMIP_PLLU_STABLE_COUNT_SHIFT);
415 clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
416 timing[PARAM_ACTIVE_DELAY_COUNT] <<
417 UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
418 writel(val, &clkrst->crc_utmip_pll_cfg2);
419
420 /* Set PLL enable delay count and crystal frequency count */
421 val = readl(&clkrst->crc_utmip_pll_cfg1);
422 clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
423 timing[PARAM_ENABLE_DELAY_COUNT] <<
424 UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
425 clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
426 timing[PARAM_XTAL_FREQ_COUNT] <<
427 UTMIP_XTAL_FREQ_COUNT_SHIFT);
428 writel(val, &clkrst->crc_utmip_pll_cfg1);
429
430 /* Disable Power Down state for PLL */
431 clrbits_le32(&clkrst->crc_utmip_pll_cfg1,
432 PLLU_POWERDOWN | PLL_ENABLE_POWERDOWN |
433 PLL_ACTIVE_POWERDOWN);
434
435 /* Recommended PHY settings for EYE diagram */
436 val = readl(&usbctlr->utmip_xcvr_cfg0);
437 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MASK,
438 0x4 << UTMIP_XCVR_SETUP_SHIFT);
439 clrsetbits_le32(&val, UTMIP_XCVR_SETUP_MSB_MASK,
440 0x3 << UTMIP_XCVR_SETUP_MSB_SHIFT);
441 clrsetbits_le32(&val, UTMIP_XCVR_HSSLEW_MSB_MASK,
442 0x8 << UTMIP_XCVR_HSSLEW_MSB_SHIFT);
443 writel(val, &usbctlr->utmip_xcvr_cfg0);
444 clrsetbits_le32(&usbctlr->utmip_xcvr_cfg1,
445 UTMIP_XCVR_TERM_RANGE_ADJ_MASK,
446 0x7 << UTMIP_XCVR_TERM_RANGE_ADJ_SHIFT);
447
448 /* Some registers can be controlled from USB1 only. */
449 if (config->periph_id != PERIPH_ID_USBD) {
450 clock_enable(PERIPH_ID_USBD);
451 /* Disable Reset if in Reset state */
452 reset_set_enable(PERIPH_ID_USBD, 0);
453 }
454 usb1ctlr = (struct usb_ctlr *)
455 ((unsigned long)config->reg & USB1_ADDR_MASK);
456 val = readl(&usb1ctlr->utmip_bias_cfg0);
457 setbits_le32(&val, UTMIP_HSDISCON_LEVEL_MSB);
458 clrsetbits_le32(&val, UTMIP_HSDISCON_LEVEL_MASK,
459 0x1 << UTMIP_HSDISCON_LEVEL_SHIFT);
460 clrsetbits_le32(&val, UTMIP_HSSQUELCH_LEVEL_MASK,
461 0x2 << UTMIP_HSSQUELCH_LEVEL_SHIFT);
462 writel(val, &usb1ctlr->utmip_bias_cfg0);
463
464 /* Miscellaneous setting mentioned in Programming Guide */
465 clrbits_le32(&usbctlr->utmip_misc_cfg0,
466 UTMIP_SUSPEND_EXIT_ON_EDGE);
467 }
468
469 /* Setting the tracking length time */
470 clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
471 UTMIP_BIAS_PDTRK_COUNT_MASK,
472 timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
473
474 /* Program debounce time for VBUS to become valid */
475 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
476 UTMIP_DEBOUNCE_CFG0_MASK,
477 timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
478
479 if (timing[PARAM_DEBOUNCE_A_TIME] > 0xFFFF) {
480 clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
481 UTMIP_DEBOUNCE_CFG0_MASK,
482 (timing[PARAM_DEBOUNCE_A_TIME] >> 1)
483 << UTMIP_DEBOUNCE_CFG0_SHIFT);
484 clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
485 UTMIP_BIAS_DEBOUNCE_TIMESCALE_MASK,
486 1 << UTMIP_BIAS_DEBOUNCE_TIMESCALE_SHIFT);
487 }
488
489 setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
490
491 /* Disable battery charge enabling bit */
492 setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
493
494 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
495 setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
496
497 /*
498 * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
499 * Setting these fields, together with default values of the
500 * other fields, results in programming the registers below as
501 * follows:
502 * UTMIP_HSRX_CFG0 = 0x9168c000
503 * UTMIP_HSRX_CFG1 = 0x13
504 */
505
506 /* Set PLL enable delay count and Crystal frequency count */
507 val = readl(&usbctlr->utmip_hsrx_cfg0);
508 clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
509 utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
510 clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
511 utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
512 writel(val, &usbctlr->utmip_hsrx_cfg0);
513
514 /* Configure the UTMIP_HS_SYNC_START_DLY */
515 clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
516 UTMIP_HS_SYNC_START_DLY_MASK,
517 utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
518
519 /* Preceed the crystal clock disable by >100ns delay. */
520 udelay(1);
521
522 /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
523 setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
524
525 if (controller->has_hostpc) {
526 if (config->periph_id == PERIPH_ID_USBD)
527 clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
528 UTMIP_FORCE_PD_SAMP_A_POWERDOWN);
529 if (config->periph_id == PERIPH_ID_USB2)
530 clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
531 UTMIP_FORCE_PD_SAMP_B_POWERDOWN);
532 if (config->periph_id == PERIPH_ID_USB3)
533 clrbits_le32(&clkrst->crc_utmip_pll_cfg2,
534 UTMIP_FORCE_PD_SAMP_C_POWERDOWN);
535 }
536 /* Finished the per-controller init. */
537
538 /* De-assert UTMIP_RESET to bring out of reset. */
539 clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
540
541 /* Wait for the phy clock to become valid in 100 ms */
542 for (loop_count = 100000; loop_count != 0; loop_count--) {
543 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
544 break;
545 udelay(1);
546 }
547 if (!loop_count)
548 return -ETIMEDOUT;
549
550 /* Disable ICUSB FS/LS transceiver */
551 clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
552
553 /* Select UTMI parallel interface */
554 init_phy_mux(config, PTS_UTMI, init);
555
556 /* Deassert power down state */
557 clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
558 UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
559 clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
560 UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
561
562 if (controller->has_hostpc) {
563 /*
564 * BIAS Pad Power Down is common among all 3 USB
565 * controllers and can be controlled from USB1 only.
566 */
567 usb1ctlr = (struct usb_ctlr *)
568 ((unsigned long)config->reg & USB1_ADDR_MASK);
569 clrbits_le32(&usb1ctlr->utmip_bias_cfg0, UTMIP_BIASPD);
570 udelay(25);
571 clrbits_le32(&usb1ctlr->utmip_bias_cfg1,
572 UTMIP_FORCE_PDTRK_POWERDOWN);
573 }
574 return 0;
575 }
576
577 #ifdef CONFIG_USB_ULPI
578 /* if board file does not set a ULPI reference frequency we default to 24MHz */
579 #ifndef CONFIG_ULPI_REF_CLK
580 #define CONFIG_ULPI_REF_CLK 24000000
581 #endif
582
583 /* set up the ULPI USB controller with the parameters provided */
init_ulpi_usb_controller(struct fdt_usb * config,enum usb_init_type init)584 static int init_ulpi_usb_controller(struct fdt_usb *config,
585 enum usb_init_type init)
586 {
587 u32 val;
588 int loop_count;
589 struct ulpi_viewport ulpi_vp;
590 struct usb_ctlr *usbctlr = config->reg;
591 int ret;
592
593 /* set up ULPI reference clock on pllp_out4 */
594 clock_enable(PERIPH_ID_DEV2_OUT);
595 clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK);
596
597 /* reset ULPI phy */
598 if (dm_gpio_is_valid(&config->phy_reset_gpio)) {
599 /*
600 * This GPIO is typically active-low, and marked as such in
601 * device tree. dm_gpio_set_value() takes this into account
602 * and inverts the value we pass here if required. In other
603 * words, this first call logically asserts the reset signal,
604 * which typically results in driving the physical GPIO low,
605 * and the second call logically de-asserts the reset signal,
606 * which typically results in driver the GPIO high.
607 */
608 dm_gpio_set_value(&config->phy_reset_gpio, 1);
609 mdelay(5);
610 dm_gpio_set_value(&config->phy_reset_gpio, 0);
611 }
612
613 /* Reset the usb controller */
614 clock_enable(config->periph_id);
615 usbf_reset_controller(config, usbctlr);
616
617 /* enable pinmux bypass */
618 setbits_le32(&usbctlr->ulpi_timing_ctrl_0,
619 ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
620
621 /* Select ULPI parallel interface */
622 init_phy_mux(config, PTS_ULPI, init);
623
624 /* enable ULPI transceiver */
625 setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
626
627 /* configure ULPI transceiver timings */
628 val = 0;
629 writel(val, &usbctlr->ulpi_timing_ctrl_1);
630
631 val |= ULPI_DATA_TRIMMER_SEL(4);
632 val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
633 val |= ULPI_DIR_TRIMMER_SEL(4);
634 writel(val, &usbctlr->ulpi_timing_ctrl_1);
635 udelay(10);
636
637 val |= ULPI_DATA_TRIMMER_LOAD;
638 val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
639 val |= ULPI_DIR_TRIMMER_LOAD;
640 writel(val, &usbctlr->ulpi_timing_ctrl_1);
641
642 /* set up phy for host operation with external vbus supply */
643 ulpi_vp.port_num = 0;
644 ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport;
645
646 ret = ulpi_init(&ulpi_vp);
647 if (ret) {
648 printf("Tegra ULPI viewport init failed\n");
649 return ret;
650 }
651
652 ulpi_set_vbus(&ulpi_vp, 1, 1);
653 ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0);
654
655 /* enable wakeup events */
656 setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC);
657
658 /* Enable and wait for the phy clock to become valid in 100 ms */
659 setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
660 for (loop_count = 100000; loop_count != 0; loop_count--) {
661 if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
662 break;
663 udelay(1);
664 }
665 if (!loop_count)
666 return -ETIMEDOUT;
667 clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
668
669 return 0;
670 }
671 #else
init_ulpi_usb_controller(struct fdt_usb * config,enum usb_init_type init)672 static int init_ulpi_usb_controller(struct fdt_usb *config,
673 enum usb_init_type init)
674 {
675 printf("No code to set up ULPI controller, please enable"
676 "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT");
677 return -ENOSYS;
678 }
679 #endif
680
config_clock(const u32 timing[])681 static void config_clock(const u32 timing[])
682 {
683 debug("%s: DIVM = %d, DIVN = %d, DIVP = %d, cpcon/lfcon = %d/%d\n",
684 __func__, timing[PARAM_DIVM], timing[PARAM_DIVN],
685 timing[PARAM_DIVP], timing[PARAM_CPCON], timing[PARAM_LFCON]);
686
687 clock_start_pll(CLOCK_ID_USB,
688 timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
689 timing[PARAM_CPCON], timing[PARAM_LFCON]);
690 }
691
fdt_decode_usb(struct udevice * dev,struct fdt_usb * config)692 static int fdt_decode_usb(struct udevice *dev, struct fdt_usb *config)
693 {
694 const char *phy, *mode;
695
696 config->reg = (struct usb_ctlr *)dev_read_addr(dev);
697 debug("reg=%p\n", config->reg);
698 mode = dev_read_string(dev, "dr_mode");
699 if (mode) {
700 if (0 == strcmp(mode, "host"))
701 config->dr_mode = DR_MODE_HOST;
702 else if (0 == strcmp(mode, "peripheral"))
703 config->dr_mode = DR_MODE_DEVICE;
704 else if (0 == strcmp(mode, "otg"))
705 config->dr_mode = DR_MODE_OTG;
706 else {
707 debug("%s: Cannot decode dr_mode '%s'\n", __func__,
708 mode);
709 return -EINVAL;
710 }
711 } else {
712 config->dr_mode = DR_MODE_HOST;
713 }
714
715 phy = dev_read_string(dev, "phy_type");
716 config->utmi = phy && 0 == strcmp("utmi", phy);
717 config->ulpi = phy && 0 == strcmp("ulpi", phy);
718 config->has_legacy_mode = dev_read_bool(dev, "nvidia,has-legacy-mode");
719 config->periph_id = clock_decode_periph_id(dev);
720 if (config->periph_id == PERIPH_ID_NONE) {
721 debug("%s: Missing/invalid peripheral ID\n", __func__);
722 return -EINVAL;
723 }
724 gpio_request_by_name(dev, "nvidia,vbus-gpio", 0, &config->vbus_gpio,
725 GPIOD_IS_OUT);
726 gpio_request_by_name(dev, "nvidia,phy-reset-gpio", 0,
727 &config->phy_reset_gpio, GPIOD_IS_OUT);
728 debug("legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, vbus=%d, phy_reset=%d, dr_mode=%d, reg=%p\n",
729 config->has_legacy_mode, config->utmi, config->ulpi,
730 config->periph_id, gpio_get_number(&config->vbus_gpio),
731 gpio_get_number(&config->phy_reset_gpio), config->dr_mode,
732 config->reg);
733
734 return 0;
735 }
736
usb_common_init(struct fdt_usb * config,enum usb_init_type init)737 int usb_common_init(struct fdt_usb *config, enum usb_init_type init)
738 {
739 int ret = 0;
740
741 switch (init) {
742 case USB_INIT_HOST:
743 switch (config->dr_mode) {
744 case DR_MODE_HOST:
745 case DR_MODE_OTG:
746 break;
747 default:
748 printf("tegrausb: Invalid dr_mode %d for host mode\n",
749 config->dr_mode);
750 return -1;
751 }
752 break;
753 case USB_INIT_DEVICE:
754 if (config->periph_id != PERIPH_ID_USBD) {
755 printf("tegrausb: Device mode only supported on first USB controller\n");
756 return -1;
757 }
758 if (!config->utmi) {
759 printf("tegrausb: Device mode only supported with UTMI PHY\n");
760 return -1;
761 }
762 switch (config->dr_mode) {
763 case DR_MODE_DEVICE:
764 case DR_MODE_OTG:
765 break;
766 default:
767 printf("tegrausb: Invalid dr_mode %d for device mode\n",
768 config->dr_mode);
769 return -1;
770 }
771 break;
772 default:
773 printf("tegrausb: Unknown USB_INIT_* %d\n", init);
774 return -1;
775 }
776
777 debug("%d, %d\n", config->utmi, config->ulpi);
778 if (config->utmi)
779 ret = init_utmi_usb_controller(config, init);
780 else if (config->ulpi)
781 ret = init_ulpi_usb_controller(config, init);
782 if (ret)
783 return ret;
784
785 set_up_vbus(config, init);
786
787 config->init_type = init;
788
789 return 0;
790 }
791
usb_common_uninit(struct fdt_usb * priv)792 void usb_common_uninit(struct fdt_usb *priv)
793 {
794 struct usb_ctlr *usbctlr;
795
796 usbctlr = priv->reg;
797
798 /* Stop controller */
799 writel(0, &usbctlr->usb_cmd);
800 udelay(1000);
801
802 /* Initiate controller reset */
803 writel(2, &usbctlr->usb_cmd);
804 udelay(1000);
805 }
806
807 static const struct ehci_ops tegra_ehci_ops = {
808 .set_usb_mode = tegra_ehci_set_usbmode,
809 .get_port_speed = tegra_ehci_get_port_speed,
810 .powerup_fixup = tegra_ehci_powerup_fixup,
811 };
812
ehci_usb_ofdata_to_platdata(struct udevice * dev)813 static int ehci_usb_ofdata_to_platdata(struct udevice *dev)
814 {
815 struct fdt_usb *priv = dev_get_priv(dev);
816 int ret;
817
818 ret = fdt_decode_usb(dev, priv);
819 if (ret)
820 return ret;
821
822 priv->type = dev_get_driver_data(dev);
823
824 return 0;
825 }
826
ehci_usb_probe(struct udevice * dev)827 static int ehci_usb_probe(struct udevice *dev)
828 {
829 struct usb_platdata *plat = dev_get_platdata(dev);
830 struct fdt_usb *priv = dev_get_priv(dev);
831 struct ehci_hccr *hccr;
832 struct ehci_hcor *hcor;
833 static bool clk_done;
834 int ret;
835
836 ret = usb_common_init(priv, plat->init_type);
837 if (ret)
838 return ret;
839 hccr = (struct ehci_hccr *)&priv->reg->cap_length;
840 hcor = (struct ehci_hcor *)&priv->reg->usb_cmd;
841 if (!clk_done) {
842 config_clock(get_pll_timing(&fdt_usb_controllers[priv->type]));
843 clk_done = true;
844 }
845
846 return ehci_register(dev, hccr, hcor, &tegra_ehci_ops, 0,
847 plat->init_type);
848 }
849
850 static const struct udevice_id ehci_usb_ids[] = {
851 { .compatible = "nvidia,tegra20-ehci", .data = USB_CTLR_T20 },
852 { .compatible = "nvidia,tegra30-ehci", .data = USB_CTLR_T30 },
853 { .compatible = "nvidia,tegra114-ehci", .data = USB_CTLR_T114 },
854 { .compatible = "nvidia,tegra210-ehci", .data = USB_CTLR_T210 },
855 { }
856 };
857
858 U_BOOT_DRIVER(usb_ehci) = {
859 .name = "ehci_tegra",
860 .id = UCLASS_USB,
861 .of_match = ehci_usb_ids,
862 .ofdata_to_platdata = ehci_usb_ofdata_to_platdata,
863 .probe = ehci_usb_probe,
864 .remove = ehci_deregister,
865 .ops = &ehci_usb_ops,
866 .platdata_auto_alloc_size = sizeof(struct usb_platdata),
867 .priv_auto_alloc_size = sizeof(struct fdt_usb),
868 .flags = DM_FLAG_ALLOC_PRIV_DMA,
869 };
870