xref: /openbmc/u-boot/board/ti/panda/panda.c (revision e8f80a5a)
1 // SPDX-License-Identifier: GPL-2.0+
2 /*
3  * (C) Copyright 2010
4  * Texas Instruments Incorporated, <www.ti.com>
5  * Steve Sakoman  <steve@sakoman.com>
6  */
7 #include <common.h>
8 #include <asm/mach-types.h>
9 #include <asm/arch/sys_proto.h>
10 #include <asm/arch/mmc_host_def.h>
11 #include <asm/arch/clock.h>
12 #include <asm/arch/gpio.h>
13 #include <asm/gpio.h>
14 #include <twl6030.h>
15 
16 #include "panda_mux_data.h"
17 
18 #ifdef CONFIG_USB_EHCI_HCD
19 #include <usb.h>
20 #include <asm/arch/ehci.h>
21 #include <asm/ehci-omap.h>
22 #endif
23 
24 #define PANDA_ULPI_PHY_TYPE_GPIO       182
25 #define PANDA_BOARD_ID_1_GPIO          101
26 #define PANDA_ES_BOARD_ID_1_GPIO        48
27 #define PANDA_BOARD_ID_2_GPIO          171
28 #define PANDA_ES_BOARD_ID_3_GPIO         3
29 #define PANDA_ES_BOARD_ID_4_GPIO         2
30 
31 DECLARE_GLOBAL_DATA_PTR;
32 
33 const struct omap_sysinfo sysinfo = {
34 	"Board: OMAP4 Panda\n"
35 };
36 
37 struct omap4_scrm_regs *const scrm = (struct omap4_scrm_regs *)0x4a30a000;
38 
39 /**
40  * @brief board_init
41  *
42  * @return 0
43  */
board_init(void)44 int board_init(void)
45 {
46 	gpmc_init();
47 
48 	gd->bd->bi_arch_number = MACH_TYPE_OMAP4_PANDA;
49 	gd->bd->bi_boot_params = (0x80000000 + 0x100); /* boot param addr */
50 
51 	return 0;
52 }
53 
board_eth_init(bd_t * bis)54 int board_eth_init(bd_t *bis)
55 {
56 	return 0;
57 }
58 
59 /*
60 * Routine: get_board_revision
61 * Description: Detect if we are running on a panda revision A1-A6,
62 *              or an ES panda board. This can be done by reading
63 *              the level of GPIOs and checking the processor revisions.
64 *              This should result in:
65 *			Panda 4430:
66 *              GPIO171, GPIO101, GPIO182: 0 1 1 => A1-A5
67 *              GPIO171, GPIO101, GPIO182: 1 0 1 => A6
68 *			Panda ES:
69 *              GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 0 1 1 => B1/B2
70 *              GPIO2, GPIO3, GPIO171, GPIO48, GPIO182: 0 0 1 1 1 => B3
71 */
get_board_revision(void)72 int get_board_revision(void)
73 {
74 	int board_id0, board_id1, board_id2;
75 	int board_id3, board_id4;
76 	int board_id;
77 
78 	int processor_rev = omap_revision();
79 
80 	/* Setup the mux for the common board ID pins (gpio 171 and 182) */
81 	writew((IEN | M3), (*ctrl)->control_padconf_core_base + UNIPRO_TX0);
82 	writew((IEN | M3), (*ctrl)->control_padconf_core_base + FREF_CLK2_OUT);
83 
84 	board_id0 = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
85 	board_id2 = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
86 
87 	if ((processor_rev >= OMAP4460_ES1_0 &&
88 	     processor_rev <= OMAP4460_ES1_1)) {
89 		/*
90 		 * Setup the mux for the ES specific board ID pins (gpio 101,
91 		 * 2 and 3.
92 		 */
93 		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
94 				GPMC_A24);
95 		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
96 				UNIPRO_RY0);
97 		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
98 				UNIPRO_RX1);
99 
100 		board_id1 = gpio_get_value(PANDA_ES_BOARD_ID_1_GPIO);
101 		board_id3 = gpio_get_value(PANDA_ES_BOARD_ID_3_GPIO);
102 		board_id4 = gpio_get_value(PANDA_ES_BOARD_ID_4_GPIO);
103 
104 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
105 		env_set("board_name", "panda-es");
106 #endif
107 		board_id = ((board_id4 << 4) | (board_id3 << 3) |
108 			(board_id2 << 2) | (board_id1 << 1) | (board_id0));
109 	} else {
110 		/* Setup the mux for the Ax specific board ID pins (gpio 101) */
111 		writew((IEN | M3), (*ctrl)->control_padconf_core_base +
112 				FREF_CLK2_OUT);
113 
114 		board_id1 = gpio_get_value(PANDA_BOARD_ID_1_GPIO);
115 		board_id = ((board_id2 << 2) | (board_id1 << 1) | (board_id0));
116 
117 #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
118 		if ((board_id >= 0x3) && (processor_rev == OMAP4430_ES2_3))
119 			env_set("board_name", "panda-a4");
120 #endif
121 	}
122 
123 	return board_id;
124 }
125 
126 /**
127  * is_panda_es_rev_b3() - Detect if we are running on rev B3 of panda board ES
128  *
129  *
130  * Detect if we are running on B3 version of ES panda board,
131  * This can be done by reading the level of GPIO 171 and checking the
132  * processor revisions.
133  * GPIO171: 1 => Panda ES Rev B3
134  *
135  * Return : return 1 if Panda ES Rev B3 , else return 0
136  */
is_panda_es_rev_b3(void)137 u8 is_panda_es_rev_b3(void)
138 {
139         int processor_rev = omap_revision();
140         int ret = 0;
141 
142         if ((processor_rev >= OMAP4460_ES1_0 &&
143              processor_rev <= OMAP4460_ES1_1)) {
144 
145                 /* Setup the mux for the common board ID pins (gpio 171) */
146                 writew((IEN | M3),
147 			(*ctrl)->control_padconf_core_base + UNIPRO_TX0);
148 
149                 /* if processor_rev is panda ES and GPIO171 is 1,it is rev b3 */
150                 ret = gpio_get_value(PANDA_BOARD_ID_2_GPIO);
151         }
152         return ret;
153 }
154 
155 #ifdef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS
156 /*
157  * emif_get_reg_dump() - emif_get_reg_dump strong function
158  *
159  * @emif_nr - emif base
160  * @regs - reg dump of timing values
161  *
162  * Strong function to override emif_get_reg_dump weak function in sdram_elpida.c
163  */
emif_get_reg_dump(u32 emif_nr,const struct emif_regs ** regs)164 void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs)
165 {
166 	u32 omap4_rev = omap_revision();
167 
168 	/* Same devices and geometry on both EMIFs */
169 	if (omap4_rev == OMAP4430_ES1_0)
170 		*regs = &emif_regs_elpida_380_mhz_1cs;
171 	else if (omap4_rev == OMAP4430_ES2_0)
172 		*regs = &emif_regs_elpida_200_mhz_2cs;
173 	else if (omap4_rev == OMAP4430_ES2_3)
174 		*regs = &emif_regs_elpida_400_mhz_1cs;
175 	else if (omap4_rev < OMAP4470_ES1_0) {
176 		if(is_panda_es_rev_b3())
177 			*regs = &emif_regs_elpida_400_mhz_1cs;
178 		else
179 			*regs = &emif_regs_elpida_400_mhz_2cs;
180 	}
181 	else
182 		*regs = &emif_regs_elpida_400_mhz_1cs;
183 }
184 
emif_get_dmm_regs(const struct dmm_lisa_map_regs ** dmm_lisa_regs)185 void emif_get_dmm_regs(const struct dmm_lisa_map_regs
186 						**dmm_lisa_regs)
187 {
188 	u32 omap_rev = omap_revision();
189 
190 	if (omap_rev == OMAP4430_ES1_0)
191 		*dmm_lisa_regs = &lisa_map_2G_x_1_x_2;
192 	else if (omap_rev == OMAP4430_ES2_3)
193 		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
194 	else if (omap_rev < OMAP4460_ES1_0)
195 		*dmm_lisa_regs = &lisa_map_2G_x_2_x_2;
196 	else
197 		*dmm_lisa_regs = &ma_lisa_map_2G_x_2_x_2;
198 }
199 
200 #endif
201 
202 /**
203  * @brief misc_init_r - Configure Panda board specific configurations
204  * such as power configurations, ethernet initialization as phase2 of
205  * boot sequence
206  *
207  * @return 0
208  */
misc_init_r(void)209 int misc_init_r(void)
210 {
211 	int phy_type;
212 	u32 auxclk, altclksrc;
213 
214 	/* EHCI is not supported on ES1.0 */
215 	if (omap_revision() == OMAP4430_ES1_0)
216 		return 0;
217 
218 	get_board_revision();
219 
220 	gpio_direction_input(PANDA_ULPI_PHY_TYPE_GPIO);
221 	phy_type = gpio_get_value(PANDA_ULPI_PHY_TYPE_GPIO);
222 
223 	if (phy_type == 1) {
224 		/* ULPI PHY supplied by auxclk3 derived from sys_clk */
225 		debug("ULPI PHY supplied by auxclk3\n");
226 
227 		auxclk = readl(&scrm->auxclk3);
228 		/* Select sys_clk */
229 		auxclk &= ~AUXCLK_SRCSELECT_MASK;
230 		auxclk |=  AUXCLK_SRCSELECT_SYS_CLK << AUXCLK_SRCSELECT_SHIFT;
231 		/* Set the divisor to 2 */
232 		auxclk &= ~AUXCLK_CLKDIV_MASK;
233 		auxclk |= AUXCLK_CLKDIV_2 << AUXCLK_CLKDIV_SHIFT;
234 		/* Request auxilary clock #3 */
235 		auxclk |= AUXCLK_ENABLE_MASK;
236 
237 		writel(auxclk, &scrm->auxclk3);
238 	} else {
239 		/* ULPI PHY supplied by auxclk1 derived from PER dpll */
240 		debug("ULPI PHY supplied by auxclk1\n");
241 
242 		auxclk = readl(&scrm->auxclk1);
243 		/* Select per DPLL */
244 		auxclk &= ~AUXCLK_SRCSELECT_MASK;
245 		auxclk |=  AUXCLK_SRCSELECT_PER_DPLL << AUXCLK_SRCSELECT_SHIFT;
246 		/* Set the divisor to 16 */
247 		auxclk &= ~AUXCLK_CLKDIV_MASK;
248 		auxclk |= AUXCLK_CLKDIV_16 << AUXCLK_CLKDIV_SHIFT;
249 		/* Request auxilary clock #3 */
250 		auxclk |= AUXCLK_ENABLE_MASK;
251 
252 		writel(auxclk, &scrm->auxclk1);
253 	}
254 
255 	altclksrc = readl(&scrm->altclksrc);
256 
257 	/* Activate alternate system clock supplier */
258 	altclksrc &= ~ALTCLKSRC_MODE_MASK;
259 	altclksrc |= ALTCLKSRC_MODE_ACTIVE;
260 
261 	/* enable clocks */
262 	altclksrc |= ALTCLKSRC_ENABLE_INT_MASK | ALTCLKSRC_ENABLE_EXT_MASK;
263 
264 	writel(altclksrc, &scrm->altclksrc);
265 
266 	omap_die_id_usbethaddr();
267 
268 	return 0;
269 }
270 
set_muxconf_regs(void)271 void set_muxconf_regs(void)
272 {
273 	do_set_mux((*ctrl)->control_padconf_core_base,
274 		   core_padconf_array_essential,
275 		   sizeof(core_padconf_array_essential) /
276 		   sizeof(struct pad_conf_entry));
277 
278 	do_set_mux((*ctrl)->control_padconf_wkup_base,
279 		   wkup_padconf_array_essential,
280 		   sizeof(wkup_padconf_array_essential) /
281 		   sizeof(struct pad_conf_entry));
282 
283 	if (omap_revision() >= OMAP4460_ES1_0)
284 		do_set_mux((*ctrl)->control_padconf_wkup_base,
285 			   wkup_padconf_array_essential_4460,
286 			   sizeof(wkup_padconf_array_essential_4460) /
287 			   sizeof(struct pad_conf_entry));
288 }
289 
290 #if defined(CONFIG_MMC)
board_mmc_init(bd_t * bis)291 int board_mmc_init(bd_t *bis)
292 {
293 	return omap_mmc_init(0, 0, 0, -1, -1);
294 }
295 
296 #if !defined(CONFIG_SPL_BUILD)
board_mmc_power_init(void)297 void board_mmc_power_init(void)
298 {
299 	twl6030_power_mmc_init(0);
300 }
301 #endif
302 #endif
303 
304 #ifdef CONFIG_USB_EHCI_HCD
305 
306 static struct omap_usbhs_board_data usbhs_bdata = {
307 	.port_mode[0] = OMAP_EHCI_PORT_MODE_PHY,
308 	.port_mode[1] = OMAP_USBHS_PORT_MODE_UNUSED,
309 	.port_mode[2] = OMAP_USBHS_PORT_MODE_UNUSED,
310 };
311 
ehci_hcd_init(int index,enum usb_init_type init,struct ehci_hccr ** hccr,struct ehci_hcor ** hcor)312 int ehci_hcd_init(int index, enum usb_init_type init,
313 		struct ehci_hccr **hccr, struct ehci_hcor **hcor)
314 {
315 	int ret;
316 	unsigned int utmi_clk;
317 
318 	/* Now we can enable our port clocks */
319 	utmi_clk = readl((void *)CM_L3INIT_HSUSBHOST_CLKCTRL);
320 	utmi_clk |= HSUSBHOST_CLKCTRL_CLKSEL_UTMI_P1_MASK;
321 	setbits_le32((void *)CM_L3INIT_HSUSBHOST_CLKCTRL, utmi_clk);
322 
323 	ret = omap_ehci_hcd_init(index, &usbhs_bdata, hccr, hcor);
324 	if (ret < 0)
325 		return ret;
326 
327 	return 0;
328 }
329 
ehci_hcd_stop(int index)330 int ehci_hcd_stop(int index)
331 {
332 	return omap_ehci_hcd_stop();
333 }
334 #endif
335 
336 /*
337  * get_board_rev() - get board revision
338  */
get_board_rev(void)339 u32 get_board_rev(void)
340 {
341 	return 0x20;
342 }
343