1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * Copyright (C) 2015, Bin Meng <bmeng.cn@gmail.com> 4 */ 5 6 #ifndef _ARCH_QEMU_H_ 7 #define _ARCH_QEMU_H_ 8 9 /* Programmable Attribute Map (PAM) Registers */ 10 #define I440FX_PAM 0x59 11 #define Q35_PAM 0x90 12 #define PAM_NUM 7 13 #define PAM_RW 0x33 14 15 /* X-Bus Chip Select Register */ 16 #define XBCS 0x4e 17 #define APIC_EN (1 << 8) 18 19 /* IDE Timing Register */ 20 #define IDE0_TIM 0x40 21 #define IDE1_TIM 0x42 22 #define IDE_DECODE_EN (1 << 15) 23 24 /* PCIe ECAM Base Address Register */ 25 #define PCIEX_BAR 0x60 26 #define BAR_EN (1 << 0) 27 28 /* I/O Ports */ 29 #define CMOS_ADDR_PORT 0x70 30 #define CMOS_DATA_PORT 0x71 31 32 #define LOW_RAM_ADDR 0x34 33 #define HIGH_RAM_ADDR 0x35 34 35 /* PM registers */ 36 #define PMBA 0x40 37 #define PMREGMISC 0x80 38 #define PMIOSE (1 << 0) 39 40 #endif /* _ARCH_QEMU_H_ */ 41