1 /*
2 * Samsung exynos4210 Display Controller (FIMD)
3 *
4 * Copyright (c) 2000 - 2011 Samsung Electronics Co., Ltd.
5 * All rights reserved.
6 * Based on LCD controller for Samsung S5PC1xx-based board emulation
7 * by Kirill Batuzov <batuzovk@ispras.ru>
8 *
9 * Contributed by Mitsyanko Igor <i.mitsyanko@samsung.com>
10 *
11 * This program is free software; you can redistribute it and/or modify it
12 * under the terms of the GNU General Public License as published by the
13 * Free Software Foundation; either version 2 of the License, or (at your
14 * option) any later version.
15 *
16 * This program is distributed in the hope that it will be useful,
17 * but WITHOUT ANY WARRANTY; without even the implied warranty of
18 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
19 * See the GNU General Public License for more details.
20 *
21 * You should have received a copy of the GNU General Public License along
22 * with this program; if not, see <http://www.gnu.org/licenses/>.
23 */
24
25 #include "qemu/osdep.h"
26 #include "hw/qdev-properties.h"
27 #include "hw/hw.h"
28 #include "hw/irq.h"
29 #include "hw/sysbus.h"
30 #include "migration/vmstate.h"
31 #include "ui/console.h"
32 #include "ui/pixel_ops.h"
33 #include "qemu/bswap.h"
34 #include "qemu/module.h"
35 #include "qemu/log.h"
36 #include "qapi/error.h"
37 #include "qom/object.h"
38
39 /* Debug messages configuration */
40 #define EXYNOS4210_FIMD_DEBUG 0
41 #define EXYNOS4210_FIMD_MODE_TRACE 0
42
43 #if EXYNOS4210_FIMD_DEBUG == 0
44 #define DPRINT_L1(fmt, args...) do { } while (0)
45 #define DPRINT_L2(fmt, args...) do { } while (0)
46 #elif EXYNOS4210_FIMD_DEBUG == 1
47 #define DPRINT_L1(fmt, args...) \
48 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
49 #define DPRINT_L2(fmt, args...) do { } while (0)
50 #else
51 #define DPRINT_L1(fmt, args...) \
52 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
53 #define DPRINT_L2(fmt, args...) \
54 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
55 #endif
56
57 #if EXYNOS4210_FIMD_MODE_TRACE == 0
58 #define DPRINT_TRACE(fmt, args...) do { } while (0)
59 #else
60 #define DPRINT_TRACE(fmt, args...) \
61 do {fprintf(stderr, "QEMU FIMD: "fmt, ## args); } while (0)
62 #endif
63
64 #define NUM_OF_WINDOWS 5
65 #define FIMD_REGS_SIZE 0x4114
66
67 /* Video main control registers */
68 #define FIMD_VIDCON0 0x0000
69 #define FIMD_VIDCON1 0x0004
70 #define FIMD_VIDCON2 0x0008
71 #define FIMD_VIDCON3 0x000C
72 #define FIMD_VIDCON0_ENVID_F (1 << 0)
73 #define FIMD_VIDCON0_ENVID (1 << 1)
74 #define FIMD_VIDCON0_ENVID_MASK ((1 << 0) | (1 << 1))
75 #define FIMD_VIDCON1_ROMASK 0x07FFE000
76
77 /* Video time control registers */
78 #define FIMD_VIDTCON_START 0x10
79 #define FIMD_VIDTCON_END 0x1C
80 #define FIMD_VIDTCON2_SIZE_MASK 0x07FF
81 #define FIMD_VIDTCON2_HOR_SHIFT 0
82 #define FIMD_VIDTCON2_VER_SHIFT 11
83
84 /* Window control registers */
85 #define FIMD_WINCON_START 0x0020
86 #define FIMD_WINCON_END 0x0030
87 #define FIMD_WINCON_ROMASK 0x82200000
88 #define FIMD_WINCON_ENWIN (1 << 0)
89 #define FIMD_WINCON_BLD_PIX (1 << 6)
90 #define FIMD_WINCON_ALPHA_MUL (1 << 7)
91 #define FIMD_WINCON_ALPHA_SEL (1 << 1)
92 #define FIMD_WINCON_SWAP 0x078000
93 #define FIMD_WINCON_SWAP_SHIFT 15
94 #define FIMD_WINCON_SWAP_WORD 0x1
95 #define FIMD_WINCON_SWAP_HWORD 0x2
96 #define FIMD_WINCON_SWAP_BYTE 0x4
97 #define FIMD_WINCON_SWAP_BITS 0x8
98 #define FIMD_WINCON_BUFSTAT_L (1 << 21)
99 #define FIMD_WINCON_BUFSTAT_H (1 << 31)
100 #define FIMD_WINCON_BUFSTATUS ((1 << 21) | (1 << 31))
101 #define FIMD_WINCON_BUF0_STAT ((0 << 21) | (0 << 31))
102 #define FIMD_WINCON_BUF1_STAT ((1 << 21) | (0 << 31))
103 #define FIMD_WINCON_BUF2_STAT ((0 << 21) | (1U << 31))
104 #define FIMD_WINCON_BUFSELECT ((1 << 20) | (1 << 30))
105 #define FIMD_WINCON_BUF0_SEL ((0 << 20) | (0 << 30))
106 #define FIMD_WINCON_BUF1_SEL ((1 << 20) | (0 << 30))
107 #define FIMD_WINCON_BUF2_SEL ((0 << 20) | (1 << 30))
108 #define FIMD_WINCON_BUFMODE (1 << 14)
109 #define IS_PALETTIZED_MODE(w) (w->wincon & 0xC)
110 #define PAL_MODE_WITH_ALPHA(x) ((x) == 7)
111 #define WIN_BPP_MODE(w) ((w->wincon >> 2) & 0xF)
112 #define WIN_BPP_MODE_WITH_ALPHA(w) \
113 (WIN_BPP_MODE(w) == 0xD || WIN_BPP_MODE(w) == 0xE)
114
115 /* Shadow control register */
116 #define FIMD_SHADOWCON 0x0034
117 #define FIMD_WINDOW_PROTECTED(s, w) ((s) & (1 << (10 + (w))))
118 /* Channel mapping control register */
119 #define FIMD_WINCHMAP 0x003C
120
121 /* Window position control registers */
122 #define FIMD_VIDOSD_START 0x0040
123 #define FIMD_VIDOSD_END 0x0088
124 #define FIMD_VIDOSD_COORD_MASK 0x07FF
125 #define FIMD_VIDOSD_HOR_SHIFT 11
126 #define FIMD_VIDOSD_VER_SHIFT 0
127 #define FIMD_VIDOSD_ALPHA_AEN0 0xFFF000
128 #define FIMD_VIDOSD_AEN0_SHIFT 12
129 #define FIMD_VIDOSD_ALPHA_AEN1 0x000FFF
130
131 /* Frame buffer address registers */
132 #define FIMD_VIDWADD0_START 0x00A0
133 #define FIMD_VIDWADD0_END 0x00C4
134 #define FIMD_VIDWADD0_END 0x00C4
135 #define FIMD_VIDWADD1_START 0x00D0
136 #define FIMD_VIDWADD1_END 0x00F4
137 #define FIMD_VIDWADD2_START 0x0100
138 #define FIMD_VIDWADD2_END 0x0110
139 #define FIMD_VIDWADD2_PAGEWIDTH 0x1FFF
140 #define FIMD_VIDWADD2_OFFSIZE 0x1FFF
141 #define FIMD_VIDWADD2_OFFSIZE_SHIFT 13
142 #define FIMD_VIDW0ADD0_B2 0x20A0
143 #define FIMD_VIDW4ADD0_B2 0x20C0
144
145 /* Video interrupt control registers */
146 #define FIMD_VIDINTCON0 0x130
147 #define FIMD_VIDINTCON1 0x134
148
149 /* Window color key registers */
150 #define FIMD_WKEYCON_START 0x140
151 #define FIMD_WKEYCON_END 0x15C
152 #define FIMD_WKEYCON0_COMPKEY 0x00FFFFFF
153 #define FIMD_WKEYCON0_CTL_SHIFT 24
154 #define FIMD_WKEYCON0_DIRCON (1 << 24)
155 #define FIMD_WKEYCON0_KEYEN (1 << 25)
156 #define FIMD_WKEYCON0_KEYBLEN (1 << 26)
157 /* Window color key alpha control register */
158 #define FIMD_WKEYALPHA_START 0x160
159 #define FIMD_WKEYALPHA_END 0x16C
160
161 /* Dithering control register */
162 #define FIMD_DITHMODE 0x170
163
164 /* Window alpha control registers */
165 #define FIMD_VIDALPHA_ALPHA_LOWER 0x000F0F0F
166 #define FIMD_VIDALPHA_ALPHA_UPPER 0x00F0F0F0
167 #define FIMD_VIDWALPHA_START 0x21C
168 #define FIMD_VIDWALPHA_END 0x240
169
170 /* Window color map registers */
171 #define FIMD_WINMAP_START 0x180
172 #define FIMD_WINMAP_END 0x190
173 #define FIMD_WINMAP_EN (1 << 24)
174 #define FIMD_WINMAP_COLOR_MASK 0x00FFFFFF
175
176 /* Window palette control registers */
177 #define FIMD_WPALCON_HIGH 0x019C
178 #define FIMD_WPALCON_LOW 0x01A0
179 #define FIMD_WPALCON_UPDATEEN (1 << 9)
180 #define FIMD_WPAL_W0PAL_L 0x07
181 #define FIMD_WPAL_W0PAL_L_SHT 0
182 #define FIMD_WPAL_W1PAL_L 0x07
183 #define FIMD_WPAL_W1PAL_L_SHT 3
184 #define FIMD_WPAL_W2PAL_L 0x01
185 #define FIMD_WPAL_W2PAL_L_SHT 6
186 #define FIMD_WPAL_W2PAL_H 0x06
187 #define FIMD_WPAL_W2PAL_H_SHT 8
188 #define FIMD_WPAL_W3PAL_L 0x01
189 #define FIMD_WPAL_W3PAL_L_SHT 7
190 #define FIMD_WPAL_W3PAL_H 0x06
191 #define FIMD_WPAL_W3PAL_H_SHT 12
192 #define FIMD_WPAL_W4PAL_L 0x01
193 #define FIMD_WPAL_W4PAL_L_SHT 8
194 #define FIMD_WPAL_W4PAL_H 0x06
195 #define FIMD_WPAL_W4PAL_H_SHT 16
196
197 /* Trigger control registers */
198 #define FIMD_TRIGCON 0x01A4
199 #define FIMD_TRIGCON_ROMASK 0x00000004
200
201 /* LCD I80 Interface Control */
202 #define FIMD_I80IFCON_START 0x01B0
203 #define FIMD_I80IFCON_END 0x01BC
204 /* Color gain control register */
205 #define FIMD_COLORGAINCON 0x01C0
206 /* LCD i80 Interface Command Control */
207 #define FIMD_LDI_CMDCON0 0x01D0
208 #define FIMD_LDI_CMDCON1 0x01D4
209 /* I80 System Interface Manual Command Control */
210 #define FIMD_SIFCCON0 0x01E0
211 #define FIMD_SIFCCON2 0x01E8
212
213 /* Hue Control Registers */
214 #define FIMD_HUECOEFCR_START 0x01EC
215 #define FIMD_HUECOEFCR_END 0x01F4
216 #define FIMD_HUECOEFCB_START 0x01FC
217 #define FIMD_HUECOEFCB_END 0x0208
218 #define FIMD_HUEOFFSET 0x020C
219
220 /* Video interrupt control registers */
221 #define FIMD_VIDINT_INTFIFOPEND (1 << 0)
222 #define FIMD_VIDINT_INTFRMPEND (1 << 1)
223 #define FIMD_VIDINT_INTI80PEND (1 << 2)
224 #define FIMD_VIDINT_INTEN (1 << 0)
225 #define FIMD_VIDINT_INTFIFOEN (1 << 1)
226 #define FIMD_VIDINT_INTFRMEN (1 << 12)
227 #define FIMD_VIDINT_I80IFDONE (1 << 17)
228
229 /* Window blend equation control registers */
230 #define FIMD_BLENDEQ_START 0x0244
231 #define FIMD_BLENDEQ_END 0x0250
232 #define FIMD_BLENDCON 0x0260
233 #define FIMD_ALPHA_8BIT (1 << 0)
234 #define FIMD_BLENDEQ_COEF_MASK 0xF
235
236 /* Window RTQOS Control Registers */
237 #define FIMD_WRTQOSCON_START 0x0264
238 #define FIMD_WRTQOSCON_END 0x0274
239
240 /* LCD I80 Interface Command */
241 #define FIMD_I80IFCMD_START 0x0280
242 #define FIMD_I80IFCMD_END 0x02AC
243
244 /* Shadow windows control registers */
245 #define FIMD_SHD_ADD0_START 0x40A0
246 #define FIMD_SHD_ADD0_END 0x40C0
247 #define FIMD_SHD_ADD1_START 0x40D0
248 #define FIMD_SHD_ADD1_END 0x40F0
249 #define FIMD_SHD_ADD2_START 0x4100
250 #define FIMD_SHD_ADD2_END 0x4110
251
252 /* Palette memory */
253 #define FIMD_PAL_MEM_START 0x2400
254 #define FIMD_PAL_MEM_END 0x37FC
255 /* Palette memory aliases for windows 0 and 1 */
256 #define FIMD_PALMEM_AL_START 0x0400
257 #define FIMD_PALMEM_AL_END 0x0BFC
258
259 typedef struct {
260 uint8_t r, g, b;
261 /* D[31..24]dummy, D[23..16]rAlpha, D[15..8]gAlpha, D[7..0]bAlpha */
262 uint32_t a;
263 } rgba;
264 #define RGBA_SIZE 7
265
266 typedef void pixel_to_rgb_func(uint32_t pixel, rgba *p);
267 typedef struct Exynos4210fimdWindow Exynos4210fimdWindow;
268
269 struct Exynos4210fimdWindow {
270 uint32_t wincon; /* Window control register */
271 uint32_t buf_start[3]; /* Start address for video frame buffer */
272 uint32_t buf_end[3]; /* End address for video frame buffer */
273 uint32_t keycon[2]; /* Window color key registers */
274 uint32_t keyalpha; /* Color key alpha control register */
275 uint32_t winmap; /* Window color map register */
276 uint32_t blendeq; /* Window blending equation control register */
277 uint32_t rtqoscon; /* Window RTQOS Control Registers */
278 uint32_t palette[256]; /* Palette RAM */
279 uint32_t shadow_buf_start; /* Start address of shadow frame buffer */
280 uint32_t shadow_buf_end; /* End address of shadow frame buffer */
281 uint32_t shadow_buf_size; /* Virtual shadow screen width */
282
283 pixel_to_rgb_func *pixel_to_rgb;
284 void (*draw_line)(Exynos4210fimdWindow *w, uint8_t *src, uint8_t *dst,
285 bool blend);
286 uint32_t (*get_alpha)(Exynos4210fimdWindow *w, uint32_t pix_a);
287 uint16_t lefttop_x, lefttop_y; /* VIDOSD0 register */
288 uint16_t rightbot_x, rightbot_y; /* VIDOSD1 register */
289 uint32_t osdsize; /* VIDOSD2&3 register */
290 uint32_t alpha_val[2]; /* VIDOSD2&3, VIDWALPHA registers */
291 uint16_t virtpage_width; /* VIDWADD2 register */
292 uint16_t virtpage_offsize; /* VIDWADD2 register */
293 MemoryRegionSection mem_section; /* RAM fragment containing framebuffer */
294 uint8_t *host_fb_addr; /* Host pointer to window's framebuffer */
295 hwaddr fb_len; /* Framebuffer length */
296 };
297
298 #define TYPE_EXYNOS4210_FIMD "exynos4210.fimd"
299 OBJECT_DECLARE_SIMPLE_TYPE(Exynos4210fimdState, EXYNOS4210_FIMD)
300
301 struct Exynos4210fimdState {
302 SysBusDevice parent_obj;
303
304 MemoryRegion iomem;
305 QemuConsole *console;
306 qemu_irq irq[3];
307 MemoryRegion *fbmem;
308
309 uint32_t vidcon[4]; /* Video main control registers 0-3 */
310 uint32_t vidtcon[4]; /* Video time control registers 0-3 */
311 uint32_t shadowcon; /* Window shadow control register */
312 uint32_t winchmap; /* Channel mapping control register */
313 uint32_t vidintcon[2]; /* Video interrupt control registers */
314 uint32_t dithmode; /* Dithering control register */
315 uint32_t wpalcon[2]; /* Window palette control registers */
316 uint32_t trigcon; /* Trigger control register */
317 uint32_t i80ifcon[4]; /* I80 interface control registers */
318 uint32_t colorgaincon; /* Color gain control register */
319 uint32_t ldi_cmdcon[2]; /* LCD I80 interface command control */
320 uint32_t sifccon[3]; /* I80 System Interface Manual Command Control */
321 uint32_t huecoef_cr[4]; /* Hue control registers */
322 uint32_t huecoef_cb[4]; /* Hue control registers */
323 uint32_t hueoffset; /* Hue offset control register */
324 uint32_t blendcon; /* Blending control register */
325 uint32_t i80ifcmd[12]; /* LCD I80 Interface Command */
326
327 Exynos4210fimdWindow window[5]; /* Window-specific registers */
328 uint8_t *ifb; /* Internal frame buffer */
329 bool invalidate; /* Image needs to be redrawn */
330 bool enabled; /* Display controller is enabled */
331 };
332
333 /* Perform byte/halfword/word swap of data according to WINCON */
fimd_swap_data(unsigned int swap_ctl,uint64_t * data)334 static inline void fimd_swap_data(unsigned int swap_ctl, uint64_t *data)
335 {
336 int i;
337 uint64_t res;
338 uint64_t x = *data;
339
340 if (swap_ctl & FIMD_WINCON_SWAP_BITS) {
341 res = 0;
342 for (i = 0; i < 64; i++) {
343 if (x & (1ULL << (63 - i))) {
344 res |= (1ULL << i);
345 }
346 }
347 x = res;
348 }
349
350 if (swap_ctl & FIMD_WINCON_SWAP_BYTE) {
351 x = bswap64(x);
352 }
353
354 if (swap_ctl & FIMD_WINCON_SWAP_HWORD) {
355 x = ((x & 0x000000000000FFFFULL) << 48) |
356 ((x & 0x00000000FFFF0000ULL) << 16) |
357 ((x & 0x0000FFFF00000000ULL) >> 16) |
358 ((x & 0xFFFF000000000000ULL) >> 48);
359 }
360
361 if (swap_ctl & FIMD_WINCON_SWAP_WORD) {
362 x = ((x & 0x00000000FFFFFFFFULL) << 32) |
363 ((x & 0xFFFFFFFF00000000ULL) >> 32);
364 }
365
366 *data = x;
367 }
368
369 /* Conversion routines of Pixel data from frame buffer area to internal RGBA
370 * pixel representation.
371 * Every color component internally represented as 8-bit value. If original
372 * data has less than 8 bit for component, data is extended to 8 bit. For
373 * example, if blue component has only two possible values 0 and 1 it will be
374 * extended to 0 and 0xFF */
375
376 /* One bit for alpha representation */
377 #define DEF_PIXEL_TO_RGB_A1(N, R, G, B) \
378 static void N(uint32_t pixel, rgba *p) \
379 { \
380 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
381 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
382 pixel >>= (B); \
383 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
384 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
385 pixel >>= (G); \
386 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
387 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
388 pixel >>= (R); \
389 p->a = (pixel & 0x1); \
390 }
391
392 DEF_PIXEL_TO_RGB_A1(pixel_a444_to_rgb, 4, 4, 4)
393 DEF_PIXEL_TO_RGB_A1(pixel_a555_to_rgb, 5, 5, 5)
394 DEF_PIXEL_TO_RGB_A1(pixel_a666_to_rgb, 6, 6, 6)
395 DEF_PIXEL_TO_RGB_A1(pixel_a665_to_rgb, 6, 6, 5)
396 DEF_PIXEL_TO_RGB_A1(pixel_a888_to_rgb, 8, 8, 8)
397 DEF_PIXEL_TO_RGB_A1(pixel_a887_to_rgb, 8, 8, 7)
398
399 /* Alpha component is always zero */
400 #define DEF_PIXEL_TO_RGB_A0(N, R, G, B) \
401 static void N(uint32_t pixel, rgba *p) \
402 { \
403 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
404 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
405 pixel >>= (B); \
406 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
407 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
408 pixel >>= (G); \
409 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
410 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
411 p->a = 0x0; \
412 }
413
414 DEF_PIXEL_TO_RGB_A0(pixel_565_to_rgb, 5, 6, 5)
415 DEF_PIXEL_TO_RGB_A0(pixel_555_to_rgb, 5, 5, 5)
416 DEF_PIXEL_TO_RGB_A0(pixel_666_to_rgb, 6, 6, 6)
417 DEF_PIXEL_TO_RGB_A0(pixel_888_to_rgb, 8, 8, 8)
418
419 /* Alpha component has some meaningful value */
420 #define DEF_PIXEL_TO_RGB_A(N, R, G, B, A) \
421 static void N(uint32_t pixel, rgba *p) \
422 { \
423 p->b = ((pixel & ((1 << (B)) - 1)) << (8 - (B))) | \
424 ((pixel >> (2 * (B) - 8)) & ((1 << (8 - (B))) - 1)); \
425 pixel >>= (B); \
426 p->g = (pixel & ((1 << (G)) - 1)) << (8 - (G)) | \
427 ((pixel >> (2 * (G) - 8)) & ((1 << (8 - (G))) - 1)); \
428 pixel >>= (G); \
429 p->r = (pixel & ((1 << (R)) - 1)) << (8 - (R)) | \
430 ((pixel >> (2 * (R) - 8)) & ((1 << (8 - (R))) - 1)); \
431 pixel >>= (R); \
432 p->a = (pixel & ((1 << (A)) - 1)) << (8 - (A)) | \
433 ((pixel >> (2 * (A) - 8)) & ((1 << (8 - (A))) - 1)); \
434 p->a = p->a | (p->a << 8) | (p->a << 16); \
435 }
436
437 DEF_PIXEL_TO_RGB_A(pixel_4444_to_rgb, 4, 4, 4, 4)
438 DEF_PIXEL_TO_RGB_A(pixel_8888_to_rgb, 8, 8, 8, 8)
439
440 /* Lookup table to extent 2-bit color component to 8 bit */
441 static const uint8_t pixel_lutable_2b[4] = {
442 0x0, 0x55, 0xAA, 0xFF
443 };
444 /* Lookup table to extent 3-bit color component to 8 bit */
445 static const uint8_t pixel_lutable_3b[8] = {
446 0x0, 0x24, 0x49, 0x6D, 0x92, 0xB6, 0xDB, 0xFF
447 };
448 /* Special case for a232 bpp mode */
pixel_a232_to_rgb(uint32_t pixel,rgba * p)449 static void pixel_a232_to_rgb(uint32_t pixel, rgba *p)
450 {
451 p->b = pixel_lutable_2b[(pixel & 0x3)];
452 pixel >>= 2;
453 p->g = pixel_lutable_3b[(pixel & 0x7)];
454 pixel >>= 3;
455 p->r = pixel_lutable_2b[(pixel & 0x3)];
456 pixel >>= 2;
457 p->a = (pixel & 0x1);
458 }
459
460 /* Special case for (5+1, 5+1, 5+1) mode. Data bit 15 is common LSB
461 * for all three color components */
pixel_1555_to_rgb(uint32_t pixel,rgba * p)462 static void pixel_1555_to_rgb(uint32_t pixel, rgba *p)
463 {
464 uint8_t comm = (pixel >> 15) & 1;
465 p->b = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
466 pixel >>= 5;
467 p->g = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
468 pixel >>= 5;
469 p->r = ((((pixel & 0x1F) << 1) | comm) << 2) | ((pixel >> 3) & 0x3);
470 p->a = 0x0;
471 }
472
473 /* Put/get pixel to/from internal LCD Controller framebuffer */
474
put_pixel_ifb(const rgba p,uint8_t * d)475 static int put_pixel_ifb(const rgba p, uint8_t *d)
476 {
477 *(uint8_t *)d++ = p.r;
478 *(uint8_t *)d++ = p.g;
479 *(uint8_t *)d++ = p.b;
480 *(uint32_t *)d = p.a;
481 return RGBA_SIZE;
482 }
483
get_pixel_ifb(const uint8_t * s,rgba * p)484 static int get_pixel_ifb(const uint8_t *s, rgba *p)
485 {
486 p->r = *(uint8_t *)s++;
487 p->g = *(uint8_t *)s++;
488 p->b = *(uint8_t *)s++;
489 p->a = (*(uint32_t *)s) & 0x00FFFFFF;
490 return RGBA_SIZE;
491 }
492
493 static pixel_to_rgb_func *palette_data_format[8] = {
494 [0] = pixel_565_to_rgb,
495 [1] = pixel_a555_to_rgb,
496 [2] = pixel_666_to_rgb,
497 [3] = pixel_a665_to_rgb,
498 [4] = pixel_a666_to_rgb,
499 [5] = pixel_888_to_rgb,
500 [6] = pixel_a888_to_rgb,
501 [7] = pixel_8888_to_rgb
502 };
503
504 /* Returns Index in palette data formats table for given window number WINDOW */
505 static uint32_t
exynos4210_fimd_palette_format(Exynos4210fimdState * s,int window)506 exynos4210_fimd_palette_format(Exynos4210fimdState *s, int window)
507 {
508 uint32_t ret;
509
510 switch (window) {
511 case 0:
512 ret = (s->wpalcon[1] >> FIMD_WPAL_W0PAL_L_SHT) & FIMD_WPAL_W0PAL_L;
513 if (ret != 7) {
514 ret = 6 - ret;
515 }
516 break;
517 case 1:
518 ret = (s->wpalcon[1] >> FIMD_WPAL_W1PAL_L_SHT) & FIMD_WPAL_W1PAL_L;
519 if (ret != 7) {
520 ret = 6 - ret;
521 }
522 break;
523 case 2:
524 ret = ((s->wpalcon[0] >> FIMD_WPAL_W2PAL_H_SHT) & FIMD_WPAL_W2PAL_H) |
525 ((s->wpalcon[1] >> FIMD_WPAL_W2PAL_L_SHT) & FIMD_WPAL_W2PAL_L);
526 break;
527 case 3:
528 ret = ((s->wpalcon[0] >> FIMD_WPAL_W3PAL_H_SHT) & FIMD_WPAL_W3PAL_H) |
529 ((s->wpalcon[1] >> FIMD_WPAL_W3PAL_L_SHT) & FIMD_WPAL_W3PAL_L);
530 break;
531 case 4:
532 ret = ((s->wpalcon[0] >> FIMD_WPAL_W4PAL_H_SHT) & FIMD_WPAL_W4PAL_H) |
533 ((s->wpalcon[1] >> FIMD_WPAL_W4PAL_L_SHT) & FIMD_WPAL_W4PAL_L);
534 break;
535 default:
536 hw_error("exynos4210.fimd: incorrect window number %d\n", window);
537 ret = 0;
538 break;
539 }
540 return ret;
541 }
542
543 #define FIMD_1_MINUS_COLOR(x) \
544 ((0xFF - ((x) & 0xFF)) | (0xFF00 - ((x) & 0xFF00)) | \
545 (0xFF0000 - ((x) & 0xFF0000)))
546 #define EXTEND_LOWER_HALFBYTE(x) (((x) & 0xF0F0F) | (((x) << 4) & 0xF0F0F0))
547 #define EXTEND_UPPER_HALFBYTE(x) (((x) & 0xF0F0F0) | (((x) >> 4) & 0xF0F0F))
548
549 /* Multiply three lower bytes of two 32-bit words with each other.
550 * Each byte with values 0-255 is considered as a number with possible values
551 * in a range [0 - 1] */
fimd_mult_each_byte(uint32_t a,uint32_t b)552 static inline uint32_t fimd_mult_each_byte(uint32_t a, uint32_t b)
553 {
554 uint32_t tmp;
555 uint32_t ret;
556
557 ret = ((tmp = (((a & 0xFF) * (b & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF : tmp;
558 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF)) / 0xFF)) > 0xFF) ?
559 0xFF00 : tmp << 8;
560 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF)) / 0xFF)) > 0xFF) ?
561 0xFF0000 : tmp << 16;
562 return ret;
563 }
564
565 /* For each corresponding bytes of two 32-bit words: (a*b + c*d)
566 * Byte values 0-255 are mapped to a range [0 .. 1] */
567 static inline uint32_t
fimd_mult_and_sum_each_byte(uint32_t a,uint32_t b,uint32_t c,uint32_t d)568 fimd_mult_and_sum_each_byte(uint32_t a, uint32_t b, uint32_t c, uint32_t d)
569 {
570 uint32_t tmp;
571 uint32_t ret;
572
573 ret = ((tmp = (((a & 0xFF) * (b & 0xFF) + (c & 0xFF) * (d & 0xFF)) / 0xFF))
574 > 0xFF) ? 0xFF : tmp;
575 ret |= ((tmp = ((((a >> 8) & 0xFF) * ((b >> 8) & 0xFF) + ((c >> 8) & 0xFF) *
576 ((d >> 8) & 0xFF)) / 0xFF)) > 0xFF) ? 0xFF00 : tmp << 8;
577 ret |= ((tmp = ((((a >> 16) & 0xFF) * ((b >> 16) & 0xFF) +
578 ((c >> 16) & 0xFF) * ((d >> 16) & 0xFF)) / 0xFF)) > 0xFF) ?
579 0xFF0000 : tmp << 16;
580 return ret;
581 }
582
583 /* These routines cover all possible sources of window's transparent factor
584 * used in blending equation. Choice of routine is affected by WPALCON
585 * registers, BLENDCON register and window's WINCON register */
586
fimd_get_alpha_pix(Exynos4210fimdWindow * w,uint32_t pix_a)587 static uint32_t fimd_get_alpha_pix(Exynos4210fimdWindow *w, uint32_t pix_a)
588 {
589 return pix_a;
590 }
591
592 static uint32_t
fimd_get_alpha_pix_extlow(Exynos4210fimdWindow * w,uint32_t pix_a)593 fimd_get_alpha_pix_extlow(Exynos4210fimdWindow *w, uint32_t pix_a)
594 {
595 return EXTEND_LOWER_HALFBYTE(pix_a);
596 }
597
598 static uint32_t
fimd_get_alpha_pix_exthigh(Exynos4210fimdWindow * w,uint32_t pix_a)599 fimd_get_alpha_pix_exthigh(Exynos4210fimdWindow *w, uint32_t pix_a)
600 {
601 return EXTEND_UPPER_HALFBYTE(pix_a);
602 }
603
fimd_get_alpha_mult(Exynos4210fimdWindow * w,uint32_t pix_a)604 static uint32_t fimd_get_alpha_mult(Exynos4210fimdWindow *w, uint32_t pix_a)
605 {
606 return fimd_mult_each_byte(pix_a, w->alpha_val[0]);
607 }
608
fimd_get_alpha_mult_ext(Exynos4210fimdWindow * w,uint32_t pix_a)609 static uint32_t fimd_get_alpha_mult_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
610 {
611 return fimd_mult_each_byte(EXTEND_LOWER_HALFBYTE(pix_a),
612 EXTEND_UPPER_HALFBYTE(w->alpha_val[0]));
613 }
614
fimd_get_alpha_aen(Exynos4210fimdWindow * w,uint32_t pix_a)615 static uint32_t fimd_get_alpha_aen(Exynos4210fimdWindow *w, uint32_t pix_a)
616 {
617 return w->alpha_val[pix_a];
618 }
619
fimd_get_alpha_aen_ext(Exynos4210fimdWindow * w,uint32_t pix_a)620 static uint32_t fimd_get_alpha_aen_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
621 {
622 return EXTEND_UPPER_HALFBYTE(w->alpha_val[pix_a]);
623 }
624
fimd_get_alpha_sel(Exynos4210fimdWindow * w,uint32_t pix_a)625 static uint32_t fimd_get_alpha_sel(Exynos4210fimdWindow *w, uint32_t pix_a)
626 {
627 return w->alpha_val[(w->wincon & FIMD_WINCON_ALPHA_SEL) ? 1 : 0];
628 }
629
fimd_get_alpha_sel_ext(Exynos4210fimdWindow * w,uint32_t pix_a)630 static uint32_t fimd_get_alpha_sel_ext(Exynos4210fimdWindow *w, uint32_t pix_a)
631 {
632 return EXTEND_UPPER_HALFBYTE(w->alpha_val[(w->wincon &
633 FIMD_WINCON_ALPHA_SEL) ? 1 : 0]);
634 }
635
636 /* Updates currently active alpha value get function for specified window */
fimd_update_get_alpha(Exynos4210fimdState * s,int win)637 static void fimd_update_get_alpha(Exynos4210fimdState *s, int win)
638 {
639 Exynos4210fimdWindow *w = &s->window[win];
640 const bool alpha_is_8bit = s->blendcon & FIMD_ALPHA_8BIT;
641
642 if (w->wincon & FIMD_WINCON_BLD_PIX) {
643 if ((w->wincon & FIMD_WINCON_ALPHA_SEL) && WIN_BPP_MODE_WITH_ALPHA(w)) {
644 /* In this case, alpha component contains meaningful value */
645 if (w->wincon & FIMD_WINCON_ALPHA_MUL) {
646 w->get_alpha = alpha_is_8bit ?
647 fimd_get_alpha_mult : fimd_get_alpha_mult_ext;
648 } else {
649 w->get_alpha = alpha_is_8bit ?
650 fimd_get_alpha_pix : fimd_get_alpha_pix_extlow;
651 }
652 } else {
653 if (IS_PALETTIZED_MODE(w) &&
654 PAL_MODE_WITH_ALPHA(exynos4210_fimd_palette_format(s, win))) {
655 /* Alpha component has 8-bit numeric value */
656 w->get_alpha = alpha_is_8bit ?
657 fimd_get_alpha_pix : fimd_get_alpha_pix_exthigh;
658 } else {
659 /* Alpha has only two possible values (AEN) */
660 w->get_alpha = alpha_is_8bit ?
661 fimd_get_alpha_aen : fimd_get_alpha_aen_ext;
662 }
663 }
664 } else {
665 w->get_alpha = alpha_is_8bit ? fimd_get_alpha_sel :
666 fimd_get_alpha_sel_ext;
667 }
668 }
669
670 /* Blends current window's (w) pixel (foreground pixel *ret) with background
671 * window (w_blend) pixel p_bg according to formula:
672 * NEW_COLOR = a_coef x FG_PIXEL_COLOR + b_coef x BG_PIXEL_COLOR
673 * NEW_ALPHA = p_coef x FG_ALPHA + q_coef x BG_ALPHA
674 */
675 static void
exynos4210_fimd_blend_pixel(Exynos4210fimdWindow * w,rgba p_bg,rgba * ret)676 exynos4210_fimd_blend_pixel(Exynos4210fimdWindow *w, rgba p_bg, rgba *ret)
677 {
678 rgba p_fg = *ret;
679 uint32_t bg_color = ((p_bg.r & 0xFF) << 16) | ((p_bg.g & 0xFF) << 8) |
680 (p_bg.b & 0xFF);
681 uint32_t fg_color = ((p_fg.r & 0xFF) << 16) | ((p_fg.g & 0xFF) << 8) |
682 (p_fg.b & 0xFF);
683 uint32_t alpha_fg = p_fg.a;
684 int i;
685 /* It is possible that blending equation parameters a and b do not
686 * depend on window BLENEQ register. Account for this with first_coef */
687 enum { A_COEF = 0, B_COEF = 1, P_COEF = 2, Q_COEF = 3, COEF_NUM = 4};
688 uint32_t first_coef = A_COEF;
689 uint32_t blend_param[COEF_NUM];
690
691 if (w->keycon[0] & FIMD_WKEYCON0_KEYEN) {
692 uint32_t colorkey = (w->keycon[1] &
693 ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) & FIMD_WKEYCON0_COMPKEY;
694
695 if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON) &&
696 (bg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) == colorkey) {
697 /* Foreground pixel is displayed */
698 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN) {
699 alpha_fg = w->keyalpha;
700 blend_param[A_COEF] = alpha_fg;
701 blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg);
702 } else {
703 alpha_fg = 0;
704 blend_param[A_COEF] = 0xFFFFFF;
705 blend_param[B_COEF] = 0x0;
706 }
707 first_coef = P_COEF;
708 } else if ((w->keycon[0] & FIMD_WKEYCON0_DIRCON) == 0 &&
709 (fg_color & ~(w->keycon[0] & FIMD_WKEYCON0_COMPKEY)) == colorkey) {
710 /* Background pixel is displayed */
711 if (w->keycon[0] & FIMD_WKEYCON0_KEYBLEN) {
712 alpha_fg = w->keyalpha;
713 blend_param[A_COEF] = alpha_fg;
714 blend_param[B_COEF] = FIMD_1_MINUS_COLOR(alpha_fg);
715 } else {
716 alpha_fg = 0;
717 blend_param[A_COEF] = 0x0;
718 blend_param[B_COEF] = 0xFFFFFF;
719 }
720 first_coef = P_COEF;
721 }
722 }
723
724 for (i = first_coef; i < COEF_NUM; i++) {
725 switch ((w->blendeq >> i * 6) & FIMD_BLENDEQ_COEF_MASK) {
726 case 0:
727 blend_param[i] = 0;
728 break;
729 case 1:
730 blend_param[i] = 0xFFFFFF;
731 break;
732 case 2:
733 blend_param[i] = alpha_fg;
734 break;
735 case 3:
736 blend_param[i] = FIMD_1_MINUS_COLOR(alpha_fg);
737 break;
738 case 4:
739 blend_param[i] = p_bg.a;
740 break;
741 case 5:
742 blend_param[i] = FIMD_1_MINUS_COLOR(p_bg.a);
743 break;
744 case 6:
745 blend_param[i] = w->alpha_val[0];
746 break;
747 case 10:
748 blend_param[i] = fg_color;
749 break;
750 case 11:
751 blend_param[i] = FIMD_1_MINUS_COLOR(fg_color);
752 break;
753 case 12:
754 blend_param[i] = bg_color;
755 break;
756 case 13:
757 blend_param[i] = FIMD_1_MINUS_COLOR(bg_color);
758 break;
759 default:
760 hw_error("exynos4210.fimd: blend equation coef illegal value\n");
761 break;
762 }
763 }
764
765 fg_color = fimd_mult_and_sum_each_byte(bg_color, blend_param[B_COEF],
766 fg_color, blend_param[A_COEF]);
767 ret->b = fg_color & 0xFF;
768 fg_color >>= 8;
769 ret->g = fg_color & 0xFF;
770 fg_color >>= 8;
771 ret->r = fg_color & 0xFF;
772 ret->a = fimd_mult_and_sum_each_byte(alpha_fg, blend_param[P_COEF],
773 p_bg.a, blend_param[Q_COEF]);
774 }
775
776 /* These routines read data from video frame buffer in system RAM, convert
777 * this data to display controller internal representation, if necessary,
778 * perform pixel blending with data, currently presented in internal buffer.
779 * Result is stored in display controller internal frame buffer. */
780
781 /* Draw line with index in palette table in RAM frame buffer data */
782 #define DEF_DRAW_LINE_PALETTE(N) \
783 static void glue(draw_line_palette_, N)(Exynos4210fimdWindow *w, uint8_t *src, \
784 uint8_t *dst, bool blend) \
785 { \
786 int width = w->rightbot_x - w->lefttop_x + 1; \
787 uint8_t *ifb = dst; \
788 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP) >> FIMD_WINCON_SWAP_SHIFT; \
789 uint64_t data; \
790 rgba p, p_old; \
791 int i; \
792 do { \
793 memcpy(&data, src, sizeof(data)); \
794 src += 8; \
795 fimd_swap_data(swap, &data); \
796 for (i = (64 / (N) - 1); i >= 0; i--) { \
797 w->pixel_to_rgb(w->palette[(data >> ((N) * i)) & \
798 ((1ULL << (N)) - 1)], &p); \
799 p.a = w->get_alpha(w, p.a); \
800 if (blend) { \
801 ifb += get_pixel_ifb(ifb, &p_old); \
802 exynos4210_fimd_blend_pixel(w, p_old, &p); \
803 } \
804 dst += put_pixel_ifb(p, dst); \
805 } \
806 width -= (64 / (N)); \
807 } while (width > 0); \
808 }
809
810 /* Draw line with direct color value in RAM frame buffer data */
811 #define DEF_DRAW_LINE_NOPALETTE(N) \
812 static void glue(draw_line_, N)(Exynos4210fimdWindow *w, uint8_t *src, \
813 uint8_t *dst, bool blend) \
814 { \
815 int width = w->rightbot_x - w->lefttop_x + 1; \
816 uint8_t *ifb = dst; \
817 uint8_t swap = (w->wincon & FIMD_WINCON_SWAP) >> FIMD_WINCON_SWAP_SHIFT; \
818 uint64_t data; \
819 rgba p, p_old; \
820 int i; \
821 do { \
822 memcpy(&data, src, sizeof(data)); \
823 src += 8; \
824 fimd_swap_data(swap, &data); \
825 for (i = (64 / (N) - 1); i >= 0; i--) { \
826 w->pixel_to_rgb((data >> ((N) * i)) & ((1ULL << (N)) - 1), &p); \
827 p.a = w->get_alpha(w, p.a); \
828 if (blend) { \
829 ifb += get_pixel_ifb(ifb, &p_old); \
830 exynos4210_fimd_blend_pixel(w, p_old, &p); \
831 } \
832 dst += put_pixel_ifb(p, dst); \
833 } \
834 width -= (64 / (N)); \
835 } while (width > 0); \
836 }
837
838 DEF_DRAW_LINE_PALETTE(1)
839 DEF_DRAW_LINE_PALETTE(2)
840 DEF_DRAW_LINE_PALETTE(4)
841 DEF_DRAW_LINE_PALETTE(8)
842 DEF_DRAW_LINE_NOPALETTE(8) /* 8bpp mode has palette and non-palette versions */
843 DEF_DRAW_LINE_NOPALETTE(16)
844 DEF_DRAW_LINE_NOPALETTE(32)
845
846 /* Special draw line routine for window color map case */
draw_line_mapcolor(Exynos4210fimdWindow * w,uint8_t * src,uint8_t * dst,bool blend)847 static void draw_line_mapcolor(Exynos4210fimdWindow *w, uint8_t *src,
848 uint8_t *dst, bool blend)
849 {
850 rgba p, p_old;
851 uint8_t *ifb = dst;
852 int width = w->rightbot_x - w->lefttop_x + 1;
853 uint32_t map_color = w->winmap & FIMD_WINMAP_COLOR_MASK;
854
855 do {
856 pixel_888_to_rgb(map_color, &p);
857 p.a = w->get_alpha(w, p.a);
858 if (blend) {
859 ifb += get_pixel_ifb(ifb, &p_old);
860 exynos4210_fimd_blend_pixel(w, p_old, &p);
861 }
862 dst += put_pixel_ifb(p, dst);
863 } while (--width);
864 }
865
866 /* Write RGB to QEMU's GraphicConsole framebuffer */
867
put_to_qemufb_pixel8(const rgba p,uint8_t * d)868 static int put_to_qemufb_pixel8(const rgba p, uint8_t *d)
869 {
870 uint32_t pixel = rgb_to_pixel8(p.r, p.g, p.b);
871 *(uint8_t *)d = pixel;
872 return 1;
873 }
874
put_to_qemufb_pixel15(const rgba p,uint8_t * d)875 static int put_to_qemufb_pixel15(const rgba p, uint8_t *d)
876 {
877 uint32_t pixel = rgb_to_pixel15(p.r, p.g, p.b);
878 *(uint16_t *)d = pixel;
879 return 2;
880 }
881
put_to_qemufb_pixel16(const rgba p,uint8_t * d)882 static int put_to_qemufb_pixel16(const rgba p, uint8_t *d)
883 {
884 uint32_t pixel = rgb_to_pixel16(p.r, p.g, p.b);
885 *(uint16_t *)d = pixel;
886 return 2;
887 }
888
put_to_qemufb_pixel24(const rgba p,uint8_t * d)889 static int put_to_qemufb_pixel24(const rgba p, uint8_t *d)
890 {
891 uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b);
892 *(uint8_t *)d++ = (pixel >> 0) & 0xFF;
893 *(uint8_t *)d++ = (pixel >> 8) & 0xFF;
894 *(uint8_t *)d++ = (pixel >> 16) & 0xFF;
895 return 3;
896 }
897
put_to_qemufb_pixel32(const rgba p,uint8_t * d)898 static int put_to_qemufb_pixel32(const rgba p, uint8_t *d)
899 {
900 uint32_t pixel = rgb_to_pixel24(p.r, p.g, p.b);
901 *(uint32_t *)d = pixel;
902 return 4;
903 }
904
905 /* Routine to copy pixel from internal buffer to QEMU buffer */
906 static int (*put_pixel_toqemu)(const rgba p, uint8_t *pixel);
fimd_update_putpix_qemu(int bpp)907 static inline void fimd_update_putpix_qemu(int bpp)
908 {
909 switch (bpp) {
910 case 8:
911 put_pixel_toqemu = put_to_qemufb_pixel8;
912 break;
913 case 15:
914 put_pixel_toqemu = put_to_qemufb_pixel15;
915 break;
916 case 16:
917 put_pixel_toqemu = put_to_qemufb_pixel16;
918 break;
919 case 24:
920 put_pixel_toqemu = put_to_qemufb_pixel24;
921 break;
922 case 32:
923 put_pixel_toqemu = put_to_qemufb_pixel32;
924 break;
925 default:
926 hw_error("exynos4210.fimd: unsupported BPP (%d)", bpp);
927 break;
928 }
929 }
930
931 /* Routine to copy a line from internal frame buffer to QEMU display */
fimd_copy_line_toqemu(int width,uint8_t * src,uint8_t * dst)932 static void fimd_copy_line_toqemu(int width, uint8_t *src, uint8_t *dst)
933 {
934 rgba p;
935
936 do {
937 src += get_pixel_ifb(src, &p);
938 dst += put_pixel_toqemu(p, dst);
939 } while (--width);
940 }
941
942 /* Parse BPPMODE_F = WINCON1[5:2] bits */
exynos4210_fimd_update_win_bppmode(Exynos4210fimdState * s,int win)943 static void exynos4210_fimd_update_win_bppmode(Exynos4210fimdState *s, int win)
944 {
945 Exynos4210fimdWindow *w = &s->window[win];
946
947 if (w->winmap & FIMD_WINMAP_EN) {
948 w->draw_line = draw_line_mapcolor;
949 return;
950 }
951
952 switch (WIN_BPP_MODE(w)) {
953 case 0:
954 w->draw_line = draw_line_palette_1;
955 w->pixel_to_rgb =
956 palette_data_format[exynos4210_fimd_palette_format(s, win)];
957 break;
958 case 1:
959 w->draw_line = draw_line_palette_2;
960 w->pixel_to_rgb =
961 palette_data_format[exynos4210_fimd_palette_format(s, win)];
962 break;
963 case 2:
964 w->draw_line = draw_line_palette_4;
965 w->pixel_to_rgb =
966 palette_data_format[exynos4210_fimd_palette_format(s, win)];
967 break;
968 case 3:
969 w->draw_line = draw_line_palette_8;
970 w->pixel_to_rgb =
971 palette_data_format[exynos4210_fimd_palette_format(s, win)];
972 break;
973 case 4:
974 w->draw_line = draw_line_8;
975 w->pixel_to_rgb = pixel_a232_to_rgb;
976 break;
977 case 5:
978 w->draw_line = draw_line_16;
979 w->pixel_to_rgb = pixel_565_to_rgb;
980 break;
981 case 6:
982 w->draw_line = draw_line_16;
983 w->pixel_to_rgb = pixel_a555_to_rgb;
984 break;
985 case 7:
986 w->draw_line = draw_line_16;
987 w->pixel_to_rgb = pixel_1555_to_rgb;
988 break;
989 case 8:
990 w->draw_line = draw_line_32;
991 w->pixel_to_rgb = pixel_666_to_rgb;
992 break;
993 case 9:
994 w->draw_line = draw_line_32;
995 w->pixel_to_rgb = pixel_a665_to_rgb;
996 break;
997 case 10:
998 w->draw_line = draw_line_32;
999 w->pixel_to_rgb = pixel_a666_to_rgb;
1000 break;
1001 case 11:
1002 w->draw_line = draw_line_32;
1003 w->pixel_to_rgb = pixel_888_to_rgb;
1004 break;
1005 case 12:
1006 w->draw_line = draw_line_32;
1007 w->pixel_to_rgb = pixel_a887_to_rgb;
1008 break;
1009 case 13:
1010 w->draw_line = draw_line_32;
1011 if ((w->wincon & FIMD_WINCON_BLD_PIX) && (w->wincon &
1012 FIMD_WINCON_ALPHA_SEL)) {
1013 w->pixel_to_rgb = pixel_8888_to_rgb;
1014 } else {
1015 w->pixel_to_rgb = pixel_a888_to_rgb;
1016 }
1017 break;
1018 case 14:
1019 w->draw_line = draw_line_16;
1020 if ((w->wincon & FIMD_WINCON_BLD_PIX) && (w->wincon &
1021 FIMD_WINCON_ALPHA_SEL)) {
1022 w->pixel_to_rgb = pixel_4444_to_rgb;
1023 } else {
1024 w->pixel_to_rgb = pixel_a444_to_rgb;
1025 }
1026 break;
1027 case 15:
1028 w->draw_line = draw_line_16;
1029 w->pixel_to_rgb = pixel_555_to_rgb;
1030 break;
1031 }
1032 }
1033
1034 #if EXYNOS4210_FIMD_MODE_TRACE > 0
exynos4210_fimd_get_bppmode(int mode_code)1035 static const char *exynos4210_fimd_get_bppmode(int mode_code)
1036 {
1037 switch (mode_code) {
1038 case 0:
1039 return "1 bpp";
1040 case 1:
1041 return "2 bpp";
1042 case 2:
1043 return "4 bpp";
1044 case 3:
1045 return "8 bpp (palettized)";
1046 case 4:
1047 return "8 bpp (non-palettized, A: 1-R:2-G:3-B:2)";
1048 case 5:
1049 return "16 bpp (non-palettized, R:5-G:6-B:5)";
1050 case 6:
1051 return "16 bpp (non-palettized, A:1-R:5-G:5-B:5)";
1052 case 7:
1053 return "16 bpp (non-palettized, I :1-R:5-G:5-B:5)";
1054 case 8:
1055 return "Unpacked 18 bpp (non-palettized, R:6-G:6-B:6)";
1056 case 9:
1057 return "Unpacked 18bpp (non-palettized,A:1-R:6-G:6-B:5)";
1058 case 10:
1059 return "Unpacked 19bpp (non-palettized,A:1-R:6-G:6-B:6)";
1060 case 11:
1061 return "Unpacked 24 bpp (non-palettized R:8-G:8-B:8)";
1062 case 12:
1063 return "Unpacked 24 bpp (non-palettized A:1-R:8-G:8-B:7)";
1064 case 13:
1065 return "Unpacked 25 bpp (non-palettized A:1-R:8-G:8-B:8)";
1066 case 14:
1067 return "Unpacked 13 bpp (non-palettized A:1-R:4-G:4-B:4)";
1068 case 15:
1069 return "Unpacked 15 bpp (non-palettized R:5-G:5-B:5)";
1070 default:
1071 return "Non-existing bpp mode";
1072 }
1073 }
1074
exynos4210_fimd_trace_bppmode(Exynos4210fimdState * s,int win_num,uint32_t val)1075 static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s,
1076 int win_num, uint32_t val)
1077 {
1078 Exynos4210fimdWindow *w = &s->window[win_num];
1079
1080 if (w->winmap & FIMD_WINMAP_EN) {
1081 printf("QEMU FIMD: Window %d is mapped with MAPCOLOR=0x%x\n",
1082 win_num, w->winmap & 0xFFFFFF);
1083 return;
1084 }
1085
1086 if ((val != 0xFFFFFFFF) && ((w->wincon >> 2) & 0xF) == ((val >> 2) & 0xF)) {
1087 return;
1088 }
1089 printf("QEMU FIMD: Window %d BPP mode set to %s\n", win_num,
1090 exynos4210_fimd_get_bppmode((val >> 2) & 0xF));
1091 }
1092 #else
exynos4210_fimd_trace_bppmode(Exynos4210fimdState * s,int win_num,uint32_t val)1093 static inline void exynos4210_fimd_trace_bppmode(Exynos4210fimdState *s,
1094 int win_num, uint32_t val)
1095 {
1096
1097 }
1098 #endif
1099
fimd_get_buffer_id(Exynos4210fimdWindow * w)1100 static inline int fimd_get_buffer_id(Exynos4210fimdWindow *w)
1101 {
1102 switch (w->wincon & FIMD_WINCON_BUFSTATUS) {
1103 case FIMD_WINCON_BUF0_STAT:
1104 return 0;
1105 case FIMD_WINCON_BUF1_STAT:
1106 return 1;
1107 case FIMD_WINCON_BUF2_STAT:
1108 return 2;
1109 default:
1110 qemu_log_mask(LOG_GUEST_ERROR, "FIMD: Non-existent buffer index\n");
1111 return 0;
1112 }
1113 }
1114
exynos4210_fimd_invalidate(void * opaque)1115 static void exynos4210_fimd_invalidate(void *opaque)
1116 {
1117 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1118 s->invalidate = true;
1119 }
1120
1121 /* Updates specified window's MemorySection based on values of WINCON,
1122 * VIDOSDA, VIDOSDB, VIDWADDx and SHADOWCON registers */
fimd_update_memory_section(Exynos4210fimdState * s,unsigned win)1123 static void fimd_update_memory_section(Exynos4210fimdState *s, unsigned win)
1124 {
1125 Exynos4210fimdWindow *w = &s->window[win];
1126 hwaddr fb_start_addr, fb_mapped_len;
1127
1128 if (!s->enabled || !(w->wincon & FIMD_WINCON_ENWIN) ||
1129 FIMD_WINDOW_PROTECTED(s->shadowcon, win)) {
1130 return;
1131 }
1132
1133 if (w->host_fb_addr) {
1134 cpu_physical_memory_unmap(w->host_fb_addr, w->fb_len, 0, 0);
1135 w->host_fb_addr = NULL;
1136 w->fb_len = 0;
1137 }
1138
1139 fb_start_addr = w->buf_start[fimd_get_buffer_id(w)];
1140 /* Total number of bytes of virtual screen used by current window */
1141 w->fb_len = fb_mapped_len = (w->virtpage_width + w->virtpage_offsize) *
1142 (w->rightbot_y - w->lefttop_y + 1);
1143
1144 /* TODO: add .exit and unref the region there. Not needed yet since sysbus
1145 * does not support hot-unplug.
1146 */
1147 if (w->mem_section.mr) {
1148 memory_region_set_log(w->mem_section.mr, false, DIRTY_MEMORY_VGA);
1149 memory_region_unref(w->mem_section.mr);
1150 w->mem_section.mr = NULL;
1151 }
1152
1153 if (w->fb_len == 0) {
1154 qemu_log_mask(LOG_GUEST_ERROR,
1155 "FIMD: Guest config means framebuffer is zero length\n");
1156 goto error_return;
1157 }
1158
1159 w->mem_section = memory_region_find(s->fbmem, fb_start_addr, w->fb_len);
1160 assert(w->mem_section.mr);
1161 assert(w->mem_section.offset_within_address_space == fb_start_addr);
1162 DPRINT_TRACE("Window %u framebuffer changed: address=0x%08x, len=0x%x\n",
1163 win, fb_start_addr, w->fb_len);
1164
1165 if (int128_get64(w->mem_section.size) != w->fb_len ||
1166 !memory_region_is_ram(w->mem_section.mr)) {
1167 qemu_log_mask(LOG_GUEST_ERROR,
1168 "FIMD: Failed to find window %u framebuffer region\n",
1169 win);
1170 goto error_return;
1171 }
1172
1173 w->host_fb_addr = cpu_physical_memory_map(fb_start_addr, &fb_mapped_len,
1174 false);
1175 if (!w->host_fb_addr) {
1176 qemu_log_mask(LOG_GUEST_ERROR,
1177 "FIMD: Failed to map window %u framebuffer\n", win);
1178 goto error_return;
1179 }
1180
1181 if (fb_mapped_len != w->fb_len) {
1182 qemu_log_mask(LOG_GUEST_ERROR,
1183 "FIMD: Window %u mapped framebuffer length is less than "
1184 "expected\n", win);
1185 cpu_physical_memory_unmap(w->host_fb_addr, fb_mapped_len, 0, 0);
1186 goto error_return;
1187 }
1188 memory_region_set_log(w->mem_section.mr, true, DIRTY_MEMORY_VGA);
1189 exynos4210_fimd_invalidate(s);
1190 return;
1191
1192 error_return:
1193 memory_region_unref(w->mem_section.mr);
1194 w->mem_section.mr = NULL;
1195 w->mem_section.size = int128_zero();
1196 w->host_fb_addr = NULL;
1197 w->fb_len = 0;
1198 }
1199
exynos4210_fimd_enable(Exynos4210fimdState * s,bool enabled)1200 static void exynos4210_fimd_enable(Exynos4210fimdState *s, bool enabled)
1201 {
1202 if (enabled && !s->enabled) {
1203 unsigned w;
1204 s->enabled = true;
1205 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1206 fimd_update_memory_section(s, w);
1207 }
1208 }
1209 s->enabled = enabled;
1210 DPRINT_TRACE("display controller %s\n", enabled ? "enabled" : "disabled");
1211 }
1212
unpack_upper_4(uint32_t x)1213 static inline uint32_t unpack_upper_4(uint32_t x)
1214 {
1215 return ((x & 0xF00) << 12) | ((x & 0xF0) << 8) | ((x & 0xF) << 4);
1216 }
1217
pack_upper_4(uint32_t x)1218 static inline uint32_t pack_upper_4(uint32_t x)
1219 {
1220 return (((x & 0xF00000) >> 12) | ((x & 0xF000) >> 8) |
1221 ((x & 0xF0) >> 4)) & 0xFFF;
1222 }
1223
exynos4210_fimd_update_irq(Exynos4210fimdState * s)1224 static void exynos4210_fimd_update_irq(Exynos4210fimdState *s)
1225 {
1226 if (!(s->vidintcon[0] & FIMD_VIDINT_INTEN)) {
1227 qemu_irq_lower(s->irq[0]);
1228 qemu_irq_lower(s->irq[1]);
1229 qemu_irq_lower(s->irq[2]);
1230 return;
1231 }
1232 if ((s->vidintcon[0] & FIMD_VIDINT_INTFIFOEN) &&
1233 (s->vidintcon[1] & FIMD_VIDINT_INTFIFOPEND)) {
1234 qemu_irq_raise(s->irq[0]);
1235 } else {
1236 qemu_irq_lower(s->irq[0]);
1237 }
1238 if ((s->vidintcon[0] & FIMD_VIDINT_INTFRMEN) &&
1239 (s->vidintcon[1] & FIMD_VIDINT_INTFRMPEND)) {
1240 qemu_irq_raise(s->irq[1]);
1241 } else {
1242 qemu_irq_lower(s->irq[1]);
1243 }
1244 if ((s->vidintcon[0] & FIMD_VIDINT_I80IFDONE) &&
1245 (s->vidintcon[1] & FIMD_VIDINT_INTI80PEND)) {
1246 qemu_irq_raise(s->irq[2]);
1247 } else {
1248 qemu_irq_lower(s->irq[2]);
1249 }
1250 }
1251
exynos4210_update_resolution(Exynos4210fimdState * s)1252 static void exynos4210_update_resolution(Exynos4210fimdState *s)
1253 {
1254 DisplaySurface *surface = qemu_console_surface(s->console);
1255
1256 /* LCD resolution is stored in VIDEO TIME CONTROL REGISTER 2 */
1257 uint32_t width = ((s->vidtcon[2] >> FIMD_VIDTCON2_HOR_SHIFT) &
1258 FIMD_VIDTCON2_SIZE_MASK) + 1;
1259 uint32_t height = ((s->vidtcon[2] >> FIMD_VIDTCON2_VER_SHIFT) &
1260 FIMD_VIDTCON2_SIZE_MASK) + 1;
1261
1262 if (s->ifb == NULL || surface_width(surface) != width ||
1263 surface_height(surface) != height) {
1264 DPRINT_L1("Resolution changed from %ux%u to %ux%u\n",
1265 surface_width(surface), surface_height(surface), width, height);
1266 qemu_console_resize(s->console, width, height);
1267 s->ifb = g_realloc(s->ifb, width * height * RGBA_SIZE + 1);
1268 memset(s->ifb, 0, width * height * RGBA_SIZE + 1);
1269 exynos4210_fimd_invalidate(s);
1270 }
1271 }
1272
exynos4210_fimd_update(void * opaque)1273 static void exynos4210_fimd_update(void *opaque)
1274 {
1275 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1276 DisplaySurface *surface;
1277 Exynos4210fimdWindow *w;
1278 DirtyBitmapSnapshot *snap;
1279 int i, line;
1280 hwaddr fb_line_addr, inc_size;
1281 int scrn_height;
1282 int first_line = -1, last_line = -1, scrn_width;
1283 bool blend = false;
1284 uint8_t *host_fb_addr;
1285 bool is_dirty = false;
1286 int global_width;
1287
1288 if (!s || !s->console || !s->enabled ||
1289 surface_bits_per_pixel(qemu_console_surface(s->console)) == 0) {
1290 return;
1291 }
1292
1293 global_width = (s->vidtcon[2] & FIMD_VIDTCON2_SIZE_MASK) + 1;
1294 exynos4210_update_resolution(s);
1295 surface = qemu_console_surface(s->console);
1296
1297 for (i = 0; i < NUM_OF_WINDOWS; i++) {
1298 w = &s->window[i];
1299 if ((w->wincon & FIMD_WINCON_ENWIN) && w->host_fb_addr) {
1300 scrn_height = w->rightbot_y - w->lefttop_y + 1;
1301 scrn_width = w->virtpage_width;
1302 /* Total width of virtual screen page in bytes */
1303 inc_size = scrn_width + w->virtpage_offsize;
1304 host_fb_addr = w->host_fb_addr;
1305 fb_line_addr = w->mem_section.offset_within_region;
1306 snap = memory_region_snapshot_and_clear_dirty(w->mem_section.mr,
1307 fb_line_addr, inc_size * scrn_height, DIRTY_MEMORY_VGA);
1308
1309 for (line = 0; line < scrn_height; line++) {
1310 is_dirty = memory_region_snapshot_get_dirty(w->mem_section.mr,
1311 snap, fb_line_addr, scrn_width);
1312
1313 if (s->invalidate || is_dirty) {
1314 if (first_line == -1) {
1315 first_line = line;
1316 }
1317 last_line = line;
1318 w->draw_line(w, host_fb_addr, s->ifb +
1319 w->lefttop_x * RGBA_SIZE + (w->lefttop_y + line) *
1320 global_width * RGBA_SIZE, blend);
1321 }
1322 host_fb_addr += inc_size;
1323 fb_line_addr += inc_size;
1324 }
1325 g_free(snap);
1326 blend = true;
1327 }
1328 }
1329
1330 /* Copy resulting image to QEMU_CONSOLE. */
1331 if (first_line >= 0) {
1332 uint8_t *d;
1333 int bpp;
1334
1335 bpp = surface_bits_per_pixel(surface);
1336 fimd_update_putpix_qemu(bpp);
1337 bpp = (bpp + 1) >> 3;
1338 d = surface_data(surface);
1339 for (line = first_line; line <= last_line; line++) {
1340 fimd_copy_line_toqemu(global_width, s->ifb + global_width * line *
1341 RGBA_SIZE, d + global_width * line * bpp);
1342 }
1343 dpy_gfx_update_full(s->console);
1344 }
1345 s->invalidate = false;
1346 s->vidintcon[1] |= FIMD_VIDINT_INTFRMPEND;
1347 if ((s->vidcon[0] & FIMD_VIDCON0_ENVID_F) == 0) {
1348 exynos4210_fimd_enable(s, false);
1349 }
1350 exynos4210_fimd_update_irq(s);
1351 }
1352
exynos4210_fimd_reset(DeviceState * d)1353 static void exynos4210_fimd_reset(DeviceState *d)
1354 {
1355 Exynos4210fimdState *s = EXYNOS4210_FIMD(d);
1356 unsigned w;
1357
1358 DPRINT_TRACE("Display controller reset\n");
1359 /* Set all display controller registers to 0 */
1360 memset(&s->vidcon, 0, (uint8_t *)&s->window - (uint8_t *)&s->vidcon);
1361 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1362 memset(&s->window[w], 0, sizeof(Exynos4210fimdWindow));
1363 s->window[w].blendeq = 0xC2;
1364 exynos4210_fimd_update_win_bppmode(s, w);
1365 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF);
1366 fimd_update_get_alpha(s, w);
1367 }
1368
1369 g_free(s->ifb);
1370 s->ifb = NULL;
1371
1372 exynos4210_fimd_invalidate(s);
1373 exynos4210_fimd_enable(s, false);
1374 /* Some registers have non-zero initial values */
1375 s->winchmap = 0x7D517D51;
1376 s->colorgaincon = 0x10040100;
1377 s->huecoef_cr[0] = s->huecoef_cr[3] = 0x01000100;
1378 s->huecoef_cb[0] = s->huecoef_cb[3] = 0x01000100;
1379 s->hueoffset = 0x01800080;
1380 }
1381
exynos4210_fimd_write(void * opaque,hwaddr offset,uint64_t val,unsigned size)1382 static void exynos4210_fimd_write(void *opaque, hwaddr offset,
1383 uint64_t val, unsigned size)
1384 {
1385 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1386 unsigned w, i;
1387 uint32_t old_value;
1388
1389 DPRINT_L2("write offset 0x%08x, value=%llu(0x%08llx)\n", offset,
1390 (long long unsigned int)val, (long long unsigned int)val);
1391
1392 switch (offset) {
1393 case FIMD_VIDCON0:
1394 if ((val & FIMD_VIDCON0_ENVID_MASK) == FIMD_VIDCON0_ENVID_MASK) {
1395 exynos4210_fimd_enable(s, true);
1396 } else {
1397 if ((val & FIMD_VIDCON0_ENVID) == 0) {
1398 exynos4210_fimd_enable(s, false);
1399 }
1400 }
1401 s->vidcon[0] = val;
1402 break;
1403 case FIMD_VIDCON1:
1404 /* Leave read-only bits as is */
1405 val = (val & (~FIMD_VIDCON1_ROMASK)) |
1406 (s->vidcon[1] & FIMD_VIDCON1_ROMASK);
1407 s->vidcon[1] = val;
1408 break;
1409 case FIMD_VIDCON2 ... FIMD_VIDCON3:
1410 s->vidcon[(offset) >> 2] = val;
1411 break;
1412 case FIMD_VIDTCON_START ... FIMD_VIDTCON_END:
1413 s->vidtcon[(offset - FIMD_VIDTCON_START) >> 2] = val;
1414 break;
1415 case FIMD_WINCON_START ... FIMD_WINCON_END:
1416 w = (offset - FIMD_WINCON_START) >> 2;
1417 /* Window's current buffer ID */
1418 i = fimd_get_buffer_id(&s->window[w]);
1419 old_value = s->window[w].wincon;
1420 val = (val & ~FIMD_WINCON_ROMASK) |
1421 (s->window[w].wincon & FIMD_WINCON_ROMASK);
1422 if (w == 0) {
1423 /* Window 0 wincon ALPHA_MUL bit must always be 0 */
1424 val &= ~FIMD_WINCON_ALPHA_MUL;
1425 }
1426 exynos4210_fimd_trace_bppmode(s, w, val);
1427 switch (val & FIMD_WINCON_BUFSELECT) {
1428 case FIMD_WINCON_BUF0_SEL:
1429 val &= ~FIMD_WINCON_BUFSTATUS;
1430 break;
1431 case FIMD_WINCON_BUF1_SEL:
1432 val = (val & ~FIMD_WINCON_BUFSTAT_H) | FIMD_WINCON_BUFSTAT_L;
1433 break;
1434 case FIMD_WINCON_BUF2_SEL:
1435 if (val & FIMD_WINCON_BUFMODE) {
1436 val = (val & ~FIMD_WINCON_BUFSTAT_L) | FIMD_WINCON_BUFSTAT_H;
1437 }
1438 break;
1439 default:
1440 break;
1441 }
1442 s->window[w].wincon = val;
1443 exynos4210_fimd_update_win_bppmode(s, w);
1444 fimd_update_get_alpha(s, w);
1445 if ((i != fimd_get_buffer_id(&s->window[w])) ||
1446 (!(old_value & FIMD_WINCON_ENWIN) && (s->window[w].wincon &
1447 FIMD_WINCON_ENWIN))) {
1448 fimd_update_memory_section(s, w);
1449 }
1450 break;
1451 case FIMD_SHADOWCON:
1452 old_value = s->shadowcon;
1453 s->shadowcon = val;
1454 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1455 if (FIMD_WINDOW_PROTECTED(old_value, w) &&
1456 !FIMD_WINDOW_PROTECTED(s->shadowcon, w)) {
1457 fimd_update_memory_section(s, w);
1458 }
1459 }
1460 break;
1461 case FIMD_WINCHMAP:
1462 s->winchmap = val;
1463 break;
1464 case FIMD_VIDOSD_START ... FIMD_VIDOSD_END:
1465 w = (offset - FIMD_VIDOSD_START) >> 4;
1466 i = ((offset - FIMD_VIDOSD_START) & 0xF) >> 2;
1467 switch (i) {
1468 case 0:
1469 old_value = s->window[w].lefttop_y;
1470 s->window[w].lefttop_x = (val >> FIMD_VIDOSD_HOR_SHIFT) &
1471 FIMD_VIDOSD_COORD_MASK;
1472 s->window[w].lefttop_y = (val >> FIMD_VIDOSD_VER_SHIFT) &
1473 FIMD_VIDOSD_COORD_MASK;
1474 if (s->window[w].lefttop_y != old_value) {
1475 fimd_update_memory_section(s, w);
1476 }
1477 break;
1478 case 1:
1479 old_value = s->window[w].rightbot_y;
1480 s->window[w].rightbot_x = (val >> FIMD_VIDOSD_HOR_SHIFT) &
1481 FIMD_VIDOSD_COORD_MASK;
1482 s->window[w].rightbot_y = (val >> FIMD_VIDOSD_VER_SHIFT) &
1483 FIMD_VIDOSD_COORD_MASK;
1484 if (s->window[w].rightbot_y != old_value) {
1485 fimd_update_memory_section(s, w);
1486 }
1487 break;
1488 case 2:
1489 if (w == 0) {
1490 s->window[w].osdsize = val;
1491 } else {
1492 s->window[w].alpha_val[0] =
1493 unpack_upper_4((val & FIMD_VIDOSD_ALPHA_AEN0) >>
1494 FIMD_VIDOSD_AEN0_SHIFT) |
1495 (s->window[w].alpha_val[0] & FIMD_VIDALPHA_ALPHA_LOWER);
1496 s->window[w].alpha_val[1] =
1497 unpack_upper_4(val & FIMD_VIDOSD_ALPHA_AEN1) |
1498 (s->window[w].alpha_val[1] & FIMD_VIDALPHA_ALPHA_LOWER);
1499 }
1500 break;
1501 case 3:
1502 if (w != 1 && w != 2) {
1503 qemu_log_mask(LOG_GUEST_ERROR,
1504 "FIMD: Bad write offset 0x%08"HWADDR_PRIx"\n",
1505 offset);
1506 return;
1507 }
1508 s->window[w].osdsize = val;
1509 break;
1510 }
1511 break;
1512 case FIMD_VIDWADD0_START ... FIMD_VIDWADD0_END:
1513 w = (offset - FIMD_VIDWADD0_START) >> 3;
1514 i = ((offset - FIMD_VIDWADD0_START) >> 2) & 1;
1515 if (i == fimd_get_buffer_id(&s->window[w]) &&
1516 s->window[w].buf_start[i] != val) {
1517 s->window[w].buf_start[i] = val;
1518 fimd_update_memory_section(s, w);
1519 break;
1520 }
1521 s->window[w].buf_start[i] = val;
1522 break;
1523 case FIMD_VIDWADD1_START ... FIMD_VIDWADD1_END:
1524 w = (offset - FIMD_VIDWADD1_START) >> 3;
1525 i = ((offset - FIMD_VIDWADD1_START) >> 2) & 1;
1526 s->window[w].buf_end[i] = val;
1527 break;
1528 case FIMD_VIDWADD2_START ... FIMD_VIDWADD2_END:
1529 w = (offset - FIMD_VIDWADD2_START) >> 2;
1530 if (((val & FIMD_VIDWADD2_PAGEWIDTH) != s->window[w].virtpage_width) ||
1531 (((val >> FIMD_VIDWADD2_OFFSIZE_SHIFT) & FIMD_VIDWADD2_OFFSIZE) !=
1532 s->window[w].virtpage_offsize)) {
1533 s->window[w].virtpage_width = val & FIMD_VIDWADD2_PAGEWIDTH;
1534 s->window[w].virtpage_offsize =
1535 (val >> FIMD_VIDWADD2_OFFSIZE_SHIFT) & FIMD_VIDWADD2_OFFSIZE;
1536 fimd_update_memory_section(s, w);
1537 }
1538 break;
1539 case FIMD_VIDINTCON0:
1540 s->vidintcon[0] = val;
1541 break;
1542 case FIMD_VIDINTCON1:
1543 s->vidintcon[1] &= ~(val & 7);
1544 exynos4210_fimd_update_irq(s);
1545 break;
1546 case FIMD_WKEYCON_START ... FIMD_WKEYCON_END:
1547 w = ((offset - FIMD_WKEYCON_START) >> 3) + 1;
1548 i = ((offset - FIMD_WKEYCON_START) >> 2) & 1;
1549 s->window[w].keycon[i] = val;
1550 break;
1551 case FIMD_WKEYALPHA_START ... FIMD_WKEYALPHA_END:
1552 w = ((offset - FIMD_WKEYALPHA_START) >> 2) + 1;
1553 s->window[w].keyalpha = val;
1554 break;
1555 case FIMD_DITHMODE:
1556 s->dithmode = val;
1557 break;
1558 case FIMD_WINMAP_START ... FIMD_WINMAP_END:
1559 w = (offset - FIMD_WINMAP_START) >> 2;
1560 old_value = s->window[w].winmap;
1561 s->window[w].winmap = val;
1562 if ((val & FIMD_WINMAP_EN) ^ (old_value & FIMD_WINMAP_EN)) {
1563 exynos4210_fimd_invalidate(s);
1564 exynos4210_fimd_update_win_bppmode(s, w);
1565 exynos4210_fimd_trace_bppmode(s, w, 0xFFFFFFFF);
1566 exynos4210_fimd_update(s);
1567 }
1568 break;
1569 case FIMD_WPALCON_HIGH ... FIMD_WPALCON_LOW:
1570 i = (offset - FIMD_WPALCON_HIGH) >> 2;
1571 s->wpalcon[i] = val;
1572 if (s->wpalcon[1] & FIMD_WPALCON_UPDATEEN) {
1573 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1574 exynos4210_fimd_update_win_bppmode(s, w);
1575 fimd_update_get_alpha(s, w);
1576 }
1577 }
1578 break;
1579 case FIMD_TRIGCON:
1580 val = (val & ~FIMD_TRIGCON_ROMASK) | (s->trigcon & FIMD_TRIGCON_ROMASK);
1581 s->trigcon = val;
1582 break;
1583 case FIMD_I80IFCON_START ... FIMD_I80IFCON_END:
1584 s->i80ifcon[(offset - FIMD_I80IFCON_START) >> 2] = val;
1585 break;
1586 case FIMD_COLORGAINCON:
1587 s->colorgaincon = val;
1588 break;
1589 case FIMD_LDI_CMDCON0 ... FIMD_LDI_CMDCON1:
1590 s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON0) >> 2] = val;
1591 break;
1592 case FIMD_SIFCCON0 ... FIMD_SIFCCON2:
1593 i = (offset - FIMD_SIFCCON0) >> 2;
1594 if (i != 2) {
1595 s->sifccon[i] = val;
1596 }
1597 break;
1598 case FIMD_HUECOEFCR_START ... FIMD_HUECOEFCR_END:
1599 i = (offset - FIMD_HUECOEFCR_START) >> 2;
1600 s->huecoef_cr[i] = val;
1601 break;
1602 case FIMD_HUECOEFCB_START ... FIMD_HUECOEFCB_END:
1603 i = (offset - FIMD_HUECOEFCB_START) >> 2;
1604 s->huecoef_cb[i] = val;
1605 break;
1606 case FIMD_HUEOFFSET:
1607 s->hueoffset = val;
1608 break;
1609 case FIMD_VIDWALPHA_START ... FIMD_VIDWALPHA_END:
1610 w = ((offset - FIMD_VIDWALPHA_START) >> 3);
1611 i = ((offset - FIMD_VIDWALPHA_START) >> 2) & 1;
1612 if (w == 0) {
1613 s->window[w].alpha_val[i] = val;
1614 } else {
1615 s->window[w].alpha_val[i] = (val & FIMD_VIDALPHA_ALPHA_LOWER) |
1616 (s->window[w].alpha_val[i] & FIMD_VIDALPHA_ALPHA_UPPER);
1617 }
1618 break;
1619 case FIMD_BLENDEQ_START ... FIMD_BLENDEQ_END:
1620 s->window[(offset - FIMD_BLENDEQ_START) >> 2].blendeq = val;
1621 break;
1622 case FIMD_BLENDCON:
1623 old_value = s->blendcon;
1624 s->blendcon = val;
1625 if ((s->blendcon & FIMD_ALPHA_8BIT) != (old_value & FIMD_ALPHA_8BIT)) {
1626 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1627 fimd_update_get_alpha(s, w);
1628 }
1629 }
1630 break;
1631 case FIMD_WRTQOSCON_START ... FIMD_WRTQOSCON_END:
1632 s->window[(offset - FIMD_WRTQOSCON_START) >> 2].rtqoscon = val;
1633 break;
1634 case FIMD_I80IFCMD_START ... FIMD_I80IFCMD_END:
1635 s->i80ifcmd[(offset - FIMD_I80IFCMD_START) >> 2] = val;
1636 break;
1637 case FIMD_VIDW0ADD0_B2 ... FIMD_VIDW4ADD0_B2:
1638 if (offset & 0x0004) {
1639 qemu_log_mask(LOG_GUEST_ERROR,
1640 "FIMD: bad write offset 0x%08"HWADDR_PRIx"\n",
1641 offset);
1642 break;
1643 }
1644 w = (offset - FIMD_VIDW0ADD0_B2) >> 3;
1645 if (fimd_get_buffer_id(&s->window[w]) == 2 &&
1646 s->window[w].buf_start[2] != val) {
1647 s->window[w].buf_start[2] = val;
1648 fimd_update_memory_section(s, w);
1649 break;
1650 }
1651 s->window[w].buf_start[2] = val;
1652 break;
1653 case FIMD_SHD_ADD0_START ... FIMD_SHD_ADD0_END:
1654 if (offset & 0x0004) {
1655 qemu_log_mask(LOG_GUEST_ERROR,
1656 "FIMD: bad write offset 0x%08"HWADDR_PRIx"\n",
1657 offset);
1658 break;
1659 }
1660 s->window[(offset - FIMD_SHD_ADD0_START) >> 3].shadow_buf_start = val;
1661 break;
1662 case FIMD_SHD_ADD1_START ... FIMD_SHD_ADD1_END:
1663 if (offset & 0x0004) {
1664 qemu_log_mask(LOG_GUEST_ERROR,
1665 "FIMD: bad write offset 0x%08"HWADDR_PRIx"\n",
1666 offset);
1667 break;
1668 }
1669 s->window[(offset - FIMD_SHD_ADD1_START) >> 3].shadow_buf_end = val;
1670 break;
1671 case FIMD_SHD_ADD2_START ... FIMD_SHD_ADD2_END:
1672 s->window[(offset - FIMD_SHD_ADD2_START) >> 2].shadow_buf_size = val;
1673 break;
1674 case FIMD_PAL_MEM_START ... FIMD_PAL_MEM_END:
1675 w = (offset - FIMD_PAL_MEM_START) >> 10;
1676 i = ((offset - FIMD_PAL_MEM_START) >> 2) & 0xFF;
1677 s->window[w].palette[i] = val;
1678 break;
1679 case FIMD_PALMEM_AL_START ... FIMD_PALMEM_AL_END:
1680 /* Palette memory aliases for windows 0 and 1 */
1681 w = (offset - FIMD_PALMEM_AL_START) >> 10;
1682 i = ((offset - FIMD_PALMEM_AL_START) >> 2) & 0xFF;
1683 s->window[w].palette[i] = val;
1684 break;
1685 default:
1686 qemu_log_mask(LOG_GUEST_ERROR,
1687 "FIMD: bad write offset 0x%08"HWADDR_PRIx"\n", offset);
1688 break;
1689 }
1690 }
1691
exynos4210_fimd_read(void * opaque,hwaddr offset,unsigned size)1692 static uint64_t exynos4210_fimd_read(void *opaque, hwaddr offset,
1693 unsigned size)
1694 {
1695 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1696 int w, i;
1697 uint32_t ret = 0;
1698
1699 DPRINT_L2("read offset 0x%08x\n", offset);
1700
1701 switch (offset) {
1702 case FIMD_VIDCON0 ... FIMD_VIDCON3:
1703 return s->vidcon[(offset - FIMD_VIDCON0) >> 2];
1704 case FIMD_VIDTCON_START ... FIMD_VIDTCON_END:
1705 return s->vidtcon[(offset - FIMD_VIDTCON_START) >> 2];
1706 case FIMD_WINCON_START ... FIMD_WINCON_END:
1707 return s->window[(offset - FIMD_WINCON_START) >> 2].wincon;
1708 case FIMD_SHADOWCON:
1709 return s->shadowcon;
1710 case FIMD_WINCHMAP:
1711 return s->winchmap;
1712 case FIMD_VIDOSD_START ... FIMD_VIDOSD_END:
1713 w = (offset - FIMD_VIDOSD_START) >> 4;
1714 i = ((offset - FIMD_VIDOSD_START) & 0xF) >> 2;
1715 switch (i) {
1716 case 0:
1717 ret = ((s->window[w].lefttop_x & FIMD_VIDOSD_COORD_MASK) <<
1718 FIMD_VIDOSD_HOR_SHIFT) |
1719 (s->window[w].lefttop_y & FIMD_VIDOSD_COORD_MASK);
1720 break;
1721 case 1:
1722 ret = ((s->window[w].rightbot_x & FIMD_VIDOSD_COORD_MASK) <<
1723 FIMD_VIDOSD_HOR_SHIFT) |
1724 (s->window[w].rightbot_y & FIMD_VIDOSD_COORD_MASK);
1725 break;
1726 case 2:
1727 if (w == 0) {
1728 ret = s->window[w].osdsize;
1729 } else {
1730 ret = (pack_upper_4(s->window[w].alpha_val[0]) <<
1731 FIMD_VIDOSD_AEN0_SHIFT) |
1732 pack_upper_4(s->window[w].alpha_val[1]);
1733 }
1734 break;
1735 case 3:
1736 if (w != 1 && w != 2) {
1737 qemu_log_mask(LOG_GUEST_ERROR,
1738 "FIMD: bad read offset 0x%08"HWADDR_PRIx"\n",
1739 offset);
1740 return 0xBAADBAAD;
1741 }
1742 ret = s->window[w].osdsize;
1743 break;
1744 }
1745 return ret;
1746 case FIMD_VIDWADD0_START ... FIMD_VIDWADD0_END:
1747 w = (offset - FIMD_VIDWADD0_START) >> 3;
1748 i = ((offset - FIMD_VIDWADD0_START) >> 2) & 1;
1749 return s->window[w].buf_start[i];
1750 case FIMD_VIDWADD1_START ... FIMD_VIDWADD1_END:
1751 w = (offset - FIMD_VIDWADD1_START) >> 3;
1752 i = ((offset - FIMD_VIDWADD1_START) >> 2) & 1;
1753 return s->window[w].buf_end[i];
1754 case FIMD_VIDWADD2_START ... FIMD_VIDWADD2_END:
1755 w = (offset - FIMD_VIDWADD2_START) >> 2;
1756 return s->window[w].virtpage_width | (s->window[w].virtpage_offsize <<
1757 FIMD_VIDWADD2_OFFSIZE_SHIFT);
1758 case FIMD_VIDINTCON0 ... FIMD_VIDINTCON1:
1759 return s->vidintcon[(offset - FIMD_VIDINTCON0) >> 2];
1760 case FIMD_WKEYCON_START ... FIMD_WKEYCON_END:
1761 w = ((offset - FIMD_WKEYCON_START) >> 3) + 1;
1762 i = ((offset - FIMD_WKEYCON_START) >> 2) & 1;
1763 return s->window[w].keycon[i];
1764 case FIMD_WKEYALPHA_START ... FIMD_WKEYALPHA_END:
1765 w = ((offset - FIMD_WKEYALPHA_START) >> 2) + 1;
1766 return s->window[w].keyalpha;
1767 case FIMD_DITHMODE:
1768 return s->dithmode;
1769 case FIMD_WINMAP_START ... FIMD_WINMAP_END:
1770 return s->window[(offset - FIMD_WINMAP_START) >> 2].winmap;
1771 case FIMD_WPALCON_HIGH ... FIMD_WPALCON_LOW:
1772 return s->wpalcon[(offset - FIMD_WPALCON_HIGH) >> 2];
1773 case FIMD_TRIGCON:
1774 return s->trigcon;
1775 case FIMD_I80IFCON_START ... FIMD_I80IFCON_END:
1776 return s->i80ifcon[(offset - FIMD_I80IFCON_START) >> 2];
1777 case FIMD_COLORGAINCON:
1778 return s->colorgaincon;
1779 case FIMD_LDI_CMDCON0 ... FIMD_LDI_CMDCON1:
1780 return s->ldi_cmdcon[(offset - FIMD_LDI_CMDCON0) >> 2];
1781 case FIMD_SIFCCON0 ... FIMD_SIFCCON2:
1782 i = (offset - FIMD_SIFCCON0) >> 2;
1783 return s->sifccon[i];
1784 case FIMD_HUECOEFCR_START ... FIMD_HUECOEFCR_END:
1785 i = (offset - FIMD_HUECOEFCR_START) >> 2;
1786 return s->huecoef_cr[i];
1787 case FIMD_HUECOEFCB_START ... FIMD_HUECOEFCB_END:
1788 i = (offset - FIMD_HUECOEFCB_START) >> 2;
1789 return s->huecoef_cb[i];
1790 case FIMD_HUEOFFSET:
1791 return s->hueoffset;
1792 case FIMD_VIDWALPHA_START ... FIMD_VIDWALPHA_END:
1793 w = ((offset - FIMD_VIDWALPHA_START) >> 3);
1794 i = ((offset - FIMD_VIDWALPHA_START) >> 2) & 1;
1795 return s->window[w].alpha_val[i] &
1796 (w == 0 ? 0xFFFFFF : FIMD_VIDALPHA_ALPHA_LOWER);
1797 case FIMD_BLENDEQ_START ... FIMD_BLENDEQ_END:
1798 return s->window[(offset - FIMD_BLENDEQ_START) >> 2].blendeq;
1799 case FIMD_BLENDCON:
1800 return s->blendcon;
1801 case FIMD_WRTQOSCON_START ... FIMD_WRTQOSCON_END:
1802 return s->window[(offset - FIMD_WRTQOSCON_START) >> 2].rtqoscon;
1803 case FIMD_I80IFCMD_START ... FIMD_I80IFCMD_END:
1804 return s->i80ifcmd[(offset - FIMD_I80IFCMD_START) >> 2];
1805 case FIMD_VIDW0ADD0_B2 ... FIMD_VIDW4ADD0_B2:
1806 if (offset & 0x0004) {
1807 break;
1808 }
1809 return s->window[(offset - FIMD_VIDW0ADD0_B2) >> 3].buf_start[2];
1810 case FIMD_SHD_ADD0_START ... FIMD_SHD_ADD0_END:
1811 if (offset & 0x0004) {
1812 break;
1813 }
1814 return s->window[(offset - FIMD_SHD_ADD0_START) >> 3].shadow_buf_start;
1815 case FIMD_SHD_ADD1_START ... FIMD_SHD_ADD1_END:
1816 if (offset & 0x0004) {
1817 break;
1818 }
1819 return s->window[(offset - FIMD_SHD_ADD1_START) >> 3].shadow_buf_end;
1820 case FIMD_SHD_ADD2_START ... FIMD_SHD_ADD2_END:
1821 return s->window[(offset - FIMD_SHD_ADD2_START) >> 2].shadow_buf_size;
1822 case FIMD_PAL_MEM_START ... FIMD_PAL_MEM_END:
1823 w = (offset - FIMD_PAL_MEM_START) >> 10;
1824 i = ((offset - FIMD_PAL_MEM_START) >> 2) & 0xFF;
1825 return s->window[w].palette[i];
1826 case FIMD_PALMEM_AL_START ... FIMD_PALMEM_AL_END:
1827 /* Palette aliases for win 0,1 */
1828 w = (offset - FIMD_PALMEM_AL_START) >> 10;
1829 i = ((offset - FIMD_PALMEM_AL_START) >> 2) & 0xFF;
1830 return s->window[w].palette[i];
1831 }
1832
1833 qemu_log_mask(LOG_GUEST_ERROR,
1834 "FIMD: bad read offset 0x%08"HWADDR_PRIx"\n", offset);
1835 return 0xBAADBAAD;
1836 }
1837
1838 static const MemoryRegionOps exynos4210_fimd_mmio_ops = {
1839 .read = exynos4210_fimd_read,
1840 .write = exynos4210_fimd_write,
1841 .valid = {
1842 .min_access_size = 4,
1843 .max_access_size = 4,
1844 .unaligned = false
1845 },
1846 .endianness = DEVICE_NATIVE_ENDIAN,
1847 };
1848
exynos4210_fimd_load(void * opaque,int version_id)1849 static int exynos4210_fimd_load(void *opaque, int version_id)
1850 {
1851 Exynos4210fimdState *s = (Exynos4210fimdState *)opaque;
1852 int w;
1853
1854 if (version_id != 1) {
1855 return -EINVAL;
1856 }
1857
1858 for (w = 0; w < NUM_OF_WINDOWS; w++) {
1859 exynos4210_fimd_update_win_bppmode(s, w);
1860 fimd_update_get_alpha(s, w);
1861 fimd_update_memory_section(s, w);
1862 }
1863
1864 /* Redraw the whole screen */
1865 exynos4210_update_resolution(s);
1866 exynos4210_fimd_invalidate(s);
1867 exynos4210_fimd_enable(s, (s->vidcon[0] & FIMD_VIDCON0_ENVID_MASK) ==
1868 FIMD_VIDCON0_ENVID_MASK);
1869 return 0;
1870 }
1871
1872 static const VMStateDescription exynos4210_fimd_window_vmstate = {
1873 .name = "exynos4210.fimd_window",
1874 .version_id = 1,
1875 .minimum_version_id = 1,
1876 .fields = (const VMStateField[]) {
1877 VMSTATE_UINT32(wincon, Exynos4210fimdWindow),
1878 VMSTATE_UINT32_ARRAY(buf_start, Exynos4210fimdWindow, 3),
1879 VMSTATE_UINT32_ARRAY(buf_end, Exynos4210fimdWindow, 3),
1880 VMSTATE_UINT32_ARRAY(keycon, Exynos4210fimdWindow, 2),
1881 VMSTATE_UINT32(keyalpha, Exynos4210fimdWindow),
1882 VMSTATE_UINT32(winmap, Exynos4210fimdWindow),
1883 VMSTATE_UINT32(blendeq, Exynos4210fimdWindow),
1884 VMSTATE_UINT32(rtqoscon, Exynos4210fimdWindow),
1885 VMSTATE_UINT32_ARRAY(palette, Exynos4210fimdWindow, 256),
1886 VMSTATE_UINT32(shadow_buf_start, Exynos4210fimdWindow),
1887 VMSTATE_UINT32(shadow_buf_end, Exynos4210fimdWindow),
1888 VMSTATE_UINT32(shadow_buf_size, Exynos4210fimdWindow),
1889 VMSTATE_UINT16(lefttop_x, Exynos4210fimdWindow),
1890 VMSTATE_UINT16(lefttop_y, Exynos4210fimdWindow),
1891 VMSTATE_UINT16(rightbot_x, Exynos4210fimdWindow),
1892 VMSTATE_UINT16(rightbot_y, Exynos4210fimdWindow),
1893 VMSTATE_UINT32(osdsize, Exynos4210fimdWindow),
1894 VMSTATE_UINT32_ARRAY(alpha_val, Exynos4210fimdWindow, 2),
1895 VMSTATE_UINT16(virtpage_width, Exynos4210fimdWindow),
1896 VMSTATE_UINT16(virtpage_offsize, Exynos4210fimdWindow),
1897 VMSTATE_END_OF_LIST()
1898 }
1899 };
1900
1901 static const VMStateDescription exynos4210_fimd_vmstate = {
1902 .name = "exynos4210.fimd",
1903 .version_id = 1,
1904 .minimum_version_id = 1,
1905 .post_load = exynos4210_fimd_load,
1906 .fields = (const VMStateField[]) {
1907 VMSTATE_UINT32_ARRAY(vidcon, Exynos4210fimdState, 4),
1908 VMSTATE_UINT32_ARRAY(vidtcon, Exynos4210fimdState, 4),
1909 VMSTATE_UINT32(shadowcon, Exynos4210fimdState),
1910 VMSTATE_UINT32(winchmap, Exynos4210fimdState),
1911 VMSTATE_UINT32_ARRAY(vidintcon, Exynos4210fimdState, 2),
1912 VMSTATE_UINT32(dithmode, Exynos4210fimdState),
1913 VMSTATE_UINT32_ARRAY(wpalcon, Exynos4210fimdState, 2),
1914 VMSTATE_UINT32(trigcon, Exynos4210fimdState),
1915 VMSTATE_UINT32_ARRAY(i80ifcon, Exynos4210fimdState, 4),
1916 VMSTATE_UINT32(colorgaincon, Exynos4210fimdState),
1917 VMSTATE_UINT32_ARRAY(ldi_cmdcon, Exynos4210fimdState, 2),
1918 VMSTATE_UINT32_ARRAY(sifccon, Exynos4210fimdState, 3),
1919 VMSTATE_UINT32_ARRAY(huecoef_cr, Exynos4210fimdState, 4),
1920 VMSTATE_UINT32_ARRAY(huecoef_cb, Exynos4210fimdState, 4),
1921 VMSTATE_UINT32(hueoffset, Exynos4210fimdState),
1922 VMSTATE_UINT32_ARRAY(i80ifcmd, Exynos4210fimdState, 12),
1923 VMSTATE_UINT32(blendcon, Exynos4210fimdState),
1924 VMSTATE_STRUCT_ARRAY(window, Exynos4210fimdState, 5, 1,
1925 exynos4210_fimd_window_vmstate, Exynos4210fimdWindow),
1926 VMSTATE_END_OF_LIST()
1927 }
1928 };
1929
1930 static const GraphicHwOps exynos4210_fimd_ops = {
1931 .invalidate = exynos4210_fimd_invalidate,
1932 .gfx_update = exynos4210_fimd_update,
1933 };
1934
1935 static const Property exynos4210_fimd_properties[] = {
1936 DEFINE_PROP_LINK("framebuffer-memory", Exynos4210fimdState, fbmem,
1937 TYPE_MEMORY_REGION, MemoryRegion *),
1938 };
1939
exynos4210_fimd_init(Object * obj)1940 static void exynos4210_fimd_init(Object *obj)
1941 {
1942 Exynos4210fimdState *s = EXYNOS4210_FIMD(obj);
1943 SysBusDevice *dev = SYS_BUS_DEVICE(obj);
1944
1945 s->ifb = NULL;
1946
1947 sysbus_init_irq(dev, &s->irq[0]);
1948 sysbus_init_irq(dev, &s->irq[1]);
1949 sysbus_init_irq(dev, &s->irq[2]);
1950
1951 memory_region_init_io(&s->iomem, obj, &exynos4210_fimd_mmio_ops, s,
1952 "exynos4210.fimd", FIMD_REGS_SIZE);
1953 sysbus_init_mmio(dev, &s->iomem);
1954 }
1955
exynos4210_fimd_realize(DeviceState * dev,Error ** errp)1956 static void exynos4210_fimd_realize(DeviceState *dev, Error **errp)
1957 {
1958 Exynos4210fimdState *s = EXYNOS4210_FIMD(dev);
1959
1960 if (!s->fbmem) {
1961 error_setg(errp, "'framebuffer-memory' property was not set");
1962 return;
1963 }
1964
1965 s->console = graphic_console_init(dev, 0, &exynos4210_fimd_ops, s);
1966 }
1967
exynos4210_fimd_class_init(ObjectClass * klass,const void * data)1968 static void exynos4210_fimd_class_init(ObjectClass *klass, const void *data)
1969 {
1970 DeviceClass *dc = DEVICE_CLASS(klass);
1971
1972 dc->vmsd = &exynos4210_fimd_vmstate;
1973 device_class_set_legacy_reset(dc, exynos4210_fimd_reset);
1974 dc->realize = exynos4210_fimd_realize;
1975 device_class_set_props(dc, exynos4210_fimd_properties);
1976 }
1977
1978 static const TypeInfo exynos4210_fimd_info = {
1979 .name = TYPE_EXYNOS4210_FIMD,
1980 .parent = TYPE_SYS_BUS_DEVICE,
1981 .instance_size = sizeof(Exynos4210fimdState),
1982 .instance_init = exynos4210_fimd_init,
1983 .class_init = exynos4210_fimd_class_init,
1984 };
1985
exynos4210_fimd_register_types(void)1986 static void exynos4210_fimd_register_types(void)
1987 {
1988 type_register_static(&exynos4210_fimd_info);
1989 }
1990
1991 type_init(exynos4210_fimd_register_types)
1992