1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Primary to Sideband (P2SB) bridge access support 4 * 5 * Copyright (c) 2017, 2021-2022 Intel Corporation. 6 * 7 * Authors: Andy Shevchenko <andriy.shevchenko@linux.intel.com> 8 * Jonathan Yong <jonathan.yong@intel.com> 9 */ 10 11 #include <linux/bits.h> 12 #include <linux/export.h> 13 #include <linux/pci.h> 14 #include <linux/platform_data/x86/p2sb.h> 15 16 #include <asm/cpu_device_id.h> 17 #include <asm/intel-family.h> 18 19 #define P2SBC 0xe0 20 #define P2SBC_HIDE BIT(8) 21 22 #define P2SB_DEVFN_DEFAULT PCI_DEVFN(31, 1) 23 #define P2SB_DEVFN_GOLDMONT PCI_DEVFN(13, 0) 24 #define SPI_DEVFN_GOLDMONT PCI_DEVFN(13, 2) 25 26 static const struct x86_cpu_id p2sb_cpu_ids[] = { 27 X86_MATCH_INTEL_FAM6_MODEL(ATOM_GOLDMONT, P2SB_DEVFN_GOLDMONT), 28 {} 29 }; 30 31 /* 32 * Cache BAR0 of P2SB device functions 0 to 7. 33 * TODO: The constant 8 is the number of functions that PCI specification 34 * defines. Same definitions exist tree-wide. Unify this definition and 35 * the other definitions then move to include/uapi/linux/pci.h. 36 */ 37 #define NR_P2SB_RES_CACHE 8 38 39 struct p2sb_res_cache { 40 u32 bus_dev_id; 41 struct resource res; 42 }; 43 44 static struct p2sb_res_cache p2sb_resources[NR_P2SB_RES_CACHE]; 45 static bool p2sb_hidden_by_bios; 46 p2sb_get_devfn(unsigned int * devfn)47 static void p2sb_get_devfn(unsigned int *devfn) 48 { 49 unsigned int fn = P2SB_DEVFN_DEFAULT; 50 const struct x86_cpu_id *id; 51 52 id = x86_match_cpu(p2sb_cpu_ids); 53 if (id) 54 fn = (unsigned int)id->driver_data; 55 56 *devfn = fn; 57 } 58 p2sb_valid_resource(const struct resource * res)59 static bool p2sb_valid_resource(const struct resource *res) 60 { 61 return res->flags & ~IORESOURCE_UNSET; 62 } 63 64 /* Copy resource from the first BAR of the device in question */ p2sb_read_bar0(struct pci_dev * pdev,struct resource * mem)65 static void p2sb_read_bar0(struct pci_dev *pdev, struct resource *mem) 66 { 67 struct resource *bar0 = &pdev->resource[0]; 68 69 /* Make sure we have no dangling pointers in the output */ 70 memset(mem, 0, sizeof(*mem)); 71 72 /* 73 * We copy only selected fields from the original resource. 74 * Because a PCI device will be removed soon, we may not use 75 * any allocated data, hence we may not copy any pointers. 76 */ 77 mem->start = bar0->start; 78 mem->end = bar0->end; 79 mem->flags = bar0->flags; 80 mem->desc = bar0->desc; 81 } 82 p2sb_scan_and_cache_devfn(struct pci_bus * bus,unsigned int devfn)83 static void p2sb_scan_and_cache_devfn(struct pci_bus *bus, unsigned int devfn) 84 { 85 struct p2sb_res_cache *cache = &p2sb_resources[PCI_FUNC(devfn)]; 86 struct pci_dev *pdev; 87 88 pdev = pci_scan_single_device(bus, devfn); 89 if (!pdev) 90 return; 91 92 p2sb_read_bar0(pdev, &cache->res); 93 cache->bus_dev_id = bus->dev.id; 94 95 pci_stop_and_remove_bus_device(pdev); 96 } 97 p2sb_scan_and_cache(struct pci_bus * bus,unsigned int devfn)98 static int p2sb_scan_and_cache(struct pci_bus *bus, unsigned int devfn) 99 { 100 /* 101 * The BIOS prevents the P2SB device from being enumerated by the PCI 102 * subsystem, so we need to unhide and hide it back to lookup the BAR. 103 */ 104 pci_bus_write_config_dword(bus, devfn, P2SBC, 0); 105 106 /* Scan the P2SB device and cache its BAR0 */ 107 p2sb_scan_and_cache_devfn(bus, devfn); 108 109 /* On Goldmont p2sb_bar() also gets called for the SPI controller */ 110 if (devfn == P2SB_DEVFN_GOLDMONT) 111 p2sb_scan_and_cache_devfn(bus, SPI_DEVFN_GOLDMONT); 112 113 pci_bus_write_config_dword(bus, devfn, P2SBC, P2SBC_HIDE); 114 115 if (!p2sb_valid_resource(&p2sb_resources[PCI_FUNC(devfn)].res)) 116 return -ENOENT; 117 118 return 0; 119 } 120 p2sb_get_bus(struct pci_bus * bus)121 static struct pci_bus *p2sb_get_bus(struct pci_bus *bus) 122 { 123 static struct pci_bus *p2sb_bus; 124 125 bus = bus ?: p2sb_bus; 126 if (bus) 127 return bus; 128 129 /* Assume P2SB is on the bus 0 in domain 0 */ 130 p2sb_bus = pci_find_bus(0, 0); 131 return p2sb_bus; 132 } 133 p2sb_cache_resources(void)134 static int p2sb_cache_resources(void) 135 { 136 unsigned int devfn_p2sb; 137 u32 value = P2SBC_HIDE; 138 struct pci_bus *bus; 139 u16 class; 140 int ret = 0; 141 142 /* Get devfn for P2SB device itself */ 143 p2sb_get_devfn(&devfn_p2sb); 144 145 bus = p2sb_get_bus(NULL); 146 if (!bus) 147 return -ENODEV; 148 149 /* 150 * When a device with same devfn exists and its device class is not 151 * PCI_CLASS_MEMORY_OTHER for P2SB, do not touch it. 152 */ 153 pci_bus_read_config_word(bus, devfn_p2sb, PCI_CLASS_DEVICE, &class); 154 if (!PCI_POSSIBLE_ERROR(class) && class != PCI_CLASS_MEMORY_OTHER) 155 return -ENODEV; 156 157 /* 158 * Prevent concurrent PCI bus scan from seeing the P2SB device and 159 * removing via sysfs while it is temporarily exposed. 160 */ 161 pci_lock_rescan_remove(); 162 163 pci_bus_read_config_dword(bus, devfn_p2sb, P2SBC, &value); 164 p2sb_hidden_by_bios = value & P2SBC_HIDE; 165 166 /* 167 * If the BIOS does not hide the P2SB device then its resources 168 * are accesilble. Cache them only if the P2SB device is hidden. 169 */ 170 if (p2sb_hidden_by_bios) 171 ret = p2sb_scan_and_cache(bus, devfn_p2sb); 172 173 pci_unlock_rescan_remove(); 174 175 return ret; 176 } 177 p2sb_read_from_cache(struct pci_bus * bus,unsigned int devfn,struct resource * mem)178 static int p2sb_read_from_cache(struct pci_bus *bus, unsigned int devfn, 179 struct resource *mem) 180 { 181 struct p2sb_res_cache *cache = &p2sb_resources[PCI_FUNC(devfn)]; 182 183 if (cache->bus_dev_id != bus->dev.id) 184 return -ENODEV; 185 186 if (!p2sb_valid_resource(&cache->res)) 187 return -ENOENT; 188 189 memcpy(mem, &cache->res, sizeof(*mem)); 190 191 return 0; 192 } 193 p2sb_read_from_dev(struct pci_bus * bus,unsigned int devfn,struct resource * mem)194 static int p2sb_read_from_dev(struct pci_bus *bus, unsigned int devfn, 195 struct resource *mem) 196 { 197 struct pci_dev *pdev; 198 int ret = 0; 199 200 pdev = pci_get_slot(bus, devfn); 201 if (!pdev) 202 return -ENODEV; 203 204 if (p2sb_valid_resource(pci_resource_n(pdev, 0))) 205 p2sb_read_bar0(pdev, mem); 206 else 207 ret = -ENOENT; 208 209 pci_dev_put(pdev); 210 211 return ret; 212 } 213 214 /** 215 * p2sb_bar - Get Primary to Sideband (P2SB) bridge device BAR 216 * @bus: PCI bus to communicate with 217 * @devfn: PCI slot and function to communicate with 218 * @mem: memory resource to be filled in 219 * 220 * If @bus is NULL, the bus 0 in domain 0 will be used. 221 * If @devfn is 0, it will be replaced by devfn of the P2SB device. 222 * 223 * Caller must provide a valid pointer to @mem. 224 * 225 * Return: 226 * 0 on success or appropriate errno value on error. 227 */ p2sb_bar(struct pci_bus * bus,unsigned int devfn,struct resource * mem)228 int p2sb_bar(struct pci_bus *bus, unsigned int devfn, struct resource *mem) 229 { 230 bus = p2sb_get_bus(bus); 231 if (!bus) 232 return -ENODEV; 233 234 if (!devfn) 235 p2sb_get_devfn(&devfn); 236 237 if (p2sb_hidden_by_bios) 238 return p2sb_read_from_cache(bus, devfn, mem); 239 240 return p2sb_read_from_dev(bus, devfn, mem); 241 } 242 EXPORT_SYMBOL_GPL(p2sb_bar); 243 p2sb_fs_init(void)244 static int __init p2sb_fs_init(void) 245 { 246 return p2sb_cache_resources(); 247 } 248 249 /* 250 * pci_rescan_remove_lock() can not be locked in sysfs PCI bus rescan path 251 * because of deadlock. To avoid the deadlock, access P2SB devices with the lock 252 * at an early step in kernel initialization and cache required resources. 253 * 254 * We want to run as early as possible. If the P2SB was assigned a bad BAR, 255 * we'll need to wait on pcibios_assign_resources() to fix it. So, our list of 256 * initcall dependencies looks something like this: 257 * 258 * ... 259 * subsys_initcall (pci_subsys_init) 260 * fs_initcall (pcibios_assign_resources) 261 */ 262 fs_initcall_sync(p2sb_fs_init); 263