1 /* SPDX-License-Identifier: GPL-2.0
2  * Marvell OcteonTX CPT driver
3  *
4  * Copyright (C) 2019 Marvell International Ltd.
5  *
6  * This program is free software; you can redistribute it and/or modify
7  * it under the terms of the GNU General Public License version 2 as
8  * published by the Free Software Foundation.
9  */
10 
11 #ifndef __OTX_CPT_HW_TYPES_H
12 #define __OTX_CPT_HW_TYPES_H
13 
14 #include <linux/types.h>
15 
16 /* Device IDs */
17 #define OTX_CPT_PCI_PF_DEVICE_ID 0xa040
18 #define OTX_CPT_PCI_VF_DEVICE_ID 0xa041
19 
20 #define OTX_CPT_PCI_PF_SUBSYS_ID 0xa340
21 #define OTX_CPT_PCI_VF_SUBSYS_ID 0xa341
22 
23 /* Configuration and status registers are in BAR0 on OcteonTX platform */
24 #define OTX_CPT_PF_PCI_CFG_BAR	0
25 #define OTX_CPT_VF_PCI_CFG_BAR	0
26 
27 #define OTX_CPT_BAR_E_CPTX_VFX_BAR0_OFFSET(a, b) \
28 	(0x000020000000ll + 0x1000000000ll * (a) + 0x100000ll * (b))
29 #define OTX_CPT_BAR_E_CPTX_VFX_BAR0_SIZE	0x400000
30 
31 /* Mailbox interrupts offset */
32 #define OTX_CPT_PF_MBOX_INT	3
33 #define OTX_CPT_PF_INT_VEC_E_MBOXX(x, a) ((x) + (a))
34 /* Number of MSIX supported in PF */
35 #define OTX_CPT_PF_MSIX_VECTORS 4
36 /* Maximum supported microcode groups */
37 #define OTX_CPT_MAX_ENGINE_GROUPS 8
38 
39 /* CPT instruction size in bytes */
40 #define OTX_CPT_INST_SIZE 64
41 /* CPT queue next chunk pointer size in bytes */
42 #define OTX_CPT_NEXT_CHUNK_PTR_SIZE 8
43 
44 /* OcteonTX CPT VF MSIX vectors and their offsets */
45 #define OTX_CPT_VF_MSIX_VECTORS 2
46 #define OTX_CPT_VF_INTR_MBOX_MASK BIT(0)
47 #define OTX_CPT_VF_INTR_DOVF_MASK BIT(1)
48 #define OTX_CPT_VF_INTR_IRDE_MASK BIT(2)
49 #define OTX_CPT_VF_INTR_NWRP_MASK BIT(3)
50 #define OTX_CPT_VF_INTR_SERR_MASK BIT(4)
51 
52 /* OcteonTX CPT PF registers */
53 #define OTX_CPT_PF_CONSTANTS		(0x0ll)
54 #define OTX_CPT_PF_RESET		(0x100ll)
55 #define OTX_CPT_PF_DIAG			(0x120ll)
56 #define OTX_CPT_PF_BIST_STATUS		(0x160ll)
57 #define OTX_CPT_PF_ECC0_CTL		(0x200ll)
58 #define OTX_CPT_PF_ECC0_FLIP		(0x210ll)
59 #define OTX_CPT_PF_ECC0_INT		(0x220ll)
60 #define OTX_CPT_PF_ECC0_INT_W1S		(0x230ll)
61 #define OTX_CPT_PF_ECC0_ENA_W1S		(0x240ll)
62 #define OTX_CPT_PF_ECC0_ENA_W1C		(0x250ll)
63 #define OTX_CPT_PF_MBOX_INTX(b)		(0x400ll | (u64)(b) << 3)
64 #define OTX_CPT_PF_MBOX_INT_W1SX(b)	(0x420ll | (u64)(b) << 3)
65 #define OTX_CPT_PF_MBOX_ENA_W1CX(b)	(0x440ll | (u64)(b) << 3)
66 #define OTX_CPT_PF_MBOX_ENA_W1SX(b)	(0x460ll | (u64)(b) << 3)
67 #define OTX_CPT_PF_EXEC_INT		(0x500ll)
68 #define OTX_CPT_PF_EXEC_INT_W1S		(0x520ll)
69 #define OTX_CPT_PF_EXEC_ENA_W1C		(0x540ll)
70 #define OTX_CPT_PF_EXEC_ENA_W1S		(0x560ll)
71 #define OTX_CPT_PF_GX_EN(b)		(0x600ll | (u64)(b) << 3)
72 #define OTX_CPT_PF_EXEC_INFO		(0x700ll)
73 #define OTX_CPT_PF_EXEC_BUSY		(0x800ll)
74 #define OTX_CPT_PF_EXEC_INFO0		(0x900ll)
75 #define OTX_CPT_PF_EXEC_INFO1		(0x910ll)
76 #define OTX_CPT_PF_INST_REQ_PC		(0x10000ll)
77 #define OTX_CPT_PF_INST_LATENCY_PC	(0x10020ll)
78 #define OTX_CPT_PF_RD_REQ_PC		(0x10040ll)
79 #define OTX_CPT_PF_RD_LATENCY_PC	(0x10060ll)
80 #define OTX_CPT_PF_RD_UC_PC		(0x10080ll)
81 #define OTX_CPT_PF_ACTIVE_CYCLES_PC	(0x10100ll)
82 #define OTX_CPT_PF_EXE_CTL		(0x4000000ll)
83 #define OTX_CPT_PF_EXE_STATUS		(0x4000008ll)
84 #define OTX_CPT_PF_EXE_CLK		(0x4000010ll)
85 #define OTX_CPT_PF_EXE_DBG_CTL		(0x4000018ll)
86 #define OTX_CPT_PF_EXE_DBG_DATA		(0x4000020ll)
87 #define OTX_CPT_PF_EXE_BIST_STATUS	(0x4000028ll)
88 #define OTX_CPT_PF_EXE_REQ_TIMER	(0x4000030ll)
89 #define OTX_CPT_PF_EXE_MEM_CTL		(0x4000038ll)
90 #define OTX_CPT_PF_EXE_PERF_CTL		(0x4001000ll)
91 #define OTX_CPT_PF_EXE_DBG_CNTX(b)	(0x4001100ll | (u64)(b) << 3)
92 #define OTX_CPT_PF_EXE_PERF_EVENT_CNT	(0x4001180ll)
93 #define OTX_CPT_PF_EXE_EPCI_INBX_CNT(b)	(0x4001200ll | (u64)(b) << 3)
94 #define OTX_CPT_PF_EXE_EPCI_OUTBX_CNT(b) (0x4001240ll | (u64)(b) << 3)
95 #define OTX_CPT_PF_ENGX_UCODE_BASE(b)	(0x4002000ll | (u64)(b) << 3)
96 #define OTX_CPT_PF_QX_CTL(b)		(0x8000000ll | (u64)(b) << 20)
97 #define OTX_CPT_PF_QX_GMCTL(b)		(0x8000020ll | (u64)(b) << 20)
98 #define OTX_CPT_PF_QX_CTL2(b)		(0x8000100ll | (u64)(b) << 20)
99 #define OTX_CPT_PF_VFX_MBOXX(b, c)	(0x8001000ll | (u64)(b) << 20 | \
100 					 (u64)(c) << 8)
101 
102 /* OcteonTX CPT VF registers */
103 #define OTX_CPT_VQX_CTL(b)		(0x100ll | (u64)(b) << 20)
104 #define OTX_CPT_VQX_SADDR(b)		(0x200ll | (u64)(b) << 20)
105 #define OTX_CPT_VQX_DONE_WAIT(b)	(0x400ll | (u64)(b) << 20)
106 #define OTX_CPT_VQX_INPROG(b)		(0x410ll | (u64)(b) << 20)
107 #define OTX_CPT_VQX_DONE(b)		(0x420ll | (u64)(b) << 20)
108 #define OTX_CPT_VQX_DONE_ACK(b)		(0x440ll | (u64)(b) << 20)
109 #define OTX_CPT_VQX_DONE_INT_W1S(b)	(0x460ll | (u64)(b) << 20)
110 #define OTX_CPT_VQX_DONE_INT_W1C(b)	(0x468ll | (u64)(b) << 20)
111 #define OTX_CPT_VQX_DONE_ENA_W1S(b)	(0x470ll | (u64)(b) << 20)
112 #define OTX_CPT_VQX_DONE_ENA_W1C(b)	(0x478ll | (u64)(b) << 20)
113 #define OTX_CPT_VQX_MISC_INT(b)		(0x500ll | (u64)(b) << 20)
114 #define OTX_CPT_VQX_MISC_INT_W1S(b)	(0x508ll | (u64)(b) << 20)
115 #define OTX_CPT_VQX_MISC_ENA_W1S(b)	(0x510ll | (u64)(b) << 20)
116 #define OTX_CPT_VQX_MISC_ENA_W1C(b)	(0x518ll | (u64)(b) << 20)
117 #define OTX_CPT_VQX_DOORBELL(b)		(0x600ll | (u64)(b) << 20)
118 #define OTX_CPT_VFX_PF_MBOXX(b, c)	(0x1000ll | ((b) << 20) | ((c) << 3))
119 
120 /*
121  * Enumeration otx_cpt_ucode_error_code_e
122  *
123  * Enumerates ucode errors
124  */
125 enum otx_cpt_ucode_error_code_e {
126 	CPT_NO_UCODE_ERROR = 0x00,
127 	ERR_OPCODE_UNSUPPORTED = 0x01,
128 
129 	/* Scatter gather */
130 	ERR_SCATTER_GATHER_WRITE_LENGTH = 0x02,
131 	ERR_SCATTER_GATHER_LIST = 0x03,
132 	ERR_SCATTER_GATHER_NOT_SUPPORTED = 0x04,
133 
134 };
135 
136 /*
137  * Enumeration otx_cpt_comp_e
138  *
139  * CPT OcteonTX Completion Enumeration
140  * Enumerates the values of CPT_RES_S[COMPCODE].
141  */
142 enum otx_cpt_comp_e {
143 	CPT_COMP_E_NOTDONE = 0x00,
144 	CPT_COMP_E_GOOD = 0x01,
145 	CPT_COMP_E_FAULT = 0x02,
146 	CPT_COMP_E_SWERR = 0x03,
147 	CPT_COMP_E_HWERR = 0x04,
148 	CPT_COMP_E_LAST_ENTRY = 0x05
149 };
150 
151 /*
152  * Enumeration otx_cpt_vf_int_vec_e
153  *
154  * CPT OcteonTX VF MSI-X Vector Enumeration
155  * Enumerates the MSI-X interrupt vectors.
156  */
157 enum otx_cpt_vf_int_vec_e {
158 	CPT_VF_INT_VEC_E_MISC = 0x00,
159 	CPT_VF_INT_VEC_E_DONE = 0x01
160 };
161 
162 /*
163  * Structure cpt_inst_s
164  *
165  * CPT Instruction Structure
166  * This structure specifies the instruction layout. Instructions are
167  * stored in memory as little-endian unless CPT()_PF_Q()_CTL[INST_BE] is set.
168  * cpt_inst_s_s
169  * Word 0
170  * doneint:1 Done interrupt.
171  *	0 = No interrupts related to this instruction.
172  *	1 = When the instruction completes, CPT()_VQ()_DONE[DONE] will be
173  *	incremented,and based on the rules described there an interrupt may
174  *	occur.
175  * Word 1
176  * res_addr [127: 64] Result IOVA.
177  *	If nonzero, specifies where to write CPT_RES_S.
178  *	If zero, no result structure will be written.
179  *	Address must be 16-byte aligned.
180  *	Bits <63:49> are ignored by hardware; software should use a
181  *	sign-extended bit <48> for forward compatibility.
182  * Word 2
183  *  grp:10 [171:162] If [WQ_PTR] is nonzero, the SSO guest-group to use when
184  *	CPT submits work SSO.
185  *	For the SSO to not discard the add-work request, FPA_PF_MAP() must map
186  *	[GRP] and CPT()_PF_Q()_GMCTL[GMID] as valid.
187  *  tt:2 [161:160] If [WQ_PTR] is nonzero, the SSO tag type to use when CPT
188  *	submits work to SSO
189  *  tag:32 [159:128] If [WQ_PTR] is nonzero, the SSO tag to use when CPT
190  *	submits work to SSO.
191  * Word 3
192  *  wq_ptr [255:192] If [WQ_PTR] is nonzero, it is a pointer to a
193  *	work-queue entry that CPT submits work to SSO after all context,
194  *	output data, and result write operations are visible to other
195  *	CNXXXX units and the cores. Bits <2:0> must be zero.
196  *	Bits <63:49> are ignored by hardware; software should
197  *	use a sign-extended bit <48> for forward compatibility.
198  *	Internal:
199  *	Bits <63:49>, <2:0> are ignored by hardware, treated as always 0x0.
200  * Word 4
201  *  ei0; [319:256] Engine instruction word 0. Passed to the AE/SE.
202  * Word 5
203  *  ei1; [383:320] Engine instruction word 1. Passed to the AE/SE.
204  * Word 6
205  *  ei2; [447:384] Engine instruction word 1. Passed to the AE/SE.
206  * Word 7
207  *  ei3; [511:448] Engine instruction word 1. Passed to the AE/SE.
208  *
209  */
210 union otx_cpt_inst_s {
211 	u64 u[8];
212 
213 	struct {
214 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
215 		u64 reserved_17_63:47;
216 		u64 doneint:1;
217 		u64 reserved_0_15:16;
218 #else /* Word 0 - Little Endian */
219 		u64 reserved_0_15:16;
220 		u64 doneint:1;
221 		u64 reserved_17_63:47;
222 #endif /* Word 0 - End */
223 		u64 res_addr;
224 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 2 - Big Endian */
225 		u64 reserved_172_191:20;
226 		u64 grp:10;
227 		u64 tt:2;
228 		u64 tag:32;
229 #else /* Word 2 - Little Endian */
230 		u64 tag:32;
231 		u64 tt:2;
232 		u64 grp:10;
233 		u64 reserved_172_191:20;
234 #endif /* Word 2 - End */
235 		u64 wq_ptr;
236 		u64 ei0;
237 		u64 ei1;
238 		u64 ei2;
239 		u64 ei3;
240 	} s;
241 };
242 
243 /*
244  * Structure cpt_res_s
245  *
246  * CPT Result Structure
247  * The CPT coprocessor writes the result structure after it completes a
248  * CPT_INST_S instruction. The result structure is exactly 16 bytes, and
249  * each instruction completion produces exactly one result structure.
250  *
251  * This structure is stored in memory as little-endian unless
252  * CPT()_PF_Q()_CTL[INST_BE] is set.
253  * cpt_res_s_s
254  * Word 0
255  *  doneint:1 [16:16] Done interrupt. This bit is copied from the
256  *	corresponding instruction's CPT_INST_S[DONEINT].
257  *  compcode:8 [7:0] Indicates completion/error status of the CPT coprocessor
258  *	for the	associated instruction, as enumerated by CPT_COMP_E.
259  *	Core software may write the memory location containing [COMPCODE] to
260  *	0x0 before ringing the doorbell, and then poll for completion by
261  *	checking for a nonzero value.
262  *	Once the core observes a nonzero [COMPCODE] value in this case,the CPT
263  *	coprocessor will have also completed L2/DRAM write operations.
264  * Word 1
265  *  reserved
266  *
267  */
268 union otx_cpt_res_s {
269 	u64 u[2];
270 	struct {
271 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
272 		u64 reserved_17_63:47;
273 		u64 doneint:1;
274 		u64 reserved_8_15:8;
275 		u64 compcode:8;
276 #else /* Word 0 - Little Endian */
277 		u64 compcode:8;
278 		u64 reserved_8_15:8;
279 		u64 doneint:1;
280 		u64 reserved_17_63:47;
281 #endif /* Word 0 - End */
282 		u64 reserved_64_127;
283 	} s;
284 };
285 
286 /*
287  * Register (NCB) otx_cpt#_pf_bist_status
288  *
289  * CPT PF Control Bist Status Register
290  * This register has the BIST status of memories. Each bit is the BIST result
291  * of an individual memory (per bit, 0 = pass and 1 = fail).
292  * otx_cptx_pf_bist_status_s
293  * Word0
294  *  bstatus [29:0](RO/H) BIST status. One bit per memory, enumerated by
295  *	CPT_RAMS_E.
296  */
297 union otx_cptx_pf_bist_status {
298 	u64 u;
299 	struct otx_cptx_pf_bist_status_s {
300 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
301 		u64 reserved_30_63:34;
302 		u64 bstatus:30;
303 #else /* Word 0 - Little Endian */
304 		u64 bstatus:30;
305 		u64 reserved_30_63:34;
306 #endif /* Word 0 - End */
307 	} s;
308 };
309 
310 /*
311  * Register (NCB) otx_cpt#_pf_constants
312  *
313  * CPT PF Constants Register
314  * This register contains implementation-related parameters of CPT in CNXXXX.
315  * otx_cptx_pf_constants_s
316  * Word 0
317  *  reserved_40_63:24 [63:40] Reserved.
318  *  epcis:8 [39:32](RO) Number of EPCI busses.
319  *  grps:8 [31:24](RO) Number of engine groups implemented.
320  *  ae:8 [23:16](RO/H) Number of AEs. In CNXXXX, for CPT0 returns 0x0,
321  *	for CPT1 returns 0x18, or less if there are fuse-disables.
322  *  se:8 [15:8](RO/H) Number of SEs. In CNXXXX, for CPT0 returns 0x30,
323  *	or less if there are fuse-disables, for CPT1 returns 0x0.
324  *  vq:8 [7:0](RO) Number of VQs.
325  */
326 union otx_cptx_pf_constants {
327 	u64 u;
328 	struct otx_cptx_pf_constants_s {
329 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
330 		u64 reserved_40_63:24;
331 		u64 epcis:8;
332 		u64 grps:8;
333 		u64 ae:8;
334 		u64 se:8;
335 		u64 vq:8;
336 #else /* Word 0 - Little Endian */
337 		u64 vq:8;
338 		u64 se:8;
339 		u64 ae:8;
340 		u64 grps:8;
341 		u64 epcis:8;
342 		u64 reserved_40_63:24;
343 #endif /* Word 0 - End */
344 	} s;
345 };
346 
347 /*
348  * Register (NCB) otx_cpt#_pf_exe_bist_status
349  *
350  * CPT PF Engine Bist Status Register
351  * This register has the BIST status of each engine.  Each bit is the
352  * BIST result of an individual engine (per bit, 0 = pass and 1 = fail).
353  * otx_cptx_pf_exe_bist_status_s
354  * Word0
355  *  reserved_48_63:16 [63:48] reserved
356  *  bstatus:48 [47:0](RO/H) BIST status. One bit per engine.
357  *
358  */
359 union otx_cptx_pf_exe_bist_status {
360 	u64 u;
361 	struct otx_cptx_pf_exe_bist_status_s {
362 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
363 		u64 reserved_48_63:16;
364 		u64 bstatus:48;
365 #else /* Word 0 - Little Endian */
366 		u64 bstatus:48;
367 		u64 reserved_48_63:16;
368 #endif /* Word 0 - End */
369 	} s;
370 };
371 
372 /*
373  * Register (NCB) otx_cpt#_pf_q#_ctl
374  *
375  * CPT Queue Control Register
376  * This register configures queues. This register should be changed only
377  * when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]).
378  * otx_cptx_pf_qx_ctl_s
379  * Word0
380  *  reserved_60_63:4 [63:60] reserved.
381  *  aura:12; [59:48](R/W) Guest-aura for returning this queue's
382  *	instruction-chunk buffers to FPA. Only used when [INST_FREE] is set.
383  *	For the FPA to not discard the request, FPA_PF_MAP() must map
384  *	[AURA] and CPT()_PF_Q()_GMCTL[GMID] as valid.
385  *  reserved_45_47:3 [47:45] reserved.
386  *  size:13 [44:32](R/W) Command-buffer size, in number of 64-bit words per
387  *	command buffer segment. Must be 8*n + 1, where n is the number of
388  *	instructions per buffer segment.
389  *  reserved_11_31:21 [31:11] Reserved.
390  *  cont_err:1 [10:10](R/W) Continue on error.
391  *	0 = When CPT()_VQ()_MISC_INT[NWRP], CPT()_VQ()_MISC_INT[IRDE] or
392  *	CPT()_VQ()_MISC_INT[DOVF] are set by hardware or software via
393  *	CPT()_VQ()_MISC_INT_W1S, then CPT()_VQ()_CTL[ENA] is cleared.  Due to
394  *	pipelining, additional instructions may have been processed between the
395  *	instruction causing the error and the next instruction in the disabled
396  *	queue (the instruction at CPT()_VQ()_SADDR).
397  *	1 = Ignore errors and continue processing instructions.
398  *	For diagnostic use only.
399  *  inst_free:1 [9:9](R/W) Instruction FPA free. When set, when CPT reaches the
400  *	end of an instruction chunk, that chunk will be freed to the FPA.
401  *  inst_be:1 [8:8](R/W) Instruction big-endian control. When set, instructions,
402  *	instruction next chunk pointers, and result structures are stored in
403  *	big-endian format in memory.
404  *  iqb_ldwb:1 [7:7](R/W) Instruction load don't write back.
405  *	0 = The hardware issues NCB transient load (LDT) towards the cache,
406  *	which if the line hits and is dirty will cause the line to be
407  *	written back before being replaced.
408  *	1 = The hardware issues NCB LDWB read-and-invalidate command towards
409  *	the cache when fetching the last word of instructions; as a result the
410  *	line will not be written back when replaced.  This improves
411  *	performance, but software must not read the instructions after they are
412  *	posted to the hardware.	Reads that do not consume the last word of a
413  *	cache line always use LDI.
414  *  reserved_4_6:3 [6:4] Reserved.
415  *  grp:3; [3:1](R/W) Engine group.
416  *  pri:1; [0:0](R/W) Queue priority.
417  *	1 = This queue has higher priority. Round-robin between higher
418  *	priority queues.
419  *	0 = This queue has lower priority. Round-robin between lower
420  *	priority queues.
421  */
422 union otx_cptx_pf_qx_ctl {
423 	u64 u;
424 	struct otx_cptx_pf_qx_ctl_s {
425 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
426 		u64 reserved_60_63:4;
427 		u64 aura:12;
428 		u64 reserved_45_47:3;
429 		u64 size:13;
430 		u64 reserved_11_31:21;
431 		u64 cont_err:1;
432 		u64 inst_free:1;
433 		u64 inst_be:1;
434 		u64 iqb_ldwb:1;
435 		u64 reserved_4_6:3;
436 		u64 grp:3;
437 		u64 pri:1;
438 #else /* Word 0 - Little Endian */
439 		u64 pri:1;
440 		u64 grp:3;
441 		u64 reserved_4_6:3;
442 		u64 iqb_ldwb:1;
443 		u64 inst_be:1;
444 		u64 inst_free:1;
445 		u64 cont_err:1;
446 		u64 reserved_11_31:21;
447 		u64 size:13;
448 		u64 reserved_45_47:3;
449 		u64 aura:12;
450 		u64 reserved_60_63:4;
451 #endif /* Word 0 - End */
452 	} s;
453 };
454 
455 /*
456  * Register (NCB) otx_cpt#_vq#_saddr
457  *
458  * CPT Queue Starting Buffer Address Registers
459  * These registers set the instruction buffer starting address.
460  * otx_cptx_vqx_saddr_s
461  * Word0
462  *  reserved_49_63:15 [63:49] Reserved.
463  *  ptr:43 [48:6](R/W/H) Instruction buffer IOVA <48:6> (64-byte aligned).
464  *	When written, it is the initial buffer starting address; when read,
465  *	it is the next read pointer to be requested from L2C. The PTR field
466  *	is overwritten with the next pointer each time that the command buffer
467  *	segment is exhausted. New commands will then be read from the newly
468  *	specified command buffer pointer.
469  *  reserved_0_5:6 [5:0] Reserved.
470  *
471  */
472 union otx_cptx_vqx_saddr {
473 	u64 u;
474 	struct otx_cptx_vqx_saddr_s {
475 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
476 		u64 reserved_49_63:15;
477 		u64 ptr:43;
478 		u64 reserved_0_5:6;
479 #else /* Word 0 - Little Endian */
480 		u64 reserved_0_5:6;
481 		u64 ptr:43;
482 		u64 reserved_49_63:15;
483 #endif /* Word 0 - End */
484 	} s;
485 };
486 
487 /*
488  * Register (NCB) otx_cpt#_vq#_misc_ena_w1s
489  *
490  * CPT Queue Misc Interrupt Enable Set Register
491  * This register sets interrupt enable bits.
492  * otx_cptx_vqx_misc_ena_w1s_s
493  * Word0
494  * reserved_5_63:59 [63:5] Reserved.
495  * swerr:1 [4:4](R/W1S/H) Reads or sets enable for
496  *	CPT(0..1)_VQ(0..63)_MISC_INT[SWERR].
497  * nwrp:1 [3:3](R/W1S/H) Reads or sets enable for
498  *	CPT(0..1)_VQ(0..63)_MISC_INT[NWRP].
499  * irde:1 [2:2](R/W1S/H) Reads or sets enable for
500  *	CPT(0..1)_VQ(0..63)_MISC_INT[IRDE].
501  * dovf:1 [1:1](R/W1S/H) Reads or sets enable for
502  *	CPT(0..1)_VQ(0..63)_MISC_INT[DOVF].
503  * mbox:1 [0:0](R/W1S/H) Reads or sets enable for
504  *	CPT(0..1)_VQ(0..63)_MISC_INT[MBOX].
505  *
506  */
507 union otx_cptx_vqx_misc_ena_w1s {
508 	u64 u;
509 	struct otx_cptx_vqx_misc_ena_w1s_s {
510 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
511 		u64 reserved_5_63:59;
512 		u64 swerr:1;
513 		u64 nwrp:1;
514 		u64 irde:1;
515 		u64 dovf:1;
516 		u64 mbox:1;
517 #else /* Word 0 - Little Endian */
518 		u64 mbox:1;
519 		u64 dovf:1;
520 		u64 irde:1;
521 		u64 nwrp:1;
522 		u64 swerr:1;
523 		u64 reserved_5_63:59;
524 #endif /* Word 0 - End */
525 	} s;
526 };
527 
528 /*
529  * Register (NCB) otx_cpt#_vq#_doorbell
530  *
531  * CPT Queue Doorbell Registers
532  * Doorbells for the CPT instruction queues.
533  * otx_cptx_vqx_doorbell_s
534  * Word0
535  *  reserved_20_63:44 [63:20] Reserved.
536  *  dbell_cnt:20 [19:0](R/W/H) Number of instruction queue 64-bit words to add
537  *	to the CPT instruction doorbell count. Readback value is the
538  *	current number of pending doorbell requests. If counter overflows
539  *	CPT()_VQ()_MISC_INT[DBELL_DOVF] is set. To reset the count back to
540  *	zero, write one to clear CPT()_VQ()_MISC_INT_ENA_W1C[DBELL_DOVF],
541  *	then write a value of 2^20 minus the read [DBELL_CNT], then write one
542  *	to CPT()_VQ()_MISC_INT_W1C[DBELL_DOVF] and
543  *	CPT()_VQ()_MISC_INT_ENA_W1S[DBELL_DOVF]. Must be a multiple of 8.
544  *	All CPT instructions are 8 words and require a doorbell count of
545  *	multiple of 8.
546  */
547 union otx_cptx_vqx_doorbell {
548 	u64 u;
549 	struct otx_cptx_vqx_doorbell_s {
550 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
551 		u64 reserved_20_63:44;
552 		u64 dbell_cnt:20;
553 #else /* Word 0 - Little Endian */
554 		u64 dbell_cnt:20;
555 		u64 reserved_20_63:44;
556 #endif /* Word 0 - End */
557 	} s;
558 };
559 
560 /*
561  * Register (NCB) otx_cpt#_vq#_inprog
562  *
563  * CPT Queue In Progress Count Registers
564  * These registers contain the per-queue instruction in flight registers.
565  * otx_cptx_vqx_inprog_s
566  * Word0
567  *  reserved_8_63:56 [63:8] Reserved.
568  *  inflight:8 [7:0](RO/H) Inflight count. Counts the number of instructions
569  *	for the VF for which CPT is fetching, executing or responding to
570  *	instructions. However this does not include any interrupts that are
571  *	awaiting software handling (CPT()_VQ()_DONE[DONE] != 0x0).
572  *	A queue may not be reconfigured until:
573  *	1. CPT()_VQ()_CTL[ENA] is cleared by software.
574  *	2. [INFLIGHT] is polled until equals to zero.
575  */
576 union otx_cptx_vqx_inprog {
577 	u64 u;
578 	struct otx_cptx_vqx_inprog_s {
579 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
580 		u64 reserved_8_63:56;
581 		u64 inflight:8;
582 #else /* Word 0 - Little Endian */
583 		u64 inflight:8;
584 		u64 reserved_8_63:56;
585 #endif /* Word 0 - End */
586 	} s;
587 };
588 
589 /*
590  * Register (NCB) otx_cpt#_vq#_misc_int
591  *
592  * CPT Queue Misc Interrupt Register
593  * These registers contain the per-queue miscellaneous interrupts.
594  * otx_cptx_vqx_misc_int_s
595  * Word 0
596  *  reserved_5_63:59 [63:5] Reserved.
597  *  swerr:1 [4:4](R/W1C/H) Software error from engines.
598  *  nwrp:1  [3:3](R/W1C/H) NCB result write response error.
599  *  irde:1  [2:2](R/W1C/H) Instruction NCB read response error.
600  *  dovf:1 [1:1](R/W1C/H) Doorbell overflow.
601  *  mbox:1 [0:0](R/W1C/H) PF to VF mailbox interrupt. Set when
602  *	CPT()_VF()_PF_MBOX(0) is written.
603  *
604  */
605 union otx_cptx_vqx_misc_int {
606 	u64 u;
607 	struct otx_cptx_vqx_misc_int_s {
608 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
609 		u64 reserved_5_63:59;
610 		u64 swerr:1;
611 		u64 nwrp:1;
612 		u64 irde:1;
613 		u64 dovf:1;
614 		u64 mbox:1;
615 #else /* Word 0 - Little Endian */
616 		u64 mbox:1;
617 		u64 dovf:1;
618 		u64 irde:1;
619 		u64 nwrp:1;
620 		u64 swerr:1;
621 		u64 reserved_5_63:59;
622 #endif /* Word 0 - End */
623 	} s;
624 };
625 
626 /*
627  * Register (NCB) otx_cpt#_vq#_done_ack
628  *
629  * CPT Queue Done Count Ack Registers
630  * This register is written by software to acknowledge interrupts.
631  * otx_cptx_vqx_done_ack_s
632  * Word0
633  *  reserved_20_63:44 [63:20] Reserved.
634  *  done_ack:20 [19:0](R/W/H) Number of decrements to CPT()_VQ()_DONE[DONE].
635  *	Reads CPT()_VQ()_DONE[DONE]. Written by software to acknowledge
636  *	interrupts. If CPT()_VQ()_DONE[DONE] is still nonzero the interrupt
637  *	will be re-sent if the conditions described in CPT()_VQ()_DONE[DONE]
638  *	are satisfied.
639  *
640  */
641 union otx_cptx_vqx_done_ack {
642 	u64 u;
643 	struct otx_cptx_vqx_done_ack_s {
644 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
645 		u64 reserved_20_63:44;
646 		u64 done_ack:20;
647 #else /* Word 0 - Little Endian */
648 		u64 done_ack:20;
649 		u64 reserved_20_63:44;
650 #endif /* Word 0 - End */
651 	} s;
652 };
653 
654 /*
655  * Register (NCB) otx_cpt#_vq#_done
656  *
657  * CPT Queue Done Count Registers
658  * These registers contain the per-queue instruction done count.
659  * cptx_vqx_done_s
660  * Word0
661  *  reserved_20_63:44 [63:20] Reserved.
662  *  done:20 [19:0](R/W/H) Done count. When CPT_INST_S[DONEINT] set and that
663  *	instruction completes, CPT()_VQ()_DONE[DONE] is incremented when the
664  *	instruction finishes. Write to this field are for diagnostic use only;
665  *	instead software writes CPT()_VQ()_DONE_ACK with the number of
666  *	decrements for this field.
667  *	Interrupts are sent as follows:
668  *	* When CPT()_VQ()_DONE[DONE] = 0, then no results are pending, the
669  *	interrupt coalescing timer is held to zero, and an interrupt is not
670  *	sent.
671  *	* When CPT()_VQ()_DONE[DONE] != 0, then the interrupt coalescing timer
672  *	counts. If the counter is >= CPT()_VQ()_DONE_WAIT[TIME_WAIT]*1024, or
673  *	CPT()_VQ()_DONE[DONE] >= CPT()_VQ()_DONE_WAIT[NUM_WAIT], i.e. enough
674  *	time has passed or enough results have arrived, then the interrupt is
675  *	sent.
676  *	* When CPT()_VQ()_DONE_ACK is written (or CPT()_VQ()_DONE is written
677  *	but this is not typical), the interrupt coalescing timer restarts.
678  *	Note after decrementing this interrupt equation is recomputed,
679  *	for example if CPT()_VQ()_DONE[DONE] >= CPT()_VQ()_DONE_WAIT[NUM_WAIT]
680  *	and because the timer is zero, the interrupt will be resent immediately.
681  *	(This covers the race case between software acknowledging an interrupt
682  *	and a result returning.)
683  *	* When CPT()_VQ()_DONE_ENA_W1S[DONE] = 0, interrupts are not sent,
684  *	but the counting described above still occurs.
685  *	Since CPT instructions complete out-of-order, if software is using
686  *	completion interrupts the suggested scheme is to request a DONEINT on
687  *	each request, and when an interrupt arrives perform a "greedy" scan for
688  *	completions; even if a later command is acknowledged first this will
689  *	not result in missing a completion.
690  *	Software is responsible for making sure [DONE] does not overflow;
691  *	for example by insuring there are not more than 2^20-1 instructions in
692  *	flight that may request interrupts.
693  *
694  */
695 union otx_cptx_vqx_done {
696 	u64 u;
697 	struct otx_cptx_vqx_done_s {
698 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
699 		u64 reserved_20_63:44;
700 		u64 done:20;
701 #else /* Word 0 - Little Endian */
702 		u64 done:20;
703 		u64 reserved_20_63:44;
704 #endif /* Word 0 - End */
705 	} s;
706 };
707 
708 /*
709  * Register (NCB) otx_cpt#_vq#_done_wait
710  *
711  * CPT Queue Done Interrupt Coalescing Wait Registers
712  * Specifies the per queue interrupt coalescing settings.
713  * cptx_vqx_done_wait_s
714  * Word0
715  *  reserved_48_63:16 [63:48] Reserved.
716  *  time_wait:16; [47:32](R/W) Time hold-off. When CPT()_VQ()_DONE[DONE] = 0
717  *	or CPT()_VQ()_DONE_ACK is written a timer is cleared. When the timer
718  *	reaches [TIME_WAIT]*1024 then interrupt coalescing ends.
719  *	see CPT()_VQ()_DONE[DONE]. If 0x0, time coalescing is disabled.
720  *  reserved_20_31:12 [31:20] Reserved.
721  *  num_wait:20 [19:0](R/W) Number of messages hold-off.
722  *	When CPT()_VQ()_DONE[DONE] >= [NUM_WAIT] then interrupt coalescing ends
723  *	see CPT()_VQ()_DONE[DONE]. If 0x0, same behavior as 0x1.
724  *
725  */
726 union otx_cptx_vqx_done_wait {
727 	u64 u;
728 	struct otx_cptx_vqx_done_wait_s {
729 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
730 		u64 reserved_48_63:16;
731 		u64 time_wait:16;
732 		u64 reserved_20_31:12;
733 		u64 num_wait:20;
734 #else /* Word 0 - Little Endian */
735 		u64 num_wait:20;
736 		u64 reserved_20_31:12;
737 		u64 time_wait:16;
738 		u64 reserved_48_63:16;
739 #endif /* Word 0 - End */
740 	} s;
741 };
742 
743 /*
744  * Register (NCB) otx_cpt#_vq#_done_ena_w1s
745  *
746  * CPT Queue Done Interrupt Enable Set Registers
747  * Write 1 to these registers will enable the DONEINT interrupt for the queue.
748  * cptx_vqx_done_ena_w1s_s
749  * Word0
750  *  reserved_1_63:63 [63:1] Reserved.
751  *  done:1 [0:0](R/W1S/H) Write 1 will enable DONEINT for this queue.
752  *	Write 0 has no effect. Read will return the enable bit.
753  */
754 union otx_cptx_vqx_done_ena_w1s {
755 	u64 u;
756 	struct otx_cptx_vqx_done_ena_w1s_s {
757 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
758 		u64 reserved_1_63:63;
759 		u64 done:1;
760 #else /* Word 0 - Little Endian */
761 		u64 done:1;
762 		u64 reserved_1_63:63;
763 #endif /* Word 0 - End */
764 	} s;
765 };
766 
767 /*
768  * Register (NCB) otx_cpt#_vq#_ctl
769  *
770  * CPT VF Queue Control Registers
771  * This register configures queues. This register should be changed (other than
772  * clearing [ENA]) only when quiescent (see CPT()_VQ()_INPROG[INFLIGHT]).
773  * cptx_vqx_ctl_s
774  * Word0
775  *  reserved_1_63:63 [63:1] Reserved.
776  *  ena:1 [0:0](R/W/H) Enables the logical instruction queue.
777  *	See also CPT()_PF_Q()_CTL[CONT_ERR] and	CPT()_VQ()_INPROG[INFLIGHT].
778  *	1 = Queue is enabled.
779  *	0 = Queue is disabled.
780  */
781 union otx_cptx_vqx_ctl {
782 	u64 u;
783 	struct otx_cptx_vqx_ctl_s {
784 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
785 		u64 reserved_1_63:63;
786 		u64 ena:1;
787 #else /* Word 0 - Little Endian */
788 		u64 ena:1;
789 		u64 reserved_1_63:63;
790 #endif /* Word 0 - End */
791 	} s;
792 };
793 
794 /*
795  * Error Address/Error Codes
796  *
797  * In the event of a severe error, microcode writes an 8-byte Error Code
798  * value (ECODE) to host memory at the Rptr address specified by the host
799  * system (in the 64-byte request).
800  *
801  * Word0
802  *  [63:56](R) 8-bit completion code
803  *  [55:48](R) Number of the core that reported the severe error
804  *  [47:0] Lower 6 bytes of M-Inst word2. Used to assist in uniquely
805  *  identifying which specific instruction caused the error. This assumes
806  *  that each instruction has a unique result location (RPTR), at least
807  *  for a given period of time.
808  */
809 union otx_cpt_error_code {
810 	u64 u;
811 	struct otx_cpt_error_code_s {
812 #if defined(__BIG_ENDIAN_BITFIELD) /* Word 0 - Big Endian */
813 		uint64_t ccode:8;
814 		uint64_t coreid:8;
815 		uint64_t rptr6:48;
816 #else /* Word 0 - Little Endian */
817 		uint64_t rptr6:48;
818 		uint64_t coreid:8;
819 		uint64_t ccode:8;
820 #endif /* Word 0 - End */
821 	} s;
822 };
823 
824 #endif /*__OTX_CPT_HW_TYPES_H */
825