1 /* 2 * Copyright 2012-15 Advanced Micro Devices, Inc. 3 * 4 * Permission is hereby granted, free of charge, to any person obtaining a 5 * copy of this software and associated documentation files (the "Software"), 6 * to deal in the Software without restriction, including without limitation 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 8 * and/or sell copies of the Software, and to permit persons to whom the 9 * Software is furnished to do so, subject to the following conditions: 10 * 11 * The above copyright notice and this permission notice shall be included in 12 * all copies or substantial portions of the Software. 13 * 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 20 * OTHER DEALINGS IN THE SOFTWARE. 21 * 22 * Authors: AMD 23 * 24 */ 25 26 #ifndef __DC_TIMING_GENERATOR_DCN10_H__ 27 #define __DC_TIMING_GENERATOR_DCN10_H__ 28 29 #include "timing_generator.h" 30 31 #define DCN10TG_FROM_TG(tg)\ 32 container_of(tg, struct optc, base) 33 34 #define TG_COMMON_REG_LIST_DCN(inst) \ 35 SRI(OTG_VSTARTUP_PARAM, OTG, inst),\ 36 SRI(OTG_VUPDATE_PARAM, OTG, inst),\ 37 SRI(OTG_VREADY_PARAM, OTG, inst),\ 38 SRI(OTG_BLANK_CONTROL, OTG, inst),\ 39 SRI(OTG_MASTER_UPDATE_LOCK, OTG, inst),\ 40 SRI(OTG_GLOBAL_CONTROL0, OTG, inst),\ 41 SRI(OTG_DOUBLE_BUFFER_CONTROL, OTG, inst),\ 42 SRI(OTG_H_TOTAL, OTG, inst),\ 43 SRI(OTG_H_BLANK_START_END, OTG, inst),\ 44 SRI(OTG_H_SYNC_A, OTG, inst),\ 45 SRI(OTG_H_SYNC_A_CNTL, OTG, inst),\ 46 SRI(OTG_H_TIMING_CNTL, OTG, inst),\ 47 SRI(OTG_V_TOTAL, OTG, inst),\ 48 SRI(OTG_V_BLANK_START_END, OTG, inst),\ 49 SRI(OTG_V_SYNC_A, OTG, inst),\ 50 SRI(OTG_V_SYNC_A_CNTL, OTG, inst),\ 51 SRI(OTG_INTERLACE_CONTROL, OTG, inst),\ 52 SRI(OTG_CONTROL, OTG, inst),\ 53 SRI(OTG_STEREO_CONTROL, OTG, inst),\ 54 SRI(OTG_3D_STRUCTURE_CONTROL, OTG, inst),\ 55 SRI(OTG_STEREO_STATUS, OTG, inst),\ 56 SRI(OTG_V_TOTAL_MAX, OTG, inst),\ 57 SRI(OTG_V_TOTAL_MID, OTG, inst),\ 58 SRI(OTG_V_TOTAL_MIN, OTG, inst),\ 59 SRI(OTG_V_TOTAL_CONTROL, OTG, inst),\ 60 SRI(OTG_TRIGA_CNTL, OTG, inst),\ 61 SRI(OTG_FORCE_COUNT_NOW_CNTL, OTG, inst),\ 62 SRI(OTG_STATIC_SCREEN_CONTROL, OTG, inst),\ 63 SRI(OTG_STATUS_FRAME_COUNT, OTG, inst),\ 64 SRI(OTG_STATUS, OTG, inst),\ 65 SRI(OTG_STATUS_POSITION, OTG, inst),\ 66 SRI(OTG_NOM_VERT_POSITION, OTG, inst),\ 67 SRI(OTG_BLACK_COLOR, OTG, inst),\ 68 SRI(OTG_CLOCK_CONTROL, OTG, inst),\ 69 SRI(OTG_VERTICAL_INTERRUPT0_CONTROL, OTG, inst),\ 70 SRI(OTG_VERTICAL_INTERRUPT0_POSITION, OTG, inst),\ 71 SRI(OTG_VERTICAL_INTERRUPT1_CONTROL, OTG, inst),\ 72 SRI(OTG_VERTICAL_INTERRUPT1_POSITION, OTG, inst),\ 73 SRI(OTG_VERTICAL_INTERRUPT2_CONTROL, OTG, inst),\ 74 SRI(OTG_VERTICAL_INTERRUPT2_POSITION, OTG, inst),\ 75 SRI(OPTC_INPUT_CLOCK_CONTROL, ODM, inst),\ 76 SRI(OPTC_DATA_SOURCE_SELECT, ODM, inst),\ 77 SRI(OPTC_INPUT_GLOBAL_CONTROL, ODM, inst),\ 78 SRI(CONTROL, VTG, inst),\ 79 SRI(OTG_VERT_SYNC_CONTROL, OTG, inst),\ 80 SRI(OTG_MASTER_UPDATE_MODE, OTG, inst),\ 81 SRI(OTG_GSL_CONTROL, OTG, inst),\ 82 SRI(OTG_CRC_CNTL, OTG, inst),\ 83 SRI(OTG_CRC0_DATA_RG, OTG, inst),\ 84 SRI(OTG_CRC0_DATA_B, OTG, inst),\ 85 SRI(OTG_CRC0_WINDOWA_X_CONTROL, OTG, inst),\ 86 SRI(OTG_CRC0_WINDOWA_Y_CONTROL, OTG, inst),\ 87 SRI(OTG_CRC0_WINDOWB_X_CONTROL, OTG, inst),\ 88 SRI(OTG_CRC0_WINDOWB_Y_CONTROL, OTG, inst),\ 89 SR(GSL_SOURCE_SELECT),\ 90 SRI(OTG_GLOBAL_CONTROL2, OTG, inst),\ 91 SRI(OTG_TRIGA_MANUAL_TRIG, OTG, inst) 92 93 #define TG_COMMON_REG_LIST_DCN1_0(inst) \ 94 TG_COMMON_REG_LIST_DCN(inst),\ 95 SRI(OTG_TEST_PATTERN_PARAMETERS, OTG, inst),\ 96 SRI(OTG_TEST_PATTERN_CONTROL, OTG, inst),\ 97 SRI(OTG_TEST_PATTERN_COLOR, OTG, inst),\ 98 SRI(OTG_MANUAL_FLOW_CONTROL, OTG, inst) 99 100 101 struct dcn_optc_registers { 102 uint32_t OTG_GLOBAL_CONTROL1; 103 uint32_t OTG_GLOBAL_CONTROL2; 104 uint32_t OTG_VERT_SYNC_CONTROL; 105 uint32_t OTG_MASTER_UPDATE_MODE; 106 uint32_t OTG_GSL_CONTROL; 107 uint32_t OTG_VSTARTUP_PARAM; 108 uint32_t OTG_VUPDATE_PARAM; 109 uint32_t OTG_VREADY_PARAM; 110 uint32_t OTG_BLANK_CONTROL; 111 uint32_t OTG_MASTER_UPDATE_LOCK; 112 uint32_t OTG_GLOBAL_CONTROL0; 113 uint32_t OTG_DOUBLE_BUFFER_CONTROL; 114 uint32_t OTG_H_TOTAL; 115 uint32_t OTG_H_BLANK_START_END; 116 uint32_t OTG_H_SYNC_A; 117 uint32_t OTG_H_SYNC_A_CNTL; 118 uint32_t OTG_H_TIMING_CNTL; 119 uint32_t OTG_V_TOTAL; 120 uint32_t OTG_V_BLANK_START_END; 121 uint32_t OTG_V_SYNC_A; 122 uint32_t OTG_V_SYNC_A_CNTL; 123 uint32_t OTG_INTERLACE_CONTROL; 124 uint32_t OTG_CONTROL; 125 uint32_t OTG_STEREO_CONTROL; 126 uint32_t OTG_3D_STRUCTURE_CONTROL; 127 uint32_t OTG_STEREO_STATUS; 128 uint32_t OTG_V_TOTAL_MAX; 129 uint32_t OTG_V_TOTAL_MID; 130 uint32_t OTG_V_TOTAL_MIN; 131 uint32_t OTG_V_TOTAL_CONTROL; 132 uint32_t OTG_TRIGA_CNTL; 133 uint32_t OTG_TRIGA_MANUAL_TRIG; 134 uint32_t OTG_MANUAL_FLOW_CONTROL; 135 uint32_t OTG_FORCE_COUNT_NOW_CNTL; 136 uint32_t OTG_STATIC_SCREEN_CONTROL; 137 uint32_t OTG_STATUS_FRAME_COUNT; 138 uint32_t OTG_STATUS; 139 uint32_t OTG_STATUS_POSITION; 140 uint32_t OTG_NOM_VERT_POSITION; 141 uint32_t OTG_BLACK_COLOR; 142 uint32_t OTG_TEST_PATTERN_PARAMETERS; 143 uint32_t OTG_TEST_PATTERN_CONTROL; 144 uint32_t OTG_TEST_PATTERN_COLOR; 145 uint32_t OTG_CLOCK_CONTROL; 146 uint32_t OTG_VERTICAL_INTERRUPT0_CONTROL; 147 uint32_t OTG_VERTICAL_INTERRUPT0_POSITION; 148 uint32_t OTG_VERTICAL_INTERRUPT1_CONTROL; 149 uint32_t OTG_VERTICAL_INTERRUPT1_POSITION; 150 uint32_t OTG_VERTICAL_INTERRUPT2_CONTROL; 151 uint32_t OTG_VERTICAL_INTERRUPT2_POSITION; 152 uint32_t OPTC_INPUT_CLOCK_CONTROL; 153 uint32_t OPTC_DATA_SOURCE_SELECT; 154 uint32_t OPTC_MEMORY_CONFIG; 155 uint32_t OPTC_INPUT_GLOBAL_CONTROL; 156 uint32_t CONTROL; 157 uint32_t OTG_GSL_WINDOW_X; 158 uint32_t OTG_GSL_WINDOW_Y; 159 uint32_t OTG_VUPDATE_KEEPOUT; 160 uint32_t OTG_CRC_CNTL; 161 uint32_t OTG_CRC_CNTL2; 162 uint32_t OTG_CRC0_DATA_RG; 163 uint32_t OTG_CRC0_DATA_B; 164 uint32_t OTG_CRC1_DATA_B; 165 uint32_t OTG_CRC2_DATA_B; 166 uint32_t OTG_CRC3_DATA_B; 167 uint32_t OTG_CRC1_DATA_RG; 168 uint32_t OTG_CRC2_DATA_RG; 169 uint32_t OTG_CRC3_DATA_RG; 170 uint32_t OTG_CRC0_WINDOWA_X_CONTROL; 171 uint32_t OTG_CRC0_WINDOWA_Y_CONTROL; 172 uint32_t OTG_CRC0_WINDOWB_X_CONTROL; 173 uint32_t OTG_CRC0_WINDOWB_Y_CONTROL; 174 uint32_t OTG_CRC1_WINDOWA_X_CONTROL; 175 uint32_t OTG_CRC1_WINDOWA_Y_CONTROL; 176 uint32_t OTG_CRC1_WINDOWB_X_CONTROL; 177 uint32_t OTG_CRC1_WINDOWB_Y_CONTROL; 178 uint32_t GSL_SOURCE_SELECT; 179 uint32_t DWB_SOURCE_SELECT; 180 uint32_t OTG_DSC_START_POSITION; 181 uint32_t OPTC_DATA_FORMAT_CONTROL; 182 uint32_t OPTC_BYTES_PER_PIXEL; 183 uint32_t OPTC_WIDTH_CONTROL; 184 uint32_t OTG_DRR_CONTROL; 185 uint32_t OTG_BLANK_DATA_COLOR; 186 uint32_t OTG_BLANK_DATA_COLOR_EXT; 187 uint32_t OTG_DRR_TRIGGER_WINDOW; 188 uint32_t OTG_M_CONST_DTO0; 189 uint32_t OTG_M_CONST_DTO1; 190 uint32_t OTG_DRR_V_TOTAL_CHANGE; 191 uint32_t OTG_GLOBAL_CONTROL4; 192 }; 193 194 #define TG_COMMON_MASK_SH_LIST_DCN(mask_sh)\ 195 SF(OTG0_OTG_VSTARTUP_PARAM, VSTARTUP_START, mask_sh),\ 196 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_OFFSET, mask_sh),\ 197 SF(OTG0_OTG_VUPDATE_PARAM, VUPDATE_WIDTH, mask_sh),\ 198 SF(OTG0_OTG_VREADY_PARAM, VREADY_OFFSET, mask_sh),\ 199 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DATA_EN, mask_sh),\ 200 SF(OTG0_OTG_BLANK_CONTROL, OTG_BLANK_DE_MODE, mask_sh),\ 201 SF(OTG0_OTG_BLANK_CONTROL, OTG_CURRENT_BLANK_STATE, mask_sh),\ 202 SF(OTG0_OTG_MASTER_UPDATE_LOCK, OTG_MASTER_UPDATE_LOCK, mask_sh),\ 203 SF(OTG0_OTG_MASTER_UPDATE_LOCK, UPDATE_LOCK_STATUS, mask_sh),\ 204 SF(OTG0_OTG_GLOBAL_CONTROL0, OTG_MASTER_UPDATE_LOCK_SEL, mask_sh),\ 205 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_UPDATE_PENDING, mask_sh),\ 206 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_BLANK_DATA_DOUBLE_BUFFER_EN, mask_sh),\ 207 SF(OTG0_OTG_DOUBLE_BUFFER_CONTROL, OTG_RANGE_TIMING_DBUF_UPDATE_MODE, mask_sh),\ 208 SF(OTG0_OTG_VUPDATE_KEEPOUT, OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN, mask_sh), \ 209 SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET, mask_sh), \ 210 SF(OTG0_OTG_VUPDATE_KEEPOUT, MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET, mask_sh), \ 211 SF(OTG0_OTG_H_TOTAL, OTG_H_TOTAL, mask_sh),\ 212 SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_START, mask_sh),\ 213 SF(OTG0_OTG_H_BLANK_START_END, OTG_H_BLANK_END, mask_sh),\ 214 SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_START, mask_sh),\ 215 SF(OTG0_OTG_H_SYNC_A, OTG_H_SYNC_A_END, mask_sh),\ 216 SF(OTG0_OTG_H_SYNC_A_CNTL, OTG_H_SYNC_A_POL, mask_sh),\ 217 SF(OTG0_OTG_H_TIMING_CNTL, OTG_H_TIMING_DIV_BY2, mask_sh),\ 218 SF(OTG0_OTG_V_TOTAL, OTG_V_TOTAL, mask_sh),\ 219 SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_START, mask_sh),\ 220 SF(OTG0_OTG_V_BLANK_START_END, OTG_V_BLANK_END, mask_sh),\ 221 SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_START, mask_sh),\ 222 SF(OTG0_OTG_V_SYNC_A, OTG_V_SYNC_A_END, mask_sh),\ 223 SF(OTG0_OTG_V_SYNC_A_CNTL, OTG_V_SYNC_A_POL, mask_sh),\ 224 SF(OTG0_OTG_INTERLACE_CONTROL, OTG_INTERLACE_ENABLE, mask_sh),\ 225 SF(OTG0_OTG_CONTROL, OTG_MASTER_EN, mask_sh),\ 226 SF(OTG0_OTG_CONTROL, OTG_START_POINT_CNTL, mask_sh),\ 227 SF(OTG0_OTG_CONTROL, OTG_DISABLE_POINT_CNTL, mask_sh),\ 228 SF(OTG0_OTG_CONTROL, OTG_FIELD_NUMBER_CNTL, mask_sh),\ 229 SF(OTG0_OTG_CONTROL, OTG_CURRENT_MASTER_EN_STATE, mask_sh),\ 230 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EN, mask_sh),\ 231 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_LINE_NUM, mask_sh),\ 232 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_SYNC_OUTPUT_POLARITY, mask_sh),\ 233 SF(OTG0_OTG_STEREO_CONTROL, OTG_STEREO_EYE_FLAG_POLARITY, mask_sh),\ 234 SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ 235 SF(OTG0_OTG_STEREO_CONTROL, OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP, mask_sh),\ 236 SF(OTG0_OTG_STEREO_STATUS, OTG_STEREO_CURRENT_EYE, mask_sh),\ 237 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_EN, mask_sh),\ 238 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_V_UPDATE_MODE, mask_sh),\ 239 SF(OTG0_OTG_3D_STRUCTURE_CONTROL, OTG_3D_STRUCTURE_STEREO_SEL_OVR, mask_sh),\ 240 SF(OTG0_OTG_V_TOTAL_MAX, OTG_V_TOTAL_MAX, mask_sh),\ 241 SF(OTG0_OTG_V_TOTAL_MID, OTG_V_TOTAL_MID, mask_sh),\ 242 SF(OTG0_OTG_V_TOTAL_MIN, OTG_V_TOTAL_MIN, mask_sh),\ 243 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MIN_SEL, mask_sh),\ 244 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_V_TOTAL_MAX_SEL, mask_sh),\ 245 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_FORCE_LOCK_ON_EVENT, mask_sh),\ 246 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK_EN, mask_sh),\ 247 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_SET_V_TOTAL_MIN_MASK, mask_sh),\ 248 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_REPLACING_MAX_EN, mask_sh),\ 249 SF(OTG0_OTG_V_TOTAL_CONTROL, OTG_VTOTAL_MID_FRAME_NUM, mask_sh),\ 250 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_CLEAR, mask_sh),\ 251 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_MODE, mask_sh),\ 252 SF(OTG0_OTG_FORCE_COUNT_NOW_CNTL, OTG_FORCE_COUNT_NOW_OCCURRED, mask_sh),\ 253 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_SELECT, mask_sh),\ 254 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_SOURCE_PIPE_SELECT, mask_sh),\ 255 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_RISING_EDGE_DETECT_CNTL, mask_sh),\ 256 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FALLING_EDGE_DETECT_CNTL, mask_sh),\ 257 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_POLARITY_SELECT, mask_sh),\ 258 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_FREQUENCY_SELECT, mask_sh),\ 259 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_DELAY, mask_sh),\ 260 SF(OTG0_OTG_TRIGA_CNTL, OTG_TRIGA_CLEAR, mask_sh),\ 261 SF(OTG0_OTG_TRIGA_MANUAL_TRIG, OTG_TRIGA_MANUAL_TRIG, mask_sh),\ 262 SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_EVENT_MASK, mask_sh),\ 263 SF(OTG0_OTG_STATIC_SCREEN_CONTROL, OTG_STATIC_SCREEN_FRAME_COUNT, mask_sh),\ 264 SF(OTG0_OTG_STATUS_FRAME_COUNT, OTG_FRAME_COUNT, mask_sh),\ 265 SF(OTG0_OTG_STATUS, OTG_V_BLANK, mask_sh),\ 266 SF(OTG0_OTG_STATUS, OTG_V_ACTIVE_DISP, mask_sh),\ 267 SF(OTG0_OTG_STATUS_POSITION, OTG_HORZ_COUNT, mask_sh),\ 268 SF(OTG0_OTG_STATUS_POSITION, OTG_VERT_COUNT, mask_sh),\ 269 SF(OTG0_OTG_NOM_VERT_POSITION, OTG_VERT_COUNT_NOM, mask_sh),\ 270 SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_B_CB, mask_sh),\ 271 SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_G_Y, mask_sh),\ 272 SF(OTG0_OTG_BLACK_COLOR, OTG_BLACK_COLOR_R_CR, mask_sh),\ 273 SF(OTG0_OTG_CLOCK_CONTROL, OTG_BUSY, mask_sh),\ 274 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_EN, mask_sh),\ 275 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_ON, mask_sh),\ 276 SF(OTG0_OTG_CLOCK_CONTROL, OTG_CLOCK_GATE_DIS, mask_sh),\ 277 SF(OTG0_OTG_VERTICAL_INTERRUPT0_CONTROL, OTG_VERTICAL_INTERRUPT0_INT_ENABLE, mask_sh),\ 278 SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_START, mask_sh),\ 279 SF(OTG0_OTG_VERTICAL_INTERRUPT0_POSITION, OTG_VERTICAL_INTERRUPT0_LINE_END, mask_sh),\ 280 SF(OTG0_OTG_VERTICAL_INTERRUPT1_CONTROL, OTG_VERTICAL_INTERRUPT1_INT_ENABLE, mask_sh),\ 281 SF(OTG0_OTG_VERTICAL_INTERRUPT1_POSITION, OTG_VERTICAL_INTERRUPT1_LINE_START, mask_sh),\ 282 SF(OTG0_OTG_VERTICAL_INTERRUPT2_CONTROL, OTG_VERTICAL_INTERRUPT2_INT_ENABLE, mask_sh),\ 283 SF(OTG0_OTG_VERTICAL_INTERRUPT2_POSITION, OTG_VERTICAL_INTERRUPT2_LINE_START, mask_sh),\ 284 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_EN, mask_sh),\ 285 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_ON, mask_sh),\ 286 SF(ODM0_OPTC_INPUT_CLOCK_CONTROL, OPTC_INPUT_CLK_GATE_DIS, mask_sh),\ 287 SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_OCCURRED_STATUS, mask_sh),\ 288 SF(ODM0_OPTC_INPUT_GLOBAL_CONTROL, OPTC_UNDERFLOW_CLEAR, mask_sh),\ 289 SF(VTG0_CONTROL, VTG0_ENABLE, mask_sh),\ 290 SF(VTG0_CONTROL, VTG0_FP2, mask_sh),\ 291 SF(VTG0_CONTROL, VTG0_VCOUNT_INIT, mask_sh),\ 292 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED, mask_sh),\ 293 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_FORCE_VSYNC_NEXT_LINE_CLEAR, mask_sh),\ 294 SF(OTG0_OTG_VERT_SYNC_CONTROL, OTG_AUTO_FORCE_VSYNC_MODE, mask_sh),\ 295 SF(OTG0_OTG_MASTER_UPDATE_MODE, MASTER_UPDATE_INTERLACED_MODE, mask_sh),\ 296 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL0_EN, mask_sh),\ 297 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL1_EN, mask_sh),\ 298 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL2_EN, mask_sh),\ 299 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_MASTER_EN, mask_sh),\ 300 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_FORCE_DELAY, mask_sh),\ 301 SF(OTG0_OTG_GSL_CONTROL, OTG_GSL_CHECK_ALL_FIELDS, mask_sh),\ 302 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_CONT_EN, mask_sh),\ 303 SF(OTG0_OTG_CRC_CNTL, OTG_CRC0_SELECT, mask_sh),\ 304 SF(OTG0_OTG_CRC_CNTL, OTG_CRC_EN, mask_sh),\ 305 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_R_CR, mask_sh),\ 306 SF(OTG0_OTG_CRC0_DATA_RG, CRC0_G_Y, mask_sh),\ 307 SF(OTG0_OTG_CRC0_DATA_B, CRC0_B_CB, mask_sh),\ 308 SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_START, mask_sh),\ 309 SF(OTG0_OTG_CRC0_WINDOWA_X_CONTROL, OTG_CRC0_WINDOWA_X_END, mask_sh),\ 310 SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_START, mask_sh),\ 311 SF(OTG0_OTG_CRC0_WINDOWA_Y_CONTROL, OTG_CRC0_WINDOWA_Y_END, mask_sh),\ 312 SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_START, mask_sh),\ 313 SF(OTG0_OTG_CRC0_WINDOWB_X_CONTROL, OTG_CRC0_WINDOWB_X_END, mask_sh),\ 314 SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_START, mask_sh),\ 315 SF(OTG0_OTG_CRC0_WINDOWB_Y_CONTROL, OTG_CRC0_WINDOWB_Y_END, mask_sh),\ 316 SF(GSL_SOURCE_SELECT, GSL0_READY_SOURCE_SEL, mask_sh),\ 317 SF(GSL_SOURCE_SELECT, GSL1_READY_SOURCE_SEL, mask_sh),\ 318 SF(GSL_SOURCE_SELECT, GSL2_READY_SOURCE_SEL, mask_sh),\ 319 SF(OTG0_OTG_GLOBAL_CONTROL2, MANUAL_FLOW_CONTROL_SEL, mask_sh) 320 321 322 323 #define TG_COMMON_MASK_SH_LIST_DCN1_0(mask_sh)\ 324 TG_COMMON_MASK_SH_LIST_DCN(mask_sh),\ 325 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC0, mask_sh),\ 326 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_INC1, mask_sh),\ 327 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_VRES, mask_sh),\ 328 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_HRES, mask_sh),\ 329 SF(OTG0_OTG_TEST_PATTERN_PARAMETERS, OTG_TEST_PATTERN_RAMP0_OFFSET, mask_sh),\ 330 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_EN, mask_sh),\ 331 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_MODE, mask_sh),\ 332 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_DYNAMIC_RANGE, mask_sh),\ 333 SF(OTG0_OTG_TEST_PATTERN_CONTROL, OTG_TEST_PATTERN_COLOR_FORMAT, mask_sh),\ 334 SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_MASK, mask_sh),\ 335 SF(OTG0_OTG_TEST_PATTERN_COLOR, OTG_TEST_PATTERN_DATA, mask_sh),\ 336 SF(ODM0_OPTC_DATA_SOURCE_SELECT, OPTC_SRC_SEL, mask_sh),\ 337 SF(OTG0_OTG_MANUAL_FLOW_CONTROL, MANUAL_FLOW_CONTROL, mask_sh),\ 338 339 #define TG_REG_FIELD_LIST_DCN1_0(type) \ 340 type VSTARTUP_START;\ 341 type VUPDATE_OFFSET;\ 342 type VUPDATE_WIDTH;\ 343 type VREADY_OFFSET;\ 344 type OTG_BLANK_DATA_EN;\ 345 type OTG_BLANK_DE_MODE;\ 346 type OTG_CURRENT_BLANK_STATE;\ 347 type OTG_MASTER_UPDATE_LOCK;\ 348 type UPDATE_LOCK_STATUS;\ 349 type OTG_UPDATE_PENDING;\ 350 type OTG_MASTER_UPDATE_LOCK_SEL;\ 351 type OTG_BLANK_DATA_DOUBLE_BUFFER_EN;\ 352 type OTG_H_TOTAL;\ 353 type OTG_H_BLANK_START;\ 354 type OTG_H_BLANK_END;\ 355 type OTG_H_SYNC_A_START;\ 356 type OTG_H_SYNC_A_END;\ 357 type OTG_H_SYNC_A_POL;\ 358 type OTG_H_TIMING_DIV_BY2;\ 359 type OTG_V_TOTAL;\ 360 type OTG_V_BLANK_START;\ 361 type OTG_V_BLANK_END;\ 362 type OTG_V_SYNC_A_START;\ 363 type OTG_V_SYNC_A_END;\ 364 type OTG_V_SYNC_A_POL;\ 365 type OTG_INTERLACE_ENABLE;\ 366 type OTG_MASTER_EN;\ 367 type OTG_START_POINT_CNTL;\ 368 type OTG_DISABLE_POINT_CNTL;\ 369 type OTG_FIELD_NUMBER_CNTL;\ 370 type OTG_CURRENT_MASTER_EN_STATE;\ 371 type OTG_STEREO_EN;\ 372 type OTG_STEREO_SYNC_OUTPUT_LINE_NUM;\ 373 type OTG_STEREO_SYNC_OUTPUT_POLARITY;\ 374 type OTG_STEREO_EYE_FLAG_POLARITY;\ 375 type OTG_STEREO_CURRENT_EYE;\ 376 type OTG_DISABLE_STEREOSYNC_OUTPUT_FOR_DP;\ 377 type OTG_3D_STRUCTURE_EN;\ 378 type OTG_3D_STRUCTURE_V_UPDATE_MODE;\ 379 type OTG_3D_STRUCTURE_STEREO_SEL_OVR;\ 380 type OTG_V_TOTAL_MAX;\ 381 type OTG_V_TOTAL_MID;\ 382 type OTG_V_TOTAL_MIN;\ 383 type OTG_V_TOTAL_MIN_SEL;\ 384 type OTG_V_TOTAL_MAX_SEL;\ 385 type OTG_VTOTAL_MID_REPLACING_MAX_EN;\ 386 type OTG_VTOTAL_MID_FRAME_NUM;\ 387 type OTG_FORCE_LOCK_ON_EVENT;\ 388 type OTG_SET_V_TOTAL_MIN_MASK_EN;\ 389 type OTG_SET_V_TOTAL_MIN_MASK;\ 390 type OTG_FORCE_COUNT_NOW_CLEAR;\ 391 type OTG_FORCE_COUNT_NOW_MODE;\ 392 type OTG_FORCE_COUNT_NOW_OCCURRED;\ 393 type OTG_TRIGA_SOURCE_SELECT;\ 394 type OTG_TRIGA_SOURCE_PIPE_SELECT;\ 395 type OTG_TRIGA_RISING_EDGE_DETECT_CNTL;\ 396 type OTG_TRIGA_FALLING_EDGE_DETECT_CNTL;\ 397 type OTG_TRIGA_POLARITY_SELECT;\ 398 type OTG_TRIGA_FREQUENCY_SELECT;\ 399 type OTG_TRIGA_DELAY;\ 400 type OTG_TRIGA_CLEAR;\ 401 type OTG_TRIGA_MANUAL_TRIG;\ 402 type OTG_STATIC_SCREEN_EVENT_MASK;\ 403 type OTG_STATIC_SCREEN_FRAME_COUNT;\ 404 type OTG_FRAME_COUNT;\ 405 type OTG_V_BLANK;\ 406 type OTG_V_ACTIVE_DISP;\ 407 type OTG_HORZ_COUNT;\ 408 type OTG_VERT_COUNT;\ 409 type OTG_VERT_COUNT_NOM;\ 410 type OTG_BLACK_COLOR_B_CB;\ 411 type OTG_BLACK_COLOR_G_Y;\ 412 type OTG_BLACK_COLOR_R_CR;\ 413 type OTG_BLANK_DATA_COLOR_BLUE_CB;\ 414 type OTG_BLANK_DATA_COLOR_GREEN_Y;\ 415 type OTG_BLANK_DATA_COLOR_RED_CR;\ 416 type OTG_BLANK_DATA_COLOR_BLUE_CB_EXT;\ 417 type OTG_BLANK_DATA_COLOR_GREEN_Y_EXT;\ 418 type OTG_BLANK_DATA_COLOR_RED_CR_EXT;\ 419 type OTG_VTOTAL_MID_REPLACING_MIN_EN;\ 420 type OTG_TEST_PATTERN_INC0;\ 421 type OTG_TEST_PATTERN_INC1;\ 422 type OTG_TEST_PATTERN_VRES;\ 423 type OTG_TEST_PATTERN_HRES;\ 424 type OTG_TEST_PATTERN_RAMP0_OFFSET;\ 425 type OTG_TEST_PATTERN_EN;\ 426 type OTG_TEST_PATTERN_MODE;\ 427 type OTG_TEST_PATTERN_DYNAMIC_RANGE;\ 428 type OTG_TEST_PATTERN_COLOR_FORMAT;\ 429 type OTG_TEST_PATTERN_MASK;\ 430 type OTG_TEST_PATTERN_DATA;\ 431 type OTG_BUSY;\ 432 type OTG_CLOCK_EN;\ 433 type OTG_CLOCK_ON;\ 434 type OTG_CLOCK_GATE_DIS;\ 435 type OTG_VERTICAL_INTERRUPT0_INT_ENABLE;\ 436 type OTG_VERTICAL_INTERRUPT0_LINE_START;\ 437 type OTG_VERTICAL_INTERRUPT0_LINE_END;\ 438 type OTG_VERTICAL_INTERRUPT1_INT_ENABLE;\ 439 type OTG_VERTICAL_INTERRUPT1_LINE_START;\ 440 type OTG_VERTICAL_INTERRUPT2_INT_ENABLE;\ 441 type OTG_VERTICAL_INTERRUPT2_LINE_START;\ 442 type OPTC_INPUT_CLK_EN;\ 443 type OPTC_INPUT_CLK_ON;\ 444 type OPTC_INPUT_CLK_GATE_DIS;\ 445 type OPTC_UNDERFLOW_OCCURRED_STATUS;\ 446 type OPTC_UNDERFLOW_CLEAR;\ 447 type OPTC_SRC_SEL;\ 448 type VTG0_ENABLE;\ 449 type VTG0_FP2;\ 450 type VTG0_VCOUNT_INIT;\ 451 type OTG_FORCE_VSYNC_NEXT_LINE_OCCURRED;\ 452 type OTG_FORCE_VSYNC_NEXT_LINE_CLEAR;\ 453 type OTG_AUTO_FORCE_VSYNC_MODE;\ 454 type MASTER_UPDATE_INTERLACED_MODE;\ 455 type OTG_GSL0_EN;\ 456 type OTG_GSL1_EN;\ 457 type OTG_GSL2_EN;\ 458 type OTG_GSL_MASTER_EN;\ 459 type OTG_GSL_FORCE_DELAY;\ 460 type OTG_GSL_CHECK_ALL_FIELDS;\ 461 type OTG_GSL_WINDOW_START_X;\ 462 type OTG_GSL_WINDOW_END_X;\ 463 type OTG_GSL_WINDOW_START_Y;\ 464 type OTG_GSL_WINDOW_END_Y;\ 465 type OTG_RANGE_TIMING_DBUF_UPDATE_MODE;\ 466 type OTG_GSL_MASTER_MODE;\ 467 type OTG_MASTER_UPDATE_LOCK_GSL_EN;\ 468 type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_START_OFFSET;\ 469 type MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_END_OFFSET;\ 470 type OTG_MASTER_UPDATE_LOCK_VUPDATE_KEEPOUT_EN;\ 471 type OTG_CRC_CONT_EN;\ 472 type OTG_CRC0_SELECT;\ 473 type OTG_CRC_EN;\ 474 type CRC0_R_CR;\ 475 type CRC0_G_Y;\ 476 type CRC0_B_CB;\ 477 type CRC1_R_CR;\ 478 type CRC1_G_Y;\ 479 type CRC1_B_CB;\ 480 type CRC2_R_CR;\ 481 type CRC2_G_Y;\ 482 type CRC2_B_CB;\ 483 type CRC3_R_CR;\ 484 type CRC3_G_Y;\ 485 type CRC3_B_CB;\ 486 type OTG_CRC0_WINDOWA_X_START;\ 487 type OTG_CRC0_WINDOWA_X_END;\ 488 type OTG_CRC0_WINDOWA_Y_START;\ 489 type OTG_CRC0_WINDOWA_Y_END;\ 490 type OTG_CRC0_WINDOWB_X_START;\ 491 type OTG_CRC0_WINDOWB_X_END;\ 492 type OTG_CRC0_WINDOWB_Y_START;\ 493 type OTG_CRC0_WINDOWB_Y_END;\ 494 type OTG_CRC_WINDOW_DB_EN;\ 495 type OTG_CRC1_WINDOWA_X_START;\ 496 type OTG_CRC1_WINDOWA_X_END;\ 497 type OTG_CRC1_WINDOWA_Y_START;\ 498 type OTG_CRC1_WINDOWA_Y_END;\ 499 type OTG_CRC1_WINDOWB_X_START;\ 500 type OTG_CRC1_WINDOWB_X_END;\ 501 type OTG_CRC1_WINDOWB_Y_START;\ 502 type OTG_CRC1_WINDOWB_Y_END;\ 503 type GSL0_READY_SOURCE_SEL;\ 504 type GSL1_READY_SOURCE_SEL;\ 505 type GSL2_READY_SOURCE_SEL;\ 506 type MANUAL_FLOW_CONTROL;\ 507 type MANUAL_FLOW_CONTROL_SEL; 508 509 #define TG_REG_FIELD_LIST(type) \ 510 TG_REG_FIELD_LIST_DCN1_0(type)\ 511 type OTG_V_SYNC_MODE;\ 512 type OTG_DRR_TRIGGER_WINDOW_START_X;\ 513 type OTG_DRR_TRIGGER_WINDOW_END_X;\ 514 type OTG_DRR_V_TOTAL_CHANGE_LIMIT;\ 515 type OTG_OUT_MUX;\ 516 type OTG_M_CONST_DTO_PHASE;\ 517 type OTG_M_CONST_DTO_MODULO;\ 518 type MASTER_UPDATE_LOCK_DB_X;\ 519 type MASTER_UPDATE_LOCK_DB_Y;\ 520 type MASTER_UPDATE_LOCK_DB_EN;\ 521 type GLOBAL_UPDATE_LOCK_EN;\ 522 type DIG_UPDATE_LOCATION;\ 523 type OTG_DSC_START_POSITION_X;\ 524 type OTG_DSC_START_POSITION_LINE_NUM;\ 525 type OPTC_NUM_OF_INPUT_SEGMENT;\ 526 type OPTC_SEG0_SRC_SEL;\ 527 type OPTC_SEG1_SRC_SEL;\ 528 type OPTC_SEG2_SRC_SEL;\ 529 type OPTC_SEG3_SRC_SEL;\ 530 type OPTC_MEM_SEL;\ 531 type OPTC_DATA_FORMAT;\ 532 type OPTC_DSC_MODE;\ 533 type OPTC_DSC_BYTES_PER_PIXEL;\ 534 type OPTC_DSC_SLICE_WIDTH;\ 535 type OPTC_SEGMENT_WIDTH;\ 536 type OPTC_DWB0_SOURCE_SELECT;\ 537 type OPTC_DWB1_SOURCE_SELECT;\ 538 type MASTER_UPDATE_LOCK_DB_START_X;\ 539 type MASTER_UPDATE_LOCK_DB_END_X;\ 540 type MASTER_UPDATE_LOCK_DB_START_Y;\ 541 type MASTER_UPDATE_LOCK_DB_END_Y;\ 542 type DIG_UPDATE_POSITION_X;\ 543 type DIG_UPDATE_POSITION_Y;\ 544 type OTG_H_TIMING_DIV_MODE;\ 545 type OTG_DRR_TIMING_DBUF_UPDATE_MODE;\ 546 type OTG_CRC_DSC_MODE;\ 547 type OTG_CRC_DATA_STREAM_COMBINE_MODE;\ 548 type OTG_CRC_DATA_STREAM_SPLIT_MODE;\ 549 type OTG_CRC_DATA_FORMAT;\ 550 type OTG_V_TOTAL_LAST_USED_BY_DRR;\ 551 type OTG_DRR_TIMING_DBUF_UPDATE_PENDING; 552 553 #define TG_REG_FIELD_LIST_DCN3_2(type) \ 554 type OTG_H_TIMING_DIV_MODE_MANUAL; 555 556 557 struct dcn_optc_shift { 558 TG_REG_FIELD_LIST(uint8_t) 559 TG_REG_FIELD_LIST_DCN3_2(uint8_t) 560 }; 561 562 struct dcn_optc_mask { 563 TG_REG_FIELD_LIST(uint32_t) 564 TG_REG_FIELD_LIST_DCN3_2(uint32_t) 565 }; 566 567 struct optc { 568 struct timing_generator base; 569 570 const struct dcn_optc_registers *tg_regs; 571 const struct dcn_optc_shift *tg_shift; 572 const struct dcn_optc_mask *tg_mask; 573 574 int opp_count; 575 576 uint32_t max_h_total; 577 uint32_t max_v_total; 578 579 uint32_t min_h_blank; 580 581 uint32_t min_h_sync_width; 582 uint32_t min_v_sync_width; 583 uint32_t min_v_blank; 584 uint32_t min_v_blank_interlace; 585 586 int vstartup_start; 587 int vupdate_offset; 588 int vupdate_width; 589 int vready_offset; 590 struct dc_crtc_timing orginal_patched_timing; 591 enum signal_type signal; 592 }; 593 594 void dcn10_timing_generator_init(struct optc *optc); 595 596 struct dcn_otg_state { 597 uint32_t v_blank_start; 598 uint32_t v_blank_end; 599 uint32_t v_sync_a_pol; 600 uint32_t v_total; 601 uint32_t v_total_max; 602 uint32_t v_total_min; 603 uint32_t v_total_min_sel; 604 uint32_t v_total_max_sel; 605 uint32_t v_sync_a_start; 606 uint32_t v_sync_a_end; 607 uint32_t h_blank_start; 608 uint32_t h_blank_end; 609 uint32_t h_sync_a_start; 610 uint32_t h_sync_a_end; 611 uint32_t h_sync_a_pol; 612 uint32_t h_total; 613 uint32_t underflow_occurred_status; 614 uint32_t otg_enabled; 615 uint32_t blank_enabled; 616 uint32_t vertical_interrupt1_en; 617 uint32_t vertical_interrupt1_line; 618 uint32_t vertical_interrupt2_en; 619 uint32_t vertical_interrupt2_line; 620 }; 621 622 void optc1_read_otg_state(struct optc *optc1, 623 struct dcn_otg_state *s); 624 625 bool optc1_get_hw_timing(struct timing_generator *tg, 626 struct dc_crtc_timing *hw_crtc_timing); 627 628 bool optc1_validate_timing( 629 struct timing_generator *optc, 630 const struct dc_crtc_timing *timing); 631 632 void optc1_program_timing( 633 struct timing_generator *optc, 634 const struct dc_crtc_timing *dc_crtc_timing, 635 int vready_offset, 636 int vstartup_start, 637 int vupdate_offset, 638 int vupdate_width, 639 const enum signal_type signal, 640 bool use_vbios); 641 642 void optc1_setup_vertical_interrupt0( 643 struct timing_generator *optc, 644 uint32_t start_line, 645 uint32_t end_line); 646 void optc1_setup_vertical_interrupt1( 647 struct timing_generator *optc, 648 uint32_t start_line); 649 void optc1_setup_vertical_interrupt2( 650 struct timing_generator *optc, 651 uint32_t start_line); 652 653 void optc1_program_global_sync( 654 struct timing_generator *optc, 655 int vready_offset, 656 int vstartup_start, 657 int vupdate_offset, 658 int vupdate_width); 659 660 bool optc1_disable_crtc(struct timing_generator *optc); 661 662 bool optc1_is_counter_moving(struct timing_generator *optc); 663 664 void optc1_get_position(struct timing_generator *optc, 665 struct crtc_position *position); 666 667 uint32_t optc1_get_vblank_counter(struct timing_generator *optc); 668 669 void optc1_get_crtc_scanoutpos( 670 struct timing_generator *optc, 671 uint32_t *v_blank_start, 672 uint32_t *v_blank_end, 673 uint32_t *h_position, 674 uint32_t *v_position); 675 676 void optc1_set_early_control( 677 struct timing_generator *optc, 678 uint32_t early_cntl); 679 680 void optc1_wait_for_state(struct timing_generator *optc, 681 enum crtc_state state); 682 683 void optc1_set_blank(struct timing_generator *optc, 684 bool enable_blanking); 685 686 bool optc1_is_blanked(struct timing_generator *optc); 687 688 void optc1_program_blank_color( 689 struct timing_generator *optc, 690 const struct tg_color *black_color); 691 692 bool optc1_did_triggered_reset_occur( 693 struct timing_generator *optc); 694 695 void optc1_enable_reset_trigger(struct timing_generator *optc, int source_tg_inst); 696 697 void optc1_disable_reset_trigger(struct timing_generator *optc); 698 699 void optc1_lock(struct timing_generator *optc); 700 701 void optc1_unlock(struct timing_generator *optc); 702 703 void optc1_enable_optc_clock(struct timing_generator *optc, bool enable); 704 705 void optc1_set_drr( 706 struct timing_generator *optc, 707 const struct drr_params *params); 708 709 void optc1_set_vtotal_min_max(struct timing_generator *optc, int vtotal_min, int vtotal_max); 710 711 void optc1_set_static_screen_control( 712 struct timing_generator *optc, 713 uint32_t event_triggers, 714 uint32_t num_frames); 715 716 void optc1_program_stereo(struct timing_generator *optc, 717 const struct dc_crtc_timing *timing, struct crtc_stereo_flags *flags); 718 719 bool optc1_is_stereo_left_eye(struct timing_generator *optc); 720 721 void optc1_clear_optc_underflow(struct timing_generator *optc); 722 723 void optc1_tg_init(struct timing_generator *optc); 724 725 bool optc1_is_tg_enabled(struct timing_generator *optc); 726 727 bool optc1_is_optc_underflow_occurred(struct timing_generator *optc); 728 729 void optc1_set_blank_data_double_buffer(struct timing_generator *optc, bool enable); 730 731 void optc1_set_timing_double_buffer(struct timing_generator *optc, bool enable); 732 733 bool optc1_get_otg_active_size(struct timing_generator *optc, 734 uint32_t *otg_active_width, 735 uint32_t *otg_active_height); 736 737 void optc1_enable_crtc_reset( 738 struct timing_generator *optc, 739 int source_tg_inst, 740 struct crtc_trigger_info *crtc_tp); 741 742 bool optc1_configure_crc(struct timing_generator *optc, 743 const struct crc_params *params); 744 745 bool optc1_get_crc(struct timing_generator *optc, 746 uint32_t *r_cr, uint32_t *g_y, uint32_t *b_cb); 747 748 bool optc1_is_two_pixels_per_containter(const struct dc_crtc_timing *timing); 749 750 void optc1_set_vtg_params(struct timing_generator *optc, 751 const struct dc_crtc_timing *dc_crtc_timing, bool program_fp2); 752 753 #endif /* __DC_TIMING_GENERATOR_DCN10_H__ */ 754