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Searched defs:OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK (Results 1 – 4 of 4) sorted by relevance

/openbmc/linux/drivers/gpu/drm/amd/include/asic_reg/dcn/
H A Ddcn_2_1_0_sh_mask.h31934 #define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK … macro
H A Ddcn_1_0_sh_mask.h25945 #define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK … macro
H A Ddcn_2_0_0_sh_mask.h35263 #define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK … macro
H A Ddcn_3_0_0_sh_mask.h34318 #define OTG5_OTG_INTERRUPT_CONTROL__OTG_GSL_VSYNC_GAP_INT_MSK_MASK … macro