1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3 * drivers/ata/sata_fsl.c
4 *
5 * Freescale 3.0Gbps SATA device driver
6 *
7 * Author: Ashish Kalra <ashish.kalra@freescale.com>
8 * Li Yang <leoli@freescale.com>
9 *
10 * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc.
11 */
12
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/of_address.h>
17 #include <linux/of_irq.h>
18 #include <linux/platform_device.h>
19 #include <linux/slab.h>
20
21 #include <scsi/scsi_host.h>
22 #include <scsi/scsi_cmnd.h>
23 #include <linux/libata.h>
24 #include <asm/io.h>
25
26 static unsigned int intr_coalescing_count;
27 module_param(intr_coalescing_count, int, S_IRUGO);
28 MODULE_PARM_DESC(intr_coalescing_count,
29 "INT coalescing count threshold (1..31)");
30
31 static unsigned int intr_coalescing_ticks;
32 module_param(intr_coalescing_ticks, int, S_IRUGO);
33 MODULE_PARM_DESC(intr_coalescing_ticks,
34 "INT coalescing timer threshold in AHB ticks");
35 /* Controller information */
36 enum {
37 SATA_FSL_QUEUE_DEPTH = 16,
38 SATA_FSL_MAX_PRD = 63,
39 SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1,
40 SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */
41
42 SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA |
43 ATA_FLAG_PMP | ATA_FLAG_NCQ |
44 ATA_FLAG_AN | ATA_FLAG_NO_LOG_PAGE),
45
46 SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH,
47 SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */
48 SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE),
49
50 /*
51 * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and
52 * chained indirect PRDEs up to a max count of 63.
53 * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will
54 * be setup as an indirect descriptor, pointing to it's next
55 * (contiguous) PRDE. Though chained indirect PRDE arrays are
56 * supported,it will be more efficient to use a direct PRDT and
57 * a single chain/link to indirect PRDE array/PRDT.
58 */
59
60 SATA_FSL_CMD_DESC_CFIS_SZ = 32,
61 SATA_FSL_CMD_DESC_SFIS_SZ = 32,
62 SATA_FSL_CMD_DESC_ACMD_SZ = 16,
63 SATA_FSL_CMD_DESC_RSRVD = 16,
64
65 SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ +
66 SATA_FSL_CMD_DESC_SFIS_SZ +
67 SATA_FSL_CMD_DESC_ACMD_SZ +
68 SATA_FSL_CMD_DESC_RSRVD +
69 SATA_FSL_MAX_PRD * 16),
70
71 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT =
72 (SATA_FSL_CMD_DESC_CFIS_SZ +
73 SATA_FSL_CMD_DESC_SFIS_SZ +
74 SATA_FSL_CMD_DESC_ACMD_SZ +
75 SATA_FSL_CMD_DESC_RSRVD),
76
77 SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS),
78 SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE +
79 SATA_FSL_CMD_DESC_AR_SZ),
80
81 /*
82 * MPC8315 has two SATA controllers, SATA1 & SATA2
83 * (one port per controller)
84 * MPC837x has 2/4 controllers, one port per controller
85 */
86
87 SATA_FSL_MAX_PORTS = 1,
88
89 SATA_FSL_IRQ_FLAG = IRQF_SHARED,
90 };
91
92 /*
93 * Interrupt Coalescing Control Register bitdefs */
94 enum {
95 ICC_MIN_INT_COUNT_THRESHOLD = 1,
96 ICC_MAX_INT_COUNT_THRESHOLD = ((1 << 5) - 1),
97 ICC_MIN_INT_TICKS_THRESHOLD = 0,
98 ICC_MAX_INT_TICKS_THRESHOLD = ((1 << 19) - 1),
99 ICC_SAFE_INT_TICKS = 1,
100 };
101
102 /*
103 * Host Controller command register set - per port
104 */
105 enum {
106 CQ = 0,
107 CA = 8,
108 CC = 0x10,
109 CE = 0x18,
110 DE = 0x20,
111 CHBA = 0x24,
112 HSTATUS = 0x28,
113 HCONTROL = 0x2C,
114 CQPMP = 0x30,
115 SIGNATURE = 0x34,
116 ICC = 0x38,
117
118 /*
119 * Host Status Register (HStatus) bitdefs
120 */
121 ONLINE = (1 << 31),
122 GOING_OFFLINE = (1 << 30),
123 BIST_ERR = (1 << 29),
124 CLEAR_ERROR = (1 << 27),
125
126 FATAL_ERR_HC_MASTER_ERR = (1 << 18),
127 FATAL_ERR_PARITY_ERR_TX = (1 << 17),
128 FATAL_ERR_PARITY_ERR_RX = (1 << 16),
129 FATAL_ERR_DATA_UNDERRUN = (1 << 13),
130 FATAL_ERR_DATA_OVERRUN = (1 << 12),
131 FATAL_ERR_CRC_ERR_TX = (1 << 11),
132 FATAL_ERR_CRC_ERR_RX = (1 << 10),
133 FATAL_ERR_FIFO_OVRFL_TX = (1 << 9),
134 FATAL_ERR_FIFO_OVRFL_RX = (1 << 8),
135
136 FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR |
137 FATAL_ERR_PARITY_ERR_TX |
138 FATAL_ERR_PARITY_ERR_RX |
139 FATAL_ERR_DATA_UNDERRUN |
140 FATAL_ERR_DATA_OVERRUN |
141 FATAL_ERR_CRC_ERR_TX |
142 FATAL_ERR_CRC_ERR_RX |
143 FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX,
144
145 INT_ON_DATA_LENGTH_MISMATCH = (1 << 12),
146 INT_ON_FATAL_ERR = (1 << 5),
147 INT_ON_PHYRDY_CHG = (1 << 4),
148
149 INT_ON_SIGNATURE_UPDATE = (1 << 3),
150 INT_ON_SNOTIFY_UPDATE = (1 << 2),
151 INT_ON_SINGL_DEVICE_ERR = (1 << 1),
152 INT_ON_CMD_COMPLETE = 1,
153
154 INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE |
155 INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR,
156
157 /*
158 * Host Control Register (HControl) bitdefs
159 */
160 HCONTROL_ONLINE_PHY_RST = (1 << 31),
161 HCONTROL_FORCE_OFFLINE = (1 << 30),
162 HCONTROL_LEGACY = (1 << 28),
163 HCONTROL_PARITY_PROT_MOD = (1 << 14),
164 HCONTROL_DPATH_PARITY = (1 << 12),
165 HCONTROL_SNOOP_ENABLE = (1 << 10),
166 HCONTROL_PMP_ATTACHED = (1 << 9),
167 HCONTROL_COPYOUT_STATFIS = (1 << 8),
168 IE_ON_FATAL_ERR = (1 << 5),
169 IE_ON_PHYRDY_CHG = (1 << 4),
170 IE_ON_SIGNATURE_UPDATE = (1 << 3),
171 IE_ON_SNOTIFY_UPDATE = (1 << 2),
172 IE_ON_SINGL_DEVICE_ERR = (1 << 1),
173 IE_ON_CMD_COMPLETE = 1,
174
175 DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG |
176 IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE |
177 IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE,
178
179 EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31),
180 DATA_SNOOP_ENABLE_V1 = (1 << 22),
181 DATA_SNOOP_ENABLE_V2 = (1 << 28),
182 };
183
184 /*
185 * SATA Superset Registers
186 */
187 enum {
188 SSTATUS = 0,
189 SERROR = 4,
190 SCONTROL = 8,
191 SNOTIFY = 0xC,
192 };
193
194 /*
195 * Control Status Register Set
196 */
197 enum {
198 TRANSCFG = 0,
199 TRANSSTATUS = 4,
200 LINKCFG = 8,
201 LINKCFG1 = 0xC,
202 LINKCFG2 = 0x10,
203 LINKSTATUS = 0x14,
204 LINKSTATUS1 = 0x18,
205 PHYCTRLCFG = 0x1C,
206 COMMANDSTAT = 0x20,
207 };
208
209 /* TRANSCFG (transport-layer) configuration control */
210 enum {
211 TRANSCFG_RX_WATER_MARK = (1 << 4),
212 };
213
214 /* PHY (link-layer) configuration control */
215 enum {
216 PHY_BIST_ENABLE = 0x01,
217 };
218
219 /*
220 * Command Header Table entry, i.e, command slot
221 * 4 Dwords per command slot, command header size == 64 Dwords.
222 */
223 struct cmdhdr_tbl_entry {
224 __le32 cda;
225 __le32 prde_fis_len;
226 __le32 ttl;
227 __le32 desc_info;
228 };
229
230 /*
231 * Description information bitdefs
232 */
233 enum {
234 CMD_DESC_RES = (1 << 11),
235 VENDOR_SPECIFIC_BIST = (1 << 10),
236 CMD_DESC_SNOOP_ENABLE = (1 << 9),
237 FPDMA_QUEUED_CMD = (1 << 8),
238 SRST_CMD = (1 << 7),
239 BIST = (1 << 6),
240 ATAPI_CMD = (1 << 5),
241 };
242
243 /*
244 * Command Descriptor
245 */
246 struct command_desc {
247 u8 cfis[8 * 4];
248 u8 sfis[8 * 4];
249 struct_group(cdb,
250 u8 acmd[4 * 4];
251 u8 fill[4 * 4];
252 );
253 u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4];
254 u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4];
255 };
256
257 /*
258 * Physical region table descriptor(PRD)
259 */
260
261 struct prde {
262 __le32 dba;
263 u8 fill[2 * 4];
264 __le32 ddc_and_ext;
265 };
266
267 /*
268 * ata_port private data
269 * This is our per-port instance data.
270 */
271 struct sata_fsl_port_priv {
272 struct cmdhdr_tbl_entry *cmdslot;
273 dma_addr_t cmdslot_paddr;
274 struct command_desc *cmdentry;
275 dma_addr_t cmdentry_paddr;
276 };
277
278 /*
279 * ata_port->host_set private data
280 */
281 struct sata_fsl_host_priv {
282 void __iomem *hcr_base;
283 void __iomem *ssr_base;
284 void __iomem *csr_base;
285 int irq;
286 int data_snoop;
287 struct device_attribute intr_coalescing;
288 struct device_attribute rx_watermark;
289 };
290
fsl_sata_set_irq_coalescing(struct ata_host * host,unsigned int count,unsigned int ticks)291 static void fsl_sata_set_irq_coalescing(struct ata_host *host,
292 unsigned int count, unsigned int ticks)
293 {
294 struct sata_fsl_host_priv *host_priv = host->private_data;
295 void __iomem *hcr_base = host_priv->hcr_base;
296 unsigned long flags;
297
298 if (count > ICC_MAX_INT_COUNT_THRESHOLD)
299 count = ICC_MAX_INT_COUNT_THRESHOLD;
300 else if (count < ICC_MIN_INT_COUNT_THRESHOLD)
301 count = ICC_MIN_INT_COUNT_THRESHOLD;
302
303 if (ticks > ICC_MAX_INT_TICKS_THRESHOLD)
304 ticks = ICC_MAX_INT_TICKS_THRESHOLD;
305 else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) &&
306 (count > ICC_MIN_INT_COUNT_THRESHOLD))
307 ticks = ICC_SAFE_INT_TICKS;
308
309 spin_lock_irqsave(&host->lock, flags);
310 iowrite32((count << 24 | ticks), hcr_base + ICC);
311
312 intr_coalescing_count = count;
313 intr_coalescing_ticks = ticks;
314 spin_unlock_irqrestore(&host->lock, flags);
315
316 dev_dbg(host->dev, "interrupt coalescing, count = 0x%x, ticks = %x\n",
317 intr_coalescing_count, intr_coalescing_ticks);
318 dev_dbg(host->dev, "ICC register status: (hcr base: 0x%p) = 0x%x\n",
319 hcr_base, ioread32(hcr_base + ICC));
320 }
321
fsl_sata_intr_coalescing_show(struct device * dev,struct device_attribute * attr,char * buf)322 static ssize_t fsl_sata_intr_coalescing_show(struct device *dev,
323 struct device_attribute *attr, char *buf)
324 {
325 return sysfs_emit(buf, "%u %u\n",
326 intr_coalescing_count, intr_coalescing_ticks);
327 }
328
fsl_sata_intr_coalescing_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)329 static ssize_t fsl_sata_intr_coalescing_store(struct device *dev,
330 struct device_attribute *attr,
331 const char *buf, size_t count)
332 {
333 unsigned int coalescing_count, coalescing_ticks;
334
335 if (sscanf(buf, "%u%u", &coalescing_count, &coalescing_ticks) != 2) {
336 dev_err(dev, "fsl-sata: wrong parameter format.\n");
337 return -EINVAL;
338 }
339
340 fsl_sata_set_irq_coalescing(dev_get_drvdata(dev),
341 coalescing_count, coalescing_ticks);
342
343 return strlen(buf);
344 }
345
fsl_sata_rx_watermark_show(struct device * dev,struct device_attribute * attr,char * buf)346 static ssize_t fsl_sata_rx_watermark_show(struct device *dev,
347 struct device_attribute *attr, char *buf)
348 {
349 unsigned int rx_watermark;
350 unsigned long flags;
351 struct ata_host *host = dev_get_drvdata(dev);
352 struct sata_fsl_host_priv *host_priv = host->private_data;
353 void __iomem *csr_base = host_priv->csr_base;
354
355 spin_lock_irqsave(&host->lock, flags);
356 rx_watermark = ioread32(csr_base + TRANSCFG);
357 rx_watermark &= 0x1f;
358 spin_unlock_irqrestore(&host->lock, flags);
359
360 return sysfs_emit(buf, "%u\n", rx_watermark);
361 }
362
fsl_sata_rx_watermark_store(struct device * dev,struct device_attribute * attr,const char * buf,size_t count)363 static ssize_t fsl_sata_rx_watermark_store(struct device *dev,
364 struct device_attribute *attr,
365 const char *buf, size_t count)
366 {
367 unsigned int rx_watermark;
368 unsigned long flags;
369 struct ata_host *host = dev_get_drvdata(dev);
370 struct sata_fsl_host_priv *host_priv = host->private_data;
371 void __iomem *csr_base = host_priv->csr_base;
372 u32 temp;
373
374 if (kstrtouint(buf, 10, &rx_watermark) < 0) {
375 dev_err(dev, "fsl-sata: wrong parameter format.\n");
376 return -EINVAL;
377 }
378
379 spin_lock_irqsave(&host->lock, flags);
380 temp = ioread32(csr_base + TRANSCFG);
381 temp &= 0xffffffe0;
382 iowrite32(temp | rx_watermark, csr_base + TRANSCFG);
383 spin_unlock_irqrestore(&host->lock, flags);
384
385 return strlen(buf);
386 }
387
sata_fsl_tag(struct ata_port * ap,unsigned int tag,void __iomem * hcr_base)388 static inline unsigned int sata_fsl_tag(struct ata_port *ap,
389 unsigned int tag,
390 void __iomem *hcr_base)
391 {
392 /* We let libATA core do actual (queue) tag allocation */
393
394 if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) {
395 ata_port_dbg(ap, "tag %d invalid : out of range\n", tag);
396 return 0;
397 }
398
399 if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) {
400 ata_port_dbg(ap, "tag %d invalid : in use!!\n", tag);
401 return 0;
402 }
403
404 return tag;
405 }
406
sata_fsl_setup_cmd_hdr_entry(struct ata_port * ap,struct sata_fsl_port_priv * pp,unsigned int tag,u32 desc_info,u32 data_xfer_len,u8 num_prde,u8 fis_len)407 static void sata_fsl_setup_cmd_hdr_entry(struct ata_port *ap,
408 struct sata_fsl_port_priv *pp,
409 unsigned int tag, u32 desc_info,
410 u32 data_xfer_len, u8 num_prde,
411 u8 fis_len)
412 {
413 dma_addr_t cmd_descriptor_address;
414
415 cmd_descriptor_address = pp->cmdentry_paddr +
416 tag * SATA_FSL_CMD_DESC_SIZE;
417
418 /* NOTE: both data_xfer_len & fis_len are Dword counts */
419
420 pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address);
421 pp->cmdslot[tag].prde_fis_len =
422 cpu_to_le32((num_prde << 16) | (fis_len << 2));
423 pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03);
424 pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F));
425
426 ata_port_dbg(ap, "cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n",
427 le32_to_cpu(pp->cmdslot[tag].cda),
428 le32_to_cpu(pp->cmdslot[tag].prde_fis_len),
429 le32_to_cpu(pp->cmdslot[tag].ttl),
430 le32_to_cpu(pp->cmdslot[tag].desc_info));
431 }
432
sata_fsl_fill_sg(struct ata_queued_cmd * qc,void * cmd_desc,u32 * ttl,dma_addr_t cmd_desc_paddr,int data_snoop)433 static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc,
434 u32 *ttl, dma_addr_t cmd_desc_paddr,
435 int data_snoop)
436 {
437 struct scatterlist *sg;
438 unsigned int num_prde = 0;
439 u32 ttl_dwords = 0;
440
441 /*
442 * NOTE : direct & indirect prdt's are contiguously allocated
443 */
444 struct prde *prd = (struct prde *)&((struct command_desc *)
445 cmd_desc)->prdt;
446
447 struct prde *prd_ptr_to_indirect_ext = NULL;
448 unsigned indirect_ext_segment_sz = 0;
449 dma_addr_t indirect_ext_segment_paddr;
450 unsigned int si;
451
452 indirect_ext_segment_paddr = cmd_desc_paddr +
453 SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16;
454
455 for_each_sg(qc->sg, sg, qc->n_elem, si) {
456 dma_addr_t sg_addr = sg_dma_address(sg);
457 u32 sg_len = sg_dma_len(sg);
458
459 /* warn if each s/g element is not dword aligned */
460 if (unlikely(sg_addr & 0x03))
461 ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n",
462 (unsigned long long)sg_addr);
463 if (unlikely(sg_len & 0x03))
464 ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n",
465 sg_len);
466
467 if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) &&
468 sg_next(sg) != NULL) {
469 prd_ptr_to_indirect_ext = prd;
470 prd->dba = cpu_to_le32(indirect_ext_segment_paddr);
471 indirect_ext_segment_sz = 0;
472 ++prd;
473 ++num_prde;
474 }
475
476 ttl_dwords += sg_len;
477 prd->dba = cpu_to_le32(sg_addr);
478 prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03));
479
480 ++num_prde;
481 ++prd;
482 if (prd_ptr_to_indirect_ext)
483 indirect_ext_segment_sz += sg_len;
484 }
485
486 if (prd_ptr_to_indirect_ext) {
487 /* set indirect extension flag along with indirect ext. size */
488 prd_ptr_to_indirect_ext->ddc_and_ext =
489 cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG |
490 data_snoop |
491 (indirect_ext_segment_sz & ~0x03)));
492 }
493
494 *ttl = ttl_dwords;
495 return num_prde;
496 }
497
sata_fsl_qc_prep(struct ata_queued_cmd * qc)498 static enum ata_completion_errors sata_fsl_qc_prep(struct ata_queued_cmd *qc)
499 {
500 struct ata_port *ap = qc->ap;
501 struct sata_fsl_port_priv *pp = ap->private_data;
502 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
503 void __iomem *hcr_base = host_priv->hcr_base;
504 unsigned int tag = sata_fsl_tag(ap, qc->hw_tag, hcr_base);
505 struct command_desc *cd;
506 u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE;
507 u32 num_prde = 0;
508 u32 ttl_dwords = 0;
509 dma_addr_t cd_paddr;
510
511 cd = (struct command_desc *)pp->cmdentry + tag;
512 cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE;
513
514 ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis);
515
516 /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */
517 if (ata_is_atapi(qc->tf.protocol)) {
518 desc_info |= ATAPI_CMD;
519 memset(&cd->cdb, 0, sizeof(cd->cdb));
520 memcpy(&cd->cdb, qc->cdb, qc->dev->cdb_len);
521 }
522
523 if (qc->flags & ATA_QCFLAG_DMAMAP)
524 num_prde = sata_fsl_fill_sg(qc, (void *)cd,
525 &ttl_dwords, cd_paddr,
526 host_priv->data_snoop);
527
528 if (qc->tf.protocol == ATA_PROT_NCQ)
529 desc_info |= FPDMA_QUEUED_CMD;
530
531 sata_fsl_setup_cmd_hdr_entry(ap, pp, tag, desc_info, ttl_dwords,
532 num_prde, 5);
533
534 ata_port_dbg(ap, "SATA FSL : di = 0x%x, ttl = %d, num_prde = %d\n",
535 desc_info, ttl_dwords, num_prde);
536
537 return AC_ERR_OK;
538 }
539
sata_fsl_qc_issue(struct ata_queued_cmd * qc)540 static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc)
541 {
542 struct ata_port *ap = qc->ap;
543 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
544 void __iomem *hcr_base = host_priv->hcr_base;
545 unsigned int tag = sata_fsl_tag(ap, qc->hw_tag, hcr_base);
546
547 ata_port_dbg(ap, "CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n",
548 ioread32(CQ + hcr_base),
549 ioread32(CA + hcr_base),
550 ioread32(CE + hcr_base), ioread32(CC + hcr_base));
551
552 iowrite32(qc->dev->link->pmp, CQPMP + hcr_base);
553
554 /* Simply queue command to the controller/device */
555 iowrite32(1 << tag, CQ + hcr_base);
556
557 ata_port_dbg(ap, "tag=%d, CQ=0x%x, CA=0x%x\n",
558 tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base));
559
560 ata_port_dbg(ap, "CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n",
561 ioread32(CE + hcr_base),
562 ioread32(DE + hcr_base),
563 ioread32(CC + hcr_base),
564 ioread32(COMMANDSTAT + host_priv->csr_base));
565
566 return 0;
567 }
568
sata_fsl_qc_fill_rtf(struct ata_queued_cmd * qc)569 static void sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc)
570 {
571 struct sata_fsl_port_priv *pp = qc->ap->private_data;
572 struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data;
573 void __iomem *hcr_base = host_priv->hcr_base;
574 unsigned int tag = sata_fsl_tag(qc->ap, qc->hw_tag, hcr_base);
575 struct command_desc *cd;
576
577 cd = pp->cmdentry + tag;
578
579 ata_tf_from_fis(cd->sfis, &qc->result_tf);
580 }
581
sata_fsl_scr_write(struct ata_link * link,unsigned int sc_reg_in,u32 val)582 static int sata_fsl_scr_write(struct ata_link *link,
583 unsigned int sc_reg_in, u32 val)
584 {
585 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
586 void __iomem *ssr_base = host_priv->ssr_base;
587 unsigned int sc_reg;
588
589 switch (sc_reg_in) {
590 case SCR_STATUS:
591 case SCR_ERROR:
592 case SCR_CONTROL:
593 case SCR_ACTIVE:
594 sc_reg = sc_reg_in;
595 break;
596 default:
597 return -EINVAL;
598 }
599
600 ata_link_dbg(link, "reg_in = %d\n", sc_reg);
601
602 iowrite32(val, ssr_base + (sc_reg * 4));
603 return 0;
604 }
605
sata_fsl_scr_read(struct ata_link * link,unsigned int sc_reg_in,u32 * val)606 static int sata_fsl_scr_read(struct ata_link *link,
607 unsigned int sc_reg_in, u32 *val)
608 {
609 struct sata_fsl_host_priv *host_priv = link->ap->host->private_data;
610 void __iomem *ssr_base = host_priv->ssr_base;
611 unsigned int sc_reg;
612
613 switch (sc_reg_in) {
614 case SCR_STATUS:
615 case SCR_ERROR:
616 case SCR_CONTROL:
617 case SCR_ACTIVE:
618 sc_reg = sc_reg_in;
619 break;
620 default:
621 return -EINVAL;
622 }
623
624 ata_link_dbg(link, "reg_in = %d\n", sc_reg);
625
626 *val = ioread32(ssr_base + (sc_reg * 4));
627 return 0;
628 }
629
sata_fsl_freeze(struct ata_port * ap)630 static void sata_fsl_freeze(struct ata_port *ap)
631 {
632 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
633 void __iomem *hcr_base = host_priv->hcr_base;
634 u32 temp;
635
636 ata_port_dbg(ap, "CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n",
637 ioread32(CQ + hcr_base),
638 ioread32(CA + hcr_base),
639 ioread32(CE + hcr_base), ioread32(DE + hcr_base));
640 ata_port_dbg(ap, "CmdStat = 0x%x\n",
641 ioread32(host_priv->csr_base + COMMANDSTAT));
642
643 /* disable interrupts on the controller/port */
644 temp = ioread32(hcr_base + HCONTROL);
645 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
646
647 ata_port_dbg(ap, "HControl = 0x%x, HStatus = 0x%x\n",
648 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
649 }
650
sata_fsl_thaw(struct ata_port * ap)651 static void sata_fsl_thaw(struct ata_port *ap)
652 {
653 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
654 void __iomem *hcr_base = host_priv->hcr_base;
655 u32 temp;
656
657 /* ack. any pending IRQs for this controller/port */
658 temp = ioread32(hcr_base + HSTATUS);
659
660 ata_port_dbg(ap, "pending IRQs = 0x%x\n", (temp & 0x3F));
661
662 if (temp & 0x3F)
663 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
664
665 /* enable interrupts on the controller/port */
666 temp = ioread32(hcr_base + HCONTROL);
667 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
668
669 ata_port_dbg(ap, "HControl = 0x%x, HStatus = 0x%x\n",
670 ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS));
671 }
672
sata_fsl_pmp_attach(struct ata_port * ap)673 static void sata_fsl_pmp_attach(struct ata_port *ap)
674 {
675 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
676 void __iomem *hcr_base = host_priv->hcr_base;
677 u32 temp;
678
679 temp = ioread32(hcr_base + HCONTROL);
680 iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL);
681 }
682
sata_fsl_pmp_detach(struct ata_port * ap)683 static void sata_fsl_pmp_detach(struct ata_port *ap)
684 {
685 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
686 void __iomem *hcr_base = host_priv->hcr_base;
687 u32 temp;
688
689 temp = ioread32(hcr_base + HCONTROL);
690 temp &= ~HCONTROL_PMP_ATTACHED;
691 iowrite32(temp, hcr_base + HCONTROL);
692
693 /* enable interrupts on the controller/port */
694 temp = ioread32(hcr_base + HCONTROL);
695 iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL);
696
697 }
698
sata_fsl_port_start(struct ata_port * ap)699 static int sata_fsl_port_start(struct ata_port *ap)
700 {
701 struct device *dev = ap->host->dev;
702 struct sata_fsl_port_priv *pp;
703 void *mem;
704 dma_addr_t mem_dma;
705 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
706 void __iomem *hcr_base = host_priv->hcr_base;
707 u32 temp;
708
709 pp = kzalloc(sizeof(*pp), GFP_KERNEL);
710 if (!pp)
711 return -ENOMEM;
712
713 mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma,
714 GFP_KERNEL);
715 if (!mem) {
716 kfree(pp);
717 return -ENOMEM;
718 }
719
720 pp->cmdslot = mem;
721 pp->cmdslot_paddr = mem_dma;
722
723 mem += SATA_FSL_CMD_SLOT_SIZE;
724 mem_dma += SATA_FSL_CMD_SLOT_SIZE;
725
726 pp->cmdentry = mem;
727 pp->cmdentry_paddr = mem_dma;
728
729 ap->private_data = pp;
730
731 ata_port_dbg(ap, "CHBA = 0x%lx, cmdentry_phys = 0x%lx\n",
732 (unsigned long)pp->cmdslot_paddr,
733 (unsigned long)pp->cmdentry_paddr);
734
735 /* Now, update the CHBA register in host controller cmd register set */
736 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
737
738 /*
739 * Now, we can bring the controller on-line & also initiate
740 * the COMINIT sequence, we simply return here and the boot-probing
741 * & device discovery process is re-initiated by libATA using a
742 * Softreset EH (dummy) session. Hence, boot probing and device
743 * discovey will be part of sata_fsl_softreset() callback.
744 */
745
746 temp = ioread32(hcr_base + HCONTROL);
747 iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL);
748
749 ata_port_dbg(ap, "HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
750 ata_port_dbg(ap, "HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
751 ata_port_dbg(ap, "CHBA = 0x%x\n", ioread32(hcr_base + CHBA));
752
753 return 0;
754 }
755
sata_fsl_port_stop(struct ata_port * ap)756 static void sata_fsl_port_stop(struct ata_port *ap)
757 {
758 struct device *dev = ap->host->dev;
759 struct sata_fsl_port_priv *pp = ap->private_data;
760 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
761 void __iomem *hcr_base = host_priv->hcr_base;
762 u32 temp;
763
764 /*
765 * Force host controller to go off-line, aborting current operations
766 */
767 temp = ioread32(hcr_base + HCONTROL);
768 temp &= ~HCONTROL_ONLINE_PHY_RST;
769 temp |= HCONTROL_FORCE_OFFLINE;
770 iowrite32(temp, hcr_base + HCONTROL);
771
772 /* Poll for controller to go offline - should happen immediately */
773 ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1);
774
775 ap->private_data = NULL;
776 dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ,
777 pp->cmdslot, pp->cmdslot_paddr);
778
779 kfree(pp);
780 }
781
sata_fsl_dev_classify(struct ata_port * ap)782 static unsigned int sata_fsl_dev_classify(struct ata_port *ap)
783 {
784 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
785 void __iomem *hcr_base = host_priv->hcr_base;
786 struct ata_taskfile tf;
787 u32 temp;
788
789 temp = ioread32(hcr_base + SIGNATURE);
790
791 ata_port_dbg(ap, "HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS));
792 ata_port_dbg(ap, "HControl = 0x%x\n", ioread32(hcr_base + HCONTROL));
793
794 tf.lbah = (temp >> 24) & 0xff;
795 tf.lbam = (temp >> 16) & 0xff;
796 tf.lbal = (temp >> 8) & 0xff;
797 tf.nsect = temp & 0xff;
798
799 return ata_port_classify(ap, &tf);
800 }
801
sata_fsl_hardreset(struct ata_link * link,unsigned int * class,unsigned long deadline)802 static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class,
803 unsigned long deadline)
804 {
805 struct ata_port *ap = link->ap;
806 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
807 void __iomem *hcr_base = host_priv->hcr_base;
808 u32 temp;
809 int i = 0;
810 unsigned long start_jiffies;
811
812 try_offline_again:
813 /*
814 * Force host controller to go off-line, aborting current operations
815 */
816 temp = ioread32(hcr_base + HCONTROL);
817 temp &= ~HCONTROL_ONLINE_PHY_RST;
818 iowrite32(temp, hcr_base + HCONTROL);
819
820 /* Poll for controller to go offline */
821 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE,
822 1, 500);
823
824 if (temp & ONLINE) {
825 ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i);
826
827 /*
828 * Try to offline controller atleast twice
829 */
830 i++;
831 if (i == 2)
832 goto err;
833 else
834 goto try_offline_again;
835 }
836
837 ata_port_dbg(ap, "hardreset, controller off-lined\n"
838 "HStatus = 0x%x HControl = 0x%x\n",
839 ioread32(hcr_base + HSTATUS),
840 ioread32(hcr_base + HCONTROL));
841
842 /*
843 * PHY reset should remain asserted for atleast 1ms
844 */
845 ata_msleep(ap, 1);
846
847 sata_set_spd(link);
848
849 /*
850 * Now, bring the host controller online again, this can take time
851 * as PHY reset and communication establishment, 1st D2H FIS and
852 * device signature update is done, on safe side assume 500ms
853 * NOTE : Host online status may be indicated immediately!!
854 */
855
856 temp = ioread32(hcr_base + HCONTROL);
857 temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE);
858 temp |= HCONTROL_PMP_ATTACHED;
859 iowrite32(temp, hcr_base + HCONTROL);
860
861 temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500);
862
863 if (!(temp & ONLINE)) {
864 ata_port_err(ap, "Hardreset failed, not on-lined\n");
865 goto err;
866 }
867
868 ata_port_dbg(ap, "controller off-lined & on-lined\n"
869 "HStatus = 0x%x HControl = 0x%x\n",
870 ioread32(hcr_base + HSTATUS),
871 ioread32(hcr_base + HCONTROL));
872
873 /*
874 * First, wait for the PHYRDY change to occur before waiting for
875 * the signature, and also verify if SStatus indicates device
876 * presence
877 */
878
879 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500);
880 if ((!(temp & 0x10)) || ata_link_offline(link)) {
881 ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n",
882 ioread32(hcr_base + HSTATUS));
883 *class = ATA_DEV_NONE;
884 return 0;
885 }
886
887 /*
888 * Wait for the first D2H from device,i.e,signature update notification
889 */
890 start_jiffies = jiffies;
891 temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10,
892 500, jiffies_to_msecs(deadline - start_jiffies));
893
894 if ((temp & 0xFF) != 0x18) {
895 ata_port_warn(ap, "No Signature Update\n");
896 *class = ATA_DEV_NONE;
897 goto do_followup_srst;
898 } else {
899 ata_port_info(ap, "Signature Update detected @ %d msecs\n",
900 jiffies_to_msecs(jiffies - start_jiffies));
901 *class = sata_fsl_dev_classify(ap);
902 return 0;
903 }
904
905 do_followup_srst:
906 /*
907 * request libATA to perform follow-up softreset
908 */
909 return -EAGAIN;
910
911 err:
912 return -EIO;
913 }
914
sata_fsl_softreset(struct ata_link * link,unsigned int * class,unsigned long deadline)915 static int sata_fsl_softreset(struct ata_link *link, unsigned int *class,
916 unsigned long deadline)
917 {
918 struct ata_port *ap = link->ap;
919 struct sata_fsl_port_priv *pp = ap->private_data;
920 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
921 void __iomem *hcr_base = host_priv->hcr_base;
922 int pmp = sata_srst_pmp(link);
923 u32 temp;
924 struct ata_taskfile tf;
925 u8 *cfis;
926 u32 Serror;
927
928 if (ata_link_offline(link)) {
929 *class = ATA_DEV_NONE;
930 return 0;
931 }
932
933 /*
934 * Send a device reset (SRST) explicitly on command slot #0
935 * Check : will the command queue (reg) be cleared during offlining ??
936 * Also we will be online only if Phy commn. has been established
937 * and device presence has been detected, therefore if we have
938 * reached here, we can send a command to the target device
939 */
940
941 ata_tf_init(link->device, &tf);
942 cfis = (u8 *) &pp->cmdentry->cfis;
943
944 /* device reset/SRST is a control register update FIS, uses tag0 */
945 sata_fsl_setup_cmd_hdr_entry(ap, pp, 0,
946 SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5);
947
948 tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */
949 ata_tf_to_fis(&tf, pmp, 0, cfis);
950
951 ata_port_dbg(ap, "Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n",
952 cfis[0], cfis[1], cfis[2], cfis[3]);
953
954 /*
955 * Queue SRST command to the controller/device, ensure that no
956 * other commands are active on the controller/device
957 */
958
959 ata_port_dbg(ap, "CQ = 0x%x, CA = 0x%x, CC = 0x%x\n",
960 ioread32(CQ + hcr_base),
961 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
962
963 iowrite32(0xFFFF, CC + hcr_base);
964 if (pmp != SATA_PMP_CTRL_PORT)
965 iowrite32(pmp, CQPMP + hcr_base);
966 iowrite32(1, CQ + hcr_base);
967
968 temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000);
969 if (temp & 0x1) {
970 ata_port_warn(ap, "ATA_SRST issue failed\n");
971
972 ata_port_dbg(ap, "Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n",
973 ioread32(CQ + hcr_base),
974 ioread32(CA + hcr_base), ioread32(CC + hcr_base));
975
976 sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror);
977
978 ata_port_dbg(ap, "HStatus = 0x%x HControl = 0x%x Serror = 0x%x\n",
979 ioread32(hcr_base + HSTATUS),
980 ioread32(hcr_base + HCONTROL),
981 Serror);
982 goto err;
983 }
984
985 ata_msleep(ap, 1);
986
987 /*
988 * SATA device enters reset state after receiving a Control register
989 * FIS with SRST bit asserted and it awaits another H2D Control reg.
990 * FIS with SRST bit cleared, then the device does internal diags &
991 * initialization, followed by indicating it's initialization status
992 * using ATA signature D2H register FIS to the host controller.
993 */
994
995 sata_fsl_setup_cmd_hdr_entry(ap, pp, 0,
996 CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE,
997 0, 0, 5);
998
999 tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */
1000 ata_tf_to_fis(&tf, pmp, 0, cfis);
1001
1002 if (pmp != SATA_PMP_CTRL_PORT)
1003 iowrite32(pmp, CQPMP + hcr_base);
1004 iowrite32(1, CQ + hcr_base);
1005 ata_msleep(ap, 150); /* ?? */
1006
1007 /*
1008 * The above command would have signalled an interrupt on command
1009 * complete, which needs special handling, by clearing the Nth
1010 * command bit of the CCreg
1011 */
1012 iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */
1013
1014 *class = ATA_DEV_NONE;
1015
1016 /* Verify if SStatus indicates device presence */
1017 if (ata_link_online(link)) {
1018 /*
1019 * if we are here, device presence has been detected,
1020 * 1st D2H FIS would have been received, but sfis in
1021 * command desc. is not updated, but signature register
1022 * would have been updated
1023 */
1024
1025 *class = sata_fsl_dev_classify(ap);
1026
1027 ata_port_dbg(ap, "ccreg = 0x%x\n", ioread32(hcr_base + CC));
1028 ata_port_dbg(ap, "cereg = 0x%x\n", ioread32(hcr_base + CE));
1029 }
1030
1031 return 0;
1032
1033 err:
1034 return -EIO;
1035 }
1036
sata_fsl_error_handler(struct ata_port * ap)1037 static void sata_fsl_error_handler(struct ata_port *ap)
1038 {
1039 sata_pmp_error_handler(ap);
1040 }
1041
sata_fsl_post_internal_cmd(struct ata_queued_cmd * qc)1042 static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc)
1043 {
1044 if (qc->flags & ATA_QCFLAG_EH)
1045 qc->err_mask |= AC_ERR_OTHER;
1046
1047 if (qc->err_mask) {
1048 /* make DMA engine forget about the failed command */
1049
1050 }
1051 }
1052
sata_fsl_error_intr(struct ata_port * ap)1053 static void sata_fsl_error_intr(struct ata_port *ap)
1054 {
1055 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1056 void __iomem *hcr_base = host_priv->hcr_base;
1057 u32 hstatus, dereg=0, cereg = 0, SError = 0;
1058 unsigned int err_mask = 0, action = 0;
1059 int freeze = 0, abort=0;
1060 struct ata_link *link = NULL;
1061 struct ata_queued_cmd *qc = NULL;
1062 struct ata_eh_info *ehi;
1063
1064 hstatus = ioread32(hcr_base + HSTATUS);
1065 cereg = ioread32(hcr_base + CE);
1066
1067 /* first, analyze and record host port events */
1068 link = &ap->link;
1069 ehi = &link->eh_info;
1070 ata_ehi_clear_desc(ehi);
1071
1072 /*
1073 * Handle & Clear SError
1074 */
1075
1076 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1077 if (unlikely(SError & 0xFFFF0000))
1078 sata_fsl_scr_write(&ap->link, SCR_ERROR, SError);
1079
1080 ata_port_dbg(ap, "hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n",
1081 hstatus, cereg, ioread32(hcr_base + DE), SError);
1082
1083 /* handle fatal errors */
1084 if (hstatus & FATAL_ERROR_DECODE) {
1085 ehi->err_mask |= AC_ERR_ATA_BUS;
1086 ehi->action |= ATA_EH_SOFTRESET;
1087
1088 freeze = 1;
1089 }
1090
1091 /* Handle SDB FIS receive & notify update */
1092 if (hstatus & INT_ON_SNOTIFY_UPDATE)
1093 sata_async_notification(ap);
1094
1095 /* Handle PHYRDY change notification */
1096 if (hstatus & INT_ON_PHYRDY_CHG) {
1097 ata_port_dbg(ap, "PHYRDY change indication\n");
1098
1099 /* Setup a soft-reset EH action */
1100 ata_ehi_hotplugged(ehi);
1101 ata_ehi_push_desc(ehi, "%s", "PHY RDY changed");
1102 freeze = 1;
1103 }
1104
1105 /* handle single device errors */
1106 if (cereg) {
1107 /*
1108 * clear the command error, also clears queue to the device
1109 * in error, and we can (re)issue commands to this device.
1110 * When a device is in error all commands queued into the
1111 * host controller and at the device are considered aborted
1112 * and the queue for that device is stopped. Now, after
1113 * clearing the device error, we can issue commands to the
1114 * device to interrogate it to find the source of the error.
1115 */
1116 abort = 1;
1117
1118 ata_port_dbg(ap, "single device error, CE=0x%x, DE=0x%x\n",
1119 ioread32(hcr_base + CE), ioread32(hcr_base + DE));
1120
1121 /* find out the offending link and qc */
1122 if (ap->nr_pmp_links) {
1123 unsigned int dev_num;
1124
1125 dereg = ioread32(hcr_base + DE);
1126 iowrite32(dereg, hcr_base + DE);
1127 iowrite32(cereg, hcr_base + CE);
1128
1129 dev_num = ffs(dereg) - 1;
1130 if (dev_num < ap->nr_pmp_links && dereg != 0) {
1131 link = &ap->pmp_link[dev_num];
1132 ehi = &link->eh_info;
1133 qc = ata_qc_from_tag(ap, link->active_tag);
1134 /*
1135 * We should consider this as non fatal error,
1136 * and TF must be updated as done below.
1137 */
1138
1139 err_mask |= AC_ERR_DEV;
1140
1141 } else {
1142 err_mask |= AC_ERR_HSM;
1143 action |= ATA_EH_HARDRESET;
1144 freeze = 1;
1145 }
1146 } else {
1147 dereg = ioread32(hcr_base + DE);
1148 iowrite32(dereg, hcr_base + DE);
1149 iowrite32(cereg, hcr_base + CE);
1150
1151 qc = ata_qc_from_tag(ap, link->active_tag);
1152 /*
1153 * We should consider this as non fatal error,
1154 * and TF must be updated as done below.
1155 */
1156 err_mask |= AC_ERR_DEV;
1157 }
1158 }
1159
1160 /* record error info */
1161 if (qc)
1162 qc->err_mask |= err_mask;
1163 else
1164 ehi->err_mask |= err_mask;
1165
1166 ehi->action |= action;
1167
1168 /* freeze or abort */
1169 if (freeze)
1170 ata_port_freeze(ap);
1171 else if (abort) {
1172 if (qc)
1173 ata_link_abort(qc->dev->link);
1174 else
1175 ata_port_abort(ap);
1176 }
1177 }
1178
sata_fsl_host_intr(struct ata_port * ap)1179 static void sata_fsl_host_intr(struct ata_port *ap)
1180 {
1181 struct sata_fsl_host_priv *host_priv = ap->host->private_data;
1182 void __iomem *hcr_base = host_priv->hcr_base;
1183 u32 hstatus, done_mask = 0;
1184 struct ata_queued_cmd *qc;
1185 u32 SError;
1186 u32 tag;
1187 u32 status_mask = INT_ON_ERROR;
1188
1189 hstatus = ioread32(hcr_base + HSTATUS);
1190
1191 sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError);
1192
1193 /* Read command completed register */
1194 done_mask = ioread32(hcr_base + CC);
1195
1196 /* Workaround for data length mismatch errata */
1197 if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) {
1198 ata_qc_for_each_with_internal(ap, qc, tag) {
1199 if (qc && ata_is_atapi(qc->tf.protocol)) {
1200 u32 hcontrol;
1201 /* Set HControl[27] to clear error registers */
1202 hcontrol = ioread32(hcr_base + HCONTROL);
1203 iowrite32(hcontrol | CLEAR_ERROR,
1204 hcr_base + HCONTROL);
1205
1206 /* Clear HControl[27] */
1207 iowrite32(hcontrol & ~CLEAR_ERROR,
1208 hcr_base + HCONTROL);
1209
1210 /* Clear SError[E] bit */
1211 sata_fsl_scr_write(&ap->link, SCR_ERROR,
1212 SError);
1213
1214 /* Ignore fatal error and device error */
1215 status_mask &= ~(INT_ON_SINGL_DEVICE_ERR
1216 | INT_ON_FATAL_ERR);
1217 break;
1218 }
1219 }
1220 }
1221
1222 if (unlikely(SError & 0xFFFF0000)) {
1223 ata_port_dbg(ap, "serror @host_intr : 0x%x\n", SError);
1224 sata_fsl_error_intr(ap);
1225 }
1226
1227 if (unlikely(hstatus & status_mask)) {
1228 ata_port_dbg(ap, "error interrupt!!\n");
1229 sata_fsl_error_intr(ap);
1230 return;
1231 }
1232
1233 ata_port_dbg(ap, "Status of all queues :\n");
1234 ata_port_dbg(ap, "done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%llx\n",
1235 done_mask,
1236 ioread32(hcr_base + CA),
1237 ioread32(hcr_base + CE),
1238 ioread32(hcr_base + CQ),
1239 ap->qc_active);
1240
1241 if (done_mask & ap->qc_active) {
1242 int i;
1243 /* clear CC bit, this will also complete the interrupt */
1244 iowrite32(done_mask, hcr_base + CC);
1245
1246 ata_port_dbg(ap, "Status of all queues: done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n",
1247 done_mask, ioread32(hcr_base + CA),
1248 ioread32(hcr_base + CE));
1249
1250 for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) {
1251 if (done_mask & (1 << i))
1252 ata_port_dbg(ap, "completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n",
1253 i, ioread32(hcr_base + CC),
1254 ioread32(hcr_base + CA));
1255 }
1256 ata_qc_complete_multiple(ap, ata_qc_get_active(ap) ^ done_mask);
1257 return;
1258
1259 } else if ((ap->qc_active & (1ULL << ATA_TAG_INTERNAL))) {
1260 iowrite32(1, hcr_base + CC);
1261 qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL);
1262
1263 ata_port_dbg(ap, "completing non-ncq cmd, CC=0x%x\n",
1264 ioread32(hcr_base + CC));
1265
1266 if (qc) {
1267 ata_qc_complete(qc);
1268 }
1269 } else {
1270 /* Spurious Interrupt!! */
1271 ata_port_dbg(ap, "spurious interrupt!!, CC = 0x%x\n",
1272 ioread32(hcr_base + CC));
1273 iowrite32(done_mask, hcr_base + CC);
1274 return;
1275 }
1276 }
1277
sata_fsl_interrupt(int irq,void * dev_instance)1278 static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance)
1279 {
1280 struct ata_host *host = dev_instance;
1281 struct sata_fsl_host_priv *host_priv = host->private_data;
1282 void __iomem *hcr_base = host_priv->hcr_base;
1283 u32 interrupt_enables;
1284 unsigned handled = 0;
1285 struct ata_port *ap;
1286
1287 /* ack. any pending IRQs for this controller/port */
1288 interrupt_enables = ioread32(hcr_base + HSTATUS);
1289 interrupt_enables &= 0x3F;
1290
1291 if (!interrupt_enables)
1292 return IRQ_NONE;
1293
1294 spin_lock(&host->lock);
1295
1296 /* Assuming one port per host controller */
1297
1298 ap = host->ports[0];
1299 if (ap) {
1300 sata_fsl_host_intr(ap);
1301 } else {
1302 dev_warn(host->dev, "interrupt on disabled port 0\n");
1303 }
1304
1305 iowrite32(interrupt_enables, hcr_base + HSTATUS);
1306 handled = 1;
1307
1308 spin_unlock(&host->lock);
1309
1310 return IRQ_RETVAL(handled);
1311 }
1312
1313 /*
1314 * Multiple ports are represented by multiple SATA controllers with
1315 * one port per controller
1316 */
sata_fsl_init_controller(struct ata_host * host)1317 static int sata_fsl_init_controller(struct ata_host *host)
1318 {
1319 struct sata_fsl_host_priv *host_priv = host->private_data;
1320 void __iomem *hcr_base = host_priv->hcr_base;
1321 u32 temp;
1322
1323 /*
1324 * NOTE : We cannot bring the controller online before setting
1325 * the CHBA, hence main controller initialization is done as
1326 * part of the port_start() callback
1327 */
1328
1329 /* sata controller to operate in enterprise mode */
1330 temp = ioread32(hcr_base + HCONTROL);
1331 iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL);
1332
1333 /* ack. any pending IRQs for this controller/port */
1334 temp = ioread32(hcr_base + HSTATUS);
1335 if (temp & 0x3F)
1336 iowrite32((temp & 0x3F), hcr_base + HSTATUS);
1337
1338 /* Keep interrupts disabled on the controller */
1339 temp = ioread32(hcr_base + HCONTROL);
1340 iowrite32((temp & ~0x3F), hcr_base + HCONTROL);
1341
1342 /* Disable interrupt coalescing control(icc), for the moment */
1343 dev_dbg(host->dev, "icc = 0x%x\n", ioread32(hcr_base + ICC));
1344 iowrite32(0x01000000, hcr_base + ICC);
1345
1346 /* clear error registers, SError is cleared by libATA */
1347 iowrite32(0x00000FFFF, hcr_base + CE);
1348 iowrite32(0x00000FFFF, hcr_base + DE);
1349
1350 /*
1351 * reset the number of command complete bits which will cause the
1352 * interrupt to be signaled
1353 */
1354 fsl_sata_set_irq_coalescing(host, intr_coalescing_count,
1355 intr_coalescing_ticks);
1356
1357 /*
1358 * host controller will be brought on-line, during xx_port_start()
1359 * callback, that should also initiate the OOB, COMINIT sequence
1360 */
1361
1362 dev_dbg(host->dev, "HStatus = 0x%x HControl = 0x%x\n",
1363 ioread32(hcr_base + HSTATUS), ioread32(hcr_base + HCONTROL));
1364
1365 return 0;
1366 }
1367
sata_fsl_host_stop(struct ata_host * host)1368 static void sata_fsl_host_stop(struct ata_host *host)
1369 {
1370 struct sata_fsl_host_priv *host_priv = host->private_data;
1371
1372 iounmap(host_priv->hcr_base);
1373 kfree(host_priv);
1374 }
1375
1376 /*
1377 * scsi mid-layer and libata interface structures
1378 */
1379 static const struct scsi_host_template sata_fsl_sht = {
1380 ATA_NCQ_SHT_QD("sata_fsl", SATA_FSL_QUEUE_DEPTH),
1381 .sg_tablesize = SATA_FSL_MAX_PRD_USABLE,
1382 .dma_boundary = ATA_DMA_BOUNDARY,
1383 };
1384
1385 static struct ata_port_operations sata_fsl_ops = {
1386 .inherits = &sata_pmp_port_ops,
1387
1388 .qc_defer = ata_std_qc_defer,
1389 .qc_prep = sata_fsl_qc_prep,
1390 .qc_issue = sata_fsl_qc_issue,
1391 .qc_fill_rtf = sata_fsl_qc_fill_rtf,
1392
1393 .scr_read = sata_fsl_scr_read,
1394 .scr_write = sata_fsl_scr_write,
1395
1396 .freeze = sata_fsl_freeze,
1397 .thaw = sata_fsl_thaw,
1398 .softreset = sata_fsl_softreset,
1399 .hardreset = sata_fsl_hardreset,
1400 .pmp_softreset = sata_fsl_softreset,
1401 .error_handler = sata_fsl_error_handler,
1402 .post_internal_cmd = sata_fsl_post_internal_cmd,
1403
1404 .port_start = sata_fsl_port_start,
1405 .port_stop = sata_fsl_port_stop,
1406
1407 .host_stop = sata_fsl_host_stop,
1408
1409 .pmp_attach = sata_fsl_pmp_attach,
1410 .pmp_detach = sata_fsl_pmp_detach,
1411 };
1412
1413 static const struct ata_port_info sata_fsl_port_info[] = {
1414 {
1415 .flags = SATA_FSL_HOST_FLAGS,
1416 .pio_mask = ATA_PIO4,
1417 .udma_mask = ATA_UDMA6,
1418 .port_ops = &sata_fsl_ops,
1419 },
1420 };
1421
sata_fsl_probe(struct platform_device * ofdev)1422 static int sata_fsl_probe(struct platform_device *ofdev)
1423 {
1424 int retval = -ENXIO;
1425 void __iomem *hcr_base = NULL;
1426 void __iomem *ssr_base = NULL;
1427 void __iomem *csr_base = NULL;
1428 struct sata_fsl_host_priv *host_priv = NULL;
1429 int irq;
1430 struct ata_host *host = NULL;
1431 u32 temp;
1432
1433 struct ata_port_info pi = sata_fsl_port_info[0];
1434 const struct ata_port_info *ppi[] = { &pi, NULL };
1435
1436 dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n");
1437
1438 hcr_base = of_iomap(ofdev->dev.of_node, 0);
1439 if (!hcr_base)
1440 goto error_exit_with_cleanup;
1441
1442 ssr_base = hcr_base + 0x100;
1443 csr_base = hcr_base + 0x140;
1444
1445 if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) {
1446 temp = ioread32(csr_base + TRANSCFG);
1447 temp = temp & 0xffffffe0;
1448 iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG);
1449 }
1450
1451 dev_dbg(&ofdev->dev, "@reset i/o = 0x%x\n",
1452 ioread32(csr_base + TRANSCFG));
1453
1454 host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL);
1455 if (!host_priv)
1456 goto error_exit_with_cleanup;
1457
1458 host_priv->hcr_base = hcr_base;
1459 host_priv->ssr_base = ssr_base;
1460 host_priv->csr_base = csr_base;
1461
1462 irq = platform_get_irq(ofdev, 0);
1463 if (irq < 0) {
1464 retval = irq;
1465 goto error_exit_with_cleanup;
1466 }
1467 host_priv->irq = irq;
1468
1469 if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2"))
1470 host_priv->data_snoop = DATA_SNOOP_ENABLE_V2;
1471 else
1472 host_priv->data_snoop = DATA_SNOOP_ENABLE_V1;
1473
1474 /* allocate host structure */
1475 host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS);
1476 if (!host) {
1477 retval = -ENOMEM;
1478 goto error_exit_with_cleanup;
1479 }
1480
1481 /* host->iomap is not used currently */
1482 host->private_data = host_priv;
1483
1484 /* initialize host controller */
1485 sata_fsl_init_controller(host);
1486
1487 /*
1488 * Now, register with libATA core, this will also initiate the
1489 * device discovery process, invoking our port_start() handler &
1490 * error_handler() to execute a dummy Softreset EH session
1491 */
1492 ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG,
1493 &sata_fsl_sht);
1494
1495 host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show;
1496 host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store;
1497 sysfs_attr_init(&host_priv->intr_coalescing.attr);
1498 host_priv->intr_coalescing.attr.name = "intr_coalescing";
1499 host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR;
1500 retval = device_create_file(host->dev, &host_priv->intr_coalescing);
1501 if (retval)
1502 goto error_exit_with_cleanup;
1503
1504 host_priv->rx_watermark.show = fsl_sata_rx_watermark_show;
1505 host_priv->rx_watermark.store = fsl_sata_rx_watermark_store;
1506 sysfs_attr_init(&host_priv->rx_watermark.attr);
1507 host_priv->rx_watermark.attr.name = "rx_watermark";
1508 host_priv->rx_watermark.attr.mode = S_IRUGO | S_IWUSR;
1509 retval = device_create_file(host->dev, &host_priv->rx_watermark);
1510 if (retval) {
1511 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1512 goto error_exit_with_cleanup;
1513 }
1514
1515 return 0;
1516
1517 error_exit_with_cleanup:
1518
1519 if (host)
1520 ata_host_detach(host);
1521
1522 if (hcr_base)
1523 iounmap(hcr_base);
1524 kfree(host_priv);
1525
1526 return retval;
1527 }
1528
sata_fsl_remove(struct platform_device * ofdev)1529 static void sata_fsl_remove(struct platform_device *ofdev)
1530 {
1531 struct ata_host *host = platform_get_drvdata(ofdev);
1532 struct sata_fsl_host_priv *host_priv = host->private_data;
1533
1534 device_remove_file(&ofdev->dev, &host_priv->intr_coalescing);
1535 device_remove_file(&ofdev->dev, &host_priv->rx_watermark);
1536
1537 ata_host_detach(host);
1538 }
1539
1540 #ifdef CONFIG_PM_SLEEP
sata_fsl_suspend(struct platform_device * op,pm_message_t state)1541 static int sata_fsl_suspend(struct platform_device *op, pm_message_t state)
1542 {
1543 struct ata_host *host = platform_get_drvdata(op);
1544
1545 ata_host_suspend(host, state);
1546 return 0;
1547 }
1548
sata_fsl_resume(struct platform_device * op)1549 static int sata_fsl_resume(struct platform_device *op)
1550 {
1551 struct ata_host *host = platform_get_drvdata(op);
1552 struct sata_fsl_host_priv *host_priv = host->private_data;
1553 int ret;
1554 void __iomem *hcr_base = host_priv->hcr_base;
1555 struct ata_port *ap = host->ports[0];
1556 struct sata_fsl_port_priv *pp = ap->private_data;
1557
1558 ret = sata_fsl_init_controller(host);
1559 if (ret) {
1560 dev_err(&op->dev, "Error initializing hardware\n");
1561 return ret;
1562 }
1563
1564 /* Recovery the CHBA register in host controller cmd register set */
1565 iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA);
1566
1567 iowrite32((ioread32(hcr_base + HCONTROL)
1568 | HCONTROL_ONLINE_PHY_RST
1569 | HCONTROL_SNOOP_ENABLE
1570 | HCONTROL_PMP_ATTACHED),
1571 hcr_base + HCONTROL);
1572
1573 ata_host_resume(host);
1574 return 0;
1575 }
1576 #endif
1577
1578 static const struct of_device_id fsl_sata_match[] = {
1579 { .compatible = "fsl,pq-sata", },
1580 { .compatible = "fsl,pq-sata-v2", },
1581 { /* sentinel */ }
1582 };
1583
1584 MODULE_DEVICE_TABLE(of, fsl_sata_match);
1585
1586 static struct platform_driver fsl_sata_driver = {
1587 .driver = {
1588 .name = "fsl-sata",
1589 .of_match_table = fsl_sata_match,
1590 },
1591 .probe = sata_fsl_probe,
1592 .remove_new = sata_fsl_remove,
1593 #ifdef CONFIG_PM_SLEEP
1594 .suspend = sata_fsl_suspend,
1595 .resume = sata_fsl_resume,
1596 #endif
1597 };
1598
1599 module_platform_driver(fsl_sata_driver);
1600
1601 MODULE_LICENSE("GPL");
1602 MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor");
1603 MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver");
1604 MODULE_VERSION("1.10");
1605