1 /* SPDX-License-Identifier: GPL-2.0-or-later */
2 /*
3 * Universal Flash Storage Host controller driver
4 * Copyright (C) 2011-2013 Samsung India Software Operations
5 *
6 * Authors:
7 * Santosh Yaraganavi <santosh.sy@samsung.com>
8 * Vinayak Holikatti <h.vinayak@samsung.com>
9 */
10
11 #ifndef _UFSHCI_H
12 #define _UFSHCI_H
13
14 #include <linux/types.h>
15 #include <ufs/ufs.h>
16
17 enum {
18 TASK_REQ_UPIU_SIZE_DWORDS = 8,
19 TASK_RSP_UPIU_SIZE_DWORDS = 8,
20 ALIGNED_UPIU_SIZE = 512,
21 };
22
23 /* UFSHCI Registers */
24 enum {
25 REG_CONTROLLER_CAPABILITIES = 0x00,
26 REG_MCQCAP = 0x04,
27 REG_UFS_VERSION = 0x08,
28 REG_CONTROLLER_DEV_ID = 0x10,
29 REG_CONTROLLER_PROD_ID = 0x14,
30 REG_AUTO_HIBERNATE_IDLE_TIMER = 0x18,
31 REG_INTERRUPT_STATUS = 0x20,
32 REG_INTERRUPT_ENABLE = 0x24,
33 REG_CONTROLLER_STATUS = 0x30,
34 REG_CONTROLLER_ENABLE = 0x34,
35 REG_UIC_ERROR_CODE_PHY_ADAPTER_LAYER = 0x38,
36 REG_UIC_ERROR_CODE_DATA_LINK_LAYER = 0x3C,
37 REG_UIC_ERROR_CODE_NETWORK_LAYER = 0x40,
38 REG_UIC_ERROR_CODE_TRANSPORT_LAYER = 0x44,
39 REG_UIC_ERROR_CODE_DME = 0x48,
40 REG_UTP_TRANSFER_REQ_INT_AGG_CONTROL = 0x4C,
41 REG_UTP_TRANSFER_REQ_LIST_BASE_L = 0x50,
42 REG_UTP_TRANSFER_REQ_LIST_BASE_H = 0x54,
43 REG_UTP_TRANSFER_REQ_DOOR_BELL = 0x58,
44 REG_UTP_TRANSFER_REQ_LIST_CLEAR = 0x5C,
45 REG_UTP_TRANSFER_REQ_LIST_RUN_STOP = 0x60,
46 REG_UTP_TASK_REQ_LIST_BASE_L = 0x70,
47 REG_UTP_TASK_REQ_LIST_BASE_H = 0x74,
48 REG_UTP_TASK_REQ_DOOR_BELL = 0x78,
49 REG_UTP_TASK_REQ_LIST_CLEAR = 0x7C,
50 REG_UTP_TASK_REQ_LIST_RUN_STOP = 0x80,
51 REG_UIC_COMMAND = 0x90,
52 REG_UIC_COMMAND_ARG_1 = 0x94,
53 REG_UIC_COMMAND_ARG_2 = 0x98,
54 REG_UIC_COMMAND_ARG_3 = 0x9C,
55
56 UFSHCI_REG_SPACE_SIZE = 0xA0,
57
58 REG_UFS_CCAP = 0x100,
59 REG_UFS_CRYPTOCAP = 0x104,
60
61 REG_UFS_MEM_CFG = 0x300,
62 REG_UFS_MCQ_CFG = 0x380,
63 REG_UFS_ESILBA = 0x384,
64 REG_UFS_ESIUBA = 0x388,
65 UFSHCI_CRYPTO_REG_SPACE_SIZE = 0x400,
66 };
67
68 /* Controller capability masks */
69 enum {
70 MASK_TRANSFER_REQUESTS_SLOTS = 0x0000001F,
71 MASK_TASK_MANAGEMENT_REQUEST_SLOTS = 0x00070000,
72 MASK_EHSLUTRD_SUPPORTED = 0x00400000,
73 MASK_AUTO_HIBERN8_SUPPORT = 0x00800000,
74 MASK_64_ADDRESSING_SUPPORT = 0x01000000,
75 MASK_OUT_OF_ORDER_DATA_DELIVERY_SUPPORT = 0x02000000,
76 MASK_UIC_DME_TEST_MODE_SUPPORT = 0x04000000,
77 MASK_CRYPTO_SUPPORT = 0x10000000,
78 MASK_LSDB_SUPPORT = 0x20000000,
79 MASK_MCQ_SUPPORT = 0x40000000,
80 };
81
82 /* MCQ capability mask */
83 enum {
84 MASK_EXT_IID_SUPPORT = 0x00000400,
85 };
86
87 enum {
88 REG_SQATTR = 0x0,
89 REG_SQLBA = 0x4,
90 REG_SQUBA = 0x8,
91 REG_SQDAO = 0xC,
92 REG_SQISAO = 0x10,
93
94 REG_CQATTR = 0x20,
95 REG_CQLBA = 0x24,
96 REG_CQUBA = 0x28,
97 REG_CQDAO = 0x2C,
98 REG_CQISAO = 0x30,
99 };
100
101 enum {
102 REG_SQHP = 0x0,
103 REG_SQTP = 0x4,
104 REG_SQRTC = 0x8,
105 REG_SQCTI = 0xC,
106 REG_SQRTS = 0x10,
107 };
108
109 enum {
110 REG_CQHP = 0x0,
111 REG_CQTP = 0x4,
112 };
113
114 enum {
115 REG_CQIS = 0x0,
116 REG_CQIE = 0x4,
117 };
118
119 enum {
120 SQ_START = 0x0,
121 SQ_STOP = 0x1,
122 SQ_ICU = 0x2,
123 };
124
125 enum {
126 SQ_STS = 0x1,
127 SQ_CUS = 0x2,
128 };
129
130 #define SQ_ICU_ERR_CODE_MASK GENMASK(7, 4)
131 #define UFS_MASK(mask, offset) ((mask) << (offset))
132
133 /* UFS Version 08h */
134 #define MINOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 0)
135 #define MAJOR_VERSION_NUM_MASK UFS_MASK(0xFFFF, 16)
136
137 #define UFSHCD_NUM_RESERVED 1
138 /*
139 * Controller UFSHCI version
140 * - 2.x and newer use the following scheme:
141 * major << 8 + minor << 4
142 * - 1.x has been converted to match this in
143 * ufshcd_get_ufs_version()
144 */
ufshci_version(u32 major,u32 minor)145 static inline u32 ufshci_version(u32 major, u32 minor)
146 {
147 return (major << 8) + (minor << 4);
148 }
149
150 /*
151 * HCDDID - Host Controller Identification Descriptor
152 * - Device ID and Device Class 10h
153 */
154 #define DEVICE_CLASS UFS_MASK(0xFFFF, 0)
155 #define DEVICE_ID UFS_MASK(0xFF, 24)
156
157 /*
158 * HCPMID - Host Controller Identification Descriptor
159 * - Product/Manufacturer ID 14h
160 */
161 #define MANUFACTURE_ID_MASK UFS_MASK(0xFFFF, 0)
162 #define PRODUCT_ID_MASK UFS_MASK(0xFFFF, 16)
163
164 /* AHIT - Auto-Hibernate Idle Timer */
165 #define UFSHCI_AHIBERN8_TIMER_MASK GENMASK(9, 0)
166 #define UFSHCI_AHIBERN8_SCALE_MASK GENMASK(12, 10)
167 #define UFSHCI_AHIBERN8_SCALE_FACTOR 10
168 #define UFSHCI_AHIBERN8_MAX (1023 * 100000)
169
170 /*
171 * IS - Interrupt Status - 20h
172 */
173 #define UTP_TRANSFER_REQ_COMPL 0x1
174 #define UIC_DME_END_PT_RESET 0x2
175 #define UIC_ERROR 0x4
176 #define UIC_TEST_MODE 0x8
177 #define UIC_POWER_MODE 0x10
178 #define UIC_HIBERNATE_EXIT 0x20
179 #define UIC_HIBERNATE_ENTER 0x40
180 #define UIC_LINK_LOST 0x80
181 #define UIC_LINK_STARTUP 0x100
182 #define UTP_TASK_REQ_COMPL 0x200
183 #define UIC_COMMAND_COMPL 0x400
184 #define DEVICE_FATAL_ERROR 0x800
185 #define CONTROLLER_FATAL_ERROR 0x10000
186 #define SYSTEM_BUS_FATAL_ERROR 0x20000
187 #define CRYPTO_ENGINE_FATAL_ERROR 0x40000
188 #define MCQ_CQ_EVENT_STATUS 0x100000
189
190 #define UFSHCD_UIC_HIBERN8_MASK (UIC_HIBERNATE_ENTER |\
191 UIC_HIBERNATE_EXIT)
192
193 #define UFSHCD_UIC_PWR_MASK (UFSHCD_UIC_HIBERN8_MASK |\
194 UIC_POWER_MODE)
195
196 #define UFSHCD_UIC_MASK (UIC_COMMAND_COMPL | UFSHCD_UIC_PWR_MASK)
197
198 #define UFSHCD_ERROR_MASK (UIC_ERROR | INT_FATAL_ERRORS)
199
200 #define INT_FATAL_ERRORS (DEVICE_FATAL_ERROR |\
201 CONTROLLER_FATAL_ERROR |\
202 SYSTEM_BUS_FATAL_ERROR |\
203 CRYPTO_ENGINE_FATAL_ERROR |\
204 UIC_LINK_LOST)
205
206 /* HCS - Host Controller Status 30h */
207 #define DEVICE_PRESENT 0x1
208 #define UTP_TRANSFER_REQ_LIST_READY 0x2
209 #define UTP_TASK_REQ_LIST_READY 0x4
210 #define UIC_COMMAND_READY 0x8
211 #define HOST_ERROR_INDICATOR 0x10
212 #define DEVICE_ERROR_INDICATOR 0x20
213 #define UIC_POWER_MODE_CHANGE_REQ_STATUS_MASK UFS_MASK(0x7, 8)
214
215 #define UFSHCD_STATUS_READY (UTP_TRANSFER_REQ_LIST_READY |\
216 UTP_TASK_REQ_LIST_READY |\
217 UIC_COMMAND_READY)
218
219 enum {
220 PWR_OK = 0x0,
221 PWR_LOCAL = 0x01,
222 PWR_REMOTE = 0x02,
223 PWR_BUSY = 0x03,
224 PWR_ERROR_CAP = 0x04,
225 PWR_FATAL_ERROR = 0x05,
226 };
227
228 /* HCE - Host Controller Enable 34h */
229 #define CONTROLLER_ENABLE 0x1
230 #define CONTROLLER_DISABLE 0x0
231 #define CRYPTO_GENERAL_ENABLE 0x2
232
233 /* UECPA - Host UIC Error Code PHY Adapter Layer 38h */
234 #define UIC_PHY_ADAPTER_LAYER_ERROR 0x80000000
235 #define UIC_PHY_ADAPTER_LAYER_ERROR_CODE_MASK 0x1F
236 #define UIC_PHY_ADAPTER_LAYER_LANE_ERR_MASK 0xF
237 #define UIC_PHY_ADAPTER_LAYER_GENERIC_ERROR 0x10
238
239 /* UECDL - Host UIC Error Code Data Link Layer 3Ch */
240 #define UIC_DATA_LINK_LAYER_ERROR 0x80000000
241 #define UIC_DATA_LINK_LAYER_ERROR_CODE_MASK 0xFFFF
242 #define UIC_DATA_LINK_LAYER_ERROR_TCX_REP_TIMER_EXP 0x2
243 #define UIC_DATA_LINK_LAYER_ERROR_AFCX_REQ_TIMER_EXP 0x4
244 #define UIC_DATA_LINK_LAYER_ERROR_FCX_PRO_TIMER_EXP 0x8
245 #define UIC_DATA_LINK_LAYER_ERROR_RX_BUF_OF 0x20
246 #define UIC_DATA_LINK_LAYER_ERROR_PA_INIT 0x2000
247 #define UIC_DATA_LINK_LAYER_ERROR_NAC_RECEIVED 0x0001
248 #define UIC_DATA_LINK_LAYER_ERROR_TCx_REPLAY_TIMEOUT 0x0002
249
250 /* UECN - Host UIC Error Code Network Layer 40h */
251 #define UIC_NETWORK_LAYER_ERROR 0x80000000
252 #define UIC_NETWORK_LAYER_ERROR_CODE_MASK 0x7
253 #define UIC_NETWORK_UNSUPPORTED_HEADER_TYPE 0x1
254 #define UIC_NETWORK_BAD_DEVICEID_ENC 0x2
255 #define UIC_NETWORK_LHDR_TRAP_PACKET_DROPPING 0x4
256
257 /* UECT - Host UIC Error Code Transport Layer 44h */
258 #define UIC_TRANSPORT_LAYER_ERROR 0x80000000
259 #define UIC_TRANSPORT_LAYER_ERROR_CODE_MASK 0x7F
260 #define UIC_TRANSPORT_UNSUPPORTED_HEADER_TYPE 0x1
261 #define UIC_TRANSPORT_UNKNOWN_CPORTID 0x2
262 #define UIC_TRANSPORT_NO_CONNECTION_RX 0x4
263 #define UIC_TRANSPORT_CONTROLLED_SEGMENT_DROPPING 0x8
264 #define UIC_TRANSPORT_BAD_TC 0x10
265 #define UIC_TRANSPORT_E2E_CREDIT_OVERFOW 0x20
266 #define UIC_TRANSPORT_SAFETY_VALUE_DROPPING 0x40
267
268 /* UECDME - Host UIC Error Code DME 48h */
269 #define UIC_DME_ERROR 0x80000000
270 #define UIC_DME_ERROR_CODE_MASK 0x1
271
272 /* UTRIACR - Interrupt Aggregation control register - 0x4Ch */
273 #define INT_AGGR_TIMEOUT_VAL_MASK 0xFF
274 #define INT_AGGR_COUNTER_THRESHOLD_MASK UFS_MASK(0x1F, 8)
275 #define INT_AGGR_COUNTER_AND_TIMER_RESET 0x10000
276 #define INT_AGGR_STATUS_BIT 0x100000
277 #define INT_AGGR_PARAM_WRITE 0x1000000
278 #define INT_AGGR_ENABLE 0x80000000
279
280 /* UTRLRSR - UTP Transfer Request Run-Stop Register 60h */
281 #define UTP_TRANSFER_REQ_LIST_RUN_STOP_BIT 0x1
282
283 /* UTMRLRSR - UTP Task Management Request Run-Stop Register 80h */
284 #define UTP_TASK_REQ_LIST_RUN_STOP_BIT 0x1
285
286 /* CQISy - CQ y Interrupt Status Register */
287 #define UFSHCD_MCQ_CQIS_TAIL_ENT_PUSH_STS 0x1
288
289 /* UICCMD - UIC Command */
290 #define COMMAND_OPCODE_MASK 0xFF
291 #define GEN_SELECTOR_INDEX_MASK 0xFFFF
292
293 #define MIB_ATTRIBUTE_MASK UFS_MASK(0xFFFF, 16)
294 #define RESET_LEVEL 0xFF
295
296 #define ATTR_SET_TYPE_MASK UFS_MASK(0xFF, 16)
297 #define CONFIG_RESULT_CODE_MASK 0xFF
298 #define GENERIC_ERROR_CODE_MASK 0xFF
299
300 /* GenSelectorIndex calculation macros for M-PHY attributes */
301 #define UIC_ARG_MPHY_TX_GEN_SEL_INDEX(lane) (lane)
302 #define UIC_ARG_MPHY_RX_GEN_SEL_INDEX(lane) (PA_MAXDATALANES + (lane))
303
304 #define UIC_ARG_MIB_SEL(attr, sel) ((((attr) & 0xFFFF) << 16) |\
305 ((sel) & 0xFFFF))
306 #define UIC_ARG_MIB(attr) UIC_ARG_MIB_SEL(attr, 0)
307 #define UIC_ARG_ATTR_TYPE(t) (((t) & 0xFF) << 16)
308 #define UIC_GET_ATTR_ID(v) (((v) >> 16) & 0xFFFF)
309
310 /* Link Status*/
311 enum link_status {
312 UFSHCD_LINK_IS_DOWN = 1,
313 UFSHCD_LINK_IS_UP = 2,
314 };
315
316 /* UIC Commands */
317 enum uic_cmd_dme {
318 UIC_CMD_DME_GET = 0x01,
319 UIC_CMD_DME_SET = 0x02,
320 UIC_CMD_DME_PEER_GET = 0x03,
321 UIC_CMD_DME_PEER_SET = 0x04,
322 UIC_CMD_DME_POWERON = 0x10,
323 UIC_CMD_DME_POWEROFF = 0x11,
324 UIC_CMD_DME_ENABLE = 0x12,
325 UIC_CMD_DME_RESET = 0x14,
326 UIC_CMD_DME_END_PT_RST = 0x15,
327 UIC_CMD_DME_LINK_STARTUP = 0x16,
328 UIC_CMD_DME_HIBER_ENTER = 0x17,
329 UIC_CMD_DME_HIBER_EXIT = 0x18,
330 UIC_CMD_DME_TEST_MODE = 0x1A,
331 };
332
333 /* UIC Config result code / Generic error code */
334 enum {
335 UIC_CMD_RESULT_SUCCESS = 0x00,
336 UIC_CMD_RESULT_INVALID_ATTR = 0x01,
337 UIC_CMD_RESULT_FAILURE = 0x01,
338 UIC_CMD_RESULT_INVALID_ATTR_VALUE = 0x02,
339 UIC_CMD_RESULT_READ_ONLY_ATTR = 0x03,
340 UIC_CMD_RESULT_WRITE_ONLY_ATTR = 0x04,
341 UIC_CMD_RESULT_BAD_INDEX = 0x05,
342 UIC_CMD_RESULT_LOCKED_ATTR = 0x06,
343 UIC_CMD_RESULT_BAD_TEST_FEATURE_INDEX = 0x07,
344 UIC_CMD_RESULT_PEER_COMM_FAILURE = 0x08,
345 UIC_CMD_RESULT_BUSY = 0x09,
346 UIC_CMD_RESULT_DME_FAILURE = 0x0A,
347 };
348
349 #define MASK_UIC_COMMAND_RESULT 0xFF
350
351 #define INT_AGGR_COUNTER_THLD_VAL(c) (((c) & 0x1F) << 8)
352 #define INT_AGGR_TIMEOUT_VAL(t) (((t) & 0xFF) << 0)
353
354 /* Interrupt disable masks */
355 enum {
356 /* Interrupt disable mask for UFSHCI v1.0 */
357 INTERRUPT_MASK_ALL_VER_10 = 0x30FFF,
358 INTERRUPT_MASK_RW_VER_10 = 0x30000,
359
360 /* Interrupt disable mask for UFSHCI v1.1 */
361 INTERRUPT_MASK_ALL_VER_11 = 0x31FFF,
362
363 /* Interrupt disable mask for UFSHCI v2.1 */
364 INTERRUPT_MASK_ALL_VER_21 = 0x71FFF,
365 };
366
367 /* CCAP - Crypto Capability 100h */
368 union ufs_crypto_capabilities {
369 __le32 reg_val;
370 struct {
371 u8 num_crypto_cap;
372 u8 config_count;
373 u8 reserved;
374 u8 config_array_ptr;
375 };
376 };
377
378 enum ufs_crypto_key_size {
379 UFS_CRYPTO_KEY_SIZE_INVALID = 0x0,
380 UFS_CRYPTO_KEY_SIZE_128 = 0x1,
381 UFS_CRYPTO_KEY_SIZE_192 = 0x2,
382 UFS_CRYPTO_KEY_SIZE_256 = 0x3,
383 UFS_CRYPTO_KEY_SIZE_512 = 0x4,
384 };
385
386 enum ufs_crypto_alg {
387 UFS_CRYPTO_ALG_AES_XTS = 0x0,
388 UFS_CRYPTO_ALG_BITLOCKER_AES_CBC = 0x1,
389 UFS_CRYPTO_ALG_AES_ECB = 0x2,
390 UFS_CRYPTO_ALG_ESSIV_AES_CBC = 0x3,
391 };
392
393 /* x-CRYPTOCAP - Crypto Capability X */
394 union ufs_crypto_cap_entry {
395 __le32 reg_val;
396 struct {
397 u8 algorithm_id;
398 u8 sdus_mask; /* Supported data unit size mask */
399 u8 key_size;
400 u8 reserved;
401 };
402 };
403
404 #define UFS_CRYPTO_CONFIGURATION_ENABLE (1 << 7)
405 #define UFS_CRYPTO_KEY_MAX_SIZE 64
406 /* x-CRYPTOCFG - Crypto Configuration X */
407 union ufs_crypto_cfg_entry {
408 __le32 reg_val[32];
409 struct {
410 u8 crypto_key[UFS_CRYPTO_KEY_MAX_SIZE];
411 u8 data_unit_size;
412 u8 crypto_cap_idx;
413 u8 reserved_1;
414 u8 config_enable;
415 u8 reserved_multi_host;
416 u8 reserved_2;
417 u8 vsb[2];
418 u8 reserved_3[56];
419 };
420 };
421
422 /*
423 * Request Descriptor Definitions
424 */
425
426 /* Transfer request command type */
427 enum {
428 UTP_CMD_TYPE_SCSI = 0x0,
429 UTP_CMD_TYPE_UFS = 0x1,
430 UTP_CMD_TYPE_DEV_MANAGE = 0x2,
431 };
432
433 /* To accommodate UFS2.0 required Command type */
434 enum {
435 UTP_CMD_TYPE_UFS_STORAGE = 0x1,
436 };
437
438 enum {
439 UTP_SCSI_COMMAND = 0x00000000,
440 UTP_NATIVE_UFS_COMMAND = 0x10000000,
441 UTP_DEVICE_MANAGEMENT_FUNCTION = 0x20000000,
442 };
443
444 /* UTP Transfer Request Data Direction (DD) */
445 enum utp_data_direction {
446 UTP_NO_DATA_TRANSFER = 0,
447 UTP_HOST_TO_DEVICE = 1,
448 UTP_DEVICE_TO_HOST = 2,
449 };
450
451 /* Overall command status values */
452 enum utp_ocs {
453 OCS_SUCCESS = 0x0,
454 OCS_INVALID_CMD_TABLE_ATTR = 0x1,
455 OCS_INVALID_PRDT_ATTR = 0x2,
456 OCS_MISMATCH_DATA_BUF_SIZE = 0x3,
457 OCS_MISMATCH_RESP_UPIU_SIZE = 0x4,
458 OCS_PEER_COMM_FAILURE = 0x5,
459 OCS_ABORTED = 0x6,
460 OCS_FATAL_ERROR = 0x7,
461 OCS_DEVICE_FATAL_ERROR = 0x8,
462 OCS_INVALID_CRYPTO_CONFIG = 0x9,
463 OCS_GENERAL_CRYPTO_ERROR = 0xA,
464 OCS_INVALID_COMMAND_STATUS = 0x0F,
465 };
466
467 enum {
468 MASK_OCS = 0x0F,
469 };
470
471 /* The maximum length of the data byte count field in the PRDT is 256KB */
472 #define PRDT_DATA_BYTE_COUNT_MAX SZ_256K
473 /* The granularity of the data byte count field in the PRDT is 32-bit */
474 #define PRDT_DATA_BYTE_COUNT_PAD 4
475
476 /**
477 * struct ufshcd_sg_entry - UFSHCI PRD Entry
478 * @addr: Physical address; DW-0 and DW-1.
479 * @reserved: Reserved for future use DW-2
480 * @size: size of physical segment DW-3
481 */
482 struct ufshcd_sg_entry {
483 __le64 addr;
484 __le32 reserved;
485 __le32 size;
486 /*
487 * followed by variant-specific fields if
488 * CONFIG_SCSI_UFS_VARIABLE_SG_ENTRY_SIZE has been defined.
489 */
490 };
491
492 /**
493 * struct utp_transfer_cmd_desc - UTP Command Descriptor (UCD)
494 * @command_upiu: Command UPIU Frame address
495 * @response_upiu: Response UPIU Frame address
496 * @prd_table: Physical Region Descriptor: an array of SG_ALL struct
497 * ufshcd_sg_entry's. Variant-specific fields may be present after each.
498 */
499 struct utp_transfer_cmd_desc {
500 u8 command_upiu[ALIGNED_UPIU_SIZE];
501 u8 response_upiu[ALIGNED_UPIU_SIZE];
502 u8 prd_table[];
503 };
504
505 /**
506 * struct request_desc_header - Descriptor Header common to both UTRD and UTMRD
507 */
508 struct request_desc_header {
509 u8 cci;
510 u8 ehs_length;
511 #if defined(__BIG_ENDIAN)
512 u8 enable_crypto:1;
513 u8 reserved2:7;
514
515 u8 command_type:4;
516 u8 reserved1:1;
517 u8 data_direction:2;
518 u8 interrupt:1;
519 #elif defined(__LITTLE_ENDIAN)
520 u8 reserved2:7;
521 u8 enable_crypto:1;
522
523 u8 interrupt:1;
524 u8 data_direction:2;
525 u8 reserved1:1;
526 u8 command_type:4;
527 #else
528 #error
529 #endif
530
531 __le32 dunl;
532 u8 ocs;
533 u8 cds;
534 __le16 ldbc;
535 __le32 dunu;
536 };
537
538 static_assert(sizeof(struct request_desc_header) == 16);
539
540 /**
541 * struct utp_transfer_req_desc - UTP Transfer Request Descriptor (UTRD)
542 * @header: UTRD header DW-0 to DW-3
543 * @command_desc_base_addr: UCD base address DW 4-5
544 * @response_upiu_length: response UPIU length DW-6
545 * @response_upiu_offset: response UPIU offset DW-6
546 * @prd_table_length: Physical region descriptor length DW-7
547 * @prd_table_offset: Physical region descriptor offset DW-7
548 */
549 struct utp_transfer_req_desc {
550
551 /* DW 0-3 */
552 struct request_desc_header header;
553
554 /* DW 4-5*/
555 __le64 command_desc_base_addr;
556
557 /* DW 6 */
558 __le16 response_upiu_length;
559 __le16 response_upiu_offset;
560
561 /* DW 7 */
562 __le16 prd_table_length;
563 __le16 prd_table_offset;
564 };
565
566 /* MCQ Completion Queue Entry */
567 struct cq_entry {
568 /* DW 0-1 */
569 __le64 command_desc_base_addr;
570
571 /* DW 2 */
572 __le16 response_upiu_length;
573 __le16 response_upiu_offset;
574
575 /* DW 3 */
576 __le16 prd_table_length;
577 __le16 prd_table_offset;
578
579 /* DW 4 */
580 __le32 status;
581
582 /* DW 5-7 */
583 __le32 reserved[3];
584 };
585
586 static_assert(sizeof(struct cq_entry) == 32);
587
588 /*
589 * UTMRD structure.
590 */
591 struct utp_task_req_desc {
592 /* DW 0-3 */
593 struct request_desc_header header;
594
595 /* DW 4-11 - Task request UPIU structure */
596 struct {
597 struct utp_upiu_header req_header;
598 __be32 input_param1;
599 __be32 input_param2;
600 __be32 input_param3;
601 __be32 __reserved1[2];
602 } upiu_req;
603
604 /* DW 12-19 - Task Management Response UPIU structure */
605 struct {
606 struct utp_upiu_header rsp_header;
607 __be32 output_param1;
608 __be32 output_param2;
609 __be32 __reserved2[3];
610 } upiu_rsp;
611 };
612
613 #endif /* End of Header */
614