1 /*
2 * QEMU PowerPC XIVE2 internal structure definitions (POWER10)
3 *
4 * Copyright (c) 2019-2022, IBM Corporation.
5 *
6 * This code is licensed under the GPL version 2 or later. See the
7 * COPYING file in the top-level directory.
8 */
9
10 #ifndef PPC_XIVE2_REGS_H
11 #define PPC_XIVE2_REGS_H
12
13 #include "qemu/bswap.h"
14
15 /*
16 * Thread Interrupt Management Area (TIMA)
17 *
18 * In Gen1 mode (P9 compat mode) word 2 is the same. However in Gen2
19 * mode (P10), the CAM line is slightly different as the VP space was
20 * increased.
21 */
22 #define TM2_W2_VALID PPC_BIT32(0)
23 #define TM2_W2_HW PPC_BIT32(1)
24 #define TM2_QW0W2_VU TM2_W2_VALID
25 #define TM2_QW0W2_LOGIC_SERV PPC_BITMASK32(4, 31)
26 #define TM2_QW1W2_VO TM2_W2_VALID
27 #define TM2_QW1W2_HO TM2_W2_HW
28 #define TM2_QW1W2_OS_CAM PPC_BITMASK32(4, 31)
29 #define TM2_QW2W2_VP TM2_W2_VALID
30 #define TM2_QW2W2_HP TM2_W2_HW
31 #define TM2_QW2W2_POOL_CAM PPC_BITMASK32(4, 31)
32 #define TM2_QW3W2_VT TM2_W2_VALID
33 #define TM2_QW3W2_HT TM2_W2_HW
34 #define TM2_QW3W2_LP PPC_BIT32(6)
35 #define TM2_QW3W2_LE PPC_BIT32(7)
36
37 /*
38 * Event Assignment Structure (EAS)
39 */
40
41 typedef struct Xive2Eas {
42 uint64_t w;
43 #define EAS2_VALID PPC_BIT(0)
44 #define EAS2_END_BLOCK PPC_BITMASK(4, 7) /* Destination EQ block# */
45 #define EAS2_END_INDEX PPC_BITMASK(8, 31) /* Destination EQ index */
46 #define EAS2_MASKED PPC_BIT(32) /* Masked */
47 #define EAS2_END_DATA PPC_BITMASK(33, 63) /* written to the EQ */
48 } Xive2Eas;
49
50 #define xive2_eas_is_valid(eas) (be64_to_cpu((eas)->w) & EAS2_VALID)
51 #define xive2_eas_is_masked(eas) (be64_to_cpu((eas)->w) & EAS2_MASKED)
52
53 void xive2_eas_pic_print_info(Xive2Eas *eas, uint32_t lisn, GString *buf);
54
55 /*
56 * Event Notifification Descriptor (END)
57 */
58
59 typedef struct Xive2End {
60 uint32_t w0;
61 #define END2_W0_VALID PPC_BIT32(0) /* "v" bit */
62 #define END2_W0_ENQUEUE PPC_BIT32(5) /* "q" bit */
63 #define END2_W0_UCOND_NOTIFY PPC_BIT32(6) /* "n" bit */
64 #define END2_W0_SILENT_ESCALATE PPC_BIT32(7) /* "s" bit */
65 #define END2_W0_BACKLOG PPC_BIT32(8) /* "b" bit */
66 #define END2_W0_PRECL_ESC_CTL PPC_BIT32(9) /* "p" bit */
67 #define END2_W0_UNCOND_ESCALATE PPC_BIT32(10) /* "u" bit */
68 #define END2_W0_ESCALATE_CTL PPC_BIT32(11) /* "e" bit */
69 #define END2_W0_ADAPTIVE_ESC PPC_BIT32(12) /* "a" bit */
70 #define END2_W0_ESCALATE_END PPC_BIT32(13) /* "N" bit */
71 #define END2_W0_FIRMWARE1 PPC_BIT32(16) /* Owned by FW */
72 #define END2_W0_FIRMWARE2 PPC_BIT32(17) /* Owned by FW */
73 #define END2_W0_AEC_SIZE PPC_BITMASK32(18, 19)
74 #define END2_W0_AEG_SIZE PPC_BITMASK32(20, 23)
75 #define END2_W0_EQ_VG_PREDICT PPC_BITMASK32(24, 31) /* Owned by HW */
76 uint32_t w1;
77 #define END2_W1_ESn PPC_BITMASK32(0, 1)
78 #define END2_W1_ESn_P PPC_BIT32(0)
79 #define END2_W1_ESn_Q PPC_BIT32(1)
80 #define END2_W1_ESe PPC_BITMASK32(2, 3)
81 #define END2_W1_ESe_P PPC_BIT32(2)
82 #define END2_W1_ESe_Q PPC_BIT32(3)
83 #define END2_W1_GEN_FLIPPED PPC_BIT32(8)
84 #define END2_W1_GENERATION PPC_BIT32(9)
85 #define END2_W1_PAGE_OFF PPC_BITMASK32(10, 31)
86 uint32_t w2;
87 #define END2_W2_RESERVED PPC_BITMASK32(4, 7)
88 #define END2_W2_EQ_ADDR_HI PPC_BITMASK32(8, 31)
89 uint32_t w3;
90 #define END2_W3_EQ_ADDR_LO PPC_BITMASK32(0, 24)
91 #define END2_W3_QSIZE PPC_BITMASK32(28, 31)
92 uint32_t w4;
93 #define END2_W4_END_BLOCK PPC_BITMASK32(4, 7)
94 #define END2_W4_ESC_END_INDEX PPC_BITMASK32(8, 31)
95 #define END2_W4_ESB_BLOCK PPC_BITMASK32(0, 3)
96 #define END2_W4_ESC_ESB_INDEX PPC_BITMASK32(4, 31)
97 uint32_t w5;
98 #define END2_W5_ESC_END_DATA PPC_BITMASK32(1, 31)
99 uint32_t w6;
100 #define END2_W6_FORMAT_BIT PPC_BIT32(0)
101 #define END2_W6_IGNORE PPC_BIT32(1)
102 #define END2_W6_CROWD PPC_BIT32(2)
103 #define END2_W6_VP_BLOCK PPC_BITMASK32(4, 7)
104 #define END2_W6_VP_OFFSET PPC_BITMASK32(8, 31)
105 #define END2_W6_VP_OFFSET_GEN1 PPC_BITMASK32(13, 31)
106 uint32_t w7;
107 #define END2_W7_TOPO PPC_BITMASK32(0, 3) /* Owned by HW */
108 #define END2_W7_F0_PRIORITY PPC_BITMASK32(8, 15)
109 #define END2_W7_F1_LOG_SERVER_ID PPC_BITMASK32(4, 31)
110 } Xive2End;
111
112 #define xive2_end_is_valid(end) (be32_to_cpu((end)->w0) & END2_W0_VALID)
113 #define xive2_end_is_enqueue(end) (be32_to_cpu((end)->w0) & END2_W0_ENQUEUE)
114 #define xive2_end_is_notify(end) \
115 (be32_to_cpu((end)->w0) & END2_W0_UCOND_NOTIFY)
116 #define xive2_end_is_backlog(end) (be32_to_cpu((end)->w0) & END2_W0_BACKLOG)
117 #define xive2_end_is_precluded_escalation(end) \
118 (be32_to_cpu((end)->w0) & END2_W0_PRECL_ESC_CTL)
119 #define xive2_end_is_escalate(end) \
120 (be32_to_cpu((end)->w0) & END2_W0_ESCALATE_CTL)
121 #define xive2_end_is_uncond_escalation(end) \
122 (be32_to_cpu((end)->w0) & END2_W0_UNCOND_ESCALATE)
123 #define xive2_end_is_silent_escalation(end) \
124 (be32_to_cpu((end)->w0) & END2_W0_SILENT_ESCALATE)
125 #define xive2_end_is_escalate_end(end) \
126 (be32_to_cpu((end)->w0) & END2_W0_ESCALATE_END)
127 #define xive2_end_is_firmware1(end) \
128 (be32_to_cpu((end)->w0) & END2_W0_FIRMWARE1)
129 #define xive2_end_is_firmware2(end) \
130 (be32_to_cpu((end)->w0) & END2_W0_FIRMWARE2)
131 #define xive2_end_is_ignore(end) \
132 (be32_to_cpu((end)->w6) & END2_W6_IGNORE)
133 #define xive2_end_is_crowd(end) \
134 (be32_to_cpu((end)->w6) & END2_W6_CROWD)
135
xive2_end_qaddr(Xive2End * end)136 static inline uint64_t xive2_end_qaddr(Xive2End *end)
137 {
138 return ((uint64_t) be32_to_cpu(end->w2) & END2_W2_EQ_ADDR_HI) << 32 |
139 (be32_to_cpu(end->w3) & END2_W3_EQ_ADDR_LO);
140 }
141
142 void xive2_end_pic_print_info(Xive2End *end, uint32_t end_idx, GString *buf);
143 void xive2_end_queue_pic_print_info(Xive2End *end, uint32_t width,
144 GString *buf);
145 void xive2_end_eas_pic_print_info(Xive2End *end, uint32_t end_idx,
146 GString *buf);
147
148 /*
149 * Notification Virtual Processor (NVP)
150 */
151 typedef struct Xive2Nvp {
152 uint32_t w0;
153 #define NVP2_W0_VALID PPC_BIT32(0)
154 #define NVP2_W0_HW PPC_BIT32(7)
155 #define NVP2_W0_ESC_END PPC_BIT32(25) /* 'N' bit 0:ESB 1:END */
156 #define NVP2_W0_PGOFIRST PPC_BITMASK32(26, 31)
157 uint32_t w1;
158 #define NVP2_W1_CO PPC_BIT32(13)
159 #define NVP2_W1_CO_PRIV PPC_BITMASK32(14, 15)
160 #define NVP2_W1_CO_THRID_VALID PPC_BIT32(16)
161 #define NVP2_W1_CO_THRID PPC_BITMASK32(17, 31)
162 uint32_t w2;
163 #define NVP2_W2_CPPR PPC_BITMASK32(0, 7)
164 #define NVP2_W2_IPB PPC_BITMASK32(8, 15)
165 #define NVP2_W2_LSMFB PPC_BITMASK32(16, 23)
166 uint32_t w3;
167 uint32_t w4;
168 #define NVP2_W4_ESC_ESB_BLOCK PPC_BITMASK32(0, 3) /* N:0 */
169 #define NVP2_W4_ESC_ESB_INDEX PPC_BITMASK32(4, 31) /* N:0 */
170 #define NVP2_W4_ESC_END_BLOCK PPC_BITMASK32(4, 7) /* N:1 */
171 #define NVP2_W4_ESC_END_INDEX PPC_BITMASK32(8, 31) /* N:1 */
172 uint32_t w5;
173 #define NVP2_W5_PSIZE PPC_BITMASK32(0, 1)
174 #define NVP2_W5_VP_END_BLOCK PPC_BITMASK32(4, 7)
175 #define NVP2_W5_VP_END_INDEX PPC_BITMASK32(8, 31)
176 uint32_t w6;
177 #define NVP2_W6_REPORTING_LINE PPC_BITMASK32(4, 31)
178 uint32_t w7;
179 #define NVP2_W7_REPORTING_LINE PPC_BITMASK32(0, 23)
180 } Xive2Nvp;
181
182 #define xive2_nvp_is_valid(nvp) (be32_to_cpu((nvp)->w0) & NVP2_W0_VALID)
183 #define xive2_nvp_is_hw(nvp) (be32_to_cpu((nvp)->w0) & NVP2_W0_HW)
184 #define xive2_nvp_is_co(nvp) (be32_to_cpu((nvp)->w1) & NVP2_W1_CO)
185
186 /*
187 * The VP number space in a block is defined by the END2_W6_VP_OFFSET
188 * field of the XIVE END. When running in Gen1 mode (P9 compat mode),
189 * the VP space is reduced to (1 << 19) VPs per block
190 */
191 #define XIVE2_NVP_SHIFT 24
192 #define XIVE2_NVP_COUNT (1 << XIVE2_NVP_SHIFT)
193
xive2_nvp_cam_line(uint8_t nvp_blk,uint32_t nvp_idx)194 static inline uint32_t xive2_nvp_cam_line(uint8_t nvp_blk, uint32_t nvp_idx)
195 {
196 return (nvp_blk << XIVE2_NVP_SHIFT) | nvp_idx;
197 }
198
xive2_nvp_idx(uint32_t cam_line)199 static inline uint32_t xive2_nvp_idx(uint32_t cam_line)
200 {
201 return cam_line & ((1 << XIVE2_NVP_SHIFT) - 1);
202 }
203
xive2_nvp_blk(uint32_t cam_line)204 static inline uint32_t xive2_nvp_blk(uint32_t cam_line)
205 {
206 return (cam_line >> XIVE2_NVP_SHIFT) & 0xf;
207 }
208
209 void xive2_nvp_pic_print_info(Xive2Nvp *nvp, uint32_t nvp_idx, GString *buf);
210
211 /*
212 * Notification Virtual Group or Crowd (NVG/NVC)
213 */
214 typedef struct Xive2Nvgc {
215 uint32_t w0;
216 #define NVGC2_W0_VALID PPC_BIT32(0)
217 #define NVGC2_W0_PGONEXT PPC_BITMASK32(26, 31)
218 uint32_t w1;
219 uint32_t w2;
220 uint32_t w3;
221 uint32_t w4;
222 uint32_t w5;
223 uint32_t w6;
224 uint32_t w7;
225 } Xive2Nvgc;
226
227 #define xive2_nvgc_is_valid(nvgc) (be32_to_cpu((nvgc)->w0) & NVGC2_W0_VALID)
228
229 void xive2_nvgc_pic_print_info(Xive2Nvgc *nvgc, uint32_t nvgc_idx,
230 GString *buf);
231
232 #endif /* PPC_XIVE2_REGS_H */
233