1 /* SPDX-License-Identifier: MIT */
2 #ifndef __NVIF_IF0012_H__
3 #define __NVIF_IF0012_H__
4 
5 #include <drm/display/drm_dp.h>
6 
7 union nvif_outp_args {
8 	struct nvif_outp_v0 {
9 		__u8 version;
10 		__u8 id;	/* DCB device index. */
11 		__u8 pad02[6];
12 	} v0;
13 };
14 
15 #define NVIF_OUTP_V0_LOAD_DETECT 0x00
16 #define NVIF_OUTP_V0_ACQUIRE     0x01
17 #define NVIF_OUTP_V0_RELEASE     0x02
18 #define NVIF_OUTP_V0_INFOFRAME   0x03
19 #define NVIF_OUTP_V0_HDA_ELD     0x04
20 #define NVIF_OUTP_V0_DP_AUX_PWR  0x05
21 #define NVIF_OUTP_V0_DP_RETRAIN  0x06
22 #define NVIF_OUTP_V0_DP_MST_VCPI 0x07
23 
24 union nvif_outp_load_detect_args {
25 	struct nvif_outp_load_detect_v0 {
26 		__u8  version;
27 		__u8  load;
28 		__u8  pad02[2];
29 		__u32 data; /*TODO: move vbios loadval parsing into nvkm */
30 	} v0;
31 };
32 
33 union nvif_outp_acquire_args {
34 	struct nvif_outp_acquire_v0 {
35 		__u8 version;
36 #define NVIF_OUTP_ACQUIRE_V0_RGB_CRT 0x00
37 #define NVIF_OUTP_ACQUIRE_V0_TV      0x01
38 #define NVIF_OUTP_ACQUIRE_V0_TMDS    0x02
39 #define NVIF_OUTP_ACQUIRE_V0_LVDS    0x03
40 #define NVIF_OUTP_ACQUIRE_V0_DP      0x04
41 		__u8 proto;
42 		__u8 or;
43 		__u8 link;
44 		__u8 pad04[4];
45 		union {
46 			struct {
47 				__u8 head;
48 				__u8 hdmi;
49 				__u8 hdmi_max_ac_packet;
50 				__u8 hdmi_rekey;
51 #define NVIF_OUTP_ACQUIRE_V0_TMDS_HDMI_SCDC_SCRAMBLE (1 << 0)
52 #define NVIF_OUTP_ACQUIRE_V0_TMDS_HDMI_SCDC_DIV_BY_4 (1 << 1)
53 				__u8 hdmi_scdc;
54 				__u8 hdmi_hda;
55 				__u8 pad06[2];
56 			} tmds;
57 			struct {
58 				__u8 dual;
59 				__u8 bpc8;
60 				__u8 pad02[6];
61 			} lvds;
62 			struct {
63 				__u8 link_nr; /* 0 = highest possible. */
64 				__u8 link_bw; /* 0 = highest possible, DP BW code otherwise. */
65 				__u8 hda;
66 				__u8 mst;
67 				__u8 pad04[4];
68 				__u8 dpcd[DP_RECEIVER_CAP_SIZE];
69 			} dp;
70 		};
71 	} v0;
72 };
73 
74 union nvif_outp_release_args {
75 	struct nvif_outp_release_vn {
76 	} vn;
77 };
78 
79 union nvif_outp_infoframe_args {
80 	struct nvif_outp_infoframe_v0 {
81 		__u8 version;
82 #define NVIF_OUTP_INFOFRAME_V0_AVI 0
83 #define NVIF_OUTP_INFOFRAME_V0_VSI 1
84 		__u8 type;
85 		__u8 head;
86 		__u8 pad03[5];
87 		__u8 data[];
88 	} v0;
89 };
90 
91 union nvif_outp_hda_eld_args {
92 	struct nvif_outp_hda_eld_v0 {
93 		__u8  version;
94 		__u8  head;
95 		__u8  pad02[6];
96 		__u8  data[];
97 	} v0;
98 };
99 
100 union nvif_outp_dp_aux_pwr_args {
101 	struct nvif_outp_dp_aux_pwr_v0 {
102 		__u8 version;
103 		__u8 state;
104 		__u8 pad02[6];
105 	} v0;
106 };
107 
108 union nvif_outp_dp_retrain_args {
109 	struct nvif_outp_dp_retrain_vn {
110 	} vn;
111 };
112 
113 union nvif_outp_dp_mst_vcpi_args {
114 	struct nvif_outp_dp_mst_vcpi_v0 {
115 		__u8  version;
116 		__u8  head;
117 		__u8  start_slot;
118 		__u8  num_slots;
119 		__u16 pbn;
120 		__u16 aligned_pbn;
121 	} v0;
122 };
123 #endif
124