xref: /openbmc/linux/drivers/net/ethernet/amd/amd8111e.h (revision 4f2c0a4acffbec01079c28f839422e64ddeff004)
1  /* SPDX-License-Identifier: GPL-2.0-or-later */
2  /*
3   * Advanced  Micro Devices Inc. AMD8111E Linux Network Driver
4   * Copyright (C) 2003 Advanced Micro Devices
5   *
6  
7  Module Name:
8  
9      amd8111e.h
10  
11  Abstract:
12  
13  	 AMD8111 based 10/100 Ethernet Controller driver definitions.
14  
15  Environment:
16  
17  	Kernel Mode
18  
19  Revision History:
20  	3.0.0
21  	   Initial Revision.
22  	3.0.1
23  */
24  
25  #ifndef _AMD811E_H
26  #define _AMD811E_H
27  
28  /* Command style register access
29  
30  Registers CMD0, CMD2, CMD3,CMD7 and INTEN0 uses a write access technique called command style access. It allows the write to selected bits of this register without altering the bits that are not selected. Command style registers are divided into 4 bytes that can be written independently. Higher order bit of each byte is the  value bit that specifies the value that will be written into the selected bits of register.
31  
32  eg., if the value 10011010b is written into the least significant byte of a command style register, bits 1,3 and 4 of the register will be set to 1, and the other bits will not be altered. If the value 00011010b is written into the same byte, bits 1,3 and 4 will be cleared to 0 and the other bits will not be altered.
33  
34  */
35  
36  /*  Offset for Memory Mapped Registers. */
37  /* 32 bit registers */
38  
39  #define  ASF_STAT		0x00	/* ASF status register */
40  #define CHIPID			0x04	/* Chip ID register */
41  #define	MIB_DATA		0x10	/* MIB data register */
42  #define MIB_ADDR		0x14	/* MIB address register */
43  #define STAT0			0x30	/* Status0 register */
44  #define INT0			0x38	/* Interrupt0 register */
45  #define INTEN0			0x40	/* Interrupt0  enable register*/
46  #define CMD0			0x48	/* Command0 register */
47  #define CMD2			0x50	/* Command2 register */
48  #define CMD3			0x54	/* Command3 resiter */
49  #define CMD7			0x64	/* Command7 register */
50  
51  #define CTRL1 			0x6C	/* Control1 register */
52  #define CTRL2 			0x70	/* Control2 register */
53  
54  #define XMT_RING_LIMIT		0x7C	/* Transmit ring limit register */
55  
56  #define AUTOPOLL0		0x88	/* Auto-poll0 register */
57  #define AUTOPOLL1		0x8A	/* Auto-poll1 register */
58  #define AUTOPOLL2		0x8C	/* Auto-poll2 register */
59  #define AUTOPOLL3		0x8E	/* Auto-poll3 register */
60  #define AUTOPOLL4		0x90	/* Auto-poll4 register */
61  #define	AUTOPOLL5		0x92	/* Auto-poll5 register */
62  
63  #define AP_VALUE		0x98	/* Auto-poll value register */
64  #define DLY_INT_A		0xA8	/* Group A delayed interrupt register */
65  #define DLY_INT_B		0xAC	/* Group B delayed interrupt register */
66  
67  #define FLOW_CONTROL		0xC8	/* Flow control register */
68  #define PHY_ACCESS		0xD0	/* PHY access register */
69  
70  #define STVAL			0xD8	/* Software timer value register */
71  
72  #define XMT_RING_BASE_ADDR0	0x100	/* Transmit ring0 base addr register */
73  #define XMT_RING_BASE_ADDR1	0x108	/* Transmit ring1 base addr register */
74  #define XMT_RING_BASE_ADDR2	0x110	/* Transmit ring2 base addr register */
75  #define XMT_RING_BASE_ADDR3	0x118	/* Transmit ring2 base addr register */
76  
77  #define RCV_RING_BASE_ADDR0	0x120	/* Transmit ring0 base addr register */
78  
79  #define PMAT0			0x190	/* OnNow pattern register0 */
80  #define PMAT1			0x194	/* OnNow pattern register1 */
81  
82  /* 16bit registers */
83  
84  #define XMT_RING_LEN0		0x140	/* Transmit Ring0 length register */
85  #define XMT_RING_LEN1		0x144	/* Transmit Ring1 length register */
86  #define XMT_RING_LEN2		0x148 	/* Transmit Ring2 length register */
87  #define XMT_RING_LEN3		0x14C	/* Transmit Ring3 length register */
88  
89  #define RCV_RING_LEN0		0x150	/* Receive Ring0 length register */
90  
91  #define SRAM_SIZE		0x178	/* SRAM size register */
92  #define SRAM_BOUNDARY		0x17A	/* SRAM boundary register */
93  
94  /* 48bit register */
95  
96  #define PADR			0x160	/* Physical address register */
97  
98  #define IFS1			0x18C	/* Inter-frame spacing Part1 register */
99  #define IFS			0x18D	/* Inter-frame spacing register */
100  #define IPG			0x18E	/* Inter-frame gap register */
101  /* 64bit register */
102  
103  #define LADRF			0x168	/* Logical address filter register */
104  
105  
106  /* Register Bit Definitions */
107  typedef enum {
108  
109  	ASF_INIT_DONE		= (1 << 1),
110  	ASF_INIT_PRESENT	= (1 << 0),
111  
112  }STAT_ASF_BITS;
113  
114  typedef enum {
115  
116  	MIB_CMD_ACTIVE		= (1 << 15 ),
117  	MIB_RD_CMD		= (1 << 13 ),
118  	MIB_CLEAR		= (1 << 12 ),
119  	MIB_ADDRESS		= (1 << 0) | (1 << 1) | (1 << 2) | (1 << 3)|
120  					(1 << 4) | (1 << 5),
121  }MIB_ADDR_BITS;
122  
123  
124  typedef enum {
125  
126  	PMAT_DET		= (1 << 12),
127  	MP_DET		        = (1 << 11),
128  	LC_DET			= (1 << 10),
129  	SPEED_MASK		= (1 << 9)|(1 << 8)|(1 << 7),
130  	FULL_DPLX		= (1 << 6),
131  	LINK_STATS		= (1 << 5),
132  	AUTONEG_COMPLETE	= (1 << 4),
133  	MIIPD			= (1 << 3),
134  	RX_SUSPENDED		= (1 << 2),
135  	TX_SUSPENDED		= (1 << 1),
136  	RUNNING			= (1 << 0),
137  
138  }STAT0_BITS;
139  
140  #define PHY_SPEED_10		0x2
141  #define PHY_SPEED_100		0x3
142  
143  /* INT0				0x38, 32bit register */
144  typedef enum {
145  
146  	INTR			= (1 << 31),
147  	PCSINT			= (1 << 28),
148  	LCINT			= (1 << 27),
149  	APINT5			= (1 << 26),
150  	APINT4			= (1 << 25),
151  	APINT3			= (1 << 24),
152  	TINT_SUM		= (1 << 23),
153  	APINT2			= (1 << 22),
154  	APINT1			= (1 << 21),
155  	APINT0			= (1 << 20),
156  	MIIPDTINT		= (1 << 19),
157  	MCCINT			= (1 << 17),
158  	MREINT			= (1 << 16),
159  	RINT_SUM		= (1 << 15),
160  	SPNDINT			= (1 << 14),
161  	MPINT			= (1 << 13),
162  	SINT			= (1 << 12),
163  	TINT3			= (1 << 11),
164  	TINT2			= (1 << 10),
165  	TINT1			= (1 << 9),
166  	TINT0			= (1 << 8),
167  	UINT			= (1 << 7),
168  	STINT			= (1 << 4),
169  	RINT0			= (1 << 0),
170  
171  }INT0_BITS;
172  
173  typedef enum {
174  
175  	VAL3			= (1 << 31),   /* VAL bit for byte 3 */
176  	VAL2			= (1 << 23),   /* VAL bit for byte 2 */
177  	VAL1			= (1 << 15),   /* VAL bit for byte 1 */
178  	VAL0			= (1 << 7),    /* VAL bit for byte 0 */
179  
180  }VAL_BITS;
181  
182  typedef enum {
183  
184  	/* VAL3 */
185  	LCINTEN			= (1 << 27),
186  	APINT5EN		= (1 << 26),
187  	APINT4EN		= (1 << 25),
188  	APINT3EN		= (1 << 24),
189  	/* VAL2 */
190  	APINT2EN		= (1 << 22),
191  	APINT1EN		= (1 << 21),
192  	APINT0EN		= (1 << 20),
193  	MIIPDTINTEN		= (1 << 19),
194  	MCCIINTEN		= (1 << 18),
195  	MCCINTEN		= (1 << 17),
196  	MREINTEN		= (1 << 16),
197  	/* VAL1 */
198  	SPNDINTEN		= (1 << 14),
199  	MPINTEN			= (1 << 13),
200  	TINTEN3			= (1 << 11),
201  	SINTEN			= (1 << 12),
202  	TINTEN2			= (1 << 10),
203  	TINTEN1			= (1 << 9),
204  	TINTEN0			= (1 << 8),
205  	/* VAL0 */
206  	STINTEN			= (1 << 4),
207  	RINTEN0			= (1 << 0),
208  
209  	INTEN0_CLEAR 		= 0x1F7F7F1F, /* Command style register */
210  
211  }INTEN0_BITS;
212  
213  typedef enum {
214  	/* VAL2 */
215  	RDMD0			= (1 << 16),
216  	/* VAL1 */
217  	TDMD3			= (1 << 11),
218  	TDMD2			= (1 << 10),
219  	TDMD1			= (1 << 9),
220  	TDMD0			= (1 << 8),
221  	/* VAL0 */
222  	UINTCMD			= (1 << 6),
223  	RX_FAST_SPND		= (1 << 5),
224  	TX_FAST_SPND		= (1 << 4),
225  	RX_SPND			= (1 << 3),
226  	TX_SPND			= (1 << 2),
227  	INTREN			= (1 << 1),
228  	RUN			= (1 << 0),
229  
230  	CMD0_CLEAR 		= 0x000F0F7F,   /* Command style register */
231  
232  }CMD0_BITS;
233  
234  typedef enum {
235  
236  	/* VAL3 */
237  	CONDUIT_MODE		= (1 << 29),
238  	/* VAL2 */
239  	RPA			= (1 << 19),
240  	DRCVPA			= (1 << 18),
241  	DRCVBC			= (1 << 17),
242  	PROM			= (1 << 16),
243  	/* VAL1 */
244  	ASTRP_RCV		= (1 << 13),
245  	RCV_DROP0	  	= (1 << 12),
246  	EMBA			= (1 << 11),
247  	DXMT2PD			= (1 << 10),
248  	LTINTEN			= (1 << 9),
249  	DXMTFCS			= (1 << 8),
250  	/* VAL0 */
251  	APAD_XMT		= (1 << 6),
252  	DRTY			= (1 << 5),
253  	INLOOP			= (1 << 4),
254  	EXLOOP			= (1 << 3),
255  	REX_RTRY		= (1 << 2),
256  	REX_UFLO		= (1 << 1),
257  	REX_LCOL		= (1 << 0),
258  
259  	CMD2_CLEAR 		= 0x3F7F3F7F,   /* Command style register */
260  
261  }CMD2_BITS;
262  
263  typedef enum {
264  
265  	/* VAL3 */
266  	ASF_INIT_DONE_ALIAS	= (1 << 29),
267  	/* VAL2 */
268  	JUMBO			= (1 << 21),
269  	VSIZE			= (1 << 20),
270  	VLONLY			= (1 << 19),
271  	VL_TAG_DEL		= (1 << 18),
272  	/* VAL1 */
273  	EN_PMGR			= (1 << 14),
274  	INTLEVEL		= (1 << 13),
275  	FORCE_FULL_DUPLEX	= (1 << 12),
276  	FORCE_LINK_STATUS	= (1 << 11),
277  	APEP			= (1 << 10),
278  	MPPLBA			= (1 << 9),
279  	/* VAL0 */
280  	RESET_PHY_PULSE		= (1 << 2),
281  	RESET_PHY		= (1 << 1),
282  	PHY_RST_POL		= (1 << 0),
283  
284  }CMD3_BITS;
285  
286  
287  typedef enum {
288  
289  	/* VAL0 */
290  	PMAT_SAVE_MATCH		= (1 << 4),
291  	PMAT_MODE		= (1 << 3),
292  	MPEN_SW			= (1 << 1),
293  	LCMODE_SW		= (1 << 0),
294  
295  	CMD7_CLEAR  		= 0x0000001B	/* Command style register */
296  
297  }CMD7_BITS;
298  
299  
300  typedef enum {
301  
302  	RESET_PHY_WIDTH		= (0xF << 16) | (0xF<< 20), /* 0x00FF0000 */
303  	XMTSP_MASK		= (1 << 9) | (1 << 8),	/* 9:8 */
304  	XMTSP_128		= (1 << 9),	/* 9 */
305  	XMTSP_64		= (1 << 8),
306  	CACHE_ALIGN		= (1 << 4),
307  	BURST_LIMIT_MASK	= (0xF << 0 ),
308  	CTRL1_DEFAULT		= 0x00010111,
309  
310  }CTRL1_BITS;
311  
312  typedef enum {
313  
314  	FMDC_MASK		= (1 << 9)|(1 << 8),	/* 9:8 */
315  	XPHYRST			= (1 << 7),
316  	XPHYANE			= (1 << 6),
317  	XPHYFD			= (1 << 5),
318  	XPHYSP			= (1 << 4) | (1 << 3),	/* 4:3 */
319  	APDW_MASK		= (1 <<	2) | (1 << 1) | (1 << 0), /* 2:0 */
320  
321  }CTRL2_BITS;
322  
323  /* XMT_RING_LIMIT		0x7C, 32bit register */
324  typedef enum {
325  
326  	XMT_RING2_LIMIT		= (0xFF << 16),	/* 23:16 */
327  	XMT_RING1_LIMIT		= (0xFF << 8),	/* 15:8 */
328  	XMT_RING0_LIMIT		= (0xFF << 0), 	/* 7:0 */
329  
330  }XMT_RING_LIMIT_BITS;
331  
332  typedef enum {
333  
334  	AP_REG0_EN		= (1 << 15),
335  	AP_REG0_ADDR_MASK	= (0xF << 8) |(1 << 12),/* 12:8 */
336  	AP_PHY0_ADDR_MASK	= (0xF << 0) |(1 << 4),/* 4:0 */
337  
338  }AUTOPOLL0_BITS;
339  
340  /* AUTOPOLL1			0x8A, 16bit register */
341  typedef enum {
342  
343  	AP_REG1_EN		= (1 << 15),
344  	AP_REG1_ADDR_MASK	= (0xF << 8) |(1 << 12),/* 12:8 */
345  	AP_PRE_SUP1		= (1 << 6),
346  	AP_PHY1_DFLT		= (1 << 5),
347  	AP_PHY1_ADDR_MASK	= (0xF << 0) |(1 << 4),/* 4:0 */
348  
349  }AUTOPOLL1_BITS;
350  
351  
352  typedef enum {
353  
354  	AP_REG2_EN		= (1 << 15),
355  	AP_REG2_ADDR_MASK	= (0xF << 8) |(1 << 12),/* 12:8 */
356  	AP_PRE_SUP2		= (1 << 6),
357  	AP_PHY2_DFLT		= (1 << 5),
358  	AP_PHY2_ADDR_MASK	= (0xF << 0) |(1 << 4),/* 4:0 */
359  
360  }AUTOPOLL2_BITS;
361  
362  typedef enum {
363  
364  	AP_REG3_EN		= (1 << 15),
365  	AP_REG3_ADDR_MASK	= (0xF << 8) |(1 << 12),/* 12:8 */
366  	AP_PRE_SUP3		= (1 << 6),
367  	AP_PHY3_DFLT		= (1 << 5),
368  	AP_PHY3_ADDR_MASK	= (0xF << 0) |(1 << 4),/* 4:0 */
369  
370  }AUTOPOLL3_BITS;
371  
372  
373  typedef enum {
374  
375  	AP_REG4_EN		= (1 << 15),
376  	AP_REG4_ADDR_MASK	= (0xF << 8) |(1 << 12),/* 12:8 */
377  	AP_PRE_SUP4		= (1 << 6),
378  	AP_PHY4_DFLT		= (1 << 5),
379  	AP_PHY4_ADDR_MASK	= (0xF << 0) |(1 << 4),/* 4:0 */
380  
381  }AUTOPOLL4_BITS;
382  
383  
384  typedef enum {
385  
386  	AP_REG5_EN		= (1 << 15),
387  	AP_REG5_ADDR_MASK	= (0xF << 8) |(1 << 12),/* 12:8 */
388  	AP_PRE_SUP5		= (1 << 6),
389  	AP_PHY5_DFLT		= (1 << 5),
390  	AP_PHY5_ADDR_MASK	= (0xF << 0) |(1 << 4),/* 4:0 */
391  
392  }AUTOPOLL5_BITS;
393  
394  
395  
396  
397  /* AP_VALUE 			0x98, 32bit ragister */
398  typedef enum {
399  
400  	AP_VAL_ACTIVE		= (1 << 31),
401  	AP_VAL_RD_CMD		= ( 1 << 29),
402  	AP_ADDR			= (1 << 18)|(1 << 17)|(1 << 16), /* 18:16 */
403  	AP_VAL			= (0xF << 0) | (0xF << 4) |( 0xF << 8) |
404  				  (0xF << 12),	/* 15:0 */
405  
406  }AP_VALUE_BITS;
407  
408  typedef enum {
409  
410  	DLY_INT_A_R3		= (1 << 31),
411  	DLY_INT_A_R2		= (1 << 30),
412  	DLY_INT_A_R1		= (1 << 29),
413  	DLY_INT_A_R0		= (1 << 28),
414  	DLY_INT_A_T3		= (1 << 27),
415  	DLY_INT_A_T2		= (1 << 26),
416  	DLY_INT_A_T1		= (1 << 25),
417  	DLY_INT_A_T0		= ( 1 << 24),
418  	EVENT_COUNT_A		= (0xF << 16) | (0x1 << 20),/* 20:16 */
419  	MAX_DELAY_TIME_A	= (0xF << 0) | (0xF << 4) | (1 << 8)|
420  				  (1 << 9) | (1 << 10),	/* 10:0 */
421  
422  }DLY_INT_A_BITS;
423  
424  typedef enum {
425  
426  	DLY_INT_B_R3		= (1 << 31),
427  	DLY_INT_B_R2		= (1 << 30),
428  	DLY_INT_B_R1		= (1 << 29),
429  	DLY_INT_B_R0		= (1 << 28),
430  	DLY_INT_B_T3		= (1 << 27),
431  	DLY_INT_B_T2		= (1 << 26),
432  	DLY_INT_B_T1		= (1 << 25),
433  	DLY_INT_B_T0		= ( 1 << 24),
434  	EVENT_COUNT_B		= (0xF << 16) | (0x1 << 20),/* 20:16 */
435  	MAX_DELAY_TIME_B	= (0xF << 0) | (0xF << 4) | (1 << 8)|
436  				  (1 << 9) | (1 << 10),	/* 10:0 */
437  }DLY_INT_B_BITS;
438  
439  
440  /* FLOW_CONTROL 		0xC8, 32bit register */
441  typedef enum {
442  
443  	PAUSE_LEN_CHG		= (1 << 30),
444  	FTPE			= (1 << 22),
445  	FRPE			= (1 << 21),
446  	NAPA			= (1 << 20),
447  	NPA			= (1 << 19),
448  	FIXP			= ( 1 << 18),
449  	FCCMD			= ( 1 << 16),
450  	PAUSE_LEN		= (0xF << 0) | (0xF << 4) |( 0xF << 8) |	 				  (0xF << 12),	/* 15:0 */
451  
452  }FLOW_CONTROL_BITS;
453  
454  /* PHY_ ACCESS			0xD0, 32bit register */
455  typedef enum {
456  
457  	PHY_CMD_ACTIVE		= (1 << 31),
458  	PHY_WR_CMD		= (1 << 30),
459  	PHY_RD_CMD		= (1 << 29),
460  	PHY_RD_ERR		= (1 << 28),
461  	PHY_PRE_SUP		= (1 << 27),
462  	PHY_ADDR		= (1 << 21) | (1 << 22) | (1 << 23)|
463  				  	(1 << 24) |(1 << 25),/* 25:21 */
464  	PHY_REG_ADDR		= (1 << 16) | (1 << 17) | (1 << 18)|	 			  	   	  	(1 << 19) | (1 << 20),/* 20:16 */
465  	PHY_DATA		= (0xF << 0)|(0xF << 4) |(0xF << 8)|
466  					(0xF << 12),/* 15:0 */
467  
468  }PHY_ACCESS_BITS;
469  
470  
471  /* PMAT0			0x190,	 32bit register */
472  typedef enum {
473  	PMR_ACTIVE		= (1 << 31),
474  	PMR_WR_CMD		= (1 << 30),
475  	PMR_RD_CMD		= (1 << 29),
476  	PMR_BANK		= (1 <<28),
477  	PMR_ADDR		= (0xF << 16)|(1 << 20)|(1 << 21)|
478  				  	(1 << 22),/* 22:16 */
479  	PMR_B4			= (0xF << 0) | (0xF << 4),/* 15:0 */
480  }PMAT0_BITS;
481  
482  
483  /* PMAT1			0x194,	 32bit register */
484  typedef enum {
485  	PMR_B3			= (0xF << 24) | (0xF <<28),/* 31:24 */
486  	PMR_B2			= (0xF << 16) |(0xF << 20),/* 23:16 */
487  	PMR_B1			= (0xF << 8) | (0xF <<12), /* 15:8 */
488  	PMR_B0			= (0xF << 0)|(0xF << 4),/* 7:0 */
489  }PMAT1_BITS;
490  
491  /************************************************************************/
492  /*                                                                      */
493  /*                      MIB counter definitions                         */
494  /*                                                                      */
495  /************************************************************************/
496  
497  #define rcv_miss_pkts				0x00
498  #define rcv_octets				0x01
499  #define rcv_broadcast_pkts			0x02
500  #define rcv_multicast_pkts			0x03
501  #define rcv_undersize_pkts			0x04
502  #define rcv_oversize_pkts			0x05
503  #define rcv_fragments				0x06
504  #define rcv_jabbers				0x07
505  #define rcv_unicast_pkts			0x08
506  #define rcv_alignment_errors			0x09
507  #define rcv_fcs_errors				0x0A
508  #define rcv_good_octets				0x0B
509  #define rcv_mac_ctrl				0x0C
510  #define rcv_flow_ctrl				0x0D
511  #define rcv_pkts_64_octets			0x0E
512  #define rcv_pkts_65to127_octets			0x0F
513  #define rcv_pkts_128to255_octets		0x10
514  #define rcv_pkts_256to511_octets		0x11
515  #define rcv_pkts_512to1023_octets		0x12
516  #define rcv_pkts_1024to1518_octets		0x13
517  #define rcv_unsupported_opcode			0x14
518  #define rcv_symbol_errors			0x15
519  #define rcv_drop_pkts_ring1			0x16
520  #define rcv_drop_pkts_ring2			0x17
521  #define rcv_drop_pkts_ring3			0x18
522  #define rcv_drop_pkts_ring4			0x19
523  #define rcv_jumbo_pkts				0x1A
524  
525  #define xmt_underrun_pkts			0x20
526  #define xmt_octets				0x21
527  #define xmt_packets				0x22
528  #define xmt_broadcast_pkts			0x23
529  #define xmt_multicast_pkts			0x24
530  #define xmt_collisions				0x25
531  #define xmt_unicast_pkts			0x26
532  #define xmt_one_collision			0x27
533  #define xmt_multiple_collision			0x28
534  #define xmt_deferred_transmit			0x29
535  #define xmt_late_collision			0x2A
536  #define xmt_excessive_defer			0x2B
537  #define xmt_loss_carrier			0x2C
538  #define xmt_excessive_collision			0x2D
539  #define xmt_back_pressure			0x2E
540  #define xmt_flow_ctrl				0x2F
541  #define xmt_pkts_64_octets			0x30
542  #define xmt_pkts_65to127_octets			0x31
543  #define xmt_pkts_128to255_octets		0x32
544  #define xmt_pkts_256to511_octets		0x33
545  #define xmt_pkts_512to1023_octets		0x34
546  #define xmt_pkts_1024to1518_octet		0x35
547  #define xmt_oversize_pkts			0x36
548  #define xmt_jumbo_pkts				0x37
549  
550  
551  /* Driver definitions */
552  
553  #define	 PCI_VENDOR_ID_AMD		0x1022
554  #define  PCI_DEVICE_ID_AMD8111E_7462	0x7462
555  
556  #define MAX_UNITS			8 /* Maximum number of devices possible */
557  
558  #define NUM_TX_BUFFERS			32 /* Number of transmit buffers */
559  #define NUM_RX_BUFFERS			32 /* Number of receive buffers */
560  
561  #define TX_BUFF_MOD_MASK         	31 /* (NUM_TX_BUFFERS -1) */
562  #define RX_BUFF_MOD_MASK         	31 /* (NUM_RX_BUFFERS -1) */
563  
564  #define NUM_TX_RING_DR			32
565  #define NUM_RX_RING_DR			32
566  
567  #define TX_RING_DR_MOD_MASK         	31 /* (NUM_TX_RING_DR -1) */
568  #define RX_RING_DR_MOD_MASK         	31 /* (NUM_RX_RING_DR -1) */
569  
570  #define MAX_FILTER_SIZE			64 /* Maximum multicast address */
571  #define AMD8111E_MIN_MTU	 	60
572  #define AMD8111E_MAX_MTU		9000
573  
574  #define PKT_BUFF_SZ			1536
575  #define MIN_PKT_LEN			60
576  
577  #define  AMD8111E_TX_TIMEOUT		(3 * HZ)/* 3 sec */
578  #define SOFT_TIMER_FREQ 		0xBEBC  /* 0.5 sec */
579  #define DELAY_TIMER_CONV		50    /* msec to 10 usec conversion.
580  						 Only 500 usec resolution */
581  #define OPTION_VLAN_ENABLE		0x0001
582  #define OPTION_JUMBO_ENABLE		0x0002
583  #define OPTION_MULTICAST_ENABLE		0x0004
584  #define OPTION_WOL_ENABLE		0x0008
585  #define OPTION_WAKE_MAGIC_ENABLE	0x0010
586  #define OPTION_WAKE_PHY_ENABLE		0x0020
587  #define OPTION_INTR_COAL_ENABLE		0x0040
588  #define OPTION_DYN_IPG_ENABLE	        0x0080
589  
590  #define PHY_REG_ADDR_MASK		0x1f
591  
592  /* ipg parameters */
593  #define DEFAULT_IPG			0x60
594  #define IFS1_DELTA			36
595  #define	IPG_CONVERGE_JIFFIES (HZ/2)
596  #define	IPG_STABLE_TIME	5
597  #define	MIN_IPG	96
598  #define	MAX_IPG	255
599  #define IPG_STEP	16
600  #define CSTATE  1
601  #define SSTATE  2
602  
603  /* Assume controller gets data 10 times the maximum processing time */
604  #define  REPEAT_CNT			10
605  
606  /* amd8111e descriptor flag definitions */
607  typedef enum {
608  
609  	OWN_BIT		=	(1 << 15),
610  	ADD_FCS_BIT	=	(1 << 13),
611  	LTINT_BIT	=	(1 << 12),
612  	STP_BIT		=	(1 << 9),
613  	ENP_BIT		=	(1 << 8),
614  	KILL_BIT	= 	(1 << 6),
615  	TCC_VLAN_INSERT	=	(1 << 1),
616  	TCC_VLAN_REPLACE =	(1 << 1) |( 1<< 0),
617  
618  }TX_FLAG_BITS;
619  
620  typedef enum {
621  	ERR_BIT 	=	(1 << 14),
622  	FRAM_BIT	=  	(1 << 13),
623  	OFLO_BIT	=       (1 << 12),
624  	CRC_BIT		=	(1 << 11),
625  	PAM_BIT		=	(1 << 6),
626  	LAFM_BIT	= 	(1 << 5),
627  	BAM_BIT		=	(1 << 4),
628  	TT_VLAN_TAGGED	= 	(1 << 3) |(1 << 2),/* 0x000 */
629  	TT_PRTY_TAGGED	=	(1 << 3),/* 0x0008 */
630  
631  }RX_FLAG_BITS;
632  
633  #define RESET_RX_FLAGS		0x0000
634  #define TT_MASK			0x000c
635  #define TCC_MASK		0x0003
636  
637  /* driver ioctl parameters */
638  #define AMD8111E_REG_DUMP_LEN	 13*sizeof(u32)
639  
640  /* amd8111e descriptor format */
641  
642  struct amd8111e_tx_dr{
643  
644  	__le16 buff_count; /* Size of the buffer pointed by this descriptor */
645  
646  	__le16 tx_flags;
647  
648  	__le16 tag_ctrl_info;
649  
650  	__le16 tag_ctrl_cmd;
651  
652  	__le32 buff_phy_addr;
653  
654  	__le32 reserved;
655  };
656  
657  struct amd8111e_rx_dr{
658  
659  	__le32 reserved;
660  
661  	__le16 msg_count; /* Received message len */
662  
663  	__le16 tag_ctrl_info;
664  
665  	__le16 buff_count;  /* Len of the buffer pointed by descriptor. */
666  
667  	__le16 rx_flags;
668  
669  	__le32 buff_phy_addr;
670  
671  };
672  struct amd8111e_link_config{
673  
674  #define SPEED_INVALID		0xffff
675  #define DUPLEX_INVALID		0xff
676  #define AUTONEG_INVALID		0xff
677  
678  	unsigned long			orig_phy_option;
679  	u16				speed;
680  	u8				duplex;
681  	u8				autoneg;
682  	u8				reserved;  /* 32bit alignment */
683  };
684  
685  enum coal_type{
686  
687  	NO_COALESCE,
688  	LOW_COALESCE,
689  	MEDIUM_COALESCE,
690  	HIGH_COALESCE,
691  
692  };
693  
694  enum coal_mode{
695  	RX_INTR_COAL,
696  	TX_INTR_COAL,
697  	DISABLE_COAL,
698  	ENABLE_COAL,
699  
700  };
701  #define MAX_TIMEOUT	40
702  #define MAX_EVENT_COUNT 31
703  struct amd8111e_coalesce_conf{
704  
705  	unsigned int rx_timeout;
706  	unsigned int rx_event_count;
707  	unsigned long rx_packets;
708  	unsigned long rx_prev_packets;
709  	unsigned long rx_bytes;
710  	unsigned long rx_prev_bytes;
711  	unsigned int rx_coal_type;
712  
713  	unsigned int tx_timeout;
714  	unsigned int tx_event_count;
715  	unsigned long tx_packets;
716  	unsigned long tx_prev_packets;
717  	unsigned long tx_bytes;
718  	unsigned long tx_prev_bytes;
719  	unsigned int tx_coal_type;
720  
721  };
722  struct ipg_info{
723  
724  	unsigned int ipg_state;
725  	unsigned int ipg;
726  	unsigned int current_ipg;
727  	unsigned int col_cnt;
728  	unsigned int diff_col_cnt;
729  	unsigned int timer_tick;
730  	unsigned int prev_ipg;
731  	struct timer_list ipg_timer;
732  };
733  
734  struct amd8111e_priv{
735  
736  	struct amd8111e_tx_dr*  tx_ring;
737  	struct amd8111e_rx_dr* rx_ring;
738  	dma_addr_t tx_ring_dma_addr;	/* tx descriptor ring base address */
739  	dma_addr_t rx_ring_dma_addr;	/* rx descriptor ring base address */
740  	const char *name;
741  	struct pci_dev *pci_dev;	/* Ptr to the associated pci_dev */
742  	struct net_device* amd8111e_net_dev; 	/* ptr to associated net_device */
743  	/* Transmit and receive skbs */
744  	struct sk_buff *tx_skbuff[NUM_TX_BUFFERS];
745  	struct sk_buff *rx_skbuff[NUM_RX_BUFFERS];
746  	/* Transmit and receive dma mapped addr */
747  	dma_addr_t tx_dma_addr[NUM_TX_BUFFERS];
748  	dma_addr_t rx_dma_addr[NUM_RX_BUFFERS];
749  	/* Reg memory mapped address */
750  	void __iomem *mmio;
751  
752  	struct napi_struct napi;
753  
754  	spinlock_t lock;	/* Guard lock */
755  	unsigned long rx_idx, tx_idx;	/* The next free ring entry */
756  	unsigned long tx_complete_idx;
757  	unsigned long tx_ring_complete_idx;
758  	unsigned long tx_ring_idx;
759  	unsigned int rx_buff_len;	/* Buffer length of rx buffers */
760  	int options;		/* Options enabled/disabled for the device */
761  
762  	unsigned long ext_phy_option;
763  	int ext_phy_addr;
764  	u32 ext_phy_id;
765  
766  	struct amd8111e_link_config link_config;
767  	int pm_cap;
768  
769  	struct net_device *next;
770  	int mii;
771  	struct mii_if_info mii_if;
772  	char opened;
773  	unsigned int drv_rx_errors;
774  	struct amd8111e_coalesce_conf coal_conf;
775  
776  	struct ipg_info  ipg_data;
777  
778  };
779  
780  /* kernel provided writeq does not write 64 bits into the amd8111e device register instead writes only higher 32bits data into lower 32bits of the register.
781  BUG? */
782  #define  amd8111e_writeq(_UlData,_memMap)   \
783  		writel(*(u32*)(&_UlData), _memMap);	\
784  		writel(*(u32*)((u8*)(&_UlData)+4), _memMap+4)
785  
786  /* maps the external speed options to internal value */
787  typedef enum {
788  	SPEED_AUTONEG,
789  	SPEED10_HALF,
790  	SPEED10_FULL,
791  	SPEED100_HALF,
792  	SPEED100_FULL,
793  }EXT_PHY_OPTION;
794  
795  static int card_idx;
796  static int speed_duplex[MAX_UNITS] = { 0, };
797  static bool coalesce[MAX_UNITS] = { [ 0 ... MAX_UNITS-1] = true };
798  static bool dynamic_ipg[MAX_UNITS] = { [ 0 ... MAX_UNITS-1] = false };
799  static unsigned int chip_version;
800  
801  #endif /* _AMD8111E_H */
802  
803